Electronic device sharing memory and method of operating same to share memory
By setting master-slave identification and access detection pins in the electronic device, multiple chips can use voltage state switching to access the memory in turn, solving the problem of increased hardware cost and power consumption, and achieving efficient memory usage.
Patent Information
- Application Number
- CN202410069433.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-17
- Publication Date
- 2025-07-18
AI Technical Summary
In modern electronic devices, when multiple single-chip systems share the same memory, the prior art leads to problems of increased hardware cost and power consumption.
By setting the master-slave identification pin and the access detection pin on the first chip and the second chip, using different voltage state switching, the memory is accessed in turn to avoid conflicts.
It reduces hardware cost and power consumption, while avoiding access conflicts between chips and improving memory usage efficiency.
Smart Images
Figure CN120336243A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to an electronic device, and particularly to an electronic device capable of enabling multiple chips to share a memory. Background Art
[0002] To meet the increasing functional requirements of modern electronic devices, multiple chips, such as multiple System on Chips (SoCs), are often required to be provided on the main board of the electronic device. Since the programs executed by the SoCs are usually stored in a memory (such as a flash memory), in addition to multiple SoCs, the main board also includes multiple corresponding memories. In some applications, the multiple SoCs on the main board may actually have the same function, that is, the programs they execute may be the same. In this case, if each SoC still independently uses its own memory to store the execution program, the hardware cost and power consumption will be greatly increased. Therefore, how to enable multiple SoCs to access the same memory to reduce the hardware cost and power consumption has become a problem to be solved. Summary of the Invention
[0003] An embodiment of the present application provides an electronic device. The electronic device includes a memory, a first chip, and a second chip. The first chip includes a first master-slave identification pin coupled to a main voltage, a first access detection pin coupled to a first voltage, and a plurality of first interface pins coupled to the memory. The first chip is configured to switch between an idle state, a detection state, and an access state based on the voltages of the first master-slave identification pin and the first access detection pin. The second chip includes a second master-slave identification pin, a second access detection pin coupled to the first access detection pin, and a plurality of second interface pins correspondingly coupled to the first interface pins and the memory. The second chip is configured to switch between an idle state, a detection state, and an access state based on the voltages of the second master-slave identification pin and the second access detection pin. When the first chip is activated, the first chip enters the idle state. When the first chip waits in the idle state for more than a predetermined idle time and the first access detection pin continuously remains at the first voltage, the first chip enters the access state to access the memory through the first interface pins and fixes the voltage of the first access detection pin at a second voltage. The first voltage is different from the second voltage.
[0004] Another embodiment of the present application provides an operating method for an electronic device. The electronic device includes a memory, a first chip, and a second chip. The first chip includes a first master-slave identification pin coupled to a main voltage, a first access detection pin coupled to a first voltage, and a plurality of first interface pins coupled to the memory. The second chip includes a second master-slave identification pin, a second access detection pin coupled to the first access detection pin, and a plurality of second interface pins correspondingly coupled to the first interface pins and the memory. The operating method of the electronic device includes when the first chip is activated, putting the first chip into an idle state, and when the first chip waits in the idle state for more than a predetermined idle time and the first access detection pin continuously remains at the first voltage, putting the first chip into an access state so that the first chip accesses the memory through the first interface pins and fixing the voltage of the first access detection pin at a second voltage. Wherein the first voltage is different from the second voltage. Description of the Drawings
[0005] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present application.
[0006] Figure 2A and Figure 2B is a flowchart of the operating methods of the first chip and the second chip in the electronic device according to an embodiment of the present application.
[0007] Figure 3 is an embodiment of the present application Figure 1 operating timing diagram of the electronic device.
[0008] Figure 4 is a schematic diagram of an electronic device according to another embodiment of the present application.
[0009] Figure 5 is an embodiment of the present application Figure 4 operating timing diagram of the electronic device.
[0010] Figure 6 is another embodiment of the present application Figure 1 operating timing diagram of the electronic device.
[0011] Figure 7 is another embodiment of the present application Figure 1 operating timing diagram of the electronic device.
[0012] Figure 8 is another embodiment of the present application Figure 1 operating timing diagram of the electronic device.
[0013] Figure 9 is another embodiment of the present application Figure 1 operating timing diagram of the electronic device.
[0014] Symbol Description
[0015] 100, 200: Electronic devices
[0016] 110: First chip
[0017] 120: Second chip
[0018] 130: Memory
[0019] 112: First master - slave identification pin
[0020] 114: First access detection pin
[0021] 116: First interface pin
[0022] 122: Second master - slave identification pin
[0023] 124: Second access detection pin
[0024] 126: Second interface pin
[0025] VM: Main voltage
[0026] VS: Slave voltage
[0027] V1: First voltage
[0028] V2: Second voltage
[0029] M1: Method
[0030] S110, S120, S122, S124, S126, S130, S140: Steps
[0031] S131, S132, S133, S134, S135, S142, S144: Steps
[0032] P1: Predetermined idle time
[0033] P2: Predetermined access time
[0034] P3: Predetermined buffer time
[0035] P4: Predetermined detection time
[0036] P5: Slave buffer time
[0037] T0, T1, T2, T3, T4, T5, T6, T7, T8: Time points
[0038] T9, T10, T11, T12, T13, T14: Time points Detailed implementation manners
[0039] Figure 1It is a schematic diagram of an electronic device 100 according to an embodiment of the present application. The electronic device 100 includes a first chip 110, a second chip 120, and a memory 130. The first chip 110 and the second chip 120 may include a processor, for example, and may access data in the memory 130 in a round-robin (or polling) manner. The memory 130 may be a flash memory, for example, but the present application is not limited thereto.
[0040] The first chip 110 may include a first master-slave identification pin 112, a first access detection pin 114, and a first interface pin 116. Similarly, the second chip 120 may include a second master-slave identification pin 122, a second access detection pin 124, and a second interface pin 126. In this embodiment, the first chip 110 and the second chip 120 may be two chips with the same function, for example, and in some embodiments, the first chip 110 and the second chip 120 may be two chips with exactly the same structure. In this case, in order for the first chip 110 and the second chip 120 to access the memory 130 in a round-robin manner without conflicts during the process, different voltages may be applied to the first master-slave identification pin 112 of the first chip 110 and the second master-slave identification pin 122 of the second chip 120, so that the first chip 110 and the second chip can be respectively used as a master chip and a slave chip with different access priorities. For example, the first master-slave identification pin 112 of the first chip 110 may be coupled to the master voltage VM, and the second master-slave identification pin 122 of the second chip 120 may be coupled to the slave voltage VS. In this case, the first chip 110 may be the master chip, and the second chip 120 may be the slave chip. In this embodiment, compared with the slave chip, the master chip can obtain the access right to the cache memory 130 preferentially, so conflicts between the two can be avoided. In some embodiments, the master voltage VM may be the power supply voltage in the electronic device 100, for example, and the slave voltage VS may be the ground voltage in the electronic device 100, for example, but the present application is not limited thereto.
[0041] The first access detection pin 114 of the first chip 110 can be coupled to the first voltage V1, and the second access detection pin 124 of the second chip 120 can be coupled to the first access detection pin 114 of the first chip 110. In this embodiment, the first chip 110 and the second chip 120 can change the voltages of the first access detection pin 114 and the second access detection pin 124 through internal circuits in a specific state. For example, the voltages of the first access detection pin 114 and the second access detection pin 124 can be changed to a second voltage V2 different from the first voltage V1. For example, the first voltage V1 can be a power supply voltage, and the second voltage V2 can be a ground voltage. In the first chip 110, the first access detection pin 114 can be coupled to the second voltage V2 through a switch. Therefore, when the first chip 110 starts to access the memory 130, the switch can be turned on, so that the voltages of the first access detection pin 114 and the second access detection pin 124 are pulled down to the second voltage V2. In this way, the second chip 120 can determine whether the memory 130 is in an accessed state according to the voltage of the second access detection pin 124. Similarly, the first chip 110 can also determine whether the memory 130 is in an accessed state according to the voltage of the first access detection pin 114.
[0042] In some embodiments, the first master-slave identification pin 112, the first access detection pin 114, the second master-slave identification pin 122, and the second access detection pin 124 can be configured by general-purpose input / output pins (General-Purpose Input / Output, GPIO) in the first chip 110 and the second chip 120.
[0043] In addition, the first interface pin 116 can be coupled to the memory 130, and the second interface pin 126 can be correspondingly coupled to the first interface pin 116 and the memory 130. Although in Figure 1 only one pin is used to represent the first interface pin 116 and the second interface pin 126 respectively, the present application is not limited thereto. In some embodiments, the first chip 110 and the second chip 120 can communicate with the memory 130 through a Serial Peripheral Interface (SPI). In this case, the first interface pin 116 can include input data pins, output data pins, and clock pins required to transmit the serial peripheral interface; the same applies to the second interface pin 126.
[0044] In this embodiment, the first chip 110 can switch between an idle state, a detection state, and an access state according to the voltages of the first master-slave identification pin 112 and the first access detection pin 114, and the second chip 120 can also switch between an idle state, a detection state, and an access state according to the voltages of the second master-slave identification pin 122 and the second access detection pin 124.
[0045] In this embodiment, Figure 2A and Figure 2B is a flowchart of an operation method M1 of the first chip 110 and the second chip 120 in the electronic device 100 according to an embodiment of the present application. The method M1 may include steps S110 to S144. In this embodiment, the first chip 110 and the second chip 120 can be based on Figure 2A and Figure 2B The shown processes and conditions switch between an idle state, a detection state, and an access state. In addition, in some embodiments, the first chip 110 and the second chip 120 may include a state machine, and the first chip 110 and the second chip 120 can perform state transformation through the state machine.
[0046] Figure 3 is an operation timing diagram of the electronic device 100 according to an embodiment of the present application. At Figure 3 , the first chip 110 and the second chip 120 can be started at time point T0 (step S110), and at this time, the first chip 110 and the second chip 120 will enter the idle state (step S120).
[0047] Next, since the master-slave identification pin 112 of the first chip 110 is coupled to the main voltage VM, the first chip 110 will be guided from step S122 to step S124. On the contrary, the second chip 120 will be guided from step S122 to step S126. In this case, since both the first chip 110 and the second chip 120 are in the idle state, the access detection pins 114 and 124 will both remain at the first voltage V1, so that the first chip 110 is determined to enter the access state in step S124 (step S130), and the second chip 120 is determined to enter the detection state in step S126 (step S140).
[0048] That is to say, as Figure 3 shown, the first chip 110 will be determined as the master chip, and when the first chip 110 waits in the idle state for more than the predetermined idle time P1 and the first access detection pin 114 continuously remains at the first voltage V1, the first chip 110 will enter the access state. In the access state, the first chip 110 can access the memory 130 through the first interface pin 116, and can fix the voltage of the first access detection pin 114 at the second voltage V2 to indicate that the memory 130 is being occupied.
[0049] In contrast, the second chip 120 is determined to be a slave chip. As Figure 3 shown, in the idle state, when the second access detection pin 124 has been at the first voltage V1 for more than a predetermined idle time P1, the second chip 120 will enter the detection state. In some embodiments, if the first chip 110 is started earlier than the second chip 120, the second chip 120 may detect that the voltage of the second access detection pin 124 changes from the first voltage V1 to the second voltage V2 before the end of the predetermined idle time P1. At this time, the second chip 120 can enter the detection state earlier.
[0050] In Figure 3 , the first chip 110 enters the access state at time point T1 and starts accessing the data in the memory 130. After the first chip 110 enters the access state and exceeds a predetermined access time P2 (step S132), the first chip 110 can determine whether there is still an access operation in progress (step S133). If so, after completing the ongoing access operation, it will enter the detection state (step S134); otherwise, if not, the first chip 110 can directly enter the detection state after step S133. When the first chip 110 enters the detection state, it will stop fixing the voltage of the first access detection pin 114 at the second voltage V2. That is to say, the voltages of the first access detection pin 114 and the second access detection pin 116 will return to the first voltage V1.
[0051] In addition, in some cases, if the first chip 110 exceeds the minimum access time after entering the access state and the first chip 110 has not issued an access instruction to the memory 130 (step S131), it means that the first chip 110 may have an error or does not need to access the memory 130. At this time, the first chip 110 can directly return to the detection state and stop fixing the voltage of the first access detection pin 114 at the second voltage V2, thereby allowing other chips, such as the second chip 120, to access the memory 130.
[0052] Furthermore, in some cases, if the first chip 110 exceeds the maximum access time after entering the access state and the first chip 110 has not stopped fixing the voltage of the first access detection pin 114 at the second voltage V2, it means that the first chip 110 may have an error. At this time, the first chip 110 can be forced to enter the detection state (step S135) and stop fixing the voltage of the first access detection pin 114 at the second voltage V2, thereby allowing other chips, such as the second chip 120, to access the memory 130. In Figure 2BIn this case, steps S131 to S134 can be parallel to step S135. If the first chip has already determined in steps S131, S133, and S134 that it needs to enter the detection state (i.e., enter step S140), then step S135 does not need to be executed anymore, and the calculation of whether the maximum access time is exceeded can be stopped.
[0053] In Figure 3 In this case, the first chip 110 will enter the detection state at time point T2 after exceeding the predetermined access time P2 when entering the access state. The first access detection pin 114 and the second access detection pin 124 will change back from the second voltage V2 to the first voltage V1. According to the conditions of step S144, the second chip 120 will enter the access state to access the memory 130 after the voltage of the second access detection pin 124 changes from the second voltage V2 to the first voltage V1 and exceeds the predetermined buffer time P3, and fix the voltage of the second access detection pin 124 at the second voltage V2.
[0054] Next, when the second chip 120 exceeds the predetermined access time P2 after entering the access state, it can complete the last ongoing access operation (steps S132, S133, and S134) as needed and enter the detection state again, and stop fixing the voltage of the second access detection pin 124 at the second voltage V2. After the first chip 110 detects that the voltage of the first access detection pin 114 changes from the second voltage V2 to the first voltage V1 and exceeds the predetermined buffer time P3, it can enter the access state again to access the memory 130 and fix the voltage of the first access detection pin 114 at the second voltage V2. In this way, the first chip 110 and the second chip 120 can access the memory 130 alternately without conflict.
[0055] In some embodiments, if the first chip 110 detects that the voltage of the first access detection pin 114 changes from the second voltage V2 to the first voltage V1 after exceeding a programming time, such as several seconds, after entering the detection state, it means that the second chip 120 may have performed a programming operation on the memory 130 to write a new execution program during the process of accessing the memory 130. At this time, the first chip 110 can immediately perform a reset operation to update the program that the first chip 110 should execute when detecting that the voltage of the first access detection pin 114 changes from the second voltage V2 to the first voltage V1.
[0056] In addition, in some embodiments, the first chip 110 and the second chip 120 may include one or more timers. The first chip 110 and the second chip 120 can start timing after entering the idle state, access state, and detection state through these timers, so as to determine whether it reaches Figure 2A and Figure 2BThe times of various state transition conditions shown, such as a predetermined idle time P1, a predetermined access time P2, and a predetermined buffer time P3.
[0057] According to Figure 2A and Figure 2B the process shown, method M1 can avoid conflicts between the first chip 110 and the second chip 120 in the electronic device 100 under various conditions.
[0058] Figure 4 is a schematic diagram of an electronic device 200 according to another embodiment of the present application, and Figure 5 is an operation timing diagram of an electronic device 200 according to an embodiment of the present application. In this embodiment, the difference between the electronic device 200 and the electronic device 100 is that the electronic device 200 only includes the first chip 110 and does not include the second chip 120. In this case, as Figure 5 shown, after the first chip 110 enters the access state (step S130), it will still complete the ongoing access operation as needed (steps S132, S133, and S134) after a predetermined access time P2, and enter the detection state at time point T3; however, in the detection state, since there is no other chip in the electronic device 200 that will access the memory 130, the first chip 110 will re-enter the access state (step S130) after the voltage of the access detection pin 114 remains at the first voltage V1 for more than a predetermined detection time P4 (step S142), and access the memory 130 again. In some embodiments, the predetermined buffer time P3 can be much smaller than the predetermined detection time P4. For example, the predetermined buffer time P3 can be several cycles of the clock signal used by the first chip 110 or the second chip 120, and the predetermined detection time P4 can be several microseconds.
[0059] In some embodiments, when it is determined that only the first chip 110 in the electronic device 200 will access the memory 130, the length of the predetermined detection time P4 can be set to be shorter, so that the efficiency of the first chip 110 accessing the memory 130 can be improved.
[0060] Figure 6 is an operation timing diagram of an electronic device 100 according to another embodiment of the present application. In Figure 4In the case where the first chip 110 enters the ultra-low power consumption state (such as the sleep state) after starting and accessing the memory 130, that is, at time point T4, and there is no longer a need to access the memory 130, the second chip 120 will enter the access state from the detection state after a predetermined buffer time P3 when the second access detection pin 124 changes from the second voltage V2 to the first voltage V1. Then, when the second chip 120 has entered the access state for more than the predetermined access time P2 and has completed the access operation, it will return to the detection state. In the case where the first chip 110 has not left the ultra-low power consumption state, the second access detection pin 124 will maintain the first voltage V1, and after the second chip 120 waits for the predetermined detection time P4 in the detection state, it can enter the access state again. However, in Figure 6 In the embodiment, the first chip 110 is just started at time point T5 when the second chip 120 enters the detection state.
[0061] According to Figure 2A the process, when the first chip 110 is started, the first chip 110 will first enter the idle state (step S120) and enter the access state (step S124) only after waiting for the predetermined idle time P1 and confirming that the voltages of the first access detection pins 114 all maintain the first voltage V1. In this embodiment, since the predetermined idle time P1 is greater than the predetermined detection time P4, the second chip 120 will preemptively enter the access state from the detection state at time point T6 after the predetermined detection time P4, and change the voltage of the second access detection pin 124 from the first voltage V1 to the second voltage V2. Correspondingly, the first chip 110 will enter the detection state (step S124), and then the first chip 110 and the second chip 120 can alternately access the memory 130 according to Figure 3 the timing diagram without conflicts.
[0062] Figure 7 is the operation timing diagram of the electronic device 100 according to another embodiment of the present application. In Figure 7 the embodiment, the second chip 120 enters the ultra-low power consumption state during operation and no longer has a need to access the memory 130. Therefore, at time point T7, it leaves the access state and stops fixing the voltage of the second access detection pin 124 at the second voltage V2. In this case, the first chip 110 will change from the detection state to the access state after a predetermined buffer time P3 when the voltage of the first access detection pin 114 changes back from the second voltage V2 to the first voltage V1, start accessing the memory 130, and fix the voltage of the first access detection pin 114 at the second voltage V2. Then, when the first chip 110 has entered the access state for more than the predetermined access time P2 and has completed the access operation, it will return to the detection state and stop fixing the voltage of the first access detection pin 114 at the second voltage V2.
[0063] In Figure 7 the embodiment, the second chip 120 is restarted at time point T8 after the first chip 110 enters the detection state and leaves the ultra-low power consumption state. In this case, according to the Figure 2A process, the second chip 120 can enter the idle state after startup. Since the pending predetermined idle time P1 is greater than the predetermined detection time P4, the first chip 110 will still preemptively enter the access state and fix the voltage of the first access detection pin 114 at the second voltage V2, while the second chip 120 will correspondingly enter the detection state (step S126). Then, the first chip 110 and the second chip 120 can alternately access the memory 130 according to the Figure 3 timing diagram without conflict.
[0064] Figure 8 is the operation timing diagram of the electronic device 100 according to another embodiment of the present application. In Figure 8 this, the first chip 110 is started at time point T9, and the second chip 120 is started at time point T10 after time point T9. In this case, the first chip 110 will preferentially enter the access state from the idle state (step S124), while the second chip 120 will detect that the voltage of the second access detection pin 124 changes from the first voltage V1 to the second voltage V2 in the idle state. Therefore, the second chip 120 will enter the detection state after the first chip 110 enters the access state (step S126). Then, the first chip 110 and the second chip 120 can alternately access the memory 130 according to the Figure 3 timing diagram without conflict.
[0065] Figure 9 is the operation timing diagram of the electronic device 100 according to another embodiment of the present application. Figure 9 In this, the second chip 120 is started at time point T11, and the first chip 110 is started at time point T12 after time point T11. In this embodiment, the gap between time point T11 and time point T12 is exactly equal to the predetermined detection time P4. In this case, after the second chip 120 enters the idle state, it will enter the detection state at time point T13 after waiting for the predetermined idle time P1 and enter the access state at time point T14 after waiting for the predetermined detection time P4 in the detection state (step S142). However, since the first chip 110 is started after the predetermined detection time P4 after the second chip 120 is started, when the first chip 110 waits for the predetermined idle time P1 in the idle state, it will also enter the access state at time point T14 (step S124).
[0066] That is to say, in Figure 9In the embodiments, the first chip 110 and the second chip 120 may enter the access state at the same time at time point T14. To avoid this conflict situation, when the slave chip enters the access state, the electronic device 100 may make the slave chip wait for an additional slave buffer time (e.g., several nanoseconds), and determine that when the enable pin of the memory 130 has not been changed during the slave buffer time, that is, confirm that no other chip accesses the memory 130 during the slave buffer time, then the slave chip will officially start accessing the memory 130.
[0067] For example, the second chip 120 will start waiting for the slave buffer time P5 from time point T14. If the voltage of the enable pin of the memory 130 does not change during the slave buffer time P5, it means that no other chip is accessing the memory 130. At this time, the second chip 120 will pull down the voltage of the enable pin of the memory 130 and start accessing the memory. However, in Figure 9 since the first chip 110 (master chip) will directly start accessing the memory 130 after entering the access state and will pull down the voltage of the enable pin of the memory 130, the second chip 120 will detect that the voltage of the enable pin of the memory 130 has been changed during the slave buffer time P5. Therefore, the second chip 120 will not further access the memory 130 and will change back from the access state to the detection state. In this way, conflicts between the first chip 110 and the second chip 120 during the process of accessing the memory 130 can be avoided.
[0068] In summary, the electronic device and the operation method of the electronic device provided by the embodiments of the present application only need to set master-slave identification pins and access detection pins on the chip and operate according to a specific process, so that two chips can access the same memory alternately without conflict. In this way, the hardware cost and power consumption required by the electronic device can be reduced, and it will not occupy too many pins of the chip.
Claims
1. An electronic device with a shared memory, comprising: A memory; A first chip, comprising: a first master-slave identification pin coupled to a main voltage; a first access detection pin coupled to a first voltage; and a first interface pin coupled to the memory, the first chip being configured to switch between an idle state, a detection state, and an access state based on the voltages of the first master-slave identification pin and the first access detection pin; and A second chip, comprising: a second master-slave identification pin; a second access detection pin coupled to the first access detection pin; and a second interface pin correspondingly coupled to the first interface pin and the memory, the second chip being configured to switch between the idle state, the detection state, and the access state based on the voltages of the second master-slave identification pin and the second access detection pin; Wherein: When the first chip is activated, the first chip enters the idle state; When the first chip waits in the idle state for more than a predetermined idle time and the first access detection pin remains at the first voltage, the first chip enters the access state to access the memory through the first interface pin and fixes the voltage of the first access detection pin at a second voltage; and The first voltage is different from the second voltage.
2. The electronic device according to claim 1, wherein: When more than a predetermined access time has elapsed after the first chip enters the access state and the first chip has completed the ongoing access operation, the first chip enters the detection state and stops fixing the voltage of the first access detection pin at the second voltage.
3. The electronic device according to claim 2, wherein: When more than a predetermined detection time has elapsed after the first chip enters the detection state and the voltage of the first access detection pin remains at the first voltage, the first chip re-enters the access state and fixes the voltage of the first access detection pin at the second voltage; and The predetermined idle time is greater than the predetermined detection time.
4. The electronic device according to claim 2, wherein: When it is detected that the voltage of the first access detection pin changes from the second voltage to the first voltage after the first chip enters the detection state for more than a programming time, the first chip performs a reset operation to update the program executed by the first chip.
5. The electronic device according to claim 1, wherein: The second master-slave identification pin is coupled to a slave voltage different from the main voltage; When the second chip is activated, the second chip enters the idle state; and When the second chip waits in the idle state for more than the predetermined idle time and the second access detection pin is at the first voltage, or when the second chip detects that the voltage of the second access detection pin changes from the first voltage to the second voltage in the idle state, the second chip enters the detection state.
6. The electronic device according to claim 5, wherein: In this detection state, after the voltage of the second access detection pin changes from the second voltage to the first voltage and exceeds a predetermined buffer time, the second chip enters the access state to access the memory, and fixes the voltage of the second access detection pin at the second voltage.
7. The electronic device according to claim 5, wherein: After the second chip enters the access state and exceeds a slave buffer time, and the voltage of the parity enable pin of the memory has not been changed, the second chip starts to access the memory.
8. The electronic device according to claim 1, wherein: After the first chip enters the access state and exceeds a minimum access time, and the first chip has not issued an access instruction to the memory, the first chip enters the detection state and stops fixing the voltage of the first access detection pin at the second voltage.
9. The electronic device according to claim 1, wherein: After the first chip enters the access state and exceeds a maximum access time, the first chip enters the detection state and stops fixing the voltage of the first access detection pin at the second voltage.
10. A method for operating an electronic device to share a memory, the electronic device including a memory, a first chip, and a second chip, the first chip including a first master-slave identification pin coupled to a main voltage, a first access detection pin coupled to a first voltage, and a first interface pin coupled to the memory, the second chip including a second master-slave identification pin, a second access detection pin coupled to the first access detection pin, and a second interface pin correspondingly coupled to the first interface pin and the memory, wherein the method includes: When the first chip is started, causing the first chip to enter an idle state; and When the first chip waits in the idle state for more than a predetermined idle time and the first access detection pin continuously remains at the first voltage: Causing the first chip to enter an access state so that the first chip accesses the memory through the first interface pin; and Fixing the voltage of the first access detection pin at a second voltage; and Wherein the first voltage is different from the second voltage.