Method for calculating timing feedback of circuit, medium, program product and computer equipment

Abstract

The invention relates to the technical field of design and manufacturing of integrated circuits, in particular to a method for calculating circuit time sequence feedback, a medium, a program product and computer equipment. The method comprises the following steps: providing a circuit netlist, and dividing the circuit netlist into a plurality of standard units and paths formed by mutually connecting the standard units; obtaining the initial time sequence total violation duration of all paths in the circuit netlist; acquiring all paths passing through the time sequence end point with violation, acquiring relaxation time corresponding to all the paths, and selecting a key path; performing weight assignment on all the standard units on the key paths based on the relaxation time of each key path, selecting the standard units as key units to modify all the key units based on a weight assignment result, and obtaining delay change of each key unit before and after modification; and obtaining time sequence feedback by combining the sum of the delay changes of each key unit with the local total violation duration. The problem of long time consumed for calculating time sequence feedback in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and particularly to a method, medium, program product and computer device for calculating timing feedback of a computing circuit. Background Art

[0002] In order to shorten the chip R & D cycle and design a chip with better performance, more and more researchers have begun to try to introduce machine learning methods into existing EDA tools. By learning existing design data through machine learning methods, the number of iterative optimizations can be effectively reduced, thereby accelerating the design cycle and improving the quality of EDA tools and design results. This approach of introducing machine learning methods can not only cope with the complexity and challenges of chip design, but also accelerate innovation and promote the development of chip technology.

[0003] Total Negative Slack (TNS) is an important indicator for measuring the timing convergence of integrated circuits. In the process of using machine learning to assist in the timing convergence of chip design, it is necessary to continuously modify the units in the circuit (mainly referring to the components in the circuit), and when performing model training, it is necessary to provide the timing feedback after modifying the netlist, that is, it is necessary to obtain the change value of the total negative slack value after modification.

[0004] The existing method for calculating timing feedback is to complete the calculation step of the total negative slack value before making changes to the path, that is, to calculate the slack time of all paths passing through each timing endpoint once. In fact, some paths are violated and some paths are not violated. Summing up the slack times of the violated paths can obtain the initial total negative slack value. Then, start to modify the paths with violations. During each modification process, it is necessary to repeat the calculation of the slack time of all paths passing through each timing endpoint again, and sum up the slack times of the violated paths to obtain the total negative slack value after modification. Subtracting the total negative slack value after modification from the initial total negative slack value can obtain the change value of the total negative slack value. However, the existing method requires recalculating the total negative slack value every time a change is made to the circuit, and the time consumed for calculating the timing feedback will be very long. Summary of the Invention

[0005] In order to solve the problem of long time consumption for calculating timing feedback in the existing method, the present invention provides a method, medium, program product and computer device for calculating timing feedback of a computing circuit.

[0006] To solve the above technical problems, the present invention provides the following technical solution: A method for calculating circuit timing feedback, which is used to quickly obtain the timing feedback when the netlist in the circuit is modified. The method includes the following steps: providing a circuit netlist, obtaining the path diagram of the circuit netlist, where the path diagram is a path formed by the connection of several standard cells; obtaining the initial total timing violation duration of all paths in the circuit netlist; obtaining the violation paths and the corresponding timing endpoints based on the path diagram, and selecting the path with the worst slack time among the violation paths as the critical path corresponding to its corresponding timing endpoint; some standard cells will appear on multiple critical paths, assigning weights to all standard cells on the critical paths based on the slack time of each critical path, and selecting standard cells as critical cells based on the result of the weight assignment; modifying all critical cells, obtaining the delay changes of each critical cell before and after the modification; summing up the delay changes of each critical cell to obtain the local total violation duration; obtaining the timing feedback based on the initial total timing violation duration and the local total violation duration.

[0007] Preferably, obtaining the initial total timing violation duration of all paths in the circuit netlist includes: obtaining the connection relationship and timing characteristics of all standard cells in the circuit netlist; where the timing characteristics include: when the standard cells are not modified, the delays of all standard cells and the slack times of all paths.

[0008] Preferably, obtaining the violation paths and the corresponding timing endpoints based on the path diagram includes: one or more than two paths share a timing endpoint; obtaining the positions of the timing endpoints in the circuit netlist; obtaining the slack times of all paths passing through a certain timing endpoint; determining whether there are negative numbers among the slack times of all paths passing through this timing endpoint; if so, it indicates that there are violation paths in this timing endpoint.

[0009] Preferably, selecting the path with the worst slack time among the violation paths as the critical path corresponding to its corresponding timing endpoint includes: if there are violation paths passing through a certain timing endpoint; sorting the slack times of all paths passing through this timing endpoint in ascending order, where the slack time includes zero, positive numbers, and negative numbers; selecting the path corresponding to the smallest sorted slack time as the path with the worst slack time.

[0010] Preferably, assigning weights to all standard cells on the critical paths includes: obtaining the slack time of the critical path; assigning weights to all standard cells on the critical path based on the value of the slack time of the critical path; if only one critical path passes through a certain standard cell, the weight value on this standard cell is the slack time value of the critical path passing through this standard cell; if two or more critical paths pass through the same standard cell, the weight value on this standard cell is the sum of the slack time values of all critical paths passing through this standard cell.

[0011] Preferably, selecting a standard cell as a critical cell further includes: the standard cell includes an input terminal and an output terminal; if the output terminal of a certain standard cell is connected to the input terminals of two or more critical cells, then the two or more critical cells are critical cells with overlapping timing; if there are overlapping critical cells in the circuit netlist, randomly select a standard cell within the critical cells with overlapping timing as the critical cell.

[0012] Preferably, obtaining the delay change of each critical cell before and after modification includes: obtaining the reference pin and scoring pin of the critical cell; modifying the critical cell, and recording the timing path delay of each pair of reference pin and scoring pin after modification; obtaining the delay change of the critical cell based on the timing path delay.

[0013] Preferably, obtaining the local total violation duration includes: Calculating ; Wherein, is the local total violation duration, is the critical cell; is the critical timing path passing through the critical cell; is the critical timing path 's slack time, is the change in the assumed arrival time.

[0014] Preferably, obtaining the timing feedback further includes: after modifying the critical cell, judging whether there is a path violation in the circuit netlist based on the local total violation duration; obtaining the new path diagram of the circuit netlist; iterating the process of selecting the standard cell as the critical cell based on the new path diagram, and selecting the emerging critical cells; modifying the new critical cells until the timing feedback is eliminated.

[0015] To solve the above technical problems, the present invention provides another technical solution as follows: a computer-readable storage medium, wherein computer instructions are stored in the computer-readable storage medium, and the computer instructions are used to cause the computer to execute the method for calculating the circuit timing feedback according to the above.

[0016] To solve the above technical problems, the present invention provides another technical solution as follows: a computer device, applied to the method for calculating the circuit timing feedback as described above, includes a memory, a processor, and a computer program stored on the memory, and the processor executes the above computer program to implement the method for calculating the circuit timing feedback.

[0017] To solve the above technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program or instruction, and the computer program or instruction implements the method for calculating the circuit timing feedback when executed by a processor.

[0018] Compared with the prior art, a method, medium, program product, and computer device for calculating circuit timing feedback provided by the present invention have the following beneficial effects: 1. A method for calculating circuit timing feedback provided by an embodiment of the present invention is used to quickly obtain timing feedback when the netlist in a circuit is modified. The method includes the following steps: providing a circuit netlist, obtaining a path graph of the circuit netlist, where the path graph is a path formed by the connection of several standard cells; obtaining the initial total timing violation duration of all paths in the circuit netlist; obtaining the violation paths and the corresponding timing endpoints of the violation paths based on the path graph, and selecting the path with the worst slack time in the violation paths as the critical path corresponding to its corresponding timing endpoint; some standard cells will appear on multiple critical paths, assigning weights to all standard cells on the critical paths based on the slack time of each critical path, and selecting standard cells as critical cells based on the result of the weight assignment; modifying all critical cells, obtaining the delay changes of each critical cell before and after the modification; summing the delay changes of each critical cell to obtain the local total violation duration; obtaining timing feedback based on the initial total timing violation duration and the local total violation duration.

[0019] In this embodiment, by specifically selecting the critical paths, then assigning weights to the standard cells on the critical paths, and selecting critical cells based on the result of the weight assignment, modifying the critical cells and obtaining the delay changes before and after the modification, aggregating the local delay changes to calculate the local total violation duration, thereby eliminating the need to calculate the delay of the entire path, concentrating the computing resources on a very small part of the circuit that truly affects the total violation value of the timing slack time, so as to shorten the calculation time of the timing feedback and improve the calculation efficiency of the timing feedback.

[0020] 2. Obtaining the initial total timing violation duration of all paths in the circuit netlist in an embodiment of the present invention includes: obtaining the connection relationship and timing characteristics of all standard cells in the circuit netlist; where the timing characteristics include: when the standard cells are not modified, the delays of all standard cells and the slack times of all paths. Obtaining the delay of each standard cell when calculating the initial total timing violation duration is convenient for calculating the delay changes of each critical cell before and after the modification later.

[0021] 3. An embodiment of the present invention also provides a computer-readable storage medium, which has the same beneficial effects as the above-mentioned method for calculating circuit timing feedback, and will not be elaborated here.

[0022] 4. An embodiment of the present invention also provides a computer device, which has the same beneficial effects as the above-mentioned method for calculating circuit timing feedback, and will not be elaborated here.

[0023] 5. A computer program product provided by an embodiment of the present invention includes a computer program or instruction, and when the computer program or instruction is executed by a processor, the method for timing feedback of the above-mentioned computing circuit is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a schematic flowchart of the method for timing feedback of a computing circuit provided by the first embodiment of the present invention.

[0026] Figure 2 It is a simplified diagram of a path diagram in the method for timing feedback of a computing circuit provided by the first embodiment of the present invention Figure 1 。

[0027] Figure 3a It is a simplified diagram of a path diagram in the method for timing feedback of a computing circuit provided by the first embodiment of the present invention Figure 1 。

[0028] Figure 3b It is for Figure 3a a schematic diagram after weight assignment to the critical path in the path diagram Figure 4 It is a simplified diagram of a path diagram in the method for timing feedback of a computing circuit provided by the first embodiment of the present invention Figure 2 。

[0029] Figure 5a It is a schematic diagram of overlapping critical units in the method for timing feedback of a computing circuit provided by the first embodiment of the present invention.

[0030] Figure 5b It is for Figure 5a modifying the critical units in

[0031] Figure 6 It is a comparison chart of calculation accuracy results.

[0032] Figure 7 It is a schematic structural diagram of a computer-readable storage medium provided by the second embodiment of the present invention.

[0033] Figure 8 It is a schematic structural diagram of a computer device provided by the third embodiment of the present invention.

[0034] Figure 9It is a schematic structural diagram of a computer program product provided by the fourth embodiment of the present invention. Detailed implementation manners

[0035] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0036] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0037] It should be understood that throughout the specification, "an embodiment" or "one embodiment" means that a specific feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of "in an embodiment" or "in one embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0038] In various embodiments of the present invention, it should be understood that the order numbers of the above processes do not necessarily mean the inevitable sequence of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0039] In the flowcharts and block diagrams in the drawings of the present invention, the possible architectures, functions and operations of systems, methods and computer program products according to various embodiments of the present application are illustrated. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, the program segment, or the part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementation solutions, the functions marked in the blocks may also occur in a different order from that marked in the drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, which is determined based on the functions involved. It should be particularly noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0040] The design of high-performance chips relies on the support of efficient and high-quality EDA tools. Considering the complexity of chip systems, existing EDA tools divide the chip design process into steps such as logic synthesis, placement and planning, clock tree synthesis, and placement and routing, simplifying the complexity of chip design by establishing a standard process. Since the connection between the optimization goals in the early stages and the power consumption and performance goals of the final chip is relatively weak, it is often difficult to achieve the power consumption and performance goals (PPA) of the chip by executing the standard process only once. To design and manufacture compliant chips, multiple iterative adjustments are required, which not only increases the R & D cycle but also the workload and cost. Therefore, more innovative and efficient methods are needed to improve the quality and efficiency of the chip design process in order to better meet market demands and shorten the time to market.

[0041] To shorten the chip R & D cycle and design chips with better performance, more and more researchers have started to introduce machine learning methods into existing EDA tools. By learning existing design data through machine learning methods, the number of iterative optimizations can be effectively reduced, thereby accelerating the design cycle and improving the quality of EDA tools and design results. This approach of introducing machine learning methods can not only handle the complexity and challenges of chip design but also accelerate innovation and drive the development of chip technology.

[0042] Integrated circuits usually have multiple start and end points. Signals start from timing origins (such as clock edges or input ports), pass through the cells and interconnect wiring in the circuit, and finally reach the timing destinations. During the process of a path from the start point to the end point, there is an arrival time and a slack time. If the arrival is later than expected, it indicates that the path is violated.

[0043] Total Negative Slack (TNS) is an important indicator for measuring the timing convergence of integrated circuits. The total timing slack violation value can be obtained by summing up the slack times corresponding to all violated paths in the integrated circuit. During the process of using machine learning to assist in chip design timing convergence, the cells in the circuit (mainly referring to the components in the circuit) need to be continuously modified, and when performing model training, timing feedback after modifying the netlist is required, that is, the change value of the total timing slack violation value after modification needs to be obtained.

[0044] The existing method for calculating timing feedback is to calculate the total timing slack total violation value before making changes to the path, that is, calculate the slack time of all paths passing through each timing endpoint once. In fact, some paths are violated and some are not. Summing up the slack times of the violated paths can obtain the initial total timing slack total violation value. It should be noted that usually when observing timing feedback, it is necessary to calculate the total timing slack total violation value once first, so as to compare it with the total timing slack total violation value after the change.

[0045] Then start to modify the paths with violations. During each modification process, it is necessary to repeat the calculation of the slack time of all paths passing through each timing endpoint again, and sum up the slack times of the violated paths to obtain the total timing slack total violation value after the change. Subtracting the total timing slack total violation value after the change from the initial total timing slack total violation value can obtain the change value of the total timing slack total violation value. However, the existing method needs to recalculate the total timing slack total violation value every time the circuit is modified, and the time consumed for calculating timing feedback will be very long.

[0046] Path delay: It is the total time of signal transmission, composed of cell and interconnect delays. Cell delay is the time of internal logic conversion of a standard cell, such as the delay of an AND gate from input change to output stability. Interconnect delay is the transmission time of a signal through wiring (metal layers and vias).

[0047] Arrival time: It is the maximum value of the path delay PD in all timing paths passing through the driving pin of the current standard cell.

[0048] Slack time: It is the difference between the timing requirement time and the actual arrival time, which directly determines the timing convergence state. The timing requirement time is the latest time when the signal must be stable at the endpoint.

[0049] To solve the above technical problems, please refer to Figure 1 , the first embodiment of the present invention provides a method for calculating circuit timing feedback, which is used to quickly obtain the timing feedback when the netlist in the circuit is modified. The above method includes the following steps: S1. Provide a circuit netlist, and obtain the path diagram of the circuit netlist. The path diagram is a path formed by the connection of several standard cells; S2. Obtain the initial total timing violation duration of all paths in the circuit netlist; S3. Based on the path diagram, obtain the violated paths and the corresponding timing endpoints of the violated paths, and select the path with the worst slack time among the violated paths as the critical path of its corresponding timing endpoint; S4. Some standard cells will appear on multiple critical paths. Based on the slack time of each critical path, weight values are assigned to all standard cells on the critical path, and standard cells are selected as critical cells based on the results of the weight assignment; S5. Modify all critical cells and obtain the delay changes of each critical cell before and after the modification; S6. Sum up the delay changes of each critical cell to obtain the local total violation duration; S7. Obtain the timing feedback based on the initial total timing violation duration and the local total violation duration.

[0050] Understandably, in this embodiment, the standard cell is a basic functional module in integrated circuit design, including basic logic units such as AND gate, OR gate, NOT gate, XOR gate, etc. It also includes complex functional units such as Flip-Flop, Latch, Adder, MUX, etc. It also includes special-purpose units such as Buffer, Level Shifter, Clock Gating Cell, etc. The path in this embodiment refers to the complete transmission path of a signal from the starting point to the ending point. The path includes the standard cells passed by the signal and physical structures such as metal lines (Metal Layer) and vias (Via) connecting these standard cells. The circuit netlist in this embodiment is composed of multiple paths.

[0051] Specifically, in order to quickly calculate the timing feedback, step S1 first obtains the circuit netlist. The path graph takes standard cells as nodes and the wiring connecting standard cells as edges to form a topological network. By automatically generating the path graph of the circuit netlist, the complex circuit connection relationship is transformed into an intuitive path structure, significantly improving the recognition efficiency of critical paths. Further, step S2 obtains the initial total timing violation duration of all paths. The initial total timing violation duration refers to the total violation value of the timing slack time when the circuit netlist has not been modified. It should be noted that the initial total timing violation duration can be calculated using existing technologies, which is simple and direct. By calculating the total violation value of the initial timing slack time, a reference value is provided for subsequent modification and optimization, avoiding repeated full-scale calculations after each modification. The purpose of step S3 is to screen out violation paths and select critical paths.

[0052] It should be understood that each path in the path graph starts from a starting point, passes through the standard cells in the circuit, and then reaches the timing ending point. There are multiple timing ending points in the path graph, and one path or at least two paths will pass through a timing ending point. As Figure 2 shown, Figure 2There is only one path 2L1 passing through the middle timing endpoint 2D1. And there are two paths 2L2 and 2L3 passing through the timing endpoint 2D2. The rectangular boxes on the paths represent standard cells, and the lines connecting the standard cells represent wiring. It should be understood that each path has an arrival time and a slack time. Generally, the slack time can measure whether a path is violated. If the slack time is negative, it indicates that the signal cannot reach the endpoint at the required time after passing through the path, which means that the path is violated. In step S3, first find all the violated paths and the corresponding timing endpoints of the violated paths. And a timing endpoint may be the endpoint of multiple violated paths. When selecting the critical path, select the path with the worst slack time among the violated paths as its critical path. It should be understood that the worst slack time means the smallest value of the slack time, that is, the actual arrival time of the signal is much longer than the required time, and the flow rate of the signal far cannot meet the designer's expectation. Exemplarily, Figure 2 Both 2L2 and 2L3 pass through the same timing endpoint 2D2, and both 2L2 and 2L3 are violated. The timing time of 2L2 is -1s, and the timing time of 2L3 is -2s. Since the slack time of 2L3 is smaller, 2L3 is the critical path. Therefore, usually the critical path of a timing endpoint is usually the path that has the greatest impact on the timing endpoint. It should be understood that in this embodiment, by focusing on the path with the most serious violation on the timing endpoint, precise optimization is carried out to avoid waste of resources.

[0053] Furthermore, in step S4, the standard cells are assigned values based on the slack time and the critical cells are selected. It should be understood that the critical path mainly includes standard cells and the wiring connecting the standard cells. The prior art usually first confirms the violated path and then modifies the cells on the violated path. That is, the modification of the prior art is not targeted, which also leads to the fact that the prior art often needs to consume a large amount of computing time when calculating the timing feedback. And in this embodiment, the standard cells are weighted based on the slack time of the critical path.

[0054] Exemplarily, such as Figure 3aAs shown, for the timing endpoint 3D1, the slack time of path 3L11 is -1 s, the slack time of path 3L12 is -2 s, and the slack time of path 3L13 is -3 s. That is, path 3L13 is the critical path. For the timing endpoint 3D2, the slack time of path 3L21 is -2 s. For the timing endpoint 3D3, the slack time of path 3L31 is -2 s, and the slack time of path 3L32 is -1 s. That is, path 3L31 is the critical path. When assigning values to standard cells, the values can be directly assigned according to the slack time. For example, the 3 standard cells passed by path 3L13 are all assigned -3 s, the 3 standard cells passed by path 3L21 are all assigned -2 s, and the 3 standard cells passed by path 3L32 are all assigned -2 s. In the path graph, some standard cells often appear on multiple critical paths. At this time, the weights of these standard cells will be automatically superimposed during the assignment. For example, standard cells 3C1 and 3C2 pass through three critical paths at the same time, and weight superimposition is required during the assignment process. Figure 3a The final weight assignment result is as Figure 3b shown. It can be seen that the weight values of standard cells 3C1 and 3C2 are the smallest. Therefore, both standard cells 3C1 and 3C2 are critical cells. It should be noted that Figure 3b the unit of the numbers within the rectangular box is seconds.

[0055] It should be understood that critical cells represent the cells with the greatest influence on the critical path. And in subsequent modifications, critical cells are also preferentially modified. In this embodiment, by quantifying the global influence weight of standard cells, it is ensured that each modification operation can maximize the improvement of the total violation value of the timing slack time. In addition, the targeted selection of standard cells greatly shortens the time for calculating the timing feedback.

[0056] Furthermore, in steps S5, S6, and S7, the critical cells are modified, the delay changes are recorded, and the local total violation value of the timing slack time is calculated by aggregating the delay changes. In the prior art, after each modification, the delay of the entire path needs to be obtained and then the total violation value of the timing slack time is statistically obtained. In this embodiment, since the critical cells are specifically selected, only the critical cells need to be modified during the modification. Therefore, only the delay changes before and after the modification of the critical cells are recorded, and the sum of the delay changes of each critical cell can be used to obtain the local total violation duration. That is, it avoids the global path traversal to calculate the delay as in the prior art, but innovatively aggregates the delays before and after the modified critical cells to obtain the local total violation duration, achieving a significant improvement in calculation efficiency.

[0057] Further, timing feedback can be obtained based on the initial total timing violation duration and the local total violation duration. It should be understood that the timing feedback is the benefit brought by directly modifying the cells in the circuit netlist. For example, if the value of the timing feedback is less than 0, it means that the modification reduces the timing violation, while if the value of the timing feedback is greater than 0, it means that the modification increases the timing violation. That is, the timing feedback is a quantitative index of the optimization effect of modifying the cells. Additionally, in this embodiment, Figure 6 shows a comparison of the accuracy of calculating the local total violation duration obtained by using the method of this embodiment and the method of calculating the total violation duration using the prior art. It can be seen that most of the results calculated based on the method proposed in this embodiment are consistent with the prior methods, and there are a small number of calculation deviations.

[0058] It can be understood that to solve the problem of the long time-consuming calculation of timing feedback in the prior art, in this embodiment, the critical paths are specifically selected, then weight values are assigned to the standard cells on the critical paths, and based on the results of the weight assignment, the critical cells are selected. The critical cells are modified and the delay changes before and after the modification are obtained, and the local delay changes are aggregated to calculate the local total violation duration. Furthermore, there is no need to calculate the delay of the entire path. By concentrating the computing resources on a very small part of the circuit that truly affects the total violation value of the timing slack time, this embodiment shortens the calculation time of the timing feedback and improves the calculation efficiency of the timing feedback.

[0059] It should be noted that in step S1, when obtaining the path graph of the circuit netlist, the delay and slack time of all paths can be marked on the path graph by using the graph traversal algorithm, which is intuitive and concise.

[0060] Further, in step S2, obtaining the initial total timing violation duration of all paths in the circuit netlist includes: Obtaining the connection relationship and timing characteristics of all standard cells in the circuit netlist; Among them, the timing characteristics include: when the standard cells are not modified, the delay of all standard cells and the slack time of all paths. It can be understood that the connection relationship of the standard cells is the wiring in the path. The timing characteristics of the standard cells in this embodiment are the delay passing through the standard cells and the slack time passing through the standard cells before the standard cells in the circuit netlist are not modified. It should be understood that when calculating the initial total timing violation duration, the delay of each standard cell is obtained together, which is convenient for calculating the delay changes of each critical cell before and after the modification later.

[0061] Specifically, the initial total timing violation duration, that is, the initial total violation value of the timing slack time, can be calculated by the following formula:

[0062] Among them, sink is a standard cell; path is a critical timing path passing through the standard cell sink, and s is the slack time of the timing path path.

[0063] It should be understood that the existing technology can be used to calculate the initial total timing violation duration, and its purpose is to provide a benchmark value for subsequent modification and optimization, avoiding repeated full-scale calculations after each modification.

[0064] Further, in step S3, obtaining the violation path and the corresponding timing end point based on the path diagram includes: One or more than two paths share a timing end point; Obtain the position of the timing end point in the circuit netlist; Obtain the slack time of all paths passing through a certain timing end point; Judge whether there is a negative number in the slack time of all paths passing through this timing end point; If there is, it indicates that there is a violation path in this timing end point.

[0065] It can be understood that the path diagram can visually obtain the position of the timing end point and all paths passing through this timing end point. When judging whether a path is a violation, a signal can be directly sent at the starting point and then monitored at the timing end point. If the slack time for the signal to reach the end point from the starting point is negative, it indicates that there must be a violation path in this timing end point. At this time, only the violation path and the corresponding timing end point need to be marked to initially confirm which paths need to be modified and optimized.

[0066] Further, in step S3, selecting the path with the worst slack time among the violation paths as the critical path corresponding to its corresponding timing end point includes: If there is a violation path passing through a certain timing end point; Sort the slack times of all paths passing through this timing end point in ascending order, where the slack time includes zero, positive numbers, and negative numbers; Select the path corresponding to the smallest sorted slack time as the path with the worst slack time.

[0067] It should be understood that the traditional method lacks selectivity in the selection of critical paths, resulting in chaotic allocation of computing resources and low computing efficiency. In this embodiment, through the slack time sorting mechanism, it is ensured that the optimization operation is preferentially targeted at the most serious violation paths. The paths are arranged in ascending order of slack time, and the paths with the smallest (i.e., the worst) slack time are processed first. Exemplarily, please refer to Figure 4 , Figure 4Among 4L1, 4L2, 4L3, 4L4, and 4L5, they pass through the same timing end point 4D1. The timing time of 4L1 is -1s, the timing time of 4L2 is -2s, the timing time of 4L3 is -3s, the timing time of 4L4 is 4s, and the timing time of 4L5 is 5s. Since 4L1, 4L2, and 4L3 all violate the rules and pass through the timing end point 4D1, after sorting all the paths passing through the timing end point 4D1, the slack times from largest to smallest are 5s, 4s, -1s, -2s, -3s in turn. -3s is the smallest sorted slack time, so 4L3 is the critical path. It should be noted that when sorting the slack times in order of size, it can be from largest to smallest or from smallest to largest. In addition, after each modification in this embodiment, the path slack time will be re-evaluated to ensure that the critical path list is updated in real time.

[0068] Further, in step S4, the weight assignment to all standard cells on the critical path includes: Obtain the slack time of the critical path; Based on the value of the slack time of the critical path, assign weights to all standard cells on the critical path; If only one critical path passes through a certain standard cell, the weight value on this standard cell is the slack time value of the critical path passing through this standard cell; If two or more critical paths pass through the same standard cell, the weight value on this standard cell is the sum of the slack time values of all critical paths passing through this standard cell.

[0069] It can be understood that when a standard cell passes through multiple critical paths at the same time, it means that this standard cell has a greater impact on the critical paths that violate the rules. If this standard cell is modified, the contribution to modifying the violation will be very large. Calculating the circuit timing feedback has two functions. One is to complete the modification of the circuit netlist as soon as possible so that the violations in the circuit netlist can be eliminated as soon as possible. The other function is to intuitively observe the contribution degree to eliminating violations after each modification. In this embodiment, weight assignment is based on the slack time, which accurately quantifies the contribution degree of standard cells to the violations in the circuit net diagram. Especially for standard cells passed through by multiple critical paths, their influence on the violation contribution degree of the circuit net diagram is relatively large. In this embodiment, for such situations, weights are assigned by the cumulative method, which can quickly locate the key positions to modify the key cells.

[0070] Further, selecting a standard cell as a key cell also includes: A standard cell includes an input end and an output end; If the output end of a certain standard cell is connected to the input ends of two or more key cells, then the two or more key cells are key cells with overlapping timing; If there are overlapping critical cells in the circuit network diagram, randomly select a standard cell within the critical cells with overlapping timing as the critical cell.

[0071] In a possible implementation, the input terminals of two or more critical cells may be connected to the output terminal of the same standard cell. At this time, these critical cells will affect each other. If they are modified simultaneously, it will cause a large modification error. Exemplarily, please refer to Figure 5a , the input terminals of critical cells 5C3 and 5C4 are both connected to the output terminal of critical cell 5C1, and the input terminals of critical cells 5C4 and 5C5 are both connected to the output terminal of critical cell 5C2. In Figure 5, critical cells 5C3 and 5C4 are critical cells with overlapping timing, and critical cells 5C4 and 5C5 are also critical cells with overlapping timing. When selecting critical cells for modification, if critical cells 5C3 and 5C4 or critical cells 5C4 and 5C5 are modified simultaneously, it will cause a relatively large violation modification error, and ultimately the violations of the two critical cells cannot be eliminated. The usual approach is to first ensure that one critical cell eliminates the violation, and then modify the other. Therefore, in this embodiment, if there are overlapping critical cells in the circuit network diagram, randomly select a standard cell within the critical cells with overlapping timing as the critical cell. As Figure 5a shown, if critical cells 5C3 and 5C4 are modified separately, only one of them needs to be randomly selected. However, critical cells 5C4 and 5C5 are also critical cells with overlapping timing. Therefore, for the situation in Figure 5, directly modify critical cell 5C4 first, which can avoid the violation modification error caused by critical cells 5C3 and 5C5 at the same time. After critical cell 5C4 is modified to eliminate the violation or become a standard cell, at this time, critical cells 5C3 and 5C5 are not critical cells with overlapping timing, and then critical cells 5C3 and 5C5 can be modified simultaneously.

[0072] It should be noted that when modifying the critical cell in this embodiment, the wiring near the connected critical cell can also be modified. As Figure 5b shown, when modifying critical cell 5C4, the wiring in the dotted part can also be modified. The critical cell described in this embodiment can refer to a circuit element or all the elements within a region, and no more details will be elaborated here.

[0073] Furthermore, in the above step S5, obtaining the delay change of each critical cell before and after modification includes: Obtain the reference pin and scoring pin of the critical cell; Modify the critical cell, and record the timing path delay of each pair of reference pins and scoring pins after modification; Obtain the delay change of the critical cell based on the timing path delay.

[0074] Understandably, the reference pin is the starting point of signal transmission in a standard cell, usually the input pin of the standard cell or the output pin driving the signal. Its function is to identify the position where the signal enters the current standard cell and serve as the starting point for timing path analysis. The scoring pin is the end point of signal transmission in the standard cell, usually the output pin of the standard cell or the downstream node where the signal is transmitted. Its function is to identify the position where the signal leaves the current cell and serve as the termination point for timing path analysis. It should be understood that in this embodiment, high-precision local impact assessment is achieved by directly measuring the pin-level delay changes before and after modifying the critical cell. By only recording the timing path delay changes of the critical pin pairs and ignoring the non-critical paths, the time for calculating the timing feedback can be significantly shortened.

[0075] Furthermore, obtaining the local total violation duration includes: When calculating the total violation value of the timing slack time, if only considering the timing end points affected by the local delay change, it is calculated using Formula 1: Formula 1:

[0076] In Formula 1, is the critical cell; is the critical timing path passing through the critical cell; is the slack time of the critical timing path . If you want to obtain the delay change of the critical cell before and after modification. Then you can introduce , is the change in the assumed arrival time, a known value set by the designer, then the total violation value of the modified timing slack time can be calculated using Formula 2: Formula 2:

[0077] In Formula 2, is the local total violation duration, is the critical cell; is the critical timing path passing through the critical cell; is the slack time of the critical timing path , is the change in the assumed arrival time.

[0078] Furthermore, after obtaining the local total violation duration, the timing feedback can be calculated in combination with the initial total violation duration of the timing. The timing feedback can be calculated using Formula 3: Formula 3:

[0079] In Formula 2, It is timing feedback. In this embodiment, the calculation of the local total violation duration depends on: the path delay variation passing through the critical cell and the sorting sequence of the critical path slack time passing through the critical cell. It should be understood that this embodiment is implemented through a localized formula, and the local total violation duration is used to replace the total violation duration obtained by calculating all paths in the prior art. It has the advantages of fast calculation speed and short calculation time consumption.

[0080] After the above step S7, obtaining the timing feedback further includes: After modifying the critical cell, based on the local total violation duration, determine whether there is a path violation in the circuit netlist; Obtain a new path graph of the circuit netlist; Based on the new path graph, iterate the process of selecting the standard cell as the critical cell above, and select a new critical cell; Modify the new critical cell until the timing feedback is eliminated.

[0081] It should be understood that the designer needs to continuously modify the standard cells in these violated paths until the path delay is eliminated and the slack time of the path meets the expectation. After each modification, the paths passing through the same timing endpoint will be optimized, and the corresponding slack time of the path will also change. However, one modification cannot guarantee that the violation will be completely eliminated. Although the slack time will approach the required time to some extent, another path passing through the same timing endpoint may become the new critical path. Therefore, when selecting a new critical cell, the steps of S3 - S4 need to be iterated. After modifying the new critical cell, the timing feedback can be quickly obtained based on the methods of steps S5 - S7, and so on in a loop until the timing feedback in the circuit net graph is eliminated, that is, the violation in the circuit net graph is eliminated. Exemplarily, please continue to refer to Figure 2 , assuming that after one modification, the timing time of 2L2 is -1s and the timing time of 2L3 is -0.5s for 2L2 and 2L3, then for the timing endpoint 2D2, 2L2 becomes the new critical path.

[0082] To further illustrate the technical effects of the method in this embodiment. Now, the following steps are adopted for effect comparison.

[0083] Step 1: Each time, only select one standard cell. After modifying the cell size, use the prior art global timing update to calculate the timing feedback.

[0084] Step 2: Each time, only select one standard cell. After modifying the cell size, calculate the timing feedback through the method proposed by the present invention.

[0085] Step 3: Each time, select ten standard cells. After modifying the cell size, calculate the timing feedback through the method proposed by the present invention.

[0086] Table 1: Comparison Table of Running Time

[0087] It can be seen that taking the calculation method of the existing technology as the standard, both the single running time and the time consumed when modifying the standard cell 100 times can be greatly reduced. Exemplarily, when the existing technology modifies the standard cell 100 times, the time consumed for calculating the timing feedback is 5213 s. While the time consumed for calculating the timing feedback by using the method proposed in this embodiment is 1023 s. The method provided in this embodiment significantly reduces the time consumed for calculating the timing feedback and can improve the efficiency by more than 30 times.

[0088] To further illustrate the calculation accuracy of the method in this embodiment.

[0089] Please refer to Figure 6 , Figure 6 which is a comparison chart of calculation accuracy results. The blue balls represent modifying one standard cell selected from Table 1, while the green balls represent modifying 10 standard cells selected from Table 1. The abscissa is the accurate total slack time violation, and the ordinate is the estimated total slack time violation. If the landing point of the ball is on the line x = y, it means the model prediction is accurate. From the illustrated results, it can be seen that the difference in calculation accuracy deteriorates slightly, but the change is small.

[0090] The second embodiment of this embodiment also provides a computer-readable storage medium, wherein computer instructions are stored in the computer-readable storage medium, and the computer instructions are used to make the computer execute the method for calculating the timing feedback of the circuit according to the above.

[0091] The computer-readable storage medium provided by the embodiment of the present invention has the same beneficial effects as the above method for calculating the timing feedback of a circuit, and will not be elaborated here.

[0092] The third embodiment of this embodiment also provides a computer device applied to the above method for calculating the timing feedback of a circuit, including a memory, a processor, and a computer program stored on the memory. The processor executes the above computer program to implement the method for calculating the timing feedback of the circuit.

[0093] The computer device provided by the embodiment of the present invention has the same beneficial effects as the above method for calculating the timing feedback of a circuit, and will not be elaborated here.

[0094] The fourth embodiment of this embodiment also provides a computer program product, including a computer program or instructions, and the computer program or instructions implement the above method for calculating the timing feedback of a circuit when executed by a processor.

[0095] The computer program product provided by the embodiments of the present invention has the same beneficial effects as the above-mentioned method for calculating circuit timing feedback, which will not be elaborated here.

[0096] The above has introduced in detail a method, medium, program product, and computer device for calculating circuit timing feedback disclosed in the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent replacements, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for calculating circuit timing feedback, which is used to quickly obtain the timing feedback when the netlist in the circuit is modified, characterized in that, The method includes the following steps: Provide a circuit netlist, obtain a path graph of the circuit netlist, where the path graph is a path formed by the connection of a number of standard cells; Obtain the initial total timing violation duration of all paths in the circuit netlist; Based on the path graph, obtain the violation paths and the corresponding timing endpoints of the violation paths, and select the path with the worst slack time among the violation paths as the critical path corresponding to its corresponding timing endpoint; Some standard cells will appear on multiple critical paths. Based on the slack time of each critical path, assign weights to all standard cells on the critical paths, and select a standard cell as a critical cell based on the result of the weight assignment; Modify all critical cells, and obtain the delay change of each critical cell before and after the modification; Sum up the delay changes of each critical cell to obtain the local total violation duration; Obtain timing feedback based on the initial total timing violation duration and the local total violation duration.

2. The method for calculating the timing feedback of a computing circuit according to claim 1, wherein: Obtaining the initial total timing violation duration of all paths in the circuit netlist includes: Obtain the connection relationship and timing characteristics of all standard cells in the circuit netlist; Among them, the timing characteristics include: when the standard cells are not modified, the delays of all standard cells and the slack times of all paths.

3. The method for calculating the timing feedback of a computing circuit according to claim 1, wherein: Based on the path graph, obtaining the violation paths and the corresponding timing endpoints of the violation paths includes: One or two or more paths share a timing endpoint; Obtain the position of the timing endpoint in the circuit netlist; Obtain the slack times of all paths passing through a certain timing endpoint; Judge whether there are negative numbers in the slack times of all paths passing through this timing endpoint; If so, it indicates that there are violation paths in this timing endpoint.

4. The method for calculating the timing feedback of a computing circuit according to claim 1, wherein: Selecting the path with the worst slack time among the violation paths as the critical path corresponding to its corresponding timing endpoint includes: If there are violation paths passing through a certain timing endpoint; Sort the slack times of all paths passing through this timing endpoint in ascending order, where the slack time includes zero, positive numbers, and negative numbers; Select the path corresponding to the smallest sorted slack time as the path with the worst slack time.

5. The method for calculating the timing feedback of a computing circuit according to claim 1, wherein: Assigning weights to all standard cells on the critical path includes: Obtain the slack time of the critical path; Based on the value of the slack time of the critical path, assign weights to all standard cells on this critical path; If only one critical path passes through a certain standard cell, the weight value on this standard cell is the slack time value of the critical path passing through this standard cell; If two or more critical paths pass through the same standard cell, the weight value on this standard cell is the sum of the slack time values of all critical paths passing through this standard cell.

6. The method for calculating the timing feedback of a computing circuit according to claim 1, wherein: Selecting a standard cell as a critical cell further includes: The standard cell includes an input terminal and an output terminal; If the output terminal of a certain standard cell is connected to the input terminals of two or more critical cells, the two or more critical cells are critical cells with overlapping timing; If there are overlapping critical cells in the circuit net graph, randomly select a standard cell from the critical cells with overlapping timing as the critical cell.

7. The method for calculating the timing feedback of a circuit according to claim 1, wherein: Obtaining the delay change of each critical cell before and after the modification includes: Obtain the reference pin and scoring pin of the critical cell; Modify the critical cell, and record the timing path delay of each pair of reference pins and scoring pins after the modification; Obtain the delay variation of the critical cell based on the timing path delay.

8. The method for calculating the timing feedback of a computing circuit according to claim 1, wherein: Obtaining the local total violation duration includes: Calculating Among them, is the local total violation duration, is the key unit; is the critical timing path passing through the key unit; is the critical timing path is the slack time of, is the change in the assumed arrival time.

9. The method for calculating the timing feedback of a computing circuit according to claim 1, wherein: Obtaining the timing feedback further includes: After modifying the critical cell, determine whether there is a path violation in the circuit netlist based on the local total violation duration; Obtain a new path graph of the circuit netlist; Iterate the process of selecting the standard cell as the critical cell based on the new path graph, and select the critical cell that appears; Modify the new critical cell until the timing feedback is eliminated.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions for causing the computer to execute the method for calculating the circuit timing feedback according to any one of claims 1 to 9.

11. A computer device, which is applied to the method for calculating circuit timing feedback as described in any one of claims 1 to 9, and is characterized in that: Comprising a memory, a processor, and a computer program stored on the memory, the processor executes the computer program to implement the method for calculating the circuit timing feedback.

12. A computer program product, characterized in that: Comprising a computer program or instruction, when the computer program or instruction is executed by a processor, it implements the method for calculating the circuit timing feedback according to any one of 1 to 9.

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