SAR ADC full-automatic size optimization design method based on formula constraint

Abstract

The invention relates to the field of integrated circuit design, and discloses an SAR ADC full-automatic size optimization design method based on formula constraint, which is used for solving the problems that the traditional manual design is low in efficiency, depends on experience and is difficult to optimize high-dimensional parameters. The method comprises the following steps: 1) establishing an analytic mapping relation between system-level indexes and sub-circuit specifications, and decomposing performance indexes to each sub-circuit module through a mathematical equation; 2) constructing a directed acyclic dependency graph, representing design variables by nodes, and representing constraint relationships by edges; 3) carrying out topological sorting on the dependency graph, and generating an execution sequence containing simulation verification, knowledge calculation and size optimization; and 4) adopting a double-layer optimization mechanism: verifying the performance of the sub-circuit and the system through circuit simulation, and performing iterative optimization until a device size scheme meeting all indexes is output when the performance does not reach the standard. According to the method, the full-automatic optimization design of the SAR ADC from the system index to the transistor size is realized.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more specifically to a full-automatic sizing optimization design method for SAR ADC based on formula constraints. Background Art

[0002] With the rapid development of the Internet of Things and intelligent sensing technologies, the analog-to-digital converter (ADC), as a core device connecting analog signals and digital systems, has become increasingly important in system-on-chip (SoC). The successive approximation register ADC (SAR ADC) has become one of the key modules widely adopted due to its excellent performance in medium-precision, high energy efficiency, and high-speed applications. However, the traditional SAR ADC design highly relies on manual experience, and the design process requires repeated adjustment of circuit parameters to meet performance indicators, resulting in a long development cycle and high costs. Especially as the process nodes continue to shrink, the circuit complexity increases exponentially, and the traditional manual design method is difficult to meet the rapidly iterative market demands.

[0003] Existing automated design methods are mainly divided into two categories: knowledge-driven and optimization-driven. The knowledge-driven method derives circuit performance and designs device sizes based on analytical equations and empirical parameters, but it relies on approximate assumptions and has a limited scope of application; the optimization-driven method (such as algorithms based on Bayesian optimization and reinforcement learning) optimizes parameters through simulation iterations, but has high computational costs and is mostly limited to small-scale circuits (such as operational amplifiers, comparators, etc. with less than 20 transistors). For complex mixed-signal circuits such as SAR ADC, existing automated solutions still have significant deficiencies: for example, the method proposed in reference [7] requires manual intervention to determine the device optimization priority; reference [8] relies on a pre-generated comparator parameter library, increasing the upfront preparation burden; although reference [9] achieves a certain degree of automation, it fails to completely eliminate manual intervention and is difficult to efficiently handle multi-layer constraint relationships at the system level and sub-circuit level. In addition, existing methods usually lack a systematic modeling of the circuit topology hierarchical dependence relationship, resulting in redundant optimization processes and difficulty in convergence.

[0004] Specifically, the existing technologies have the following problems:

[0005] 1. Strong manual dependence: Expert experience is required to intervene in the optimization process, which is prone to introducing human errors and the design efficiency is limited;

[0006] 2. Insufficient scalability: The optimization algorithm is difficult to handle the high-dimensional parameter space of SAR ADC, especially the optimization ability for complex systems containing multiple sub-circuits (such as sampling switches, capacitor arrays, pre-amplifiers, etc.) is limited;

[0007] 3. Lack of global coordination: The coupling relationship between system-level performance metrics and sub-circuit design parameters is not effectively modeled, leading to the disconnection between local optimization and global objectives;

[0008] 4. High simulation cost: Traditional optimization methods require a large number of simulation iterations, and the sub-circuit level optimization is separated from system-level verification, further extending the design cycle.

[0009] In view of the above problems, there is an urgent need for a fully automated design method for SAR ADCs that can efficiently decompose system-level performance requirements into sub-circuit design constraints and achieve global parameter coordination through a hierarchical optimization framework, thereby reducing manual intervention while ensuring that circuit performance, power consumption and other metrics fully meet the standards. Summary of the Invention

[0010] The object of the present invention is to solve the problems of low efficiency, dependence on manual experience and difficulty in high-dimensional parameter optimization in the traditional manual design of successive approximation analog-to-digital converters (SAR ADCs). A fully automated two-level optimization method based on analytical equations and dependency graphs is proposed, which realizes an automated design process from performance metrics to transistor sizes through the collaboration of system-level metric decomposition and sub-circuit Bayesian optimization.

[0011] To achieve the above object, the present invention adopts the following technical means:

[0012] The present invention provides a fully automated size optimization design method for SAR ADCs based on formula constraints, including the following steps:

[0013] Step 1: Construct a mapping relationship between system-level performance metrics and sub-circuit design specifications, and decompose the input performance metrics into each sub-circuit module of the SAR ADC through analytical equations;

[0014] Step 2: Generate a dependency graph based on the analytical equations. The dependency graph is a directed acyclic graph (DAG), where nodes represent design variables and edges represent the constraint relationships between variables;

[0015] Step 3: Perform a topological sort on the dependency graph to generate a topological sequence that includes verification simulation, knowledge-driven calculation, and transistor size optimization;

[0016] Step 4: Execute automated design using a two-level optimization mechanism:

[0017] System-level optimization loop: Allocate performance metrics to each sub-circuit design constraint through iterative decomposition;

[0018] Local optimization loop: Use the Bayesian optimization algorithm (BO) to optimize the transistor size parameters for each sub-circuit;

[0019] Step 5: Verify the sub-circuit and system-level performance through circuit simulation. If the constraint conditions are not met, return to Step 4 for iterative optimization until a complete device size scheme that meets all design specifications is output.

[0020] In the above method, the construction of the mapping relationship from the system-level performance index to the sub-circuit design specification in Step 1 includes:

[0021] Step 1.1 Input the system-level performance index: Receive the high-level design specifications including the resolution N, sampling frequency f s , input amplitude V fs ;

[0022] Step 1.2 Define the sub-circuit performance constraint equations:

[0023] a) For the bootstrap sample-and-hold switch, calculate the load capacitance based on the noise constraint:

[0024]

[0025] And set the effective number of bits ENOB ≥ N + D, where D is an empirical parameter;

[0026] b) For the capacitive digital-to-analog converter (CDAC), determine the capacitance value through the unit capacitance C u = C L / 2 (N / 2) and constrain the standard deviation

[0027] c) For the preamplifier, calculate the minimum gain A os ≥ 20log V (V 10 ·2 os ) based on the comparator offset voltage V (N+1) , and derive the bandwidth f -3dB ≥ ln(1 - PSA) / (-2π·PSTR·T comp ) based on the establishment accuracy PSA and the timing ratio PSTR;

[0028] d) For the comparator, constrain the comparison period through the transmission gate on-resistance R on，max , load capacitance C L,max and the empirical parameter

[0029] g;

[0030]

[0031] At the same time, limit the propagation delay T pd ≤ 0.2T comp ;

[0032] e) For the SAR logic and clock control module, constrain the hold time:

[0033] T h ≥ 1.5t0 = 1.5R on，max C tot ln(2 N+E )

[0034] where C tot is the total capacitance value of the CDAC common terminal;

[0035] Step 1.3: Coupling index decomposition: Map the system-level indicators N, f s , V fs to each sub-circuit design variable C L , C u , σ u , A V ,, f -3dB , T pd through the analytical equations in Step 1.2, and establish a hierarchical constraint relationship chain.

[0036] In the above method, the construction of the dependency graph described in Step 2 includes:

[0037] Step 2.1: Based on the analytical equations in Step 1, extract all design variables and their constraint relationships;

[0038] Step 2.2: Define each variable as an independent node in the dependency graph, and split the mathematical expressions in the constraint relationships into directed edges, where:

[0039] Each constraint equation only allows a single left-hand side variable (LHS variable), and the remaining variables are used as right-hand side variables (RHS variables);

[0040] Establish directed edges from system performance indicators to sub-module performance indicators to form an acyclic dependency path;

[0041] Step 2.3: According to the directed edge connection rules, generate a directed acyclic graph (DAG) containing system-level variables, sub-circuit variables, and empirical parameters:

[0042] System-level indicators are used as the root nodes;

[0043] Sub-circuit performance indicators are used as sub-nodes;

[0044] Step 2.4: Verify the integrity of the DAG to ensure that the DAG is an acyclic graph and all sub-circuit performance constraints are connected to system-level indicators and physical dimension parameters through dependency edges.

[0045] In the above method, the construction of the dependency graph described in Step 3 includes:

[0046] Step 3.1: Perform a topological sort on the dependency graph to determine the calculation order from the root node (system-level metrics) to the child nodes (sub-circuit performance parameters);

[0047] Step 3.2: Take the set of empirical parameters {D, E, PSA, PSTR} as independent decision variables and preferentially allocate them to the system-level optimization loop for iterative search;

[0048] Step 3.3: Perform a topological sort on the set of physical parameters {channel length L, channel width W, number of fingers}, generating a local optimization sequence for each sub-circuit, where the sequence satisfies:

[0049] The gain A of the preamplifier V and the bandwidth f -3dB The optimization needs to be performed after the comparator offset voltage V os is optimized;

[0050] The unit capacitance C of the CDAC u The optimization needs to be performed after the bootstrap switch load capacitance C L is optimized;

[0051] Step 3.4: Generate a hybrid execution process based on the sequence, where:

[0052] The system-level metrics are verified through simulation calculations;

[0053] The sub-circuit performance metrics are calculated through knowledge-driven analytical equations;

[0054] The sub-circuit performance metrics are verified through SPEC simulations;

[0055] The transistor size optimization is completed through the Bayesian optimization (BO) algorithm;

[0056] The process ensures that the calculation or optimization of the RHS variables for each node is completed before its LHS variables.

[0057] In the above method, the two-level optimization mechanism described in step 4 includes the following sub-steps:

[0058] Step 4.1: Start the system-level optimization loop and traverse all empirical parameters based on the topological sequence. The empirical parameters include the effective bit margin D, comparison cycle margin E, preamplifier settling accuracy PSA, and preamplifier settling time ratio PSTR;

[0059] Step 4.2: Search for a combination of empirical parameters that satisfies the global constraints through Bayesian optimization (BO). The objective function is the weighted loss function of the constraints of each sub-circuit, and the loss calculation uses logarithmic scale normalization to eliminate magnitude differences;

[0060] Step 4.3: Execute the local optimization loop for each sub-circuit:

[0061] a) Trigger transistor sizing optimization according to the topological sequence, with the input variables being channel length L, width W, and the exponent fingers;

[0062] b) Call the Cadence Spectre simulator to verify the performance of the sub-circuit. If the constraints are violated, feedback the deviation to the system-level loss function;

[0063] Step 4.4: Dynamically update the feasible regions of the empirical parameters and device sizes until all sub-circuits meet the constraints or the maximum number of iterations is reached.

[0064] In the above method, the simulation verification and iterative optimization in Step 5 include the following sub-steps:

[0065] Step 5.1: Integrate the optimized sub-circuit netlist to generate a complete SAR ADC circuit;

[0066] Step 5.2: Perform system-level simulation to extract the signal-to-noise distortion ratio (SNDR), power consumption, and area metrics;

[0067] Step 5.3: Evaluate the deviation between the metrics and the input performance requirements. If there are unsatisfied constraints:

[0068] a) Trace back the dependency graph in reverse to locate the sub-circuit modules that violate the constraints;

[0069] b) Adjust the local optimization weights of the corresponding sub-circuits and update the system-level loss function;

[0070] c) Return to Step 4.2 to re-optimize the empirical parameters and transistor sizes;

[0071] Step 5.4: If all constraints are met, output the final device size scheme and performance report.

[0072] Since the present invention adopts the above technical means, it has the following beneficial effects:

[0073] 1. Fully automated design process, significantly reducing manual dependence

[0074] By constructing the analytical mapping relationship (Step 1.2) and the dependency graph (DAG) (Step 2) between the system-level performance metrics and the sub-circuit design parameters, the traditional manually experienced-driven metric decomposition process is transformed into an automated constraint chain generation, solving the problems of low efficiency and high error risk caused by manual intervention. Experiments show that in the TSMC 28nm process, the design cycle of a 12-bit SAR ADC is shortened to 62 minutes ( Figure 3 ), and iterative failures caused by empirical deviations are effectively avoided.

[0075] 2. Co - optimization of high - dimensional parameters to break through the bottleneck of complex constraints

[0076] Adopt a two - level optimization mechanism (Step 4), and the system - level loop dynamically allocates the performance margin of sub - circuits

[0077] (Empirical parameters such as D, E, etc.), and the local optimization loop accurately tunes the transistor dimensions (L, W, fingers) based on the Bayesian algorithm (BO), solving the optimization problem in the high - dimensional parameter space. For example, in the design of a 14 - bit ADC, the global optimizer coordinates 12 mutually restrictive performance indicators, and through the weighted loss function (Step 4.2) and logarithmic normalization processing, achieves multi - objective balance. Finally, the output SNDR reaches 79.99dB, and the FoMs index is better than that of similar solutions ( Figure 3 ).

[0078] 3. Hierarchical dependency modeling to improve both optimization efficiency and accuracy

[0079] The topological sorting based on the directed acyclic graph (DAG) (Step 3) ensures that the calculation order of design variables is strictly consistent with the physical dependency relationship of the circuit. For example, the optimization of the pre - amplifier gain is only triggered after the optimization of the comparator offset voltage is completed (Step 3.3), shortening the time consumed by the traditional manual sorting method.

[0080] 4. Greatly reduce the simulation cost and enhance the design robustness

[0081] Through the hybrid execution process (Step 3.4), the system - level simulation is only used for final verification, and the sub - circuit level adopts a strategy combining knowledge - driven calculation and local BO, reducing the number of full - system simulations. Experimental data shows that the total number of simulations for the 14 - bit design is controlled within 5000 times, and the total optimization time is controlled within 2 hours ( Figure 3 ).

[0082] 5. Wide process adaptability and strong scalability

[0083] The dependency graph (DAG) supports flexible expansion. For adding a new sub - circuit module, only the corresponding parsing equations and node connection rules need to be supplemented (Step 2.2), without reconstructing the overall framework. For example, for advanced process nodes (such as 28nm FinFET), by adjusting the PDK parameter range (L: 16nm - 30nm) and the coefficients of the constraint equations, a compliant size scheme can still be quickly generated, verifying the process universality of the method.

[0084] In summary, through the coordination of system - level index decomposition, dependency relationship modeling, and hierarchical optimization technologies, the present invention realizes the automation, high - efficiency, and high - precision of the full process of SAR ADC design, providing a reliable solution for the rapid iteration of complex mixed - signal circuits. Brief Description of the Drawings

[0085] Figure 1 This is the flowchart of the design method of the present invention;

[0086] Figure 2 Table I is the variable and relationship table, where σ u，constraint represents the unit capacitance deviation constraint, and T comp，constraint represents the comparison time constraint;

[0087] Figure 3 Table II is the performance comparison table;

[0088] Figure 4 Table III is the overall performance simulation result and time-consuming table;

[0089] Figure 5 is the typical SAR ADC architecture;

[0090] Figure 6 is the SAR ADC sub-circuit topology structure;

[0091] Figure 7 is the clock signal timing diagram;

[0092] Figure 8 is an example of the dependency graph;

[0093] Figure 9 is the definition of the comparator propagation delay: t2 - t1. Specific implementation manners

[0094] The following will give a detailed description of the embodiments of the present invention. Although the present invention will be described and explained in conjunction with some specific implementation manners, it should be noted that the present invention is not limited to these implementation manners only. On the contrary, any modifications or equivalent replacements made to the present invention should be covered within the scope of the claims of the present invention.

[0095] In addition, in order to better illustrate the present invention, numerous specific details are given in the following specific implementation manners. Those skilled in the art will understand that the present invention can also be implemented without these specific details.

[0096] I. Algorithm framework

[0097] This section will detail Figure 6 the core algorithm of the optimization framework shown. Due to the high complexity of the SAR ADC device size design, an overall optimization strategy cannot be adopted, and the problem needs to be decomposed into sub-circuit level optimization tasks through the divide-and-conquer method. This process is achieved through index mapping, that is, the system-level performance indicators are converted into the design specifications of each sub-circuit through an analytical method. After each sub-circuit is independently optimized, it is integrated into a complete SAR ADC for performance verification.

[0098] A. Problem modeling

[0099] Convert system-level and sub-circuit-level performance requirements into a set of variables and relationships. In the Figure 5 architecture shown, each sub-circuit module is as Figure 6 shown, and the optimization objectives and design constraints are summarized in Table I. The sub-circuit performance indicators are not only constrained by system-level objectives but also affected by the coupling relationships between modules. Define as follows:

[0100] Variables: Include physical constants (such as Boltzmann constant k), empirical values (such as selecting the settling accuracy of the operational amplifier within the range of 0.5 to 0.9), system-level indicators (such as ADC resolution N), and sub-circuit indicators (such as preamplifier gain)

[0101] Relationships: Constraint conditions composed of equations or inequalities

[0102] The design constraints of each sub-circuit are described in detail as follows:

[0103] 1. Bootstrap sampling switch, Figure 6 a in

[0104] The load capacitance CL is determined by the noise constraint:

[0105]

[0106] where k is the Boltzmann constant, T is the absolute temperature, and V fs is the input amplitude.

[0107] The effective number of bits (ENOB) as an optimization objective needs to satisfy:

[0108] ENOB ≥ N + D

[0109] D is an empirical parameter.

[0110] 2. Capacitive digital-to-analog converter (CDAC)

[0111] Figure 6 e in is the segmented capacitor array CDAC, and its unit capacitance C u and standard deviation σ u need to satisfy:

[0112]

[0113] 3. Preamplifier, Figure 6 b in

[0114] The gain AV of the three-stage cascaded structure is determined by the comparator offset voltage Vos and the resolution N:

[0115] A V ≥ 20log 10 (V os 2 N+1 )

[0116] Bandwidth f -3dB Limited by the comparator comparison time T comp (See Figure 7 ), the signal amplification needs to be completed within a partial period of T comp . Define the preamplifier settling time ratio (PSTA) as the ratio of the comparator clock cycle (value range [0.5, 0.9]), and the preamplifier settling accuracy (PSA) as the output accuracy within the settling period (same value range). The constraint is:

[0117]

[0118] 4. Comparator, Figure 6 In which c

[0119] Figure 6 Figure c shows the StrongARM latch comparator widely used in SAR ADCs, which has the characteristics of high speed, high precision and strong anti-noise ability. The core performance indicators of comparator design include:

[0120] Comparison period (Tcomp): The time required for a complete comparison operation

[0121] Propagation delay (Tpd): As Figure 9 shown, it is defined as the time interval from the start of the comparison operation to the start of the SAR logic (the comparison must be completed within this time)

[0122] Offset voltage (Vos): The detection threshold offset of the input differential voltage

[0123] To improve the comparison accuracy, a preamplifier is usually added at the front end of the comparator to enable the comparator to more accurately detect small voltage differences by amplifying the input signal.

[0124] 5. SAR logic and clock control:

[0125] As Figure 6 shown in Figure d, the SAR logic unit and the clock management module have a decisive impact on the accuracy, speed, power consumption and stability of the ADC. The SAR logic unit controls the successive approximation process, while the clock management module ensures the precise timing synchronization of the sampling and comparison operations, which is crucial for achieving high-performance and high-precision ADCs.

[0126] Timing parameter definition (see Figure 7 ):

[0127] T sample : Sampling time;

[0128] T1 / T2: Bottom plate sampling timing control signal;

[0129] Th : Holding time;

[0130] T comp : Comparator duty cycle;

[0131] The present invention sets the sampling time T sample = T comp .

[0132] Timing constraint conditions:

[0133] 1. Sampling / holding period: It is necessary to ensure that the CDAC is fully established during this stage

[0134] When adopting the bottom plate sampling architecture, it is necessary to comprehensively consider the CDAC establishment time and the preamplifier transmission delay

[0135] Holding time T h and comparison period T comp (Integer multiple of the quantization period) should satisfy: The CDAC is established within the remaining period T comp - T pd of the comparison period.

[0136] 2. CDAC switch model:

[0137] Except for the input signal, all control signals of the CDAC are driven by transmission gate switches. When the switch is turned on, it can be equivalent to a low-pass filter, and the following constraint conditions are derived:

[0138]

[0139] T h ≥ 1.5t0 = 1.5R on，max C tot ln(2 N+E )

[0140]

[0141] Parameter definition:

[0142] R on，max = max{R on，BS , R on，TG}

[0143] R on，BS : Bootstrap sampling switch on-resistance;

[0144] R on，TG : Transmission gate switch on-resistance;

[0145] C L，max : Most significant bit (MSB) capacitance value, representing the maximum load capacitance during the switch stage;

[0146] E: Experience value, with a value range of [1, 3];

[0147] C tot : Total capacitance value connected to the common terminal voltage V during the holding stage cm ;

[0148] B. Dependency Graph Construction Based on the defined variables and relationship set, construct the dependency graph required for the optimization framework. As shown in Table I of Figure 2 , each variable may appear on both sides of the relational expression, but this framework follows the single left-hand side value principle: each relational expression only allows a single variable to be on the left-hand side (LHS), thereby establishing a dependency path from the LHS variable to all variables on the right-hand side (RHS). Considering variables as nodes and dependency paths as directed edges, an acyclic dependency graph can be constructed (partial examples are shown in Figure 8 ). Under this assumption, the dependency graph satisfies the properties of a directed acyclic graph (DAG), and topological sorting can be used to ensure that all RHS variables are calculated or verified before the corresponding LHS variables.

[0149] Index Decomposition Process:

[0150] After the constraint evaluation is completed through the propagation of the dependency graph, the system-level performance index is decomposed to the sub-circuit level;

[0151] Perform local Bayesian optimization (BO) on each sub-circuit to meet its independent constraints;

[0152] After verifying that the constraints are met using the simulation results, pass the performance index downward along the topological order to calculate the constraint conditions of other sub-circuits.

[0153] C. Optimization Process

[0154] As shown in Figure 1 , Bayesian optimization (BO) is the core optimization engine of this framework. After the dependency graph is constructed:

[0155] Start the system-level optimization loop: Search for a set of empirical parameters that balance performance and feasibility

[0156] Termination condition: All constraints are met or the maximum number of iterations is reached (experimental results show that convergence can be achieved in a single iteration)

[0157] Execute sub-circuit level BO: Directly optimize device physical parameters (such as transistor length / width L, W), and the parameter value range is defined by the PDK. The deviation of non-compliant sub-circuits is included in the system-level BO loss function.

[0158] Loss Function Normalization:

[0159] For different magnitude indicators (such as the preamplifier bandwidth ≈ 10 5-8Hz vs Comparator Propagation Delay ≈ 10 -10-9 s), the loss is evaluated using a logarithmic scale to eliminate magnitude differences:

[0160] Example: Target bandwidth 100M Hz, measured 10M Hz → Loss value = log(100M) - log(10M) = 1 (instead of linear difference 90M);

[0161] Note: All experimental metrics in this experiment are positive values and this method is applicable; for other scenarios, an advanced normalization strategy needs to be adopted (see the discussion in Section V for details).

[0162] IV. Experimental Results

[0163] This framework is implemented based on Python 3.9 and runs on a CentOS7.9 system with an Intel Xeon Gold 5320 processor (96 cores). The experiment uses the TSMC 28-nanometer process and is verified through the Cadence Spectre simulator. The transistor parameter setting ranges are:

[0164] - Channel length L: [30 nm, 1 μm]

[0165] - Channel width W: [100 nm, 3 μm]

[0166] - Exponent (fingers): [1, 100]

[0167] Bayesian optimization (BO) is implemented using the Optuna library, with a maximum of 5000 total simulation times and a sub-circuit level BO parallelism of 20 threads.

[0168] Performance comparison:

[0169] Table II shows the measured results of two design specifications (14-bit 500KS / s and 12-bit 1MS / s). The 14-bit design achieves an 80dB signal-to-noise distortion ratio (SNDR) with a power consumption of 153.6 μW; the 12-bit design has an SNDR

[0170] of 70.3dB and a power consumption of 72.81 μW. The Schreier / Walden energy efficiency metric is used for evaluation:

[0171]

[0172] where P represents the total power consumption of the analog-to-digital converter (ADC);

[0173] Power consumption distribution characteristics:

[0174] - 14-bit design: 62% of the power consumption comes from the synchronous SAR logic, and further optimization can be achieved by adopting an asynchronous architecture;

[0175] - 12-bit design: The proportion of the dynamic power consumption of the comparator in high-speed scenarios increases significantly

[0176] Optimization efficiency:

[0177] When the resolution is increased from 12 bits to 14 bits and the sampling rate is decreased from 1 MHz to 500 kS / s:

[0178] - The number of convergence iterations of the comparator decreases

[0179] - The optimization time of the bootstrap circuit and the preamplifier increases (the enhanced constraints are due to high-precision requirements)

[0180] Figure 4 The real-time optimization time and parameter tuning amount of each sub-circuit are listed in detail. The overall performance index (FoM) is comparable to that of the manual optimization scheme, verifying the effectiveness of the automated method.

Claims

1. A fully automatic size optimization design method for SAR ADC based on formula constraints, characterized in that, It includes the following steps: Step 1: Construct the mapping relationship between system-level performance metrics and sub-circuit design specifications, and decompose the input performance metrics into each sub-circuit module of the SAR ADC through an analytical equation; Step 2: Generate a dependency graph based on the analytical equation, where the dependency graph is a directed acyclic graph (DAG), nodes in the graph represent design variables, and edges represent the constraint relationships between variables; Step 3: Perform a topological sort on the dependency graph to generate a topological sequence that includes verification simulation, knowledge-driven calculation, and transistor size optimization; Step 4: Execute automated design using a two-level optimization mechanism: System-level optimization loop: Allocate performance metrics to each sub-circuit design constraint through iterative decomposition; Local optimization loop: Use the Bayesian optimization algorithm to optimize the transistor size parameters for each sub-circuit; Step 5: Verify the performance of the sub-circuit and system level through circuit simulation. If the constraint conditions are not met, return to Step 4 for iterative optimization until a complete device size solution that meets all design specifications is output.

2. The method according to claim 1, wherein The construction of the mapping relationship from the system-level performance metrics to the sub-circuit design specifications in Step 1 includes: Step 1.1 Input system-level performance metrics: Receive high-level design metrics including resolution N, sampling frequency f s , input amplitude V fs ; Step 1.2 Define the sub-circuit performance constraint equation: a) For the bootstrap sample-and-hold switch, calculate the load capacitance based on the noise constraint: And set the effective number of bits ENOB ≥ N + D, where D is an empirical parameter; b) For the capacitive digital-to-analog converter (CDAC), the capacitance value is determined by the unit capacitance C u = C L / 2 (N / 2) and the standard deviation is constrained c) For the preamplifier, calculate the minimum gain A according to the comparator offset voltage V os ≥ 20log V (V 10 · 2 os ) and derive the bandwidth f based on the settling accuracy PSA and the timing ratio PSTR (N+1) ≥ ln(1 - PSA) / (-2π·PSTR·T -3dB ); comp ) d) For the comparator, the comparison period is constrained by the on-resistance R of the transmission gate on，max , the load capacitance C L,max , and the empirical parameter E: At the same time, limit the propagation delay T pd ≤0.2T comp ; e) For the SAR logic and clock control module, constrain the hold time: T h ≥1.5t0 = 1.5R on，max C tot ln(2 N+E ) Among which C tot is the total capacitance value of the common terminal of the CDAC; Step 1.3: Coupling index decomposition: Map the system-level indicators N, f s , V fs to each sub-circuit design variable C L , C u , σ u , A V , f -3dB , T pd through the analytical equation in Step 1.2, and establish a hierarchical constraint relationship chain.

3. The method according to claim 2, wherein The construction of the dependency graph described in Step 2 includes: Step 2.1: Based on the analytical equation in Step 1, extract all design variables and their constraint relationships; Step 2.2: Define each variable as an independent node in the dependency graph, and split the mathematical expressions in the constraint relationships into directed edges, where: Each constraint relation only allows a single left-value variable, and the remaining variables are used as right-value variables; Establish a directed edge from the system performance metric to the sub-module performance metric to form an acyclic dependency path; Step 2.3: According to the directed edge connection rule, generate a directed acyclic graph DAG that includes system-level variables, sub-circuit variables, and empirical parameters: The system-level metric is used as the root node; The sub-circuit performance metrics are used as child nodes; Step 2.4: Verify the integrity of the DAG to ensure that the DAG is an acyclic graph and all sub-circuit performance constraints are connected to the system-level metrics and physical size parameters through dependency edges.

4. The method according to claim 3, characterized in that, The construction of the dependency graph described in Step 3 includes: Step 3.1: Perform a topological sort on the dependency graph to determine the calculation order from the root node to the child nodes; Step 3.2: Use the set of empirical parameters {D, E, PSA, PSTR} as independent decision variables and preferentially allocate them to the system-level optimization loop for iterative search; Step 3.3: Perform a topological sort on the sub-circuit performance metrics to generate a local optimization sequence in units of sub-circuits, and the sequence satisfies: Gain A of the preamplifier V and bandwidth f -3dB Optimization needs to be performed at the comparator offset voltage V os after the optimization is completed; CDAC unit capacitor C u Optimization needs to be performed on the bootstrap switch load capacitor C L Execute after the optimization is completed; Step 3.4: Generate a hybrid execution process based on the sequence, where: The system-level metric verification is completed through simulation calculation; The sub-circuit performance metrics are calculated through knowledge-driven analytical equations; The sub-circuit performance metric verification is completed through SPEC simulation; The transistor size optimization is completed through the Bayesian optimization algorithm; The process ensures that the calculation or optimization of the RHS variable for each node is completed before its LHS variable.

5. The method according to claim 6, characterized in that, The two-level optimization mechanism described in step 4 includes the following sub-steps: Step 4.1: Start the system-level optimization loop, traverse all empirical parameters based on the topological sequence, and the empirical parameters include the significant digit margin D, the comparison period margin E, the preamplifier establishment accuracy PSA, and the preamplifier establishment time ratio PSTR; Step 4.2: Search for a combination of empirical parameters that satisfy the global constraints through Bayesian optimization. The objective function is the weighted loss function of the constraints of each sub-circuit, and logarithmic scale normalization is used for loss calculation to eliminate magnitude differences; Step 4.3: Execute a local optimization loop for each sub-circuit: a) Trigger transistor sizing optimization according to the topological sequence, and the input variables are channel length L, width W, and the exponent fingers; b) Call the Cadence Spectre simulator to verify the performance of the sub-circuit. If the constraints are violated, the deviation is fed back to the system-level loss function; Step 4.4: Dynamically update the feasible regions of the empirical parameters and device sizes until all sub-circuits meet the constraints or reach the maximum number of iterations.

6. The method according to claim 5, wherein The simulation verification and iterative optimization described in step 5 include the following sub-steps: Step 5.1: Integrate the optimized sub-circuit netlist to generate a complete SAR ADC circuit; Step 5.2: Perform system-level simulation to extract the signal-to-noise distortion ratio, power consumption, and area metrics; Step 5.3: Evaluate the deviation between the metrics and the input performance requirements. If there are unsatisfied constraints: a) Trace back the dependency graph in reverse to locate the sub-circuit module that violates the constraints; b) Adjust the local optimization weight of the corresponding sub-circuit and update the system-level loss function; c) Return to step 4.2 to re-optimize the empirical parameters and transistor sizes; Step 5.4: If all constraints are met, output the final device size scheme and performance report.

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