Low-power-consumption ultrahigh-frequency tag coding circuit
Through the design of clock frequency division and gated clock circuit, combined with data transmission control, the low power consumption and small area of ultra-high frequency RFID tag chip are achieved, solving the problem of large-scale area and power consumption of tag chips.
Patent Information
- Application Number
- CN202510249004.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2025-07-18
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The overall area of the ultra-high frequency RFID tag chip is large and the encoding circuit power consumption accounts for a high proportion, resulting in a large power consumption of the tag chip.
The clock divides the system clock according to the target encoding mode by using a clock frequency division circuit, and the sub-circuit is switched by a gated clock circuit. The encoding circuit determines the target encoding mode according to the preset query command, and synchronizes the encoded data through the data transmission control circuit.
The overall area of the tag chip in which the encoding circuit is located is effectively reduced, and the power consumption proportion of the encoding circuit in the entire tag chip circuit is reduced.
Smart Images
Figure CN120337968A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of radio frequency technology, and particularly to a low-power ultra-high frequency tag encoding circuit. Background Art
[0002] In related technologies, radio frequency identification (RFID) technology is a technology in which a reader non-contactingly completes target identification through radio and conducts data interaction. According to the characteristics of the RFID reverse link communication, that is, a passive tag mainly obtains energy from the radio frequency signal transmitted by the reader and simultaneously transmits data information to the reader, that is, the backscatter technology is used to transmit target information to the reader. Since there are multiple encoding methods for the reverse link encoding of ultra-high frequency RFID tags, and each encoding method corresponds to multiple encoding rates, a variety of logic gate circuits need to be set inside the tag, resulting in a relatively large overall area of the tag chip. Moreover, during the working process, the encoding circuit processes the working state, which further leads to a relatively large power consumption ratio of the encoding circuit in the entire tag chip circuit.
[0003] In summary, the technical problems existing in related technologies need to be improved. Summary of the Invention
[0004] The main purpose of the embodiments of this application is to propose a low-power ultra-high frequency tag encoding circuit, which can effectively reduce the overall area of the tag chip where the encoding circuit is located and reduce the power consumption ratio of the encoding circuit in the entire tag chip circuit.
[0005] To achieve the above purpose, the embodiments of this application propose a low-power ultra-high frequency tag encoding circuit, and the low-power ultra-high frequency tag encoding circuit includes:
[0006] A clock division circuit, which is used to divide the system clock according to the data rate corresponding to the target encoding mode to obtain an encoding clock;
[0007] A gated clock circuit, which is used to control the switching of each sub-circuit in the low-power ultra-high frequency tag encoding circuit;
[0008] An encoding circuit, which is used to determine the target encoding mode according to the preset parameters in the preset query command, and encode the data to be encoded through the target encoding mode to obtain encoded output data;
[0009] A data transmission control circuit, which is used to select multiple types of data to obtain the data to be encoded, synchronize the data to be encoded according to the encoding clock, serially transmit the data to be encoded to the encoding circuit, and after receiving the encoded output data returned by the encoding circuit, transmit the encoded output data to a tag reader through an antenna.
[0010] In some embodiments, the clock division circuit includes a division coefficient calculation module and a clock division module; the division coefficient calculation module is used to calculate a division coefficient according to the calibration symbol of the preamble and the division bit rate; the clock division module is used to perform a division process on the system clock according to the division coefficient.
[0011] In some embodiments, the data transmission control circuit includes a stored data transmission module, a random number transmission module, a check data transmission module, an encoding control module, and a transmission control module;
[0012] The stored data transmission module, the random number transmission module, or the check data transmission module transmits corresponding data to the encoding control module and the transmission control module after receiving a return command sent by the controller module;
[0013] The encoding control module is used to determine the data type of the encoding circuit according to the received data;
[0014] The transmission control module is used to generate an encoding control signal and select a data transmission clock, and transmit the received data to the encoding circuit.
[0015] In some embodiments, the encoding circuit includes an encoding mode determination module, a preamble encoding module, and a data encoding module; the encoding mode determination module is used to determine the target encoding mode from several candidate encoding modes according to preset parameters in a preset query command; the preamble encoding module is used to encode the preamble signal of the data to be encoded according to the target encoding mode; the data encoding module is used to encode the data to be encoded according to the target encoding mode after completing the encoding of the preamble signal.
[0016] In some embodiments, the candidate encoding modes include an FM0 encoding mode and a Miller encoding mode, and the Miller encoding mode includes a Miller2 encoding mode, a Miller4 encoding mode, and a Miller8 encoding mode.
[0017] In some embodiments, the FM0 encoding mode and the Miller encoding mode adopt a common encoding state mechanism.
[0018] In some embodiments, when the encoding circuit encodes the current data to be encoded, the data sending control circuit synchronously prepares the next set of data to be encoded.
[0019] In some embodiments, the encoding output data obtained by encoding the data to be encoded through the target encoding mode includes:
[0020] Dividing the data to be encoded into a preamble signal, a pre - synchronization code signal, data bits, or an end - frame signal;
[0021] Encoding the preamble signal, the pre - synchronization code signal, the data bits, and the end - frame signal according to the target encoding mode under an encoding clock to obtain single - bit encoded data as the encoding output data.
[0022] In some embodiments, the data processing process of the data sending control circuit includes:
[0023] When receiving the TRext signal sent by the controller circuit, prepare the pre - synchronization code;
[0024] While adding the command return data behind the pre - synchronization code, if it is determined that the command return data needs to be check - encoded, generate a check code and add the check code behind the command return data, and then send the data after adding the check code to the encoding circuit; if it is determined that the command return data does not need to be check - encoded, send the data after adding the command return data to the encoding circuit; the command return data includes the output data of the stored data sending module or the random number sending module.
[0025] In some embodiments, the data format of the data sent by the data sending control circuit to the encoding circuit includes a first format and a second format. The first format includes pre - synchronization data, basic data, a check code, and an end bit; the second format includes pre - synchronization data, basic data, and an end bit.
[0026] The embodiments of the present application at least include the following beneficial effects: The present application provides a low-power ultra-high-frequency tag encoding circuit. In this solution, a clock division circuit is set to divide the system clock according to the data rate corresponding to the target encoding mode to obtain an encoding clock. A gated clock circuit is used to control the switching of each sub-circuit. After the encoding circuit determines the target encoding mode according to the preset parameters in the preset query command, it encodes the data to be encoded based on the target encoding mode to obtain encoded output data. At the same time, a data sending control circuit selects multiple types of data to obtain the data to be encoded, synchronizes the data to be encoded according to the encoding clock, serially sends the data to be encoded to the encoding circuit, and then after receiving the encoded output data returned by the encoding circuit, sends the encoded output data to the tag reader through the antenna, so that while ensuring the effective reading of tag data by the reader, the overall area of the tag chip where the encoding circuit is located can be effectively reduced, and the power consumption ratio of the encoding circuit in the entire tag chip circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 is a schematic diagram of the modules of the low-power ultra-high-frequency tag encoding circuit provided by the embodiments of the present application;
[0028] Figure 2 is a structural diagram of the command parameter processing of the frequency division circuit provided by the embodiments of the present application;
[0029] Figure 3 is a circuit diagram for switching FM0 and Miller encoded data provided by the embodiments of the present application;
[0030] Figure 4 is a waveform diagram for implementing Miller encoded data -0 and data -1 provided by the embodiments of the present application;
[0031] Figure 5 is a basic function and state diagram shared by FM0 and Miller encoding provided by the embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0032] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods that are consistent with some aspects of the embodiments of the present application.
[0033] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".
[0034] The terms "at least one", "a plurality of", "each", "any one", etc. used in this application, at least one includes one, two or more than two, a plurality of includes two or more than two, each refers to each one of the corresponding plurality, and any one refers to any one of the plurality.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0036] In the related art, Radio Frequency Identification (RFID) technology is a technology in which a reader non-contactingly completes target identification through radio and conducts data interaction. According to the characteristics of RFID reverse link communication, that is, passive tags mainly obtain energy from the radio frequency signals emitted by the reader and at the same time transmit data information to the reader, that is, the backscatter technology is used to transmit target information to the reader. Since there are multiple coding methods for the reverse link coding of ultra-high frequency RFID tags, and each coding method corresponds to multiple coding rates, a variety of logic gate circuits need to be set inside the tag, resulting in a relatively large overall area of the tag chip. Moreover, during the working process, the coding circuit will process the working state, which further leads to a relatively large power consumption ratio of the coding circuit in the entire tag chip circuit.
[0037] In view of this, an ultra-high frequency tag coding circuit with low power consumption is provided in the embodiments of this application, which can effectively reduce the overall area of the tag chip where the coding circuit is located and reduce the power consumption ratio of the coding circuit in the entire tag chip circuit.
[0038] The following specifically elaborates on the embodiments of this application in conjunction with the accompanying drawings:
[0039] Figure 1 is an optional flowchart of the ultra-high frequency tag coding circuit with low power consumption provided by the embodiments of this application, Figure 1The low-power ultra-high frequency tag encoding circuit in it may include but is not limited to a clock division circuit, a gated clock circuit, an encoding circuit, and a data transmission control circuit. Specifically, the clock division circuit is used to divide the system clock according to the data rate corresponding to the target encoding mode to obtain an encoding clock, so that the minimum clock frequency input to the data encoding module does not affect the encoding accuracy; the gated clock circuit is used to control the switching of each sub-circuit in the low-power ultra-high frequency tag encoding circuit, so that the instantaneous current and power consumption can be reduced by disabling unnecessary sub-circuit clocks; the encoding circuit is used to determine the target encoding mode according to the preset parameters in the preset query command, and encode the data to be encoded through the target encoding mode to obtain encoded output data; the data transmission control circuit is used to select multiple types of data to obtain the data to be encoded, synchronize the data to be encoded according to the encoding clock, serially send the data to be encoded to the encoding circuit, and after receiving the encoded output data returned by the encoding circuit, send the encoded output data to the tag reader through the antenna.
[0040] In the embodiment of the present application, as Figure 1 shown, the data transmission control circuit includes a stored data transmission module, a random number transmission module, a verification data transmission module, an encoding control module, and a transmission control module; the stored data transmission module, the random number transmission module, or the verification data transmission module sends the corresponding data to the encoding control module and the said transmission control module after receiving the return command sent by the controller module; the encoding control module is used to determine the data type of the encoding circuit according to the received data; the transmission control module is used to generate an encoding control signal and select a data transmission clock, and send the received data to the encoding circuit. Specifically, the stored data transmission module (EE_Data transmission module) is used to retrieve and forward the EEPROM stored data, the random number transmission module is used to retrieve and forward the RNG_Reg data, and the verification data transmission module (CRC-16 transmission module) is used to retrieve and forward the CRC_Reg data.
[0041] As Figure 1As shown in the figure, the encoding circuit includes an encoding mode determination module, a preamble encoding module, and a data encoding module. The encoding mode determination module is configured to determine the target encoding mode from a plurality of candidate encoding modes according to the preset parameters in the preset query command. The preamble encoding module is configured to encode the preamble signal of the data to be encoded according to the target encoding mode. The data encoding module is configured to encode the data to be encoded according to the target encoding mode after completing the encoding of the preamble signal. It can be understood that the candidate encoding modes include the FM0 encoding mode and the Miller encoding mode, and the Miller encoding mode includes the Miller2 encoding mode, the Miller4 encoding mode, and the Miller8 encoding mode. The FM0 encoding mode and the Miller encoding mode adopt a common encoding state mechanism, that is, data processing of the two encoding modes is completed under the same hardware architecture, so that the number of logic gate circuits can be reduced, and thus the area of the tag chip can be reduced.
[0042] Specifically, when the encoding circuit encodes the current data to be encoded, the data sending control circuit synchronously prepares the next set of data to be encoded, so that data processing can be performed in a pipeline manner, thereby shortening the tag response time. It can be understood that when the encoding circuit obtains the encoded output data by encoding the data to be encoded through the target encoding mode, the data to be encoded can be divided into a pilot signal, a preamble signal, data bits, or an end frame signal, and then encoded according to the target encoding mode under the encoding clock for the pilot signal, the preamble signal, the data bits, and the end frame signal to obtain single-bit encoded data as the encoded output data (Data_out).
[0043] In the embodiment of the present application, the preset query command may be a Query command, and the preset parameter in the preset query command may be the specified parameter M in the Query command. It can be understood that due to the different target encoding modes, their corresponding encoding clocks are also different. According to the ISO / IEC 18000-6C protocol, the ultra-high frequency transmission link frequency is controlled by the command parameter. As Figure 2 shown, the clock frequency division circuit includes a division coefficient calculation module and a clock frequency division module. The division coefficient calculation module is configured to calculate the division coefficient according to the calibration symbol of the preamble and the division bit rate. The clock frequency division module is configured to perform frequency division processing on the system clock according to the division coefficient. Through Figure 2It can be seen that the frequency division circuit in the circuit design is responsible for performing multi-frequency division processing on the system clock according to the different data rates required for different coding modes, so as to output the data transmission clock and the coding clock. In the embodiment of the present application, the system clock (CLK_sys) frequency division method is adopted to obtain the coding clock applicable to different coding modes, so as to achieve the purpose of reducing power consumption and area. The parameters DR and TRcal of the Query command in the protocol determine the coding clock and the data transmission clock. The division ratio N is obtained by parsing the Query command. Therefore, the clock frequency division circuit only changes its division ratio N when it receives the Query command, and the division ratio N only changes once during its inventory cycle, and the frequency division circuit only operates once. Therefore, it is not necessary to calculate the division ratio multiple times, and thus the circuit power consumption of this module can be reduced.
[0044] The backscatter link frequency (BLF) specified in the ISO / IEC 18000-6C protocol, and its determination formula is
[0045]
[0046] In the formula, DR is the division ratio, which is a parameter in the Query instruction, and its value can be selected from two values: 8 and 64 / 3; TRcal is the calibration symbol of Tag to Reader for the preamble.
[0047] In this embodiment, the system clock is used to count TRcal, and the counting result is stored in TRcal_CNT. According to DR and TRcal, the frequency of the coding clock (CLK_BLF) can be directly adjusted. Therefore, the calculation formula of the division ratio N is as follows:
[0048]
[0049] In the formula, f s is the designed system clock.
[0050] The data transmission clock is determined by the coding clock and the M parameter in the Query command. According to different values of M, different division ratios are selected, and finally the data transmission clock of the sending link is obtained. Therefore, the data transmission clock is the result of frequency division of the coding clock by selecting the coding mode.
[0051] It can be understood that in traditional tag chip designs, all sequential circuits consume power every clock cycle. However, not all sub-circuits are performing useful functions while consuming a large amount of power. Therefore, disabling the clocks of unnecessary sub-modules can significantly reduce the instantaneous current and power, which helps to increase the recognition distance of the tag. In this embodiment, a clock gating enable signal is generated according to the data preparation of the transmission control circuit during the transmission stage to perform clock control on five modules during the tag transmission stage, namely the CRC module (check data transmission module), the EEPROM module (stored data transmission module), the RNG module (random number transmission module), the data transmission control circuit, and the encoding circuit. Through clock gating in this embodiment, the sub-circuits are only active when needed, thus saving the power consumption of the tag during the response process.
[0052] In the embodiment of the present application, the main function of the data transmission control circuit is to generate corresponding return data. These return data may be from the EEPROM, or may be a handle generated by the RNG module, or may be a CRC16 check code generated by the CRC module. The command return signal received from the controller module is input to the encoding control module through the EE_Data transmission module, the RNG transmission module, and the CRC-16 transmission module to determine the data type returned to the encoding circuit. The transmission control module generates an encoding control signal and selects the data transmission clock. The data encoding module encodes different return data according to these signals. To meet the requirement of shortening the tag response time, during the return data period, when the data encoding module interacts with other modules such as the CRC module, the EEPROM module, and the RNG module, a pipelined operation is adopted. While the encoding circuit performs the encoding operation on the current data, the CRC encoding is performed on the output data to be encoded. After the encoding circuit finishes encoding the current data, the CRC calculation is completed and the CRC_Reg signal is returned. The encoding circuit continues to perform the encoding operation on the 16-bit CRC_Reg signal, thereby saving the running time of the data passing through the CRC calculation circuit, effectively reducing the time of the return data, and omitting the number of registers for temporarily caching the basic data, optimizing the overall area of the encoding circuit, and further optimizing the area of the tag chip.
[0053] It can be understood that the data processing process of the data sending control circuit is to prepare the preamble after receiving the TRext signal sent by the controller circuit; when adding the command return data behind the preamble, if it is determined that the command return data needs to be verified and encoded, generate the verification code and add the verification code behind the command return data, and then send the data after adding the verification code to the encoding circuit; if it is determined that the command return data does not need to be verified and encoded, send the data after adding the command return data to the encoding circuit; wherein, the command return data includes the output data of the storage data sending module or the random number sending module. Exemplarily, after the data sending control circuit is started, it receives the TRext signal from the data sending control circuit, prepares the preamble, and then adds the data output by the controller module behind the preamble. The command return data refers to the handle generated by the random number module or the internal EEPROM data read by the EEPROM module. While adding the basic data, according to the command return signal, it is determined whether the basic data needs to be CRC encoded. If CRC encoding is required, generate the CRC verification code and add it behind the basic data. If CRC encoding is not required, directly input the basic data into the encoding circuit. Taking the Read command and the QueryRep command return signals as examples, the data returned by the Read instruction is {data 0 + the requested storage word + handle + CRC-16}, and it is necessary to run the EE_Data sending module to cache the data read by the EEPROM and the encoding control module to control the data sending, and run the CRC-16 sending module to send the data obtained by CRC encoding. The returned data of QueryRep only needs the basic data {RN16}, and at this time, only the random number sending module needs to be run to send the RN16. Therefore, the data prepared by the data sending control circuit for the encoding circuit mainly has a first format and a second format. The first format is preamble + basic data + CRC verification code + end bit, and the second format is preamble + basic data + end bit.
[0054] In the embodiments of the present application, according to the provisions of the ISO / IEC 18000-6C protocol, the tag mainly uses two encoding modes, FM0 and Miller, for data transmission. Specifically, the FM0 encoding circuit rule is as follows: First, judge the M value. When the M value is 00, FM0 encoding is performed; otherwise, Miller encoding is performed. After determining the encoding mode, it is also necessary to determine whether the preamble of the data needs to carry a leading zero (Tone). If TRext is 1, a frame header with 12 leading zeros needs to be sent before sending the synchronization code; otherwise, the synchronization code without a leading zero is sent. In data encoding, regardless of whether the transmitted data is 0 or 1, the baseband phase is inverted at each data boundary. There is no phase inversion inside data 1, while there is a phase inversion in the middle of data 0. When implementing FM0 encoding, the data is divided into 4 states (S1 to S4) in the design and jumps according to the specified state machine. After determining the data value to be sent for each bit, a bit data length counter for transmission is generated, and the data sequence to be transmitted is constructed according to the count value. This state encoding should also have a storage function, such as Figure 3 As shown, when encoding a data, the encoded data in the previous clock cycle corresponds to the encoded data in the next clock cycle, because whether the next bit needs to be flipped depends on whether the previous bit data is high level or low level. According to the FM0 encoding rule, the encoding process of the FM0 encoding circuit of the present invention is as follows: First, encode the preamble and pre-synchronization code of the data according to TRext, and then perform data encoding. When the initial value of the encoding signal is "0" and the input Data_in is "0", it jumps to state S1 in the next clock cycle, and at this time the encoding signal becomes "1", because there is a jump in the middle of data 0. When the input Data_in is "1", it jumps to state S2 in the next clock cycle, and at this time the encoding signal is still "0", and there is no jump between the encoded data. Similarly, the encoding signals in states S2 and S3 will be flipped or maintained according to Data_in. Finally, at the end of each data encoding, the encoding signal is automatically flipped.
[0055] The rules for the Miller encoding circuit are as follows: First, judge the value of M. When the value of M is 00, FM0 encoding is performed; for other values, Miller encoding is performed. After determining the encoding mode, it is also necessary to determine whether the preamble of the data needs to carry a leading zero (Tone). If TRext is 1, a frame header with 16 leading zeros needs to be sent first and then the synchronization code; otherwise, a synchronization code with 4 leading zeros is sent. There are transitions in two cases: between two adjacent data "0"s or within a single data "1". Due to different values of the parameter M in the Query command, it is divided into four forms: when M is equal to 2, there are two subcarriers for the data bits; when M is 4, there are four subcarriers; when M is 8, there are eight subcarriers. At the end of Miller encoding, there also needs to be an end flag signal bit Dummy, whose form conforms to the encoding rules of Miller code and also has two, four, and eight subcarriers respectively. As Figure 4 shown, when implementing Miller encoding, the design divides the data into 4 states, S1 to S4, and the state machine jumps according to the regulations in the above figure. Determine the data value to be sent for each bit, generate a bit data length counter for transmission, and construct the data sequence to be sent according to the count value. It can be seen from the state transitions of Miller code that the transition of Miller code is determined by the level state in the previous clock cycle, which is the same as FM0 encoding. In this embodiment, the implementation method of Miller code is to perform an exclusive OR operation on the data generated by the Miller encoding mode and the encoding clock with a specific frequency. For example, as Figure 3 shown, when M is equal to 4, it is the waveform-transformed data encoding signal obtained by performing an exclusive OR operation on the data generated by the Miller encoding mode and the clock signal after being divided by four. According to this encoding rule, the encoding process of the Miller encoding circuit in this embodiment is as follows: First, encode the preamble and pre-synchronization code of the data according to TRext, and then perform data encoding. When the initial value encoding signal is "1" and the input Data_in is "0", it jumps to state S1 in the next clock cycle, and the encoding signal is still "1" at this time because there is no transition in the middle of data 0. When the input Data_in is "1", it jumps to state S2 in the next clock cycle, and the encoding signal changes from "1" to "0" at this time, with a transition between the encoding data. Similarly, the encoding signals in states S2 and S3 will be flipped or maintained according to Data_in. Finally, at the end of each data encoding, the encoding signal is automatically flipped. Finally, an exclusive OR operation is performed on the data generated by the Miller encoding mode and the clock CLK_BLF with a specific frequency to generate the output encoding signal.
[0056] Furthermore, the FM0 and Miller encodings in the embodiments of this application determine the selection of the encoding mode Mode according to the value of the parameter M. Under the encoding state machine of S1 - S4, different divisions of the state transitions of S1 - S4 will be made according to the two different encoding modes of FM0 and Miller, asFigure 5 As shown. Traditional encoding circuits use separate state machines for encoding state transitions according to different encoding modes such as FM0 and Miller. Since the encoding waveforms of S1 - S4 are the same, only in the FM0 encoding mode, states S2 and S3 are data - 0 data encodings, and states S1 and S4 are data - 0 data encodings; in the Miller encoding mode, states S2 and S3 are data - 1 data encodings, and states S1 and S4 are data - 1 data encodings. Therefore, the encoding circuit design of the embodiment of the present application adopts a shared encoding state machine, combines the separately encoded FM0 and Miller encoding circuits, and in the S1 - S4 encoding states, the encoding operation in the current S state and subsequent state transitions will be determined according to the Mode signal. For example, when the encoded data is "1001", in the FM0 mode, if the starting state of data - 1 is set as S1, when the next encoded data received is 0, the state jumps to S3, when the next encoded data received is 0, S3 does not jump, and finally when the next encoded data received is 1, the state of S3 jumps to S4; in the Miller mode, if the starting state of data - 1 is set as S2, when the next encoded data received is 0, the state jumps to S4, when the next encoded data received is 0, the state of S4 jumps to S1, and finally when the next encoded data received is 1, the state of S3 jumps to S2. Making encoding mode judgments and divisions in the same encoding state can convert the originally independent encoding states into shared encoding states, saving the chip area of the encoding circuit design.
[0057] In summary, the low - power ultra - high - frequency tag encoding circuit provided by the embodiment of the present application can implement encoding in both FM0 and Miller encoding modes, and the FM0 and Miller encodings share the encoding module states, thereby reducing the design of the logic gate circuit inside the tag and effectively reducing the overall area of the tag chip. At the same time, the embodiment of the present application divides the encoding frequency according to different encoding modes and performs gated - clock management on each module running the transmitted data, greatly reducing the power consumption ratio of the encoding circuit in the entire tag chip circuit.
[0058] The embodiments described in the embodiment of the present application are for more clearly illustrating the technical solutions of the embodiment of the present application, and do not constitute a limitation on the technical solutions provided by the embodiment of the present application. Those skilled in the art know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiment of the present application are equally applicable to similar technical problems.
[0059] Those skilled in the art can understand that the technical solutions shown in the figure do not constitute a limitation on the embodiment of the present application, and may include more or fewer steps than those shown, or combine certain steps, or different steps.
[0060] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0061] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof.
[0062] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of this application and the above accompanying drawings are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order different from those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.
[0063] The preferred embodiments of the embodiments of this application have been described above with reference to the accompanying drawings, but this does not limit the scope of the rights of the embodiments of this application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of this application shall fall within the scope of the rights of the embodiments of this application.
Claims
1. A low-power ultra-high-frequency tag encoding circuit, characterized in that The low-power ultra-high frequency tag encoding circuit includes: A clock division circuit, which is used to divide the system clock according to the data rate corresponding to the target encoding mode to obtain an encoding clock; A gated clock circuit, which is used to control the on / off of each sub-circuit in the low-power ultra-high frequency tag encoding circuit; An encoding circuit, which is used to determine the target encoding mode according to the preset parameters in the preset query command, and encode the data to be encoded through the target encoding mode to obtain encoded output data; A data transmission control circuit, which is used to select multiple types of data to obtain the data to be encoded, synchronize the data to be encoded according to the encoding clock, serially transmit the data to be encoded to the encoding circuit, and after receiving the encoded output data returned by the encoding circuit, transmit the encoded output data to the tag reader through the antenna.
2. The low-power ultra-high frequency tag encoding circuit according to claim 1, wherein The clock division circuit includes a division coefficient calculation module and a clock division module; The division coefficient calculation module is used to calculate the division coefficient according to the calibration symbol of the preamble and the division bit rate; the clock division module is used to divide the system clock according to the division coefficient.
3. The low-power ultra-high frequency tag encoding circuit according to claim 1, wherein The data transmission control circuit includes a stored data transmission module, a random number transmission module, a check data transmission module, an encoding control module, and a transmission control module; The stored data transmission module, the random number transmission module, or the check data transmission module transmits the corresponding data to the encoding control module and the transmission control module after receiving the return command sent by the controller module; The encoding control module is used to determine the data type of the encoding circuit according to the received data; The transmission control module is used to generate an encoding control signal and select a data transmission clock, and transmit the received data to the encoding circuit.
4. The low-power ultra-high frequency tag encoding circuit according to claim 1, characterized in that The encoding circuit includes an encoding mode judgment module, a preamble encoding module, and a data encoding module; the encoding mode judgment module is used to determine the target encoding mode from several candidate encoding modes according to the preset parameters in the preset query command; the preamble encoding module is used to encode the preamble signal of the data to be encoded according to the target encoding mode; The data encoding module is used to encode the data to be encoded according to the target encoding mode after completing the encoding of the preamble signal.
5. The low-power ultra-high frequency tag encoding circuit according to claim 4, characterized in that, The candidate encoding modes include the FM0 encoding mode and the Miller encoding mode, and the Miller encoding mode includes the Miller2 encoding mode, the Miller4 encoding mode, and the Miller8 encoding mode.
6. The low-power ultra-high frequency tag encoding circuit according to claim 5, characterized in that, The FM0 encoding mode and the Miller encoding mode adopt a common encoding state mechanism.
7. The low-power ultra-high frequency tag encoding circuit according to claim 1, wherein When the encoding circuit encodes the current data to be encoded, the data transmission control circuit synchronously prepares the next set of data to be encoded.
8. The low-power ultra-high frequency tag encoding circuit according to claim 1, characterized in that, The encoded output data obtained by encoding the data to be encoded through the target encoding mode includes: Divide the data to be encoded into a preamble signal, a pre - synchronization code signal, data bits, or an end - frame signal; Encode the preamble signal, the pre - synchronization code signal, the data bits, and the end - frame signal according to the target encoding mode under the encoding clock to obtain single - bit encoded data as the encoded output data.
9. The low-power ultra-high frequency tag encoding circuit according to claim 3, characterized in that, The data - processing process of the data - transmission control circuit includes: Prepare a pre - synchronization code after receiving the TRext signal sent by the controller circuit; When adding the command - return data behind the pre - synchronization code, if it is determined that the command - return data needs to be parity - encoded, generate a parity code and add the parity code behind the command - return data, and then send the data after adding the parity code to the encoding circuit; if it is determined that the command - return data does not need to be parity - encoded, send the data after adding the command - return data to the encoding circuit; the command - return data includes the output data of the stored - data transmission module or the random - number transmission module.
10. The low-power ultra-high frequency tag encoding circuit according to claim 9, wherein, The data format sent by the data - transmission control circuit to the encoding circuit includes a first format and a second format. The first format includes pre - synchronization data, basic data, a parity code, and an end bit; the second format includes pre - synchronization data, basic data, and an end bit.