Semiconductor device

Abstract

The purpose of the present disclosure is to provide a semiconductor device capable of improving reliability. A semiconductor device according to the present disclosure includes an insulating sheet (4) on which one die pad (5) is disposed, an insulating sheet (8) on which a plurality of die pads (9) are disposed, semiconductor switches (6) and rectifier diodes (7) disposed on the die pads (5), semiconductor switches (10) and rectifier diodes (11) disposed on the respective die pads (9), and a heat sink (15) bonded to the insulating sheet (4) and the insulating sheet (8).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Conventionally, a semiconductor device including a converter circuit, a brake circuit, and an inverter circuit has been disclosed (for example, refer to Patent Document 1). In the semiconductor device disclosed in Patent Document 1, a resin-made insulating sheet is provided on one surface of a heat sink, a frame is provided on the insulating sheet, and a semiconductor chip and wires are bonded to the frame. Then, the insulating sheet, the frame, the semiconductor chip, and the wires are sealed with a molding resin. Prior Art Documents Patent Documents

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-65339 Summary of the Invention Technical Problem to be Solved by the Invention

[0004] The mechanical properties of a metal-made member and a resin-made member are different. Therefore, due to environmental stresses such as temperature and humidity, internal stresses such as shrinkage and expansion of different types of members are generated. This internal stress causes the insulating sheet to peel off from the heat sink, thereby affecting the reliability of the semiconductor device. In the semiconductor device disclosed in Patent Document 1, stress easily concentrates at the corners of the insulating sheet, etc., and thus the insulating sheet easily peels off. Accordingly, in the conventional semiconductor device, there is room for improvement in terms of improving reliability.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor device capable of improving reliability. Technical Means for Solving the Technical Problem

[0006] To solve the above problems, the semiconductor device of the present disclosure includes: a first insulating material on which a first chip pad is disposed; a second insulating material on which a plurality of second chip pads are disposed; a first semiconductor element disposed on the first chip pad; a second semiconductor element disposed on each of the second chip pads; and a heat sink joined to the first insulating material and the second insulating material. Advantageous Effects of the Invention

[0007] According to the present disclosure, reliability can be improved. Brief Description of the Drawings

[0008] Figure 1 It is a top view showing an example of the structure of the semiconductor device according to Embodiment 1. Figure 2It is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1. Figure 3 It is a cross-sectional view for explaining the internal stress in the semiconductor device according to the prior art. Figure 4 It is a top view for explaining the internal stress in the semiconductor device according to the prior art. Figure 5 It is a cross-sectional view for explaining the internal stress in the semiconductor device according to Embodiment 1. Figure 6 It is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 2. Figure 7 It is a cross-sectional view for explaining the internal stress in the semiconductor device according to Embodiment 2. Figure 8 It is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 3. Figure 9 It is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 4. Figure 10 It is a cross-sectional view for explaining the internal stress in the semiconductor device according to Embodiment 4. Detailed Embodiments

[0009] <Embodiment 1> Figure 1 It is a top view showing an example of the structure of the semiconductor device according to Embodiment 1. In addition, Figure 2 It is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0010] The semiconductor device according to Embodiment 1 includes an inverter circuit and a converter circuit 3. The inverter circuit is composed of an inverter P-side circuit 1 as the high side and an inverter N-side circuit 2 as the low side.

[0011] In the inverter P-side circuit 1, one chip pad 5 (first chip pad) is arranged on one insulating sheet 4 (first insulating material). On the chip pad 5, three pairs of semiconductor switches 6 and rectifier diodes 7, that is, a total of six semiconductor elements (first semiconductor elements) are arranged. The semiconductor switch 6 is, for example, an IGBT (Insulated Gate Bipolar Transistor). The chip pad 5 is made of, for example, copper and is a part of the frame constituting the semiconductor device.

[0012] In the inverter N-side circuit 2, three chip pads 9 (second chip pads) are arranged on an insulating sheet 8 (second insulating material). A pair of semiconductor switches 10 and rectifying diodes 11, that is, a total of two semiconductor elements (second semiconductor elements), are respectively arranged on one chip pad 9. Thus, in the inverter N-side circuit 2, similar to the inverter P-side circuit 1, a total of six semiconductor elements are arranged in the area where one insulating sheet 8 is arranged. Each chip pad 9 corresponds to the U phase, V phase, and W phase. By arranging the three chip pads 9 together on the insulating sheet 8, the cost can be reduced.

[0013] In the converter circuit 3, four chip pads 13 (third chip pads) are arranged on an insulating sheet 12 (third insulating material). Three rectifying diodes 14 are arranged on one chip pad 13 (P-side converter) among the four chip pads 13. In addition, one rectifying diode 14 (corresponding to the U phase, V phase, or W phase) is respectively arranged on the remaining three chip pads 13 (N-side converter). Thus, in the converter circuit 3, similar to the inverter P-side circuit 1 and the inverter N-side circuit 2, a total of six semiconductor elements are arranged in the area where one insulating sheet 12 is arranged. In the converter circuit 3, since there is no semiconductor switch, miniaturization can be achieved accordingly, and it is possible to make the converter circuit 3 have substantially the same size as the inverter P-side circuit 1 and the inverter N-side circuit 2. By arranging the four chip pads 13 together on the insulating sheet 12, an attempt is made to reduce the cost.

[0014] The insulating sheets 4, 8, 12 are joined to the heat sink 15. The heat sink 15 has the function of releasing the heat generated respectively in the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 to the outside. In order to improve the heat dissipation performance, the heat sink 15 can be made of a metal material such as aluminum.

[0015] The molding resin 16 (sealing resin) seals the insulating sheets 4, 8, 12, the chip pads 5, 9, 13, the semiconductor switches 6, 10, and the rectifying diodes 7, 11, 13. The molding resin 16 has insulation properties and can be made of, for example, epoxy resin.

[0016] In addition, in a top view, the area of the insulating sheet 4 in the inverter P-side circuit 1 is preferably 90% or more and 110% or less of the area of the insulating sheet 8 in the inverter N-side circuit 2. By making the area of the insulating sheet 4 substantially the same as the area of the insulating sheet 8, the surface characteristics of the insulating sheet 4 and the insulating sheet 8 are substantially the same. Thus, the internal stress of the semiconductor device can be made uniform, and a semiconductor device resistant to environmental stress can be achieved.

[0017] When viewed from above, the area of the insulating sheet 12 in the converter circuit 3 is preferably 90% or more and 110% or less of the area of the insulating sheet 4 in the inverter P-side circuit 1 or the area of the insulating sheet 8 in the inverter N-side circuit 2. By making the area of the insulating sheet 4 substantially the same as the area of the insulating sheet 12, the surface characteristics of the insulating sheet 4 and the insulating sheet 12 are substantially the same. Thereby, the internal stress of the semiconductor device can be made uniform, and a semiconductor device resistant to environmental stress can be realized.

[0018] Although not shown, in the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3, wiring is performed using any material such as wires and electrodes to form a circuit.

[0019] Although not shown, the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 each have external terminals for electrically connecting to the outside. The molding resin 16 seals the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 so that the external terminals are exposed to the outside. The inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 each output current or a control signal to the outside of the molding resin 16 via the external terminals.

[0020] Although not shown, the semiconductor device according to Embodiment 1 may have a structure further including a brake circuit. In this case, the semiconductor device may include a pair of semiconductor switches and a pair of rectifier diodes constituting the brake circuit. The brake circuit may be formed on any one of the insulating sheet 4 in the inverter P-side circuit 1, the insulating sheet 8 in the inverter N-side circuit 2, and the insulating sheet 12 in the converter circuit 3, but is preferably formed on the insulating sheet 12 in the converter circuit 3.

[0021] Between the chip pads 5 in the inverter P-side circuit 1, the chip pads 9 in the inverter N-side circuit 2, and the chip pads 13 in the converter circuit 3 and the heat sink 15, the insulating sheets 4, 8, and 12 are in close contact without gaps, respectively, so as to ensure Figure 2 a heat dissipation path with low thermal resistance in the vertical direction ( Figure 2 the wavy arrows in). Here, the chip pads 5, the chip pads 9, and the chip pads 13 are also referred to as concentrated heat dissipation chip pads. The concentrated heat dissipation chip pads may be arranged at intervals so as not to interfere with each other thermally.

[0022] The insulating sheets 4, 8, and 12 are divided and arranged according to each concentrated heat dissipation chip pad. By making the width of the region where the insulating sheets 4, 8, and 12 are divided narrower than the distance between the concentrated heat dissipation chip pads, the insulating distance between the concentrated heat dissipation chip pads and the heat sink 15 is ensured.

[0023] When the semiconductor device operates, heat is generally generated in the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3. Since the semiconductor elements in each of the above circuits perform similar operations independently, the heat generation amounts are almost the same. However, since the operations of the semiconductor elements in each circuit are different, the heat generation amounts in each circuit are different. Therefore, thermal interference may occur between the circuits serving as heat sources. For example, heat is transferred from the inverter P-side circuit 1 to the inverter N-side circuit 2 and the converter circuit 3 via the heat sink 15. In addition, the opposite situation may also occur.

[0024] To effectively release the heat generated by the semiconductor device to the outside, it is ideal to transfer heat in the vertical direction while minimizing thermal interference with adjacent chip pads. In the semiconductor device according to Embodiment 1, the mutual interference of the heat generated in the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 is reduced, and a heat dissipation path for transferring to the heat sink 15 via the insulating sheet directly below the chip pad is ensured. Thereby, the non-uniform temperature distribution in the insulating sheet caused by the uneven heat generation of the semiconductor elements can be suppressed.

[0025] Since the linear expansion coefficients of the various materials constituting the semiconductor device are non-uniform, it is inevitable that the semiconductor device warps due to environmental stress. Environmental stress includes temperature gradients caused by the heat generation of the semiconductor elements constituting the semiconductor device, external temperature changes, humidity, etc. When the semiconductor device is subjected to environmental stress, internal stress is generated due to the relative position changes between the chip pads 5, 9, 13, the insulating sheets 4, 8, 12, the heat sink 15, and the molding resin 16. In particular, when stress is generated at the bonding interfaces between the insulating sheets 4, 8, 12 and the heat sink 15 and between the insulating sheets 4, 8, 12 and the chip pads 5, 9, 13, the insulating sheets 4, 8, 12 are peeled off, and this peeling gradually expands, eventually leading to peeling of the entire surface.

[0026] Figure 3 is a cross-sectional view for explaining the internal stress in the semiconductor device according to the prior art. In addition, Figure 4 is a top view for explaining the internal stress in the semiconductor device according to the prior art. Additionally, in Figure 3 the illustration of the semiconductor elements is omitted. In the semiconductor device according to the prior art, an insulating sheet 17 is disposed on the heat sink 15. In Figure 3 the white arrows indicate the stress directions, and the black arrows indicate the intensities of the internal stress.

[0027] As Figure 3 and 4As shown, compared with the central part of the insulating sheet 17, stress is more likely to concentrate at the end parts such as the corners and side parts of the insulating sheet 17. Therefore, such end parts usually become the peeling starting points 18. The larger the size of the semiconductor device, the more likely it is to warp, and the internal stress also increases.

[0028] On the other hand, as Figure 5 shown, in the semiconductor device according to Embodiment 1, the internal stress caused by the overall warping is locally applied to the insulating sheet 4 in the inverter P-side circuit 1, the insulating sheet 8 in the inverter N-side circuit 2, and the insulating sheet 12 in the converter circuit 3, respectively. However, in the semiconductor device according to Embodiment 1, compared with the single insulating sheet 17 included in the semiconductor device according to the prior art (refer to Figure 3 and Figure 4 ), each of the insulating sheets 4, 8, and 12 does not pull on each other. Therefore, the stress in the gap part between the end parts of the insulating sheets 4, 8, and 12 and the chip pads 5, 9, and 13 is alleviated. As a result, it is possible to prevent the peeling of the insulating sheets 4, 8, and 12 without damaging the bonding interface between the heat sink 15 and the insulating sheets 4, 8, and 12. In addition, in Figure 5 , the illustration of the semiconductor element is omitted.

[0029] Although it is also possible to consider a method of using an insulating sheet as a resin component with high adhesion to improve the bonding strength, in most cases, it is technically difficult because it will lead to an increase in cost or sacrifice other characteristics. According to Embodiment 1, a highly reliable semiconductor device can be achieved by using existing materials.

[0030] <Embodiment 2> Figure 6 is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 2.

[0031] As Figure 6 shown, the semiconductor device according to Embodiment 2 is characterized in that it is divided into three heat sinks 19, 20, and 21 by the regions between the insulating sheets 4, 8, and 12. In addition, in Figure 6 , although the illustration of the semiconductor element is omitted, it is the same as in Embodiment 1 (refer to Figure 1 and Figure 2 ).

[0032] Specifically, the heat sinks 19 and 20 are divided by the region between the insulating sheets 4 and 12. In addition, the heat sinks 20 and 21 are divided by the region between the insulating sheets 4 and 8.

[0033] Figure 7 is a cross-sectional view for explaining the internal stress in the semiconductor device according to Embodiment 2. In addition, in Figure 7Although the illustration of the semiconductor element is omitted, it is the same as that of the first embodiment (see Figure 1 , 2 ). In Figure 7 , the white arrow indicates the stress direction, and the black arrow indicates the intensity of the internal stress.

[0034] When the semiconductor device operates, the molding resin 16 absorbs moisture from the environment and expands, while the heat sink 15 hardly expands. In the semiconductor device according to the second embodiment, since it is divided into three heat sinks 19, 20, and 21, even when the molding resin 16 expands and the semiconductor device warps, the divided heat sinks 19, 20, and 21 can easily follow the expansion direction of the molding resin 16, so that the stress applied to the insulating sheets 4, 8, and 12 is relieved. As a result, the bonding interface between the insulating sheets 4, 8, and 12 and the heat sinks 19, 20, and 21 is not damaged, and thus the peeling of the insulating sheets 4, 8, and 12 can be prevented.

[0035] <Embodiment 3> Figure 8 FIG. is a cross-sectional view showing an example of the structure of the semiconductor device according to the third embodiment.

[0036] As Figure 8 shown, the semiconductor device according to the third embodiment is characterized in that the heat sink 22 is comb-shaped. In addition, in Figure 8 , although the illustration of the semiconductor element is omitted, it is the same as that of the first embodiment (see Figure 1 , 2 ). In Figure 8 , the black arrow indicates the intensity of the internal stress.

[0037] Specifically, the heat sink 22 has recesses (grooves) in the regions between the insulating sheet 4 and the insulating sheet 8, and between the insulating sheet 4 and the insulating sheet 12. The recesses are provided on the surface side of the heat sink 22 to which the insulating sheets 4, 8, and 12 are bonded.

[0038] With this configuration, like the semiconductor device according to the second embodiment, the heat sink 22 can easily follow the warping of the semiconductor device due to temperature change or moisture absorption, and since the heat sink 22 is formed by connecting a single metal plate, the number of components can be reduced without increasing, which helps to simplify the assembly process.

[0039] <Embodiment 4> Figure 9 FIG. is a cross-sectional view showing an example of the structure of the semiconductor device according to the fourth embodiment.

[0040] As Figure 9 shown, the semiconductor device according to the fourth embodiment is characterized in that the heat sink 23 is comb-shaped. In addition, inFigure 9 Although the illustration of the semiconductor element is omitted, it is the same as that of the first embodiment (see Figure 1 , 2 ).

[0041] Specifically, the heat sink 23 has a recess (groove) on the surface side opposite to the surface to which the insulating sheet 17 is joined.

[0042] In Figure 3 the semiconductor device according to the prior art shown, when the molding resin 16 absorbs moisture and expands, the heat sink 15 resists this expansion and thus applies stress to the insulating sheet 17.

[0043] On the other hand, in the semiconductor device according to the fourth embodiment, as Figure 10 shown, by providing a recess in the heat sink 23, the heat sink 23 is likely to warp along the expansion direction of the molding resin 16. Therefore, the effect of relieving the internal stress of the semiconductor device can be obtained. In addition, in Figure 10 , the white arrow indicates the stress direction. In Figure 10 Although the illustration of the semiconductor element and the chip pad is omitted, it is the same as that of the first embodiment (see Figure 1 , 2 ).

[0044] In addition, in the semiconductor device according to the fourth embodiment, like the semiconductor device according to the first embodiment, the insulating sheet 17 can be divided into insulating sheets 4, 8, and 12. Specifically, the heat sink 23 has recesses (grooves) in the regions between the insulating sheet 4 and the insulating sheet 8, and between the insulating sheet 4 and the insulating sheet 12. The recesses are provided on the surface side opposite to the surface of the heat sink 23 to which the insulating sheets 4, 8, and 12 are joined. In this case, the internal stress can be further relieved. However, even when using a single insulating sheet 17, the same effect can be expected. In addition, when the insulating sheet 17 is divided like the insulating sheets 4, 8, and 12, it is not necessary to make the division positions of the insulating sheets 4, 8, and 12 coincide with the positions of the recesses of the heat sink. The heat sink 23 can have two or more recesses.

[0045] <Modifications of the First to Fourth Embodiments> In the first to fourth embodiments, the case of using an insulating sheet as a member for insulating each of the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 from the outside has been described. However, as long as it can be insulated from the outside, it is not limited to the insulating sheet. For example, a ceramic insulating substrate can be used as a member for insulating from the outside.

[0046] In addition, within the scope of the present disclosure, the respective embodiments can be freely combined, or the respective embodiments can be appropriately modified or omitted.

[0047] <Supplementary Note> Hereinafter, each aspect of the present disclosure is summarized and described as supplementary notes.

[0048] (Supplementary Note 1) A semiconductor device, comprising: a first insulating material on which a first chip pad is disposed; a second insulating material on which a plurality of second chip pads are disposed; a first semiconductor element disposed on the first chip pad; a second semiconductor element disposed on each of the second chip pads; and a heat sink joined to the first insulating material and the second insulating material. (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the second insulating material is provided with at least three of the second chip pads. (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein, in a plan view, the area of the first insulating material is 90% or more and 110% or less of the area of the second insulating material. (Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, further comprising a third insulating material on which a plurality of third chip pads are disposed, the heat sink being joined to the third insulating material. (Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein the third insulating material is provided with at least four of the third chip pads. (Supplementary Note 6) The semiconductor device according to Supplementary Note 4 or 5, wherein, in a plan view, the area of the third insulating material is 90% or more and 110% or less of the area of the first insulating material or the second insulating material. (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the heat sink has a recess in a region between the first insulating material and the second insulating material. (Supplementary Note 8) The semiconductor device according to Supplementary Note 7, wherein the recess is provided on a surface side of the heat sink to which the first insulating material and the second insulating material are joined. (Supplementary Note 9) The semiconductor device according to Note 7, wherein the recess is provided on a surface side of the heat sink opposite to the surface to which the first insulating material and the second insulating material are bonded. (Note 10) The semiconductor device according to any one of Notes 4 to 6, further comprising an insulating encapsulating resin that encapsulates the first insulating material, the second insulating material, the third insulating material, the first chip pad, the second chip pad, the third chip pad, the first semiconductor element, and the second semiconductor element. Reference Signs

[0049] 1 Inverter P-side circuit, 2 Inverter N-side circuit, 3 Converter circuit, 4 Insulating sheet, 5 Chip pad, 6 Semiconductor switch, 7 Rectifier diode, 8 Insulating sheet, 9 Chip pad, 10 Semiconductor switch, 11 Rectifier diode, 12 Insulating sheet, 13 Chip pad, 14 Rectifier diode, 15 Heat sink, 16 Molding resin, 17 Insulating sheet, 18 Starting point of peeling, 19 Heat sink, 20 Heat sink, 21 Heat sink, 22 Heat sink, 23 Heat sink.

Claims

1. A semiconductor device, characterized in that, Comprising: A first insulating material configured with a first chip pad; A second insulating material configured with a plurality of second chip pads; A first semiconductor element disposed on the first chip pad; A second semiconductor element disposed on each of the second chip pads; and A heat sink joined to the first insulating material and the second insulating material.

2. The semiconductor device according to claim 1, wherein The second insulating material is configured with at least three of the second chip pads.

3. The semiconductor device according to claim 1, wherein In a top view, the area of the first insulating material is 90% or more and 110% or less of the area of the second insulating material.

4. The semiconductor device according to claim 1 or 2, wherein Further comprising a third insulating material configured with a plurality of third chip pads, The heat sink is joined to the third insulating material.

5. The semiconductor device according to claim 4, wherein The third insulating material is configured with at least four of the third chip pads.

6. The semiconductor device according to claim 4, wherein In a top view, the area of the third insulating material is 90% or more and 110% or less of the area of the first insulating material or the second insulating material.

7. The semiconductor device according to any one of claims 1 to 3, wherein The heat sink has a recess in a region between the first insulating material and the second insulating material.

8. The semiconductor device according to claim 7, wherein The recess is provided on a surface side of the heat sink to which the first insulating material and the second insulating material are joined.

9. The semiconductor device according to claim 7, wherein The recess is provided on a surface side of the heat sink opposite to the surface to which the first insulating material and the second insulating material are joined.

10. The semiconductor device according to claim 4, wherein Further comprising an insulating encapsulating resin that encapsulates the first insulating material, the second insulating material, the third insulating material, the first chip pad, the second chip pad, the third chip pad, the first semiconductor element, and the second semiconductor element.

Images