Biasing techniques for low distortion amplifiers

Abstract

The invention relates to bias techniques for low distortion amplifiers. Biasing techniques for reducing amplifier distortion are described. The adjusting loop is used for keeping the sum of collector currents input into the differential pair constant. The regulation loop includes an error correction amplifier that compares the sum of the input differential pair of collector currents with a reference current and regulates the control voltage at the transistor control terminals to maintain the current equal to or proportional to the reference current.

Description

Technical Field

[0001] This document relates to electronic circuit design, and more particularly, to techniques for biasing amplifier circuits. Background Art

[0002] Low-distortion amplifiers are an important component in many analog and mixed-signal systems. For example, they are widely used in the analog front-ends of high-resolution ADCs and DACs. In these applications, the amplifier needs to faithfully preserve the amplitude and phase information of the signal without introducing additional harmonics.

[0003] There are several non-ideal factors that can cause an amplifier to distort the signal, such as bias current modulation, non-linearity in transistors, noise, etc. Bias current modulation is one of the main distortion mechanisms in certain amplifier topologies. It occurs because the bias current of the input differential pair can be modulated with the input signal or other signals, resulting in signal-dependent distortion.

[0004] To mitigate this problem, certain biasing techniques and compensation methods have been developed. These techniques generally aim to keep the bias current and / or the operating point of key transistors constant during signal swings. Some common methods include using regulated cascode circuits, incorporating negative feedback, and adding correction circuits to eliminate the distortion-causing mechanisms.

[0005] By carefully analyzing the root causes of distortion and designing compensation methods, the total harmonic distortion (THD) performance of the amplifier can be significantly improved. Low-distortion amplifiers with THD of -100 dB or below have been demonstrated. These ultra-low distortion amplifiers enable high-performance data conversion and signal conditioning systems. Summary of the Invention

[0006] The present invention relates to a biasing technique for reducing distortion in an amplifier. The inventors have recognized that a regulation loop can be used to keep the sum of the collector currents of the input differential pair constant. The regulation loop includes an error correction amplifier that compares the sum of the collector currents of the input differential pair with a reference current and adjusts the control voltage at the control terminal of the transistor to keep the current equal to or proportional to the reference current.

[0007] In some aspects, the present disclosure relates to an amplifier circuit, comprising: a differential transistor pair configured and arranged to generate a summing current from a single transistor in the differential transistor pair; a transistor coupled to the differential transistor pair; and an error correction amplifier coupled to the control terminal of the transistor and configured to: compare a representation of the summing current with a representation of a reference current; and based on the comparison, adjust the voltage at the control terminal of the transistor.

[0008] In some aspects, the present invention relates to a method for a biased amplifier circuit, the method comprising: coupling a transistor to a differential transistor pair; generating a summing current from the differential transistor pair; comparing a representation of the summing current with a representation of a reference current using an error correction amplifier coupled to a control terminal of the transistor; and adjusting a voltage at the control terminal of the transistor based on the comparison and using the error correction amplifier.

[0009] In some aspects, the present disclosure relates to an amplifier circuit, comprising: a differential transistor pair configured and arranged to generate a summing current from a single transistor in the differential transistor pair, the differential transistor pair having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, wherein the differential transistor pair is configured and arranged to generate a summing current; a transistor coupled to the differential transistor pair, the transistor having a third control terminal; a first sense resistor coupled to the differential transistor pair, wherein the first sense resistor is configured to generate a first voltage in response to the summing current from the differential transistor pair; a reference current source coupled to the transistor and configured to generate a reference current; a second sense resistor coupled to the reference current source, wherein the second sense resistor is configured to generate a second voltage in response to the reference current; and an error correction amplifier having: a non-inverting input coupled to the first sense resistor and configured to receive the first voltage generated by the first sense resistor; and an inverting input coupled to the second sense resistor and configured to receive the second voltage generated by the second sense resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, which are not necessarily to scale, the same numbers may describe similar components in different views. Similar numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0011] Figure 1 is a schematic diagram of an example of an operational amplifier circuit.

[0012] Figure 2 is an example of an existing amplifier circuit.

[0013] Figure 3 is a schematic diagram of an example of an amplifier circuit that can implement the various techniques of the present disclosure.

[0014] Figure 4 is a schematic diagram of another example of an amplifier circuit that can implement the various techniques of the present disclosure.

[0015] Figure 5It is a schematic diagram of another example of an amplifier circuit that can implement various technologies of the present disclosure.

[0016] Figure 6 It shows one aspect of the subject matter according to one embodiment.

[0017] Figure 7 It is a flowchart of an example of a method for operating an amplifier circuit. Detailed Description

[0018] The inventors have recognized that amplifier distortion may occur when the bias current of the input differential pair is modulated with the input signal. This modulation is caused by the finite output impedance of the bias current source and the parasitic capacitance that couples the signal to the bias node.

[0019] The present invention relates to a bias technique for reducing distortion in an amplifier. The inventors have recognized that an adjustment loop can be used to keep the sum of the collector currents of the input differential pair constant. The adjustment loop includes an error correction amplifier that compares the sum of the collector currents of the input differential pair with a reference current and adjusts the control voltage at the control terminal of the transistor to keep the current equal to or proportional to the reference current.

[0020] Figure 1 It is a schematic diagram of an example of an operational amplifier circuit. The operational amplifier circuit 100 is configured for single-ended to differential conversion. In this configuration, the reference voltage VREF is at a fixed DC voltage, and the input node is receiving a time-varying input signal VIN. Therefore, both the VP and VN nodes vary with the input signal VIN. Although many non-idealities cause distortion, bias current modulation is one of the main sources of distortion in this configuration.

[0021] Figure 2 It is an example of an existing amplifier circuit. Regarding Figure 2 the amplifier circuit 200, the origin of tail current modulation and distortion is described as follows. For simplicity,

[0022] Summation

[0023] V in (t) = V in cos(ωt) [1]

[0024] where V in is the amplitude of the input signal and ω is the signal frequency. The voltage at the non-inverting node of the operational amplifier is given by:

[0025] V p (t) = V p cos(ωt) [2]

[0026] where V pis the amplitude, which is the scaled version V in , depending on R G 、R F and V ocm .

[0027] In addition, the differential voltage between the non-inverting node and the inverting node is approximately

[0028] V dm (t) = V dm cos(ωt) [3]

[0029] where V dm is the amplitude of the differential signal, which is a function of the output voltage V (vop，von) at the signal frequency and the loop gain A L (s).

[0030]

[0031] For simplicity, assume that V in (t), V p (i), and V dm (t) are in phase, i.e., the phase shift is ignored. To maintain reasonably low distortion, V dm is usually less than 10 millivolts. The voltage V p is usually much greater than V dm , so the operational amplifier common-mode voltage can be approximated as the voltage at the non-inverting node, or:

[0032] V cm (t) = V p cos(ωt) [5]

[0033] Figure 2 The collector currents of the transistors Q1 and Q2 in the input stage of

[0034]

[0035] are given by:

[0036]

[0037] The result of the exponential function expansion is as follows:

[0038]

[0039] According to equations [9] and

[10] , the following results can be obtained:

[0040]

[0041] Assume that V dm << VT , then,

[0042]

[0043] According to equations [8],

[13] ,

[14] , and assuming β >> 1, we find that

[0044]

[0045] As long as V dm (t) is small enough compared to the threshold voltage V T , the above approximations given by equations

[13] and

[14] will result in negligible errors. In a non - restrictive numerical example, assume that at room temperature V dm (t) = 10 mV, then and the error is only 0.5%. At the same time this will only result in an error of 1.8%.

[0046] Due to the finite early voltage of Q3 and the parasitic capacitance at node E, the bias current of the input differential pair is a non - linear function of the common - mode voltage V cm (t) with coefficients g1, g2, …, g n . The tail current is given by the following equation:

[0047] I tail (t) = I dc + g1V cm (t) + g2V m 2 (t) + g3V m 3 (t) + …

[16]

[0048] For simplicity, temporarily ignore the higher - order harmonic components, and thus assume the following:

[0049] I tail (t) ≈ I dc + g1V cm (t)

[17]

[0050] Combining equations

[15] and

[17] gives the following result:

[0051]

[0052] According to equations [3], [5], and

[18] ,

[0053]

[0054] Therefore,

[0055]

[0056] Therefore, the intermodulation between the bias current and the voltage across the input differential pair results in second-order harmonics and DC offset. In the above derivation, only the DC component and the fundamental component of the bias current are considered. If its higher-order harmonics are included in the analysis, the total harmonic distortion will be more serious. Therefore, in order to design a low-distortion amplifier, it is crucial to suppress the bias current modulation.

[0057] In the above analysis, the base-collector capacitance C of the input transistor is ignored. μ In addition to being process-related, the capacitance is linearly proportional to the device size and has a non-linear relationship with the reverse bias voltage of the base-collector junction.

[0058] Figure 3 FIG. is a schematic diagram of an example of an amplifier circuit that can implement various techniques of the present disclosure. In the input stage, an adjustment loop is used to keep the sum of the collector currents of the input differential pair constant. The adjustment loop includes at least an input differential pair, a reference current, a sense resistor, an error correction amplifier, and a transistor, such as a transfer transistor. Figure 3 The illustrated amplifier circuit 300 includes bipolar junction transistors.

[0059] The amplifier circuit 300 includes a differential transistor pair, and the differential transistor pair includes transistor Q1 and transistor Q2. Transistor Q1 is configured to receive a positive input voltage Vp, and transistor Q2 is configured to receive a negative input voltage Vn. The differential pair configuration and arrangement of transistors Q1 and Q2 are configured to generate a summing current from a single transistor in the differential transistor pair at node 302.

[0060] In some examples, the amplifier circuit 300 includes a first sense resistor Rs coupled to the differential transistor pair, where the first sense resistor Rs is configured to generate a representation of the summing current at node 302 from the differential transistor pair.

[0061] The amplifier circuit 300 further includes a transistor Q3, such as a transfer transistor, coupled to the differential transistor pair. For example, the emitter terminals of the differential transistor pair are coupled together at node E, and node E is also coupled to the collector terminal of transistor Q3.

[0062] The error correction amplifier 304 is coupled to the control terminal 310 (e.g., the base terminal) of the transistor Q3. The total current of the input differential transistor pair is sensed, e.g., by the sense resistor Rs, and applied to the non-inverting input of the error correction amplifier 304. The error correction amplifier 304 compares a representation of the sum current with a representation of a reference current applied to the inverting input of the error correction amplifier 304, e.g., a reference current generated by the reference current source 306. In some examples, the amplifier circuit 300 includes a second sense resistor Rr coupled to the reference current source 306, where the second sense resistor is configured to generate a representation of the reference current.

[0063] As Figure 3 seen in the example shown, the reference current source 306 is coupled to the control terminal 310 of the transistor Q3, e.g., the emitter of the transistor. Then, the error correction amplifier 304 adjusts the control voltage of the transistor Q3, e.g., the base voltage, based on the comparison result to maintain the current equal to or proportional to the reference current.

[0064] In some examples, the collector of the transistor Q1 is coupled to the first resistor Rd, and the collector of the transistor Q2 is coupled to the second resistor Rd.

[0065] The amplifier circuit 300 further includes a gain stage 308 configured to receive the differential output voltage Vod generated between the collector of the transistor Q1 and the collector of the transistor Q2. The gain stage 308 generates a differential output voltage Vop and Von.

[0066] In this way, Figure 3 the amplifier circuit 300 provides a low-distortion input stage with bias current regulation and has at least three advantages compared to the prior art: 1) higher output impedance; 2) wider input common-mode range; 3) insensitive to parasitic capacitances at the emitters of Q1, Q2 and the collector of Q3.

[0067] The displacement current through the capacitor exceeds the Figure 2 regulation loop in Figure 5 thereby reducing the total harmonic distortion (THD). To further improve the THD, as

[0068] Figure 4 shown, a second transistor pair is included, e.g., replicas of the input transistors Q1 and Q2. The replicas re-modulate the reference current of the regulation loop, thereby canceling the base-collector capacitance current of the input differential pair. Figure 4 includes features similar to those shown and described above with respect to Figure 3 shown and described, and like reference numerals are used for these features. For brevity, these features will not be described in detail again.

[0069] In Figure 4 the example shown, compared to the bipolar junction transistor (BJT) of the amplifier circuit 300 of Figure 3 , the amplifier circuit 400 includes a field effect transistor (FET). Specifically, Figure 4 the differential transistor pair in Figure 3 includes FETs M1 and M2, and the BJT Q3 of Figure 3 is replaced by FET M3. The source terminals of FETs M1 and M2 are connected at node E, and node E is coupled to the drain terminal of FET M3.

[0070] The error correction amplifier 304 is coupled to the control terminal 310 (e.g., the gate terminal) of FET M3. The operation of the amplifier circuit 400 is similar to that of the amplifier circuit 300 of Figure 3 and will not be described in detail for the sake of brevity.

[0071] Figure 5 is a schematic diagram of another example of an amplifier circuit in which the various techniques of the present disclosure can be implemented. Figure 5 includes features similar to those shown and described above with respect to Figure 3 and like reference numerals are used for these features. For the sake of brevity, these features will not be described in detail.

[0072] The amplifier circuit 500 includes a second transistor pair Q1d and Q2d. The transistor Q1d has a control terminal 502 coupled to the control terminal 504 of the transistor Q1 of the differential transistor pair. The transistor Q2d has a control terminal 506 coupled to the control terminal 508 of the transistor Q2 of the differential transistor pair. The control terminal 502 of the transistor Q1d is configured to receive an input signal Vp, and the control terminal 506 of the transistor Q2d is configured to receive an input signal Vn.

[0073] The first summing current generated by the input differential transistor pair is sensed, e.g., by a sense resistor Rs, and is applied to the non-inverting input of the error correction amplifier 304. Similar to the differential pair of transistors Q1 and Q2, the pair of transistors Q1d and Q2d is configured and arranged to generate a second summing current from a single transistor of Q1 and Q2d at node 510. The summing current at node 510, together with a reference current from the reference current source 306, is applied to the inverting input of the error correction amplifier 304.

[0074] The error correction amplifier 304 compares a representation of the first summing current with the representation of the reference current and the sum of the second summing current. As in Figure 5In the example shown, reference current source 306 is coupled to control terminal 310 of transistor Q3, such as the emitter of the transistor. Error correction amplifier 304 then adjusts the control voltage, such as the base voltage, of transistor Q3 based on the comparison result to keep the current equal to or proportional to the reference current.

[0075] In some examples, the amplifier circuit 300 includes a second sense resistor Rr coupled to the reference current source 306 , wherein the second sense resistor is configured to generate a representation of the reference current.

[0076] In some examples, a single transistor in the second pair of transistors is a replica of a single transistor in the first differential transistor pair. That is, transistors Q1d and Q2d are replica transistors of transistors Q1 and Q2. A "replica transistor" refers to a transistor that is designed and configured to mirror the electrical characteristics and behavior of another transistor in a circuit. This includes having substantially the same size and layout as the target transistor, ensuring that the performance of the replica transistor closely matches the performance of the target transistor under a variety of operating conditions.

[0077] Transistor pairs Q1d and Q2d are included, i.e., replicas of input transistors Q1 and Q2, to further improve THD. These replicas re-modulate the reference current of the regulation loop, thereby canceling the base-collector capacitance current of the input differential pair Q1 and Q2.

[0078] Figure 6 is a schematic diagram of another example of an amplifier circuit that may implement the various techniques of this disclosure. Figure 6 Including the above reference Figure 5 Similar features are shown and described, and similar reference numerals are used for these features. For the sake of brevity, these features will not be described in detail.

[0079] exist Figure 6 In the example shown, Figure 5 Compared to the bipolar junction transistor (BJT) of the amplifier circuit 500, the amplifier circuit 600 includes a field effect transistor (FET). Specifically, Figure 6 The differential transistor pair in includes FETs M1 and M2 coupled to FETs M1d and M2d, respectively, and Figure 5 The BJT Q3 is replaced by the FET M3. The source terminals of the FETs M1 and M2 are connected at a node E, and the node E is coupled to the drain terminal of the FET M3.

[0080] The error correction amplifier 304 is coupled to the control terminal 310 (eg, gate terminal) of the FET M3. The operation of the amplifier circuit 600 is similar to Figure 5 For the sake of brevity, the amplifier circuit 500 will not be described in detail.

[0081] Figure 7 It is a flowchart of an example of a method 700 for an operational amplifier circuit. At block 702, method 700 includes coupling a transistor to a differential transistor pair.

[0082] At block 704, method 700 includes generating a summing current from the differential pair of transistors.

[0083] At block 706, method 700 includes comparing a representation of the summing current with a representation of a reference current using an error correction amplifier coupled to a control terminal of the transistor.

[0084] At block 708, method 700 includes adjusting a voltage at the control terminal of the transistor based on the comparison and using the error correction amplifier.

[0085] In some examples, method 700 includes coupling a first sense resistor to the differential transistor pair to generate a representation of the summing current from the differential transistor pair.

[0086] In some examples, method 700 includes coupling a reference current source to the transistor and generating a reference current through the reference current source.

[0087] In some examples, method 700 includes coupling a second sense resistor to the reference current source to generate a representation of the reference current.

[0088] In some examples, the differential transistor pair is a first differential transistor, where the first differential pair transistor has a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and where the summing current is a first summing current, and method 700 further includes: coupling a second pair of transistors having a first control terminal to the first control terminal of the first differential transistor pair; coupling the second control terminal to the second control terminal of the first differential transistor pair; receiving the first input signal via the first control terminal of the second pair of transistors; receiving the second input signal via the second control terminal of the second pair of transistors; generating a second summing current from a single one of the second pair of transistors via the second pair of transistors, where comparing the representation of the summing current with the representation of the reference current using the error correction amplifier includes: comparing the first summing current representation with the sum of the reference voltage and the representation of the second summing current.

[0089] In some examples, coupling the transistor to the differential transistor pair includes coupling a bipolar junction transistor to a differential bipolar junction transistor pair.

[0090] In some examples, coupling the transistor to the differential transistor pair includes coupling a field effect transistor to a differential field effect transistor pair.

[0091] Various Annotations

[0092] Each non - limiting claim or example described herein can exist independently, or can be arranged or combined in various ways with one or more other examples.

[0093] The detailed description above includes references to the accompanying drawings that form a part of the detailed description. The drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". These examples may include elements in addition to those shown or described. However, the inventors also contemplate examples that provide only those elements shown or described. In addition, the inventors also contemplate examples that use any combination or permutation of those elements (or one or more of their claims), whether with respect to a particular example (or one or more of its other claims), or with respect to other examples (or one or more of their claims) shown or described herein.

[0094] If there is any inconsistency in the usage between this document and any document incorporated by reference, the usage in this document shall prevail.

[0095] In this document, the terms "a" or "an", which are common in patent documents, are used to include one or more, independent of any other instance or usage of "at least one" or "one or more". In this document, the term "or" is used to refer to non - exclusivity, such that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise stated. In this document, the terms "comprising" and "wherein" are used as the plain - English equivalents of the respective terms "including" and "in which". Further, in the following claims, the terms "comprising" and "including" are open - ended, that is, a system, apparatus, article, composition, formulation, or method that includes other elements in addition to those listed after such terms in the claims is still considered to fall within the scope of that claim. Further, in the following claims, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0096] The method examples described herein can be implemented, at least in part, by a machine or a computer. Some examples can include a computer-readable medium or a machine-readable medium encoded with instructions that are operable to configure an electronic device to perform the methods described in the above examples. The implementation of such methods can include code, such as microcode, assembly language code, high-level language code, etc. Such code can include computer-readable instructions for performing various methods. The code can form part of a computer program product. Further, in one example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or otherwise. Examples of such tangible computer-readable media can include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0097] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more of their claims) can be used in combination with each other. Other embodiments can be used, such as by those of ordinary skill in the art after reading the above description. The abstract is provided to comply with 37 C.F.R. § 1.72(b) so that readers can quickly ascertain the nature of the technical disclosure. The submission of this document is on the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Also, in the above detailed description, various features can be combined to simplify the disclosure. This should not be construed to mean that the unclaimed disclosed features are essential to any claim. Rather, the subject matter of the invention may lie in less than all of the features of a particular disclosed embodiment. Thus, the following claims are incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. An amplifier circuit, comprising: A differential transistor pair configured and arranged to generate a summing current from a single transistor in the differential transistor pair; A transistor coupled to the differential transistor pair; And An error correction amplifier coupled to a control terminal of the transistor and configured to: Compare a representation of the summing current with a representation of a reference current; And Based on the comparison, adjust a voltage at the control terminal of the transistor.

2. The amplifier circuit according to claim 1, comprising: A first sense resistor coupled to the differential transistor pair, wherein the first sense resistor is configured to generate a representation of the summing current from the differential transistor pair.

3. The amplifier circuit according to claim 1, comprising: A reference current source coupled to the transistor and configured to generate the reference current.

4. The amplifier circuit according to claim 3, comprising: A second sense resistor coupled to the reference current source, wherein the second sense resistor is configured to generate a representation of the reference current.

5. The amplifier circuit according to claim 1, wherein the differential transistor pair comprises bipolar junction transistors.

6. The amplifier circuit according to claim 1, wherein the differential transistor pair comprises field effect transistors.

7. The amplifier circuit according to claim 1, wherein the differential transistor pair is a first differential transistor pair, wherein the first differential transistor pair has a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and wherein the summing current is a first summing current, and the amplifier circuit further comprises: A second transistor pair, a first control terminal of which is coupled to the first control terminal of the first differential transistor pair, and a second control terminal of which is coupled to the second control terminal of the first differential transistor pair, the first control terminal of the second transistor pair receiving the first input signal, and the second control terminal of the second transistor pair receiving the second input signal, Wherein the second transistor pair is configured and arranged to generate a second summing current from a single transistor in the second transistor pair, and Wherein the error correction amplifier configured to compare a representation of the summing current with a representation of the reference current is configured to: Compare the representation of the first summing current with the representation of the reference current and the sum of the second summing current.

8. The amplifier circuit according to claim 7, wherein the single transistor in the second transistor pair is a replica of the single transistor in the first differential transistor pair.

9. A method for biasing an amplifier circuit, the method comprising: Coupling a transistor to a differential transistor pair; Generating a summing current from the differential transistor pair; Using an error correction amplifier coupled to a control terminal of the transistor to compare a representation of the summing current with a representation of the reference current; And Based on the comparison and using the error correction amplifier to adjust a voltage at the control terminal of the transistor.

10. The method according to claim 9, comprising: Couple a first sense resistor to the differential transistor pair to generate a representation of the summing current from the differential transistor pair.

11. The method according to claim 9, comprising: Couple a reference current source to the transistor; and Generate a reference current through the reference current source.

12. The method according to claim 9, comprising: Couple a second sense resistor to the reference current source to generate a representation of the reference current.

13. The method according to claim 9, wherein the differential transistor pair is a first differential transistor pair, wherein the first differential transistor pair has a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and wherein the summing current is a first summing current, the method further comprising: Couple a second transistor pair having a first control terminal to the first control terminal of the first differential transistor pair; Couple the second control terminal to the second control terminal of the first differential transistor pair; Receive the first input signal via the first control terminal of the second transistor pair; Receive the second input signal via the second control terminal of the second transistor pair; Generate a second summing current from a single one of the second transistor pair via the second transistor pair; Wherein, comparing the representation of the summing current with the representation of the reference current using an error correction amplifier comprises: Comparing the representation of the first summing current with the sum of the representation of the reference current and the second summing current.

14. The method according to claim 13, wherein the single one of the second transistor pair is a replica of the single one of the first differential transistor pair.

15. The method according to claim 9, wherein coupling the transistor to the differential transistor pair comprises: Couple a bipolar junction transistor to a differential bipolar junction transistor pair.

16. The method according to claim 9, wherein coupling the transistor to the differential transistor pair comprises: Couple a field effect transistor to a differential field effect transistor pair.

17. An amplifier circuit, comprising: A differential transistor pair configured and arranged to generate a summing current from a single transistor of the differential transistor pair, the differential transistor pair having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, wherein the differential transistor pair is configured and arranged to generate a summing current; A transistor coupled to the differential transistor pair, the transistor having a third control terminal; A first sense resistor coupled to the differential transistor pair, wherein the first sense resistor is configured to generate a first voltage in response to the summing current from the differential transistor pair; A reference current source coupled to the transistor and configured to generate a reference current; A second sense resistor coupled to the reference current source, wherein the second sense resistor is configured to generate a second voltage in response to the reference current; and An error correction amplifier having: A non-inverting input coupled to the first sense resistor and configured to receive the first voltage generated by the first sense resistor; and The inverting input, coupled to the second sense resistor, and configured to receive a second voltage generated by the second sense resistor.

18. The amplifier circuit according to claim 17, wherein the differential transistor pair is a first differential transistor pair having a first control terminal for receiving a first input signal and a second control terminal for receiving a second input signal, and wherein the summing current is a first summing current, and the amplifier circuit further comprises: A second transistor pair, having a first control terminal coupled to the first control terminal of the first differential transistor pair and a second control terminal coupled to the second control terminal of the first differential transistor pair, the first control terminal of the second transistor pair receiving the first input signal and the second control terminal of the second transistor pair receiving the second input signal, wherein the second transistor pair is configured and arranged to generate a second summing current from a single one of the second transistor pair, and wherein an error correction amplifier configured to compare a representation of the summing current with a representation of a reference current is configured to: Compare a representation of the first summing current with a representation of the reference current and the sum of the second summing current.

19. The amplifier circuit according to claim 18, wherein the single one of the second transistor pair is a replica of the single one of the first differential transistor pair.

20. The amplifier circuit according to claim 17, wherein the differential transistor pair comprises bipolar junction transistors.

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