Clock circuit and clock switching circuit
Through clock signal delay and synchronization processing, combined with the improved TSPC forwarding register and clock-free tree delay line, the problem of glitches and clock loss in traditional clock switching circuits is solved, and stable glitch-free clock switching is achieved.
Patent Information
- Application Number
- CN202510396668.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-18
AI Technical Summary
The traditional clock switching circuit will experience glitches when the clock selection signal and the clock signal are inverted at the same time, resulting in the clock signal not meeting the pulse width requirements of the flip-flop, and is sensitive to clock deviation, so it cannot switch normally in the case of clock loss.
The clock signal delay circuit, the first synchronization circuit and the clock output circuit are adopted to ensure that the clock selection signal is glitch-free under clock loss or normal conditions through clock signal delay and synchronization processing, and reduce the sensitivity to clock deviation through improved TSPC forwarding along the trigger register and clock tree-free delay line.
The clock signal switching without glitches during the clock switching process is realized, which improves the stability of the circuit and anti-clock loss ability, reduces the sensitivity to clock deviation, and ensures that the circuit works normally in various situations.
Smart Images
Figure CN120342367A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of clock switching, and particularly to a clock circuit and a clock switching circuit. Background Art
[0002] In a traditional one-out-of-two clock switching circuit, a synchronous circuit is required to synchronize the clock selection signal in both clock domains, and the synchronization requires an input clock signal. However, when the clock selection signal and the clock signal are inverted simultaneously, glitches occur during the clock switching process. Due to the presence of glitches, the clock signal cannot meet the pulse width requirements of the flip-flop. Summary of the Invention
[0003] This application provides a clock circuit and a clock switching circuit to at least solve the problem of glitches occurring during clock switching when the clock selection signal and the clock signal are inverted simultaneously in the related art.
[0004] This application provides a clock circuit, including: a clock signal delay circuit, a first synchronous circuit, and a clock output circuit. Among them,
[0005] The clock signal delay circuit, its first input terminal is the clock signal access terminal, its second input terminal is the delay control signal access terminal, and it is used to delay the clock signal by a first preset time based on the delay control signal to obtain a clock delay signal;
[0006] The first synchronous circuit, its first input terminal is the clock selection signal access terminal, its second input terminal is connected to the output terminal of the clock signal delay circuit, and it is used to synchronize the clock selection signal to the clock domain of the clock signal; when the clock signal is lost or normal, it realizes the flip of the clock selection signal; and deburrs the output signal;
[0007] The clock output circuit (3), its first input terminal is the clock signal access terminal, its second input terminal is connected to the output terminal of the first synchronous circuit, and it is used to output or not output the clock signal based on the output signal of the first synchronous circuit according to the level of the output signal of the first synchronous circuit.
[0008] This application also provides a clock switching circuit, including: a preprocessing circuit, a selection output circuit, and more than two clock circuits. The two clock circuits are denoted as the first clock circuit and the second clock circuit. Among them,
[0009] A preprocessing circuit, whose first input terminal is a clock selection signal input terminal, whose second input terminal is connected to the inverted signal of the output signal of the first synchronization circuit of the first clock circuit, whose third input terminal is connected to the inverted signal of the output signal of the first synchronization circuit of the second clock circuit, whose first output terminal is connected to the first input terminal of the first synchronization circuit of the first clock circuit, whose second output terminal is connected to the first input terminal of the first synchronization circuit of the second clock circuit, and which is used to output a correct clock selection signal;
[0010] The clock signal input terminal of the first clock circuit, which is used to access the first clock;
[0011] The clock signal input terminal of the second clock circuit, which is used to access the second clock;
[0012] A selection output circuit, whose first input terminal is connected to the output terminal of the first synchronization circuit of the first clock circuit, whose second input terminal is connected to the output terminal of the first synchronization circuit of the second clock circuit, and which is used to output the first clock or the second clock.
[0013] Through this application, since the clock signal delay circuit delays the clock signal and uses it as the synchronization signal of the first synchronization circuit, and the first synchronization circuit synchronizes the clock selection signal to the corresponding clock domain based on this synchronization signal, therefore, whether the clock signal is lost or normal, the clock selection signal can be flipped, and at the same time, the first synchronization circuit has no glitches in the output signal, which can solve the technical problem of glitches occurring during clock switching and achieve the technical effect of glitch-free clock switching. Brief Description of the Drawings
[0014] In order to more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings described below are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0015] Figure 1 It is a composition diagram of a clock circuit provided by an embodiment of this application;
[0016] Figure 2 It is a composition diagram of the clock signal delay circuit provided by an embodiment of this application;
[0017] Figure 3 It is a specific circuit structure diagram of the first synchronization sub-circuit and the second synchronization sub-circuit provided by an embodiment of this application;
[0018] Fig. 4(a) is a composition diagram of the clock gating circuit provided by an embodiment of this application;
[0019] Fig. 4(b) is an input / output waveform diagram of the clock gating circuit provided by an embodiment of this application;
[0020] Figure 5 This is the specific circuit structure diagram of the clock tree-free delay line provided by the embodiment of the present application;
[0021] Figure 6 This is the specific circuit of the clock signal delay circuit provided by the embodiment of the present application;
[0022] Figure 7 This is the composition diagram of the two-to-one clock switching circuit provided by the embodiment of the present application;
[0023] Figure 8 This is the input-output waveform diagram of the two-to-one clock switching circuit provided by the embodiment of the present application.
[0024] Figure 9 This is the composition diagram of the four-to-one clock switching circuit provided by the embodiment of the present application. Detailed implementation manners
[0025] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0026] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.
[0027] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.
[0028] Existing clock switching circuits usually adopt mechanical or analog circuit methods to implement. These methods may generate clock jitter or glitches during switching, affecting the stability and performance of the circuit.
[0029] A glitch-free clock switching circuit, also known as a glitch-free circuit or a seamless clock switching circuit. When the chip is running, it is necessary to switch the clock source through gating, and the generated glitch phenomenon may cause the driving circuit to generate metastability, and there may also be a metastability problem of the gating circuit for the switching of unrelated clocks.
[0030] In a traditional glitch-free clock switching circuit, a rising-edge triggered DFF is added before a data flip-flop (DFF). By means of pipelining buffering, the metastability phenomenon is improved, and at this time, there are no longer any mandatory requirements for the clock phase and the clock selection signal. The two-to-one clock switching circuit implemented by traditional technology uses two clocks as inputs and outputs one clock through a clock selection signal. The clock selection signal is synchronized in two clock domains respectively in terms of circuit structure, so as to ensure that there are no glitches generated at the output port when switching the clock using the clock selection signal.
[0031] However, this circuit has two defects. First, since there is no clock dependency relationship between the clock signal and the clock selection signal, the switching of the clock selection signal can occur at any moment. When the switching of the clock selection signal flips together with the clock edge, glitches may appear during the switching process. Due to the existence of glitches, the clock signal cannot meet the requirements of the pulse width of the flip-flop. Second, when the input clock corresponding to the output clock is turned off during operation, the circuit locks up and cannot complete the clock switching. Since the circuit structure requires that the clock selection SEL signal must be synchronized in both clock domains, but synchronization requires an input clock signal, and at this time, the input clock of a one-way clock synchronization circuit is turned off, so the switching signal cannot be synchronized, and the glitch-free clock switching circuit cannot switch anymore. Therefore, this circuit requires both clocks to work properly without loss in order to enable the selection signal to control the turning on and off of the selectable clock. If the current working clock is lost, the circuit will not be able to switch to another clock source, resulting in the subsequent circuit stopping working. Therefore, if there may be a scenario of clock loss, this clock seamless switching circuit generally cannot be used.
[0032] In addition, the flip-flop of this circuit requires complementary input clock signals. Therefore, another drawback of the existing clock switching circuit technology is that it is very sensitive to clock skew.
[0033] Based on the above problems, embodiments of the present application provide a clock circuit, as Figure 1 shown, including: a clock signal delay circuit 1, a first synchronization circuit 2, and a clock output circuit 3.
[0034] As Figure 1 shown, for the clock signal delay circuit 1, its first input terminal is a clock signal access terminal, its second input terminal is a delay control signal access terminal, and it is used to delay the clock signal by a first preset time based on the delay control signal to obtain a clock delay signal. Among them, the clock signal access terminal is used to access the clock signal CLK, and the delay control signal access terminal is used to access the delay control signal OE.
[0035] Specifically, to synchronize the clock selection signal to the clock domain of the clock signal, the clock signal is required as the synchronization clock signal of the synchronization circuit. However, if the clock signal and the clock selection signal flip simultaneously, glitches will occur during subsequent clock switching. Therefore, a clock signal delay circuit 1 is set up to delay the clock signal so that the clock signal and the clock selection signal do not flip simultaneously.
[0036] As Figure 1 shown, the first synchronization circuit 2 has its first input terminal as the clock selection signal access terminal, and its second input terminal is connected to the output terminal of the clock signal delay circuit 1. Among them, the clock selection signal access terminal is used to access the clock selection signal SEL.
[0037] Specifically, the first synchronization circuit 2 has the following three functions:
[0038] (1) Synchronize the clock selection signal to the clock of the clock signal.
[0039] (2) Implement the flip of the clock selection signal when the clock signal is lost or normal. The synchronization clock signal of the first synchronization circuit 2 is the clock delay signal. Therefore, even if the clock signal is lost, due to the existence of the clock delay signal, the synchronization clock signal will not change immediately, so that the flip of the clock selection signal can still be achieved.
[0040] (3) Deburr the output signal. The first synchronization circuit 2 can incorporate sub-circuits such as a filter circuit to further achieve a glitch-free output signal.
[0041] As Figure 1 shown, the clock output circuit 3 has its first input terminal as the clock signal access terminal, its second input terminal is connected to the output terminal of the first synchronization circuit 2, and it is used to output or not output the clock signal based on the output signal of the first synchronization circuit 2 according to the level of the output signal of the first synchronization circuit 2.
[0042] Specifically, when the clock selection signal is at the first level, the clock output circuit 3 outputs a clock signal at the first level. When the clock selection signal is at the second level, the clock output circuit 3 outputs a clock signal at the second level. Among them, the first level can be a high level, the second level can be a low level, or the first level can be a low level, and the second level can be a high level. There is no limitation here.
[0043] In some optional implementation manners, such as Figure 2As shown, the clock signal delay circuit 1 includes: N cascaded delay sub-circuits 11, where N is a positive integer greater than or equal to 3. Among them, the first input terminal of each stage of the delay sub-circuit 11 is the delay control signal access terminal; the second input terminal of the first stage of the delay sub-circuit 11 is the clock signal access terminal, and the output terminal of the first stage of the delay sub-circuit 11 outputs a clock delay signal; the clock delay control signal is used to control the state of each stage of the delay sub-circuit 11 to delay the clock signal by a first preset time.
[0044] Specifically, the clock delay control signal is an N-bit control signal, and each bit of the control signal controls a delay sub-circuit 11. By determining whether each bit of the control signal is set to 1 or 0, each delay sub-circuit 11 is determined, and finally the magnitude of the first preset time is determined.
[0045] Specifically, in order to control each delay sub-circuit 11, each stage of the delay sub-circuit 11 also beats the delay control signal and synchronizes it to a specific clock domain, and makes the output signal free of glitches.
[0046] In some alternative embodiments, the delay sub-circuits 11 of the 1st to the (N - 1)th stage include a second synchronization circuit 111, a clock gating circuit 112, a D flip-flop 113, and a clock-tree-free delay line 114, and the delay sub-circuit 11 of the Nth stage includes a clock-tree-free delay line 114.
[0047] Specifically, for the second synchronization circuit 111, its first input terminal is the delay control signal access terminal, its second input terminal is connected to the output terminal of the clock gating circuit 112, and it is used to synchronize the delay control signal to the clock domain of the clock signal and make the output signal free of glitches.
[0048] Specifically, for the D flip-flop 113, its first input terminal is connected to the output terminal of the second synchronization circuit 111, its second input terminal is connected to the output terminal of the clock gating circuit 112, and it is used to output a trigger signal.
[0049] Specifically, for the clock gating circuit 112, it is used to deburr the clock of the D flip-flop 113.
[0050] Specifically, (1) the first-level clock-tree-free delay line 114, whose first input terminal is the clock signal access terminal, whose second input terminal is connected to the output terminal of the D flip-flop 113, whose third input terminal is connected to the first input terminal of the clock gating circuit 112, and whose third input terminal is also the clock signal access terminal, whose fourth input terminal is connected to the second output terminal of the second-level clock-tree-free delay line 114, whose first output terminal is connected to the first input terminal of the second-level clock-tree-free delay line 114, and whose output terminal is the output terminal of the clock signal delay circuit 1; (2) the second to N-1 level clock-tree-free delay lines 114, whose first input terminal is connected to the first output terminal of the previous-level clock-tree-free delay line 114, whose second input terminal is connected to the output terminal of the D flip-flop 113, whose third input terminal is connected to the first input terminal of the clock gating circuit 112, and whose third input terminal is also the clock signal access terminal, whose fourth input terminal is connected to the second output terminal of the Nth-level clock-tree-free delay line 114; (3) the Nth-level clock-tree-free delay line 114, whose first input terminal is connected to the first output terminal of the (N-1)th-level clock-tree-free delay line 114, whose second input terminal inputs the value 1, whose third input terminal is the clock signal access terminal, and whose fourth input terminal is connected to its first output terminal; the clock-tree-free delay line 114 is used to delay the clock signal by a second preset time based on the trigger signal; the second preset time is less than the first preset time.
[0051] Specifically, the working principle of the traditional delay line is to use digital technology to control the delay time of the signal. It usually includes a memory, where the signal is stored and moves one position along the register at the falling edge of each clock cycle. The clock signal lines are replaced by a single signal line. In fact, this logic signal line has a large overhead in circuit implementation. The existence of the clock tree causes an inherent delay in the traditional delay line, severely restricting the minimum phase shift range of the digital controlled phase shifter and increasing the circuit power consumption at the same time.
[0052] Optionally, in this embodiment, the clock-tree-free delay line 114 is improved on the basis of the traditional delay line. There is no clock tree in the entire delay line of this circuit. It is all built by logic gate circuits, and the delay amount of the clock signal is controlled by the delay control signal.
[0053] In some alternative embodiments, the first synchronization circuit 2 and the second synchronization circuit 111 are two-level synchronization circuits based on TSPCR. The two-level synchronization circuit based on TSPCR includes: a first synchronization sub-circuit and a second synchronization sub-circuit. Among them, for the first synchronization sub-circuit, its first input terminal is the first input terminal of the two-level synchronization circuit based on TSPCR, its second input terminal is the second input terminal of the two-level synchronization circuit based on TSPCR, and its output terminal is connected to the first input terminal of the second synchronization sub-circuit; for the second synchronization sub-circuit, its second input terminal is the second input terminal of the two-level synchronization circuit based on TSPCR, and its output terminal is the output terminal of the two-level synchronization circuit based on TSPCR.
[0054] Specifically, the True Single Phase Clock (TSPC) circuit is a digital logic design technique that uses a single clock signal instead of the traditional two complementary clock signals. However, in the traditional TSPC circuit, the level is stored through the parasitic capacitance of the node. In this case, the circuit cannot operate at too low a frequency. If the clock period is too long, the storage state will be destroyed due to subthreshold conduction and transistor leakage caused by the source and drain junctions. Based on this, this embodiment is a two-stage synchronous circuit based on an improved TSPC positive-edge triggered register. This circuit uses the improved TSPC positive-edge triggered register to reduce the sensitivity of the circuit to clock skew, and uses the two-stage synchronous circuit to further reduce the probability of output glitches.
[0055] Specifically, a two-stage synchronous circuit refers to a synchronous logic circuit composed of two flip-flops, where the output of the first flip-flop serves as the input of the second flip-flop. It is usually used to eliminate metastability and clock skew problems and improve the synchronous performance of the circuit. However, if the clock skews of the two flip-flops do not match, it may lead to performance problems.
[0056] In some alternative embodiments, as Figure 3 shown, both the first synchronous sub-circuit 21 and the second synchronous sub-circuit 22 include: a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NOT gate NOT1, and a first capacitor C1.
[0057] As Figure 3As shown in the figure, for the first PMOS transistor P1, its drain is the first power supply terminal, its source is connected to the drain of the second PMOS transistor P2, and its gate is the first input terminal of the two-stage synchronization circuit based on TSPCR; for the second PMOS transistor P2, its drain is connected to the drain of the first NMOS transistor N1 and the gate of the fourth PMOS transistor P4, and its gate is the second input terminal of the two-stage synchronization circuit based on TSPCR; for the first NMOS transistor N1, its source is connected to the source of the second NMOS transistor N2, and its gate is the first input terminal of the two-stage synchronization circuit based on TSPCR; for the third PMOS transistor P3, its drain is the first power supply terminal, its source is connected to the drain of the fourth PMOS transistor P4 and the gate of the fifth PMOS transistor P5, and its gate is the first input terminal of the two-stage synchronization circuit based on TSPCR; for the fourth PMOS transistor P4, its source is connected to the drain of the second NMOS transistor N2; for the second NMOS transistor N2, its gate is the second input terminal of the two-stage synchronization circuit based on TSPCR; for the fifth PMOS transistor P5, its drain is the first power supply terminal, its source is connected to the input terminal of the first NOT gate NOT1, the drain of the sixth PMOS transistor P6, and the first terminal of the first capacitor C1; for the sixth PMOS transistor P6, its source is connected to the drain of the third NMOS transistor N3, and its gate is the second input terminal of the two-stage synchronization circuit based on TSPCR; for the third NMOS transistor N3, its source is connected to the source of the second NMOS transistor N2 and the first terminal of the first capacitor C1, its source is the second power supply terminal, and its gate is connected to the source of the third PMOS transistor P3; for the first NOT gate NOT1, its output terminal is the output terminal of the two-stage synchronization circuit based on TSPCR; for the first capacitor C1, it is used to deburr the output signal by making the discharge speed of the source of the fifth PMOS transistor P5 lower than that of the source of the third PMOS transistor P3.
[0058] Figure 3 When the two-stage synchronization circuit based on TSPCR is applied to the first synchronization circuit 2, the D terminal is the clock selection signal access terminal, and the CLK terminal is the clock selection signal access terminal; Figure 3 When the two-stage synchronization circuit based on TSPCR is applied to the first synchronization circuit 2, the D terminal is the delay control signal access terminal, used to access a one-bit control signal of the delay control signal, and the CLK terminal is connected to the output terminal of the clock gating circuit 112.
[0059] Specifically, Figure 3 is the structure diagram of the two-stage synchronization circuit based on the improved TSPCR. By combining the characteristics of the improved TSPCR positive-edge triggered register and the characteristics of the traditional two-stage synchronization circuit, the two-stage synchronization circuit based on TSPCR is built. At the output terminals (QN0 and )Improve the circuit. That is, by introducing a capacitor at the output of the third stage, the charge stored at the output node QN is increased to be more than the charge stored at node Y. When the charge stored at node QN is more than the charge stored at node Y, the discharge speed of node QN is less than the discharge speed of node Y. By reducing the discharge speed of node QN so that the discharge speed of node QN is less than the discharge speed of node Y, the mechanism for generating the above-mentioned glitch does not exist, so the generation of glitches can be avoided.
[0060] Specifically, analyze the parameters of each device in the circuit through the operating frequency of the circuit, as follows:
[0061] It is known that the time constant τ is related to the equivalent capacitance and equivalent resistance of the output node, that is
[0062] τ = R * C (1)
[0063] Assume that the operating frequency of the circuit is f out , then the time constant is:
[0064]
[0065] Among them, the time constant is composed of the rise time constant τ LH and the rise time constant τ HL , then
[0066] τ tw = τ LH + τ HL (3)
[0067] The rise time constant τ LH is:
[0068]
[0069] Among them, k p5 is the coefficient of the fifth PMOS transistor P5; V TP is the threshold voltage; the output capacitance C out is calculated as follows:
[0070] C out = C L + C DSP6 + C GDP6 + C GDP5 + C1 (5)
[0071] Among them, C L is the input capacitance of the fourth-stage inverter; C DSP6 is the drain-source capacitance of the sixth PMOS transistor P6; C GDP6 is the gate-drain capacitance of the sixth PMOS transistor P6; C GDP5 is the gate-drain capacitance of the fifth PMOS transistor P5; C1 is the first capacitor C1.
[0072] Fall time constant τ HL is:
[0073] τ LH =(R7 + R8)C out +R7C x (6)
[0074] Wherein, C x is the drain parasitic capacitance of the third NMOS transistor N3; R7 is the equivalent resistance of the third NMOS transistor N3; R8 is the equivalent resistance of the sixth PMOS transistor P6.
[0075] The calculation of each parameter in formula (6) is as follows:
[0076] C x =C GSN2 +C SBN2 +C GDN3 +C DBN3 (7)
[0077]
[0078] Wherein, C GSN2 is the gate-source capacitance of the second NMOS transistor N2; C SBN4 is the source capacitance of the second NMOS transistor N2; C SDN2 is the source-drain capacitance of the second NMOS transistor N2; C GDN3 is the drain-source capacitance of the third NOS transistor; C DBN3 is the drain capacitance of the third NMOS transistor N3; K PN3 is the coefficient of the third NMOS transistor; V GSN3 is the gate-source voltage of the third NOS transistor; K PP6 is the coefficient of the sixth PMOS transistor P6; V GSP6 is the gate-source voltage of the sixth PMOS transistor P6.
[0079] In some alternative embodiments, as shown in FIG. 4(a), the clock gating circuit 112 includes: a positive latch 1121 and a first OR gate OR1.
[0080] Specifically, for the positive latch 1121, its first input terminal is the first input terminal of the clock gating circuit 112, its second input terminal is the second input terminal of the clock gating circuit 112, and its output terminal is connected to the first input terminal of the first OR gate OR1; for the first OR gate OR1, its second input terminal is the second input terminal of the clock gating circuit 112, and its output terminal is the output terminal of the clock gating circuit 112.
[0081] Specifically, the latch-based clock gating circuit 112 can effectively latch the clock enable signal value without affecting the periodicity of the clock signal. The working principle of the latch is level-sensitive and is divided into a positive latch 1121 and a negative latch. The principles of the positive latch 1121 and the negative latch are as follows:
[0082] Positive latch 1121: When the clock signal is at a high level, the input signal is passed to the output, which is transparent to the input and output signals. When the clock signal is at a low level, the input signal is sampled at the rising edge of the clock and then passed to the output, and at this time the latch works in the hold state.
[0083] Negative latch: When the clock signal is at a low level, the input signal is passed to the output, which is transparent to the input and output signals. When the clock signal is at a high level, the input signal is sampled at the rising edge of the clock and then passed to the output, and at this time the latch works in the hold state.
[0084] Specifically, in the clock gating technology in Fig. 4(a), by adding additional logic units in the circuit and optimizing the clock tree structure, the power consumption is reduced. The latch-based clock gating circuit 112 is adding a level-triggered latch on the basis of the gated clock circuit. By introducing a level-sensitive latch at the output end of the clock enable signal to solve the glitch problem, the latch output is updated only within the low or high level of the clock, thus ensuring the stability of the input of the AND gate. Therefore, the latch-based clock gating circuit 112 can effectively latch the clock enable signal value without affecting the periodicity of the clock signal.
[0085] Fig. 4(b) shows the input and output waveforms of the clock gating circuit 112. When the clock signal CLK of the positive latch 1121 is at a low level, the input signal is sampled at the rising edge of the clock and then passed to the output OEG, and at this time the positive latch 1121 works in the hold state. When the clock signal CLK is at a high level, the input signal E is passed to the output OEG, which is transparent to the input and output signals. The OEG signal only sends a state transition when CLK is at a high level. Therefore, when CLK is at a high level, CLKG is also at a high level and is not affected by the state transition of OEG, and at this time the glitch caused by the transition of the input signal E is masked.
[0086] In some alternative embodiments, such as Figure 5 shown, the clockless delay line 114 includes: a second NOT gate NOT2, a first AND gate AND1, a second AND gate AND2, and a third AND gate AND3.
[0087] Specifically, for the second NOT gate NOT2, (1) for the second NOT gate NOT2 at the 1st to N - 1st levels, its input terminal is the input terminal of the clockless tree delay line 114, and its output terminal is connected to the first input terminal of the first AND gate AND1; (2) for the second NOT gate NOT2 at the Nth level, its input terminal inputs the value 1, and its output terminal is connected to the first input terminal of the first AND gate AND1.
[0088] Specifically, for the first AND gate AND1, (1) for the first AND gate AND1, its second input terminal is connected to the second input terminal of the clock gating circuit 112, and its output terminal is connected to the first input terminal of the third AND gate AND3; (2) for the second AND gate AND2 of the delay sub - circuit 11 at the 1st level, its first input terminal is connected to the input terminal of the second NOT gate NOT2, its second input terminal is the clock signal access terminal, and its output terminal is connected to the second input terminal of the second AND gate AND2 of the delay sub - circuit 11 at the 2nd level; for the second AND gate AND2 of the delay sub - circuit 11 at the 2nd to N - 1st levels, its first input terminal is connected to the input terminal of the second NOT gate NOT2, its second input terminal is connected to the second input terminal of the first AND gate AND1, and its output terminal is connected to the second input terminal of the second AND gate AND2 of the subsequent delay sub - circuit 11; for the second AND gate AND2 of the delay sub - circuit 11 at the Nth level, its first input terminal is connected to the input terminal of the second NOT gate NOT2, its second input terminal is connected to the second input terminal of the first AND gate AND1, and its output terminal is connected to the second input terminal of the third AND gate AND3 at its own level; (3) for the third AND gate AND3 of the delay sub - circuit 11 at the 1st level, its second input terminal is connected to the output terminal of the third AND gate AND3 of the delay sub - circuit 11 at the 2nd level, and its output terminal is the output terminal of the clock signal delay circuit 1; for the third AND gate AND3 of the delay sub - circuit 11 at the 2nd to Nth levels, its second input terminal is connected to the output terminal of the third AND gate AND3 of the subsequent delay sub - circuit 11.
[0089] Specifically, Figure 5 The clockless tree delay line 114 is an improvement on the traditional delay line. There is no clock tree in the entire delay line of this circuit. It is all built by logic gate circuits, and the delay amount of the clock signal is controlled by the input signals OE[0], OE[1]…OE[n]. By changing the clock frequency or the number of steps the control signal moves in the register, the delay of the signal can be precisely controlled. Specifically:
[0090] When OE[2:0]=000, the delay of the input clock CLK_IN through 2 NOT gates (1, 2) is 2t NAND ;
[0091] When OE[2:0]=001, the delay of the input clock CLK_IN through 4 NOT gates (3, 4, 5, 2) is 4t NAND ;
[0092] When OE[n+1:n-1] = 011, the total delay of the input clock CLK_IN is 2(n+1)t NAND 。
[0093] Based on the above, a specific circuit diagram example of the clock signal delay circuit 1 is as Figure 6 shown. To avoid the generation of OE signal glitches, in the CLKG clock domain, the OE signal is synchronized to the gated clock CLKG clock domain by the second synchronization circuit 111 for two beats, denoted as OER. The OER signal is connected to the input terminal of the D flip-flop 113, and the output signal of the D flip-flop 113 is denoted as the OEG signal. At this time, the OEG signal is transmitted to the clock tree-free delay line 114, and the D flip-flop 113 avoids the situation where the switching of the OE signal generates glitches at the output clock CLK_OUT port. The switching of multiple OEs is transmitted bit by bit from high to low to the node OEG of the delay line.
[0094] Therefore, the clock signal delay circuit 1 of this embodiment has the following advantages:
[0095] (1) Achieve precise delay of the control signal OE, while avoiding the generation of unwanted spikes or glitches during the conversion of the control signal OE. These glitches may cause mis-triggering or unstable behavior of the circuit.
[0096] (2) The variable delay sub-circuit 11 and the measurement delay integration unit of the measurement delay line are highly consistent. Realized by building logic gates, the delay characteristics are exactly mirrored, and stable operation and performance can still be maintained under PVT variations.
[0097] In some alternative embodiments, as Figure 7 shown, the clock output circuit 3 includes: a fourth AND gate ADD4, wherein the first input terminal of the fourth AND gate ADD4 is the clock signal access terminal, its second input terminal is connected to the output terminal of the first synchronization circuit 2, and its output terminal is the output terminal of the clock circuit.
[0098] The embodiment of the present application also provides a clock switching circuit, as Figure 7 shown, including: a preprocessing circuit 4, a selection output circuit 5, and clock circuits of two or more embodiments and any of their alternative embodiments. The two clock circuits are denoted as the first clock circuit and the second clock circuit.
[0099] A preprocessing circuit 4, whose first input terminal is a clock selection signal input terminal, whose second input terminal is connected to the inverted signal of the output signal of the first synchronization circuit 2 of the first clock circuit, whose third input terminal is connected to the inverted signal of the output signal of the first synchronization circuit 2 of the second clock circuit, whose first output terminal is connected to the first input terminal of the first synchronization circuit 2 of the first clock circuit, whose second output terminal is connected to the first input terminal of the first synchronization circuit 2 of the second clock circuit, and which is used to output a correct clock selection signal;
[0100] The clock signal input terminal of the first clock circuit, which is used to access the first clock CLK0;
[0101] The clock signal input terminal of the second clock circuit, which is used to access the second clock CLK1;
[0102] A selection output circuit 5, whose first input terminal is connected to the output terminal of the first synchronization circuit 2 of the first clock circuit, whose second input terminal is connected to the output terminal of the first synchronization circuit 2 of the second clock circuit, and which is used to output the first clock or the second clock.
[0103] Specifically, Figure 7 It is a two-to-one clock switching circuit, and its specific waveform is as Figure 8 shown. The signal of CLK0 is denoted as CLK0_Delay after delay. The clock selection signal SEL = 0, and the input clock CLK0 is selected. The clock selection signal SEL = 1, and the input clock CLK1 is selected. In the traditional circuit, after the original CLK0 signal is lost, the flip-flop DFF0 cannot be inverted, and the circuit will have a deadlock. However, this circuit introduces a clock signal delay circuit 1 to obtain CLK0_Delay and CLK1_Delay signals. The CLK0_Delay and CLK1_Delay signals are used as the synchronization signals of the synchronization circuit. Thus, even in the case of CLK loss, the flip of the clock selection signal is still realized, thereby avoiding circuit deadlock. By performing a beating process on the SEL signal and then realizing seamless switching through the feedback line.
[0104] In some alternative embodiments, as Figure 7 shown, the preprocessing circuit 4 includes: a third NOT gate NOT3, a fifth AND gate ADD5, and a sixth AND gate ADD6. Among them, for the third NOT gate NOT3, its input terminal is the clock selection signal input terminal, and its output terminal is connected to the second input terminal of the sixth gate; for the fifth AND gate ADD5, its first input terminal is the clock selection signal input terminal, its second input terminal is connected to the inverted signal of the output signal of the first synchronization circuit 2 of the second clock circuit, and its output terminal is connected to the first input terminal of the first synchronization circuit 2 of the first clock circuit; for the sixth AND gate ADD6, its first input terminal is connected to the inverted signal of the output signal of the first synchronization circuit 2 of the first clock circuit, and its output terminal is connected to the first input terminal of the first synchronization circuit 2 of the second clock circuit.
[0105] Optionally, in addition to implementing two-way clock switching, this embodiment can implement four-to-one or multi-to-one glitch-free clock switching by adding the number of stages of the delay line of the glitch-free control signal circuit and the number of cascaded stages of the feedback line. The circuit structure diagram of the four-to-one clock signal switching is as Figure 9 shown. Figure 9 In the figure, en123_sync means taking the OR of the three signals en1_sync, en2_sync, and en3_sync; en023_sync means taking the OR of the three signals en0_sync, en2_sync, and en3_sync; en013_sync means taking the OR of the three signals en0_sync, en1_sync, and en3_sync. The control delay line can implement an adaptive clock delay adjustment mechanism and design user interface signals. It allows users to manually or automatically adjust the clock delay phase according to their needs, and dynamically adjust the clock delay phase according to the working state and performance requirements of the circuit. In addition, the glitch-free clock switching circuit can be used in combination with buffers and filters on the clock path to improve the quality of the clock signal, reduce noise and glitches.
[0106] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation.
[0107] The above provides a detailed introduction to a clock circuit and a clock switching circuit of the present application. Specific examples are used in this article to elaborate on the principle and implementation of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.
Claims
1. A clock circuit, characterized in that, Comprising: A clock signal delay circuit (1), a first synchronization circuit (2), and a clock output circuit (3), wherein, The clock signal delay circuit (1), whose first input terminal is a clock signal access terminal, whose second input terminal is a delay control signal access terminal, and which is used to delay the clock signal by a first preset time based on the delay control signal to obtain a clock delay signal; The first synchronization circuit (2), whose first input terminal is a clock selection signal access terminal, whose second input terminal is connected to the output terminal of the clock signal delay circuit (1), and which is used to synchronize the clock selection signal to the clock domain of the clock signal, and to achieve a flip of the clock selection signal in the case of clock signal loss or normal condition; and to deburr the output signal; The clock output circuit (3), whose first input terminal is a clock signal access terminal, whose second input terminal is connected to the output terminal of the first synchronization circuit (2), and which is used to output or not output the clock signal based on the output signal of the first synchronization circuit (2) according to the level of the output signal of the first synchronization circuit (2).
2. The clock circuit according to claim 1, wherein The clock signal delay circuit (1) includes: N cascaded delay sub - circuits (11), where N is a positive integer greater than or equal to 3, and wherein, The first input terminal of each stage of the delay sub - circuit (11) is a delay control signal access terminal; The second input terminal of the first stage of the delay sub - circuit (11) is a clock signal access terminal, and the output terminal of the first stage of the delay sub - circuit (11) outputs a clock delay signal; The clock delay control signal is used to control the state of each stage of the delay sub - circuit (11) to delay the clock signal by a first preset time.
3. The clock circuit according to claim 2, wherein The delay sub - circuits (11) of the 1st to the (N - 1)th stage include a second synchronization circuit (111), a clock gating circuit (112), a D - flip - flop (113), and a clock - tree - free delay line (114), and the delay sub - circuit (11) of the Nth stage includes a clock - tree - free delay line (114), where, The second synchronization circuit (111), whose first input terminal is a delay control signal access terminal, whose second input terminal is connected to the output terminal of the clock gating circuit (112), and which is used to synchronize the delay control signal to the clock domain of the clock signal and to deburr the output signal; The D - flip - flop (113), whose first input terminal is connected to the output terminal of the second synchronization circuit (111), whose second input terminal is connected to the output terminal of the clock gating circuit (112), and which is used to output a trigger signal; The clock gating circuit (112), which is used to deburr the clock of the D - flip - flop (113); The first - stage clock - tree - free delay line (114), whose first input terminal is a clock signal access terminal, whose second input terminal is connected to the output terminal of the D - flip - flop (113), whose third input terminal is connected to the first input terminal of the clock gating circuit (112) and is also a clock signal access terminal, whose fourth input terminal is connected to the second output terminal of the second - stage clock - tree - free delay line (114), whose first output terminal is connected to the first input terminal of the second - stage clock - tree - free delay line (114), and whose output terminal is the output terminal of the clock signal delay circuit (1); The clock-tree-free delay lines (114) at the 2nd to N-1th levels, whose first input terminal is connected to the first output terminal of the clock-tree-free delay line (114) of the previous level, whose second input terminal is connected to the output terminal of the D flip-flop (113), whose third input terminal is connected to the first input terminal of the clock gating circuit (112), and whose third input terminal is also the clock signal access terminal, and whose fourth input terminal is connected to the second output terminal of the clock-tree-free delay line (114) of the Nth level; The clock-tree-free delay line (114) of the Nth level, whose first input terminal is connected to the first output terminal of the clock-tree-free delay line (114) of the N-1th level, whose second input terminal inputs the value 1, whose third input terminal is the clock signal access terminal, and whose fourth input terminal is connected to its first output terminal; The clock-tree-free delay line (114) is used to delay the clock signal by a second preset time based on the trigger signal; The second preset time is less than the first preset time.
4. The clock circuit according to claim 3, wherein The first synchronization circuit (2) and the second synchronization circuit (111) are two-stage synchronization circuits based on TSPCR. The two-stage synchronization circuit based on TSPCR includes: a first synchronization sub-circuit and a second synchronization sub-circuit, where, The first synchronization sub-circuit, whose first input terminal is the first input terminal of the two-stage synchronization circuit based on TSPCR, whose second input terminal is the second input terminal of the two-stage synchronization circuit based on TSPCR, and whose output terminal is connected to the first input terminal of the second synchronization sub-circuit; The second synchronization sub-circuit, whose second input terminal is the second input terminal of the two-stage synchronization circuit based on TSPCR, and whose output terminal is the output terminal of the two-stage synchronization circuit based on TSPCR.
5. The clock circuit according to claim 4, wherein Both the first synchronization sub-circuit and the second synchronization sub-circuit include: a first NMOS transistor (N1), a second NMOS transistor (N2), a third NMOS transistor (N3), a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), a fourth PMOS transistor (P4), a fifth PMOS transistor (P5), a sixth PMOS transistor (P6), a first NOT gate (NOT1), and a first capacitor (C1), where, The first PMOS transistor (P1), whose drain is the first power supply terminal, whose source is connected to the drain of the second PMOS transistor (P2), and whose gate is the first input terminal of the two-stage synchronization circuit based on TSPCR; The second PMOS transistor (P2), whose drain is connected to the drain of the first NMOS transistor (N1) and the gate of the fourth PMOS transistor (P4), and whose gate is the second input terminal of the two-stage synchronization circuit based on TSPCR; The first NMOS transistor (N1), whose source is connected to the source of the second NMOS transistor (N2), and whose gate is the first input terminal of the two-stage synchronization circuit based on TSPCR; The third PMOS transistor (P3), whose drain is the first power supply terminal, whose source is connected to the drain of the fourth PMOS transistor (P4) and the gate of the fifth PMOS transistor (P5), and whose gate is the first input terminal of the two-stage synchronization circuit based on TSPCR; The fourth PMOS transistor (P4), whose source is connected to the drain of the second NMOS transistor (N2); The second NMOS transistor (N2), whose gate is the second input terminal of the two-stage synchronous circuit based on TSPCR; The fifth PMOS transistor (P5), whose drain is the first power supply terminal, and whose source is connected to the input terminal of the first NOT gate, the drain of the sixth PMOS transistor (P6), and the first end of the first capacitor (C1); The sixth PMOS transistor, whose source is connected to the drain of the third NMOS transistor (N3), and whose gate is the second input terminal of the two-stage synchronous circuit based on TSPCR; The third NMOS transistor (N3), whose source is connected to the source of the second NMOS transistor (N2) and the first end of the first capacitor (C1), whose source is the second power supply terminal, and whose gate is connected to the source of the third PMOS transistor (P3); The first NOT gate, whose output terminal is the output terminal of the two-stage synchronous circuit based on TSPCR; The first capacitor (C1), which is used to deburr the output signal by making the discharge speed of the source of the fifth PMOS transistor (P5) lower than that of the source of the third PMOS transistor (P3).
6. The clock circuit according to claim 3, wherein The clock gating circuit (112) includes: a positive latch (1121) and a first OR gate (OR1), where, The positive latch (1121), whose first input terminal is the first input terminal of the clock gating circuit (112), whose second input terminal is the second input terminal of the clock gating circuit (112), and whose output terminal is connected to the first input terminal of the first OR gate (OR1); The first OR gate (OR1), whose second input terminal is the second input terminal of the clock gating circuit (112), and whose output terminal is the output terminal of the clock gating circuit (112).
7. The clock circuit according to claim 3, characterized in that, The clockless tree delay line (114) includes: a second NOT gate (NOT2), a first AND gate (AND1), a second AND gate (AND2), and a third AND gate (AND3), where, The second NOT gates (NOT2) of the 1st to N-1st levels, whose input terminals are the input terminals of the clockless tree delay line (114), and whose output terminals are connected to the first input terminal of the first AND gate (AND1); the second NOT gate (NOT2) of the Nth level, whose input terminal inputs the value 1, and whose output terminal is connected to the first input terminal of the first AND gate (AND1); The first AND gate (AND1), whose second input terminal is connected to the second input terminal of the clock gating circuit (112), and whose output terminal is connected to the first input terminal of the third AND gate (AND3); The second AND gate (AND2) of the delay sub-circuit (11) at the first stage, whose first input terminal is connected to the input terminal of the second NOT gate (NOT2), whose second input terminal is a clock signal access terminal, and whose output terminal is connected to the second input terminal of the second AND gate (AND2) of the delay sub-circuit (11) at the second stage; the second AND gate (AND2) of the delay sub-circuits (11) from the second to the N-1th stage, whose first input terminal is connected to the input terminal of the second NOT gate (NOT2), whose second input terminal is connected to the second input terminal of the first AND gate (AND1), and whose output terminal is connected to the second input terminal of the second AND gate (AND2) of the subsequent stage of the delay sub-circuit (11); the second AND gate (AND2) of the delay sub-circuit (11) at the Nth stage, whose first input terminal is connected to the input terminal of the second NOT gate (NOT2), whose second input terminal is connected to the second input terminal of the first AND gate (AND1), and whose output terminal is connected to the second input terminal of the third AND gate (AND3) at its own stage; The third AND gate (AND3) of the delay sub-circuit (11) at the first stage, whose second input terminal is connected to the output terminal of the third AND gate (AND3) of the delay sub-circuit (11) at the second stage, and whose output terminal is the output terminal of the clock signal delay circuit (1); the third AND gates (AND3) of the delay sub-circuits (11) from the second to the Nth stage, whose second input terminal is connected to the output terminal of the third AND gate (AND3) of the subsequent stage of the delay sub-circuit (11).
8. The clock circuit according to claim 1, characterized in that The clock output circuit (3) includes: a fourth AND gate (ADD4), where The fourth AND gate (ADD4), whose first input terminal is a clock signal access terminal, whose second input terminal is connected to the output terminal of the first synchronization circuit (2), and whose output terminal is the output terminal of the clock circuit.
9. A clock switching circuit, characterized in that, Comprising: A preprocessing circuit (4), a selection output circuit (5), and two clock circuits as claimed in any one of claims 1-8, the two clock circuits being denoted as a first clock circuit and a second clock circuit, where The preprocessing circuit (4), whose first input terminal is a clock selection signal input terminal, whose second input terminal receives the inverted signal of the output signal of the first synchronization circuit (2) of the first clock circuit, whose third input terminal receives the inverted signal of the output signal of the first synchronization circuit (2) of the second clock circuit, whose first output terminal is connected to the first input terminal of the first synchronization circuit (2) of the first clock circuit, whose second output terminal is connected to the first input terminal of the first synchronization circuit (2) of the second clock circuit, and which is used to output a correct clock selection signal; The clock signal access terminal of the first clock circuit, which is used to access the first clock; The clock signal access terminal of the second clock circuit, which is used to access the second clock; The selection output circuit (5), whose first input terminal is connected to the output terminal of the first synchronization circuit (2) of the first clock circuit, whose second input terminal is connected to the output terminal of the first synchronization circuit (2) of the second clock circuit, and which is used to output the first clock or the second clock.
10. The clock switching circuit according to claim 9, characterized in that, The preprocessing circuit (4) includes: a third NOT gate (NOT3), a fifth AND gate (ADD5), a sixth AND gate (ADD6), where The third NOT gate (NOT3), whose input terminal is the clock selection signal input terminal, and whose output terminal is connected to the second input terminal of the sixth gate; The fifth AND gate (ADD5), whose first input terminal is the clock selection signal input terminal, whose second input terminal is connected to the opposite signal of the output signal of the first synchronization circuit (2) of the second clock circuit, and whose output terminal is connected to the first input terminal of the first synchronization circuit (2) of the first clock circuit; The sixth AND gate (ADD6), whose first input terminal is connected to the opposite signal of the output signal of the first synchronization circuit (2) of the first clock circuit, and whose output terminal is connected to the first input terminal of the first synchronization circuit (2) of the second clock circuit.