A constant on-time generating circuit

Abstract

The present invention proposes a constant on-time generation circuit, comprising a first RS flip-flop I1, a comparison signal control circuit, a first comparison signal generation circuit, a second comparison signal generation circuit, a reset signal control circuit, a test auxiliary circuit, and a selector I2. The second end of the test auxiliary circuit is connected to the set end of the first RS flip-flop I1 via the selector I2, and the output signal of the first RS flip-flop I1 is calibrated via the test auxiliary circuit and the reset signal control circuit. The output signal of the previous-stage circuit is connected to the set end of the first RS flip-flop I1 via the selector I2, and the input delay of the reset end of the first RS flip-flop I1 is eliminated by dynamic adjustment of the reset signal control circuit. The present invention first calibrates resistance and capacitance errors using a foreground calibration mode, and then, after entering a normal operating mode, dynamically adjusts the output delay of the calibration comparator to achieve accurate control of the constant on-time, thereby accurately controlling the operating frequency of the switching power supply.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a constant on-time generating circuit. Background Art

[0002] Constant On-Time (COT) switching power supplies have been widely used in recent years due to their simple structure, fast response speed, and high efficiency under low load conditions. Figure 1 The basic principle block diagram of the constant on-time controlled step-down switching power supply (BUCK). Figure 1 As shown in the figure, when the output voltage VOUT is lower than the reference voltage VREF, the output voltage VTRIG of comparator X0 increases. After receiving the VTRIG signal, the constant on-time generation circuit I0 generates a pulse signal with a fixed time width TON to the subsequent control logic. The control logic turns on the PMOS switch MP0 for the fixed time, causing VOUT to increase, thus achieving closed-loop control of VOUT.

[0003] Compared to traditional pulse-width control (PWM) switching power supplies, a disadvantage of constant on-time control switching power supplies is that they lack a fixed-frequency clock input. Their operating frequency or period is determined by their input and output voltages and the constant on-time. Taking a step-down switching power supply as an example, based on the principle that the current in inductor L remains zero within a given cycle in a steady-state state, the current increase when the PMOS switch MP0 turns on is equal to the current decrease when the NMOS switch MN0 turns on. This translates to (VIN - VOUT) / L*TON = VOUT / L*(T-TON), where VIN is the input voltage, VOUT is the output voltage, L is the inductor value, TON is the constant on-time, and T is the switching period. Simplifying this, the period T = VIN / VOUT*TON. Because the frequency is not fixed, it can induce switching noise of varying frequencies within the system. Therefore, an improved constant on-time generation circuit dynamically adjusts the constant on-time based on the input and output voltages, ensuring that the on-time is proportional to VOUT / VIN, maintaining a constant period.

[0004] Figure 2This is an improved constant on-time generator circuit commonly used today. Op amp A1, PMOS transistor MP1, and resistor R1 form a feedback loop. Controlled by input voltage VIN, a current VIN / R1 is generated across load resistor R1. PMOS transistors MP2 and MP1 form a current mirror, mirroring the current across resistor R1 to capacitor C1. This current is then charged when switch S2 is open. The circuit operates as follows: Initially, S2 is closed, pulling the top plate voltage of C1 low. Comparator X1 outputs 0, and the reset signal from RS flip-flop I1 is negated. Upon receiving trigger signal VTRIG from the previous stage, the constant on-time generator circuit sets RS flip-flop I1, causing output VTON to 1. Simultaneously, its controlled switch S2 opens, allowing MP2 to begin charging C1 with a current equal to VIN / R1. When the top plate voltage of C1 exceeds output voltage VOUT, comparator X1 flips, outputting 1. This resets the RS flip-flop, causing output VTON to 0. S2 closes, returning the circuit to its initial state. The duration of the VTON high voltage 1, or the constant on-time, is equal to the time it takes for C1 to charge to VOUT. Ideally, VTON = C1 * VOUT / (VIN / R1) = VOUT / VIN * C1 * R1, which is proportional to VOUT / VIN. This theoretically ensures a constant switching period. However, in practical circuits, the comparator flips with a certain delay, and may not flip exactly when C1's top plate charges to VOUT. Furthermore, the values ​​of capacitor C1 and resistor R1 vary with process technology. The switching cycle of a switching power supply still exhibits considerable randomness.

[0005] Based on this, a new solution is needed to more accurately control the constant on-time and thus accurately control the switching frequency of the switching power supply. Summary of the Invention

[0006] The object of the present invention is to provide a constant on-time generating circuit, which can accurately control the constant on-time according to the changes in the input and output voltages of a switching power supply, thereby accurately controlling the switching frequency of the switching power supply.

[0007] According to one aspect of the present invention, a constant on-time generating circuit is provided, comprising a first RS flip-flop I1, a comparison signal control circuit, a first comparison signal generating circuit, a second comparison signal generating circuit, a reset signal control circuit, a test auxiliary circuit, and a selector I2.

[0008] The comparison signal control circuit is connected to a first end of the first comparison signal generating circuit and a first end of the second comparison signal generating circuit; a second end of the first comparison signal generating circuit is connected to a first end of the reset signal control circuit; a second end of the reset signal control circuit is connected to a reset end of the first RS flip-flop I1; a second end of the second comparison signal generating circuit is connected to a first end of the test auxiliary circuit; a second end of the test auxiliary circuit is connected to a first input end of the selector I2; a second input end of the selector I2 is connected to an output signal of a previous-stage circuit; and an output end of the selector I2 is connected to a set end of the first RS flip-flop I1.

[0009] In a calibration mode, the second terminal of the test auxiliary circuit is connected to the set terminal of the first RS flip-flop I1 through the selector I2, and the output signal of the first RS flip-flop I1 is calibrated through the test auxiliary circuit and the reset signal control circuit;

[0010] In normal working mode, the output signal of the previous stage circuit is connected to the set terminal of the first RS trigger I1 through the selector I2, and the input delay of the reset terminal of the first RS trigger I1 is eliminated through dynamic adjustment of the reset signal control circuit.

[0011] In the constant on-time generation circuit provided by the present invention, the comparison signal control circuit includes a first amplifier A1, a first PMOS transistor MP1, a resistor R1, and a second PMOS transistor MP2. The negative input terminal of the first amplifier A1 is connected to an input voltage, the positive input terminal of the first amplifier A1 is connected to the drain of the first PMOS transistor MP1 and the first end of the resistor R1, and the output terminal of the first amplifier A1 is connected to the gate terminal of the first PMOS transistor MP1 and the gate terminal of the second PMOS transistor MP2. The source terminal of the first PMOS transistor MP1 and the source terminal of the second PMOS transistor MP2 are connected to a power supply, the second end of the resistor R1 is grounded, and the drain terminal of the second PMOS transistor MP2 is connected to the first end of the first comparison signal generation circuit and the first end of the second comparison signal generation circuit.

[0012] In the constant on-time generating circuit provided by the present invention, the first comparison signal generating circuit includes a first switch S1, a first capacitor C1, and a second switch S2. The first end of the first switch S1 is connected to the drain end of the second PMOS transistor MP2, the second end of the first switch S1 is connected to the upper plate of the first capacitor C1, the first end of the second switch S2, and the first end of the reset signal control circuit, and the lower plate of the first capacitor C1 and the second end of the second switch S2 are grounded.

[0013] In the constant on-time generating circuit provided by the present invention, the reset signal control circuit includes a sampling compensation circuit and a first comparator X1, the positive input terminal of the first comparator X1 is connected to the upper plate of the first capacitor C1, the negative input terminal of the first comparator X1 is connected to the sampling compensation circuit, and the output terminal of the first comparator X1 is connected to the reset terminal of the first RS trigger I1.

[0014] In the constant on-time generation circuit provided by the present invention, the sampling compensation circuit includes a third switch S3, a second amplifier A2, and a third capacitor C3. The first end of the third switch S3 is connected to the upper plate of the first capacitor C1, the positive input end of the second amplifier A2 is connected to the output voltage, the negative input end of the second amplifier A2 is connected to the second end of the third switch S3 and the first end of the third capacitor C3, and the output end of the second amplifier A2 is connected to the negative input end of the first comparator X1 and the second end of the third capacitor C3.

[0015] In the constant on-time generating circuit provided by the present invention, the second comparison signal generating circuit includes a fourth switch S4 and a second capacitor C2, a first end of the fourth switch S4 is connected to the drain end of the second PMOS transistor MP2, a second end of the fourth switch S4 is connected to the upper plate of the second capacitor C2 and the first end of the test auxiliary circuit, and the lower plate of the second capacitor C2 is grounded.

[0016] In the constant on-time generation circuit provided by the present invention, the test auxiliary circuit includes a third amplifier A3, a fifth switch S5, a sixth switch S6, a fourth capacitor C4, and a second comparator X2. The positive input of the third amplifier A3 is connected to the output voltage, the negative input of the third amplifier A3 is connected to the first end of the sixth switch S6 and the first end of the fourth capacitor C4, the output of the third amplifier A3 is connected to the second end of the fourth capacitor C4 and the negative input of the second comparator X2, the positive input of the second comparator X2 is connected to the first end of the fifth switch S5, the second end of the sixth switch S6, and the upper plate of the second capacitor C2, the output of the second comparator X2 is connected to the first input of the selector I2, and the second end of the fifth switch S5 is grounded.

[0017] The implementation of the constant on-time generation circuit of the present invention has the following beneficial effects: the constant on-time generation circuit provided by the present invention includes dynamically adjusting the negative input terminal voltage of the first comparator through a sampling compensation circuit composed of a third switch S3, a second amplifier A2, and a third capacitor C3, so that the upper plate of the first capacitor accurately flips when charged to the VOUT voltage; at the same time, a test auxiliary circuit composed of the third amplifier, a fifth switch, a sixth switch, a fourth capacitor, and a second comparator is used to perform foreground calibration on the constant on-time generation circuit to eliminate changes in the capacitor resistance value caused by process fluctuations; ultimately, the output constant on-time is accurately controlled, thereby accurately controlling the switching frequency of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive work.

[0019] Figure 1 The schematic diagram of a constant on-time controlled step-down switching power supply (BUCK);

[0020] Figure 2 The present invention provides a circuit diagram of an existing improved constant on-time generating circuit;

[0021] Figure 3 Shown Figure 2 The timing diagram of the improved constant on-time generating circuit shown;

[0022] Figure 4 A schematic diagram of a constant on-time generating circuit provided by an embodiment of the present invention;

[0023] Figure 5 A circuit diagram of a constant on-time generating circuit provided by one embodiment of the present invention;

[0024] Figure 6 for Figure 5 The equivalent circuit of the constant on-time generating circuit shown in the foreground calibration mode;

[0025] Figure 7 for Figure 5 The timing diagram of the constant on-time generating circuit shown in the foreground calibration mode;

[0026] Figure 8 for Figure 5 The equivalent circuit of the constant on-time generating circuit shown in the figure is in normal operating mode;

[0027] Figure 9 for Figure 5 The timing diagram of the constant on-time generating circuit in normal operating mode is shown. DETAILED DESCRIPTION

[0028] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate exemplary embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0030] The general idea of ​​the present invention is: in the foreground calibration mode, the constant on-time generating circuit outputs a square wave with a period of the target constant on-time, which is convenient for measuring and calibrating the resistance and capacitance values; in the normal working mode, the comparator delay is dynamically calibrated to achieve accurate control of the constant on-time.

[0031] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the drawings and specific implementation methods of the specification. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0032] Figure 1 This is the schematic diagram of a conventional constant on-time (COT) step-down switching power supply (BUCK). The control logic controls the switching of the power PMOS transistor MP0 and the power NMOS transistor MN0 to generate a square wave output, which is then filtered by a filter composed of an inductor and capacitor to produce the output voltage VOUT. When VOUT falls below the reference voltage VREF, the comparator X0 output voltage VTRIG becomes logic 1. Upon receiving the VTRIG signal, the constant on-time generation circuit I0 generates a pulse signal VTON with a fixed duration. Based on this signal, the control logic circuit turns on the power PMOS transistor for a fixed duration, pulling VOUT up one or more times until VOUT exceeds VREF, thus achieving closed-loop control of the VOUT output amplitude.

[0033] Figure 2This circuit is an improved version of the prior art constant on-time generation circuit, used to generate constant on-time pulses in a constant on-time controlled switching power supply. Op amp A1, PMOS transistor MP1, and resistor R1 form a feedback loop. Under the control of voltage VIN, a current VIN / R1 is generated across load resistor R1. PMOS transistors MP2 and MP1 form a current mirror, mirroring the current across load resistor R1 to capacitor C1, which charges when switch S2 is off. The operating process is as follows: In the initial state, switch S2 is closed, pulling the voltage on the top plate of capacitor C1 low. Comparator X1 outputs 0, and the reset signal of RS flip-flop I1 is negated. After the constant on-time generation circuit receives the trigger signal VTRIG from the previous circuit, RS flip-flop I1 is set, and the output VTON changes to 1. Simultaneously, its control switch S2 opens, and PMOS transistor MP2 begins charging capacitor C1 with a charging current equal to VIN / R1. When the voltage on the top plate of capacitor C1 exceeds the output voltage VOUT, comparator X1 flips and outputs 1, resetting the RS flip-flop, and the output VTON changes to 0. Simultaneously, switch S2 closes, and the circuit returns to the initial state. The duration of VTON's high voltage 1, or the constant on-time, is equal to the time it takes for capacitor C1 to charge to VOUT. Ideally, VTON = C1*VOUT / (VIN / R1) = VOUT / VIN*C1*R1, which is proportional to VOUT / VIN, thus theoretically maintaining a constant switching period. However, due to various non-ideal factors, such as comparator flip-flop delay and resistor and capacitor value errors, accurate control cannot be achieved.

[0034] Figure 4 Schematic diagram of a constant on-time generating circuit provided by one embodiment of the present invention; Figure 4As shown, the constant on-time generating circuit provided by the present invention includes a first RS trigger I1, a comparison signal control circuit 100, a first comparison signal generating circuit 200, a second comparison signal generating circuit 300, a reset signal control circuit 400, a test auxiliary circuit 500 and a selector I2, wherein the comparison signal control circuit 100 is connected to the first end of the first comparison signal generating circuit 200 and the first end of the second comparison signal generating circuit 300, the second end of the first comparison signal generating circuit 200 is connected to the first end of the reset signal control circuit 400, the second end of the reset signal control circuit 400 is connected to the reset end of the first RS trigger I1, the second end of the second comparison signal generating circuit 300 is connected to the first end of the test auxiliary circuit 500, and the test auxiliary circuit 500 is connected to the reset end of the first RS trigger I1. The second end of the test auxiliary circuit 500 is connected to the first input end of the selector I2, the second input end of the selector I2 is connected to the output signal of the previous level circuit, and the output end of the selector I2 is connected to the set end of the first RS trigger I1. In the calibration mode, the second end of the test auxiliary circuit 500 is connected to the set end of the first RS trigger I1 through the selector I2, and the output signal of the first RS trigger I1 is calibrated through the test auxiliary circuit 500 and the reset signal control circuit 400; in the normal working mode, the output signal of the previous level circuit is connected to the set end of the first RS trigger I1 through the selector I2, and the input delay of the reset end of the first RS trigger I1 is eliminated through the dynamic adjustment of the reset signal control circuit 400.

[0035] Figure 5 A circuit diagram of a constant on-time generating circuit provided in one embodiment of the present invention; specifically, in one embodiment of the present invention, the comparison signal control circuit 100 includes a first amplifier A1, a first PMOS transistor MP1, a resistor R1, and a second PMOS transistor MP2. The negative input terminal of the first amplifier A1 is connected to an input voltage, the positive input terminal of the first amplifier A1 is connected to the drain of the first PMOS transistor MP1 and the first end of the resistor R1, and the output terminal of the first amplifier A1 is connected to the gate terminal of the first PMOS transistor MP1 and the gate terminal of the second PMOS transistor MP2; the source terminal of the first PMOS transistor MP1 and the source terminal of the second PMOS transistor MP2 are connected to a power supply, the second end of the resistor R1 is grounded, and the drain terminal of the second PMOS transistor MP2 is connected to the first end of the first comparison signal generating circuit and the first end of the second comparison signal generating circuit.

[0036] Specifically, in one embodiment of the present invention, the first comparison signal generating circuit 200 includes a first switch S1, a first capacitor C1, and a second switch S2. The first end of the first switch S1 is connected to the drain end of the second PMOS transistor MP2, the second end of the first switch S1 is connected to the upper plate of the first capacitor C1, the first end of the second switch S2, and the first end of the reset signal control circuit, and the lower plate of the first capacitor C1 and the second end of the second switch S2 are grounded.

[0037] Specifically, in one embodiment of the present invention, the reset signal control circuit 400 includes a sampling compensation circuit 410 and a first comparator X1, the positive input terminal of the first comparator X1 is connected to the upper plate of the first capacitor C1, the negative input terminal of the first comparator X1 is connected to the sampling compensation circuit 410, and the output terminal of the first comparator X1 is connected to the reset terminal of the first RS trigger I1.

[0038] Specifically, in one embodiment of the present invention, the sampling compensation circuit 410 includes a third switch S3, a second amplifier A2 and a third capacitor C3. The first end of the third switch S3 is connected to the upper plate of the first capacitor C1, the positive input end of the second amplifier A2 is connected to the output voltage, the negative input end of the second amplifier A2 is connected to the second end of the third switch S3 and the first end of the third capacitor C3, and the output end of the second amplifier A2 is connected to the negative input end of the first comparator X1 and the second end of the third capacitor C3.

[0039] Specifically, in one embodiment of the present invention, the second comparison signal generating circuit includes a fourth switch S4 and a second capacitor C2, a first end of the fourth switch S4 is connected to the drain end of the second PMOS tube MP2, a second end of the fourth switch S4 is connected to the upper plate of the second capacitor C2 and the first end of the test auxiliary circuit, and the lower plate of the second capacitor C2 is grounded.

[0040] Specifically, in one embodiment of the present invention, the test auxiliary circuit includes a third amplifier A3, a fifth switch S5, a sixth switch S6, a fourth capacitor C4, and a second comparator X2. The positive input terminal of the third amplifier A3 is connected to the output voltage, the negative input terminal of the third amplifier A3 is connected to the first end of the sixth switch S6 and the first end of the fourth capacitor C4, the output terminal of the third amplifier A3 is connected to the second end of the fourth capacitor C4 and the negative input terminal of the second comparator X2, the positive input terminal of the second comparator X2 is connected to the first end of the fifth switch S5, the second end of the sixth switch S6 and the upper plate of the second capacitor C2, the output terminal of the second comparator X2 is connected to the first input terminal of the selector I2, and the second end of the fifth switch S5 is grounded.

[0041] The present invention provides a constant on-time generation circuit. The circuit first calibrates the resistance and capacitance errors using a foreground calibration mode. After entering a normal operating mode, the circuit dynamically adjusts the output delay of a calibration comparator to achieve accurate control of the constant on-time, thereby accurately controlling the operating frequency of a switching power supply.

[0042] The following combination Figure 6 and Figure 7 The working process of the foreground calibration mode of the present invention is described as follows:

[0043] refer to Figure 6In foreground calibration mode, the first selector I2 selects the output of the second comparator X2 as the set signal for the first RS flip-flop I1. Initially, the first switch S1 is closed, the fourth switch S4 is open, and the second and third switches S2 and S3 are simultaneously open. The second PMOS transistor MP2 charges the first capacitor C1 with a current equal to VIN / R1. When the top plate voltage of the first capacitor C1 exceeds the negative terminal voltage VR1 of the first comparator X1, the output voltage VRST of the first comparator X1 becomes 1, and the output voltage VTON of the first RS flip-flop I1 becomes 0. Simultaneously, the output voltage VTON of the first RS flip-flop I1 becomes 0, and the first switch S1 opens, the fourth switch S4 closes, and the fifth and sixth switches S5 and S6 are opened. The second PMOS transistor MP2 begins charging the second capacitor C2. During the charging process of the second capacitor C2, the third switch S3 is closed, sampling the top plate voltage of the first capacitor C1. The difference between the top plate voltage and the output voltage VOUT is integrated by the second amplifier A2 onto the third capacitor C3, causing the output voltage VR1 of the second amplifier A2 to change in opposite directions. Specifically, when the output voltage VOUT exceeds the top plate voltage of the first capacitor C1, the output voltage VR1 of the second amplifier A2 increases; when the output voltage VOUT falls below the top plate voltage of the first capacitor C1, the output voltage VR1 of the second amplifier A2 decreases. The third switch S3 is then opened, and the second switch S2 is closed, clearing the charge on the first capacitor C1. At this point, the second capacitor C2 is still charging. Similarly, when the top plate voltage of the second capacitor C2 exceeds the negative terminal voltage VR2 of the second comparator X2, the output terminal voltage VSET of the second comparator X2 becomes 1, and the output voltage VTON of the first RS flip-flop I1 becomes 1. At the same time that the output voltage VTON of the first RS flip-flop I1 changes to 1, the fourth switch S4 opens, the first switch S1 closes, the second switch S2 opens, and the second PMOS transistor MP2 begins charging the first capacitor C1 again. During the charging process of the first capacitor C1, the sixth switch S6 closes, sampling the top plate voltage of the second capacitor C2. The difference between the top plate voltage and the output voltage VOUT is integrated by the third amplifier A3 onto the fourth capacitor C4, causing the output voltage VR2 of the third amplifier A3 to change in opposite directions. Specifically, when the output voltage VOUT exceeds the top plate voltage of the second capacitor C2, the output voltage VR2 of the third amplifier A3 increases; when the output voltage VOUT falls below the top plate voltage of the second capacitor C2, the output voltage VR2 of the third amplifier A3 decreases. The output voltage VTON of the first RS flip-flop I1 completes one cycle, resulting in a periodic square wave waveform. After multiple cycles, the output voltages VR1 and VR2 of the second and third amplifiers A2 are modulated to a level slightly lower than VOUT, so that the final charged voltages of the first and second capacitors C1 and C2 equal the output voltage VOUT.The square wave period T output by the output voltage VTON of the first RS trigger I1 is equal to VOUT / VIN*R1(C1+C2). The foreground test mode understands the process deviation of the capacitor and resistor by testing this frequency, and calibrates the frequency by adjusting the R1 value. The calibrated R1 value will be used in the normal working mode.

[0044] The following combination Figure 8 and Figure 9 The working process of the normal working mode of the present invention is described as follows:

[0045] Normal working mode is as follows Figure 8 As shown, the first selector I2 selects the output signal VTRIG of the previous-stage circuit as the set signal for the first RS flip-flop I1. The fifth switch S5, the sixth switch S6, the third amplifier A3, the second comparator X2, and the fourth capacitor C4 are all disconnected and excluded from the circuit. The first switch S1 and the fourth switch S4 are always closed. When the trigger signal VTRIG received from the previous-stage circuit is 1, the first RS flip-flop I1 outputs 1. Simultaneously, the second switch S2 is disconnected, and the second PMOS transistor MP2 charges the first capacitor C1 and the second capacitor C2 with a current of VIN / R1. When the top plate voltage of the first capacitor C1 and the second capacitor C2 exceeds the negative terminal voltage VR1 of the first comparator X1, the output terminal VRST of the first comparator X1 changes to 1, and the output voltage VTON of the first RS flip-flop I1 changes to 0. The circuit outputs a constant-time on pulse. While waiting for the next VTRIG signal, the third switch S3 closes to sample the top plate voltages of the first and second capacitors C1 and C2. The difference between the top plate voltages and the output voltage VOUT is integrated by the second amplifier A2 onto the third capacitor C3, causing the output voltage VR1 of the second amplifier A2 to change in opposite directions. Specifically, when the output voltage VOUT exceeds the top plate voltages of the first and second capacitors C1 and C2, the output voltage VR1 of the second amplifier A2 increases; when the output voltage VOUT falls below the top plate voltages of the first and second capacitors C1 and C2, the output voltage VR1 of the second amplifier A2 decreases. The third switch S3 then opens, and the second switch S2 closes, clearing the charge on the first and second capacitors C1 and C2. After several cycles of regulation, the output voltage VR1 of the second amplifier A2 stabilizes at a value slightly lower than VOUT, bringing the final charged voltages of the first and second capacitors C1 and C2 equal to VOUT. Thus, the width of a constant-time on pulse, TON, equals VOUT / VIN*R1*(C1+C2), which is equal to the cycle value calibrated in the foreground calibration mode. The switching power supply uses constant on-time control with this time width, and its period is always equal to R1*(C1+C2). It is not affected by input and output voltages and process deviations, achieving precise control.

[0046] In summary, the present invention provides a constant on-time generating circuit, which can accurately control the constant on-time according to the changes in the input and output voltages of the switching power supply, thereby accurately controlling the switching frequency of the switching power supply.

[0047] In each of the descriptions provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0048] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0049] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0050] It should be noted that the above embodiments illustrate rather than limit the invention, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising several different elements and by means of appropriately programmed computers. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A constant on-time generating circuit, characterized in that: The invention comprises a first RS trigger I1, a comparison signal control circuit (100), a first comparison signal generating circuit (200), a second comparison signal generating circuit (300), a reset signal control circuit (400), a test auxiliary circuit (500) and a selector I2, The comparison signal control circuit (100) is connected to a first end of the first comparison signal generating circuit (200) and a first end of the second comparison signal generating circuit (300); the second end of the first comparison signal generating circuit (200) is connected to a first end of the reset signal control circuit (400); the second end of the reset signal control circuit (400) is connected to a reset end of the first RS trigger I1; the second end of the second comparison signal generating circuit (300) is connected to a first end of the test auxiliary circuit (500); the second end of the test auxiliary circuit (500) is connected to a first input end of the selector I2; the second input end of the selector I2 is connected to an output signal of a previous stage circuit; the output end of the selector I2 is connected to a set end of the first RS trigger I1; In a calibration mode, the second end of the test auxiliary circuit (500) is connected to the set end of the first RS trigger I1 via the selector I2, and the output signal of the first RS trigger I1 is calibrated via the test auxiliary circuit (500) and the reset signal control circuit (400); In normal working mode, the output signal of the upper-level circuit is connected to the set terminal of the first RS trigger I1 through the selector I2, and the input delay of the reset terminal of the first RS trigger I1 is eliminated through dynamic adjustment of the reset signal control circuit (400).

2. The constant on-time generating circuit according to claim 1, wherein: The comparison signal control circuit (100) comprises a first amplifier A1, a first PMOS transistor MP1, a resistor R1, and a second PMOS transistor MP2; the negative input terminal of the first amplifier A1 is connected to an input voltage; the positive input terminal of the first amplifier A1 is connected to the drain of the first PMOS transistor MP1 and the first end of the resistor R1; the output terminal of the first amplifier A1 is connected to the gate terminal of the first PMOS transistor MP1 and the gate terminal of the second PMOS transistor MP2; the source terminal of the first PMOS transistor MP1 and the source terminal of the second PMOS transistor MP2 are connected to a power supply; the second end of the resistor R1 is grounded; and the drain terminal of the second PMOS transistor MP2 is connected to the first end of the first comparison signal generating circuit and the first end of the second comparison signal generating circuit.

3. The constant on-time generating circuit according to claim 2, wherein: The first comparison signal generating circuit (200) comprises a first switch S1, a first capacitor C1 and a second switch S2, wherein the first end of the first switch S1 is connected to the drain end of the second PMOS transistor MP2, the second end of the first switch S1 is connected to the upper plate of the first capacitor C1, the first end of the second switch S2 and the first end of the reset signal control circuit, and the lower plate of the first capacitor C1 and the second end of the second switch S2 are grounded.

4. The constant on-time generating circuit according to claim 3, wherein: The reset signal control circuit (400) comprises a sampling compensation circuit (410) and a first comparator X1, wherein the positive input terminal of the first comparator X1 is connected to the upper plate of the first capacitor C1, the negative input terminal of the first comparator X1 is connected to the sampling compensation circuit (410), and the output terminal of the first comparator X1 is connected to the reset terminal of the first RS trigger I1.

5. The constant on-time generating circuit according to claim 4, wherein: The sampling compensation circuit (410) comprises a third switch S3, a second amplifier A2 and a third capacitor C3, wherein the first end of the third switch S3 is connected to the upper plate of the first capacitor C1, the positive input end of the second amplifier A2 is connected to the output voltage, the negative input end of the second amplifier A2 is connected to the second end of the third switch S3 and the first end of the third capacitor C3, and the output end of the second amplifier A2 is connected to the negative input end of the first comparator X1 and the second end of the third capacitor C3.

6. The constant on-time generating circuit according to claim 2, wherein: The second comparison signal generating circuit includes a fourth switch S4 and a second capacitor C2, a first end of the fourth switch S4 is connected to the drain end of the second PMOS transistor MP2, a second end of the fourth switch S4 is connected to the upper plate of the second capacitor C2 and the first end of the test auxiliary circuit, and a lower plate of the second capacitor C2 is grounded.

7. The constant on-time generating circuit according to claim 6, wherein: The test auxiliary circuit includes a third amplifier A3, a fifth switch S5, a sixth switch S6, a fourth capacitor C4, and a second comparator X2. The positive input of the third amplifier A3 is connected to the output voltage, the negative input of the third amplifier A3 is connected to the first end of the sixth switch S6 and the first end of the fourth capacitor C4, the output of the third amplifier A3 is connected to the second end of the fourth capacitor C4 and the negative input of the second comparator X2, the positive input of the second comparator X2 is connected to the first end of the fifth switch S5, the second end of the sixth switch S6, and the upper plate of the second capacitor C2, the output of the second comparator X2 is connected to the first input of the selector I2, and the second end of the fifth switch S5 is grounded.

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