Binary digit equal comparator and method

Abstract

The invention discloses a binary digit equal comparator and method, and belongs to the technical field of integrated circuits. The comparator is composed of a digital selection module located at the front stage and a digital comparison module located at the rear stage, the digital selection module comprises a plurality of either-or units, binary input data A and binary input data B are input into the either-or units, and positive and negative signals of the input data A serve as control signals to select positive and negative signals of the input data B; the digital comparison module comprises an MOS reset tube and a plurality of MOS digital input tubes, and the drain electrode of the MOS reset tube is connected with the drain electrode of the MOS digital input tubes and serves as an output end; a comparison code output by the digital selection module is connected to an MOS digital input tube of the digital comparison module to serve as a gating control signal. The digit of the comparator is related to the number of input tubes of the digital selection module and the digital comparison module, the digit is completely proportional to the area, and the comparator has the advantages of low design complexity, small area, low power consumption and the like.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology, and relates to a binary digital comparator including MOS transistors, in particular to a binary digital comparator and method that can implement the function of binary digital equality comparating, occupy less resources and have low power consumption. Background Art

[0002] Binary digital comparators are usually present in various circuits such as microprocessors, communication systems, encryption devices, image processing, 3D graphics, etc. Implementing low-power and small-area designs is one of the crucial issues in digital CMOS circuits.

[0003] Digital comparators basically involve the comparison of two n-bit binary numbers and are a key part of almost all digital systems. Digital comparators can be classified into two categories: full comparators and equality comparators. A full comparator compares two n-bit binary numbers to determine which is larger or whether they are equal. In a full comparator, given two n-bit binary input data A and input data B, they can respectively identify three conditions, namely A > B, A < B, and A = B. "Ternary Logic Dynamic CMOS Comparators" (Advanced Materials Research, 2011, 317: 1177-1182) proposed equality comparators. As the name implies, in equality comparators, they only judge whether two inputs are equal. This equality comparator is usually used in integrated circuit modules with large area constraints, such as pixel circuits of image sensors or other module circuits for implementing the comparison of multiple signal magnitudes.

[0004] Traditional comparator designs use subtractor and adder components to perform comparisons of large digits, which can lead to latency problems. Priority-based comparators significantly affect the circuit complexity and the deterioration of operating speed as the input increases.

[0005] Shilparani Panda et al. proposed a low-power 64-bit CMOS binary comparator in the article "ANovel Dedicated Low Power 64Bit DigitalComparator Using Cmos Logic" (Journal of Embedded Systems, 2014, 2(2): 28-31), which realizes whether a number is greater than, equal to, or less than another number, and improves the power consumption and speed of the circuit.

[0006] Nalini Bodasingi et al. proposed an improved priority encoder technology in the paper "Modified priority encoder based hardware-efficient N-bit comparator" (International Journal of Electronics Letters, 2023, 11(4): 426-438). The area of the proposed 32-bit digital comparator is 573.73 units, which is 20% higher than that of the traditional comparator, and the speed is increased by 50% compared with the traditional comparator.

[0007] Kim, J.Y, Yoo, H.J. et al. in "Bitwise competition logic for compact digital comparator"

[0008] (2007 IEEE Asian Solid-State Circuits Conference. IEEE, 2007: 59-62) The improved digital comparator consumes 964 transistor levels in a 32-bit comparator and has a power consumption of 2.53 mW at a frequency of 200 MHz.

[0009] The novel multiplexer-based technology proposed by D.N. Mukherjee et al. in the paper "A Novel Design of 12-bit Digital Comparator Using Multiplexer for High Speed Application in 32-nm CMOS Technology" (IETE Journal of Research, 2022, 68(2): 1350-1357) aims to achieve low power consumption, small area and high-speed performance. The design uses multiplexers and consists of two sub-modules. The first sub-module uses two 2:1 multiplexers to judge the equality of each bit in 2-bit data; the second sub-module uses three 2:1 multiplexers to judge whether (A) is less than or equal to (B), and finally determines whether (A) is greater than (B) through a NOR gate. The number of required transistors is 8N + 2. The power consumption of the multiplexer-based 2-bit comparator is reduced to 0.09 μW. Compared with the existing transmission-gate logic-based 2-bit comparator, the power consumption is reduced by about 78%, and the number of transistors is reduced by about 75.67% from 18, reducing the overall area. Based on this, the power consumption of the 12-bit digital comparator based on the novel technology is optimized to 0.56 μW, and the number of transistors is 106. For the multiplexer-based comparator that only judges the equality of each bit in 2-bit data, the number of transistors consumed by the 2-bit comparator is 10; the number of transistors of the 12-bit digital comparator is 50.

[0010] A faster, more energy-efficient, or more compact digital comparator will be required for future circuits. Therefore, in the design, it is meaningful to design a binary digital comparator with low hardware resource overhead and low power consumption. Summary of the Invention

[0011] The object to be solved by the present invention is to provide a digital comparator circuit that can implement the binary digital comparison function, occupies less resources and has low power consumption, meeting the requirements of the system for area and power consumption.

[0012] To achieve the above object, the technical solution of the present invention is as follows:

[0013] A binary digital equality comparator, which consists of a digital selection module at the front stage and a digital comparison module at the rear stage. The digital selection module includes several one - of - two units, whose inputs are binary input data A and input data B, and the positive and negative signals of input data A are used as control signals to select the positive and negative signals of input data B. The digital comparison module includes a MOS reset transistor and several MOS digital input transistors. The drain of the MOS reset transistor is connected to the drain of the MOS digital input transistors and serves as the output terminal. The comparison code output by the digital selection module is connected to the MOS digital input transistors of the digital comparison module as the control signal for gating.

[0014] Further, the number of the digital selection modules and the number of the MOS digital input transistors in the digital comparison module are both the same as the number of bits n of the binary input data A and input data B.

[0015] Further, n MOS digital input transistors are connected in series with each other.

[0016] Further, the MOS reset transistor and the MOS digital input transistor at the highest bit form the comparator output channel.

[0017] Further, the reset signal RST is connected to the gate of the MOS reset transistor, and the reset signal RST performs a high - level reset on the output of the digital comparison module through the MOS reset transistor.

[0018] Further, when the n - bit digital input to the MOS digital input transistors of the digital input comparator from the output of the digital selection module, all MOS digital input transistors are turned on to form a charge discharge path to reduce the voltage to 0V.

[0019] Further, both the MOS reset transistor and the MOS digital input transistor are NMOS transistors.

[0020] A comparison method using the binary digital equality comparator of the present invention includes:

[0021] The positive and negative signals of input data A are used as control signals to select the positive and negative signals of input data B through the one - of - two of the digital selection module.

[0022] When A and B are equal, the comparison code C output at the output terminal of the digital selection module outputs a comparison code all of whose bits are 1. The connection between the digital comparison module and the digital selection module is that the comparison code C output by the digital selection module is connected to the gates of the MOS digital input transistors of the digital comparison module as the control signal for gating. At this time, the gates of the MOS digital input transistors are connected to a high potential, all MOS digital input transistors are turned on, the voltage drops to 0, causing the output signal D to flip. At this time, it indicates that A = B.

[0023] When the binary digits A and B are not equal, at least one of the comparison codes C output at the output terminal of the digital selection module is 0. When the comparison code is input to the gates of the MOS digital input transistors of the digital comparison module, at least one MOS transistor is in the off state. At this time, the discharge path is not conducting, and the voltage at the output terminal remains at a high potential, and the output signal D does not flip. At this time, it indicates that A≠B.

[0024] Further, before another set of binary digits is compared, the comparator is reset through an external reset signal RST, and the voltage at the output terminal reaches a high potential.

[0025] The beneficial effects of the present invention include:

[0026] 1. The number of bits of the binary digit equality comparator can be controlled according to the actual circuit requirements. To increase or decrease the number of bits, only the number of digital selection modules and digital input units needs to be increased or decreased;

[0027] 2. The area of the binary digit equality comparator is related to the number of its bits. When increasing the number of bits, its area only increases by the corresponding number of digital selection modules and digital input units, and will not increase geometrically;

[0028] 3. The power consumption of the binary digit equality comparator is related to the number of its bits. When increasing the number of bits, its power consumption increase is also much lower than that of other types of comparators. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The principle block diagram of the binary digit equality comparator in the present invention is shown.

[0030] Figure 2 The circuit schematic diagram of the digital comparison module in the present invention is shown.

[0031] Figure 3 The connection mode block diagram of the digital selection module and the digital comparison module in the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0033] As Figure 1 shown, the binary digit equality comparator of the present invention is composed of a digital selection module at the front stage and a digital comparison module at the rear stage. The front-stage digital selection module includes a two-way selection unit; the rear-stage digital comparison module includes a reset unit and a digital input unit. The connection relationships of its various parts are as Figure 2As shown in the figure. The number of digital selection modules and the number of transistors in the digital input unit of the digital comparison module are both the same as the number of bits of the binary input data A and B. That is, when the number of bits of the binary input data A and B is n bits, the number of digital selection modules and the number of transistors in the digital input unit of the digital comparison module are both n.

[0034] The digital selection module takes the binary input data A and B as inputs. That is, the positive and negative signals of digital A are used as control signals to select the positive and negative signals of input data B through the one-bit selection of the digital selection module. When A and B are equal, the comparison code C output at the output end of the digital selection module outputs a comparison code all of 1. The connection between the digital comparison module and the digital selection module is that the comparison code C output by the digital selection module is connected to the gate of the NMOS transistor of the digital input unit of the digital comparison module as the gating control signal. At this time, the gate of the NMOS transistor of the digital input unit is connected to a high potential, so that all the NMOS digital input transistors are turned on, discharging the charge at the output end, and the voltage drops to 0. At this time, it means A = B. Before the next comparison of another group of binary numbers, the comparator is reset through the external reset signal RST, and the voltage at the output end reaches the high potential again. Similarly, when the binary numbers A and B are not equal, at least one of the comparison codes C output at the output end of the digital selection module is 0. When the comparison code is input to the gate of the digital input unit of the digital comparison module, at least one NMOS transistor is in the off state. At this time, the discharge path of the digital input unit is not turned on, and the voltage at the output end still remains at the high potential, and the output signal D does not flip. At this time, it means A ≠ B.

[0035] Embodiment

[0036] As Figure 3 shown in the figure, the digital selection module inputs signals A and B; the signal RST is responsible for resetting the digital comparison module before each comparator starts to work. Specifically, it performs a high-level reset on the output end of the digital comparison module.

[0037] As Figure 2 shown in the figure, when the number of bits of the binary input data A and B is set to 9 bits, the number of digital selection modules and the number of transistors in the digital input unit of the digital comparison module are 9 at this time. First, the binary input data A and B are respectively subjected to logical comparison through the input end of the digital selection module. Each corresponding bit in A and B is logically selected in the corresponding digital selection module. When the corresponding bit numbers are the same, the corresponding bit of the output comparison code C outputs a high potential 1. When the corresponding bit numbers are different, the corresponding bit of the output comparison code C outputs a low potential 0. Thus, a 9-bit combination of comparison codes is output in parallel.

[0038] The 9-bit comparison codes output in parallel by the digital selection module are sequentially connected to the gates of the transistors in the digital input unit of the digital comparison module to control the conduction and cutoff of the transistors in the digital input unit. These 9-bit digital input unit transistors are connected in series. Therefore, when all 9-bit comparison codes are at a high potential, the channel conducts; otherwise, the channel cuts off.

[0039] Before the digital comparison module compares two 9-bit binary numbers A and B, the reset signal RST changes from a high level to a low level, and the voltage across its two ends is reset to a high level through the PMOS reset transistor. When the comparison starts, the reset signal RST changes from a low level to a high level, and the input data A and B are input, and the comparator starts to work. Then the digital input unit receives the 9-bit comparison code C output from the digital selection module, and thus determines whether all the comparison codes C are at a high potential. If so, all the NMOS transistors in the digital input unit conduct, and the path starts to discharge, and the voltage drops to a low potential. At this time, it indicates that the binary number A = B; otherwise, the NMOS transistors in the digital input unit do not conduct, and the voltage remains at a high potential. At this time, it indicates that the binary number A ≠ B.

[0040] From the utilization of transistor-level resources of the binary digital comparator of the present invention, the number of transistors required = N × the number of digital storage selection modules + N × the number of NMOS transistors for the digital input unit + the number of reset transistors = N × (2nmos) + N × (1nmos) + 1 = 3N + 1.

[0041] In the present invention, substituting the transistor-level circuit scale of the 9-bit digital equality comparator into the formula (3N + 1) gives 28 transistors, while in the prior art "ANovel Design of 12-bit Digital Comparator Using Multiplexer forHigh Speed Application in 32-nm CMOS Technology", the transistor-level circuit scales are all in the order of hundreds to thousands, and the scale difference is more than one order of magnitude.

[0042] By simulating the binary digital comparator, an external counter is used to give the number A and compare it with the pre-stored data B. During the entire 9-bit counter counting and comparison period, the average power consumption is on the order of a few nW. While the average power consumption of similar binary digital comparators is on the order of μW or even mW.

[0043] It can be seen from the embodiments that the binary digital comparator of the present invention can directly implement binary digital comparisons of any number of bits by modifying the number of digital selection modules and the number of transistors in the digital input unit, and the control circuit of the binary digital comparator is simple, and the overall hardware resource overhead is small.

Claims

1. A binary digital equality comparator, characterized in that, The comparator consists of a digital selection module located at the front stage and a digital comparison module located at the rear stage; The digital selection module includes a number of one - of - two units. Its inputs are binary input data A and input data B. The positive and negative signals of input data A are used as control signals to select the positive and negative signals of input data B; The digital comparison module includes a MOS reset transistor and a number of MOS digital input transistors. The drain of the MOS reset transistor is connected to the drains of the MOS digital input transistors and serves as the output terminal; The comparison code output by the digital selection module is connected to the MOS digital input transistors of the digital comparison module as the control signal for gating.

2. The comparator according to claim 1, wherein: The number of the digital selection modules and the number of MOS digital input transistors in the digital comparison module are both the same as the number of bits n of the binary input data A and input data B.

3. The comparator according to claim 2, wherein: The n MOS digital input transistors are connected in series with each other.

4. The comparator according to claim 3, wherein: The MOS reset transistor and any one of the MOS digital input transistors form the comparator output channel.

5. The comparator according to claim 4, wherein: The reset signal RST is connected to the gate of the MOS reset transistor. The reset signal RST performs a high - level reset on the output of the digital comparison module through the MOS reset transistor.

6. The comparator according to claim 5, wherein: When the n - bit digital output from the digital selection module is input to the MOS digital input transistors of the comparator, all the MOS digital input transistors are turned on to form a charge discharge path to reduce the voltage to 0V.

7. The comparator according to any one of claims 1 - 6, wherein: The MOS reset transistor is an NMOS transistor.

8. The comparator according to any one of claims 1 - 6, wherein: The MOS digital input transistors are NMOS transistors.

9. A comparison method for a binary digital comparator according to any one of claims 1-8, characterized in that, Including: The positive and negative signals of input data A are used as control signals to select the positive and negative signals of input data B through the one - of - two of the digital selection module; When A and B are equal, the comparison code C output by the output terminal of the digital selection module outputs a comparison code with all 1s. The connection between the digital comparison module and the digital selection module is that the comparison code C output by the digital selection module is connected to the gates of the MOS digital input transistors of the digital comparison module as the control signal for gating. At this time, the gates of the MOS digital input transistors are connected to a high potential, all the MOS digital input transistors are turned on, the voltage drops to 0, causing the output signal D to flip. At this time, it indicates that A = B; When the binary numbers A and B are not equal, at least one of the comparison codes C output by the output terminal of the digital selection module is 0. When the comparison code is input to the gates of the MOS digital input transistors of the digital comparison module, at least one MOS transistor is in the off state. At this time, the discharge path is not conducting, and the voltage at the output terminal still remains at a high potential, and the output signal D does not flip. At this time, it indicates that A ≠ B.

10. The comparison method according to claim 9, wherein: Before comparing another set of binary digits, the comparator is reset by an external reset signal RST, and the voltage at the output terminal reaches a high potential.

Images