A time constant calibration circuit for a continuous-time sigma-delta modulator

Abstract

The present invention belongs to the field of integrated circuit technology and specifically relates to a circuit for calibrating the time constant of a continuous-time sigma-delta modulator. By using a fixed-time integration method and utilizing multiples of the sigma-delta modulator's system sampling clock period as the integration time, this circuit not only reduces the need for an additional high-frequency calibration clock but also enables high-precision time constant calibration even in the presence of system clock errors. This design significantly reduces the deviation between the system transfer function of an actual sigma-delta modulator circuit and that of an ideal system, ensuring high modulator performance. Furthermore, by employing the same operational amplifier and proportional capacitors and resistors as those used in the modulator circuit, the circuit emulates the actual integration process to the greatest extent possible, further improving calibration accuracy.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a calibration circuit for a time constant of a continuous-time sigma-delta modulator. Background Art

[0002] In the design of a continuous-time sigma-delta modulator, the integrator time constant (determined by resistor R and capacitor C) is crucial for ensuring system performance. However, during actual chip manufacturing, due to process variations, the actual resistor and capacitor values ​​can deviate significantly from the designed values, resulting in time constant deviations of up to 50% or more. A variation of more than 10% in the integrator coefficient significantly degrades the performance of the sigma-delta modulator, especially in systems with high out-of-band gain. Therefore, accurately calibrating the integrator time constant becomes a key challenge in ensuring the performance of continuous-time sigma-delta modulators.

[0003] Existing calibration methods, such as analog calibration schemes based on current mirror integration, have multiple error sources, including current mirror mismatch, parasitic capacitance effects, and kickback noise in the dynamic comparator. These factors can lead to inaccurate calibration results, thereby affecting the overall performance of the modulator. Summary of the Invention

[0004] The purpose of the present invention is to provide a calibration circuit for the time constant of a continuous-time sigma-delta modulator, and adopt a static comparator to avoid the defects existing in some traditional calibration circuits, with higher calibration accuracy, so as to solve the problems raised in the above background technology.

[0005] To achieve the above-mentioned object, the present invention adopts the following technical solution: a calibration circuit for the time constant of a continuous-time sigma-delta modulator, comprising an integrator, a static comparator, and a digital logic circuit; wherein the integrator is a copy of the integrator circuit in the sigma-delta modulator, and comprises an input resistor R1, an integrating capacitor array C, a fixed resistor R2, an operational amplifier, and switches S1, S2, and S3; the access area of ​​the integrating capacitor array C is adjusted by controlling the switch with a digital codeword; the input end of the integrator is connected to a reference voltage V REFP and V REFN , the output end is connected to the integrating capacitor array C; the output end of the integrator is connected to the input end of the static comparator, and the output end of the static comparator is connected to the digital logic circuit through a D flip-flop; the digital logic circuit adjusts the digital code value of the integrating capacitor array C according to the output result of the comparator.

[0006] Preferably, the working modes of the integrator include a differential amplification mode and an integrator mode.

[0007] Preferably, the input end of the integrator includes four branches: V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2; switches S1 and S3 are driven by the same clock Control, switch S2 is controlled by the clock Control; the integrator is switched between the differential amplifier mode and the integrator mode by switching the switch.

[0008] Preferably, in the differential amplifier mode, switches S1 and S3 are closed, the operational amplifier works as a differential amplifier, and the input terminal V IP Connect V REFP -R1-S1 branch, input terminal V IN Connect V REFN -R1-S1 branch; in integrator mode, switches S1 and S3 are open, switch S2 is closed, the operational amplifier works in integrator mode, and the input terminal V IP Connect V REFN -R1-S2 branch, input terminal V IN Connect V REFP -R1-S2 branch.

[0009] Preferably, in the integrator mode, the integrating capacitor array C is charged and discharged under the action of a constant differential current, the charging and discharging time is controlled by the frequency division of the system sampling clock, and the integration process lasts for n system sampling clock cycles, where n is a preset integer; after the integration is completed, the differential output voltage of the operational amplifier is compared by a static comparator to determine whether the actual value of the integrating capacitor array C meets the designed time constant.

[0010] Preferably, the output result of the static comparator is delayed after the integration is completed and latched by the D flip-flop at the rising edge of the clock; the output signal of the D flip-flop is sampled by the digital logic circuit to adjust the digital code value of the integrating capacitor array C.

[0011] Preferably, the digital logic circuit adjusts the digital code value of the integrating capacitor array C by binary division; if the output result of the comparator is 0, the access area of ​​the integrating capacitor array C is reduced; if the output result of the comparator is 1, the access area of ​​the integrating capacitor array C is increased; after N cycles, N is the number of digital code bits of the integrating capacitor array C, and finally the calibrated time constant is obtained.

[0012] Preferably, the static comparator is a fully differential structure, and its positive input terminal is connected to the output terminal V ON , the negative input terminal is connected to the output terminal V OP .

[0013] Technical effects and advantages of the present invention: Compared with the prior art, the present invention provides a continuous-time sigma-delta modulator time constant calibration circuit with the following advantages:

[0014] The present invention replaces the traditional dynamic comparator with a differential structure and a static comparator, effectively avoiding calibration errors caused by current mirror mismatch, parasitic capacitance errors, and dynamic comparator kickback noise. By using a fixed-time integration method and utilizing the system sampling clock period of the sigma-delta modulator as the integration time, not only is the need for an additional high-frequency calibration clock reduced, but high-precision time constant calibration can also be achieved even when there is a deviation in the system clock period. This design can significantly reduce the deviation between the system transfer function of the actual sigma-delta modulator circuit and the ideal system, ensuring the high performance of the modulator. At the same time, by using the same operational amplifier and proportional capacitors and resistors as the modulator circuit, the real integration process is simulated to the greatest extent possible, thereby further improving the accuracy of the calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A circuit diagram of a calibration circuit of the present invention;

[0016] Figure 2 It is a timing logic diagram of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0018] The present invention provides a calibration circuit for a time constant of a continuous-time sigma-delta modulator, comprising an integrator, a static comparator and a digital logic circuit;

[0019] The integrator is a copy of the integrator circuit in the sigma-delta modulator, including input resistor R1, integrating capacitor array C, fixed resistor R2, operational amplifier, and switches S1, S2, and S3.

[0020] The access area of ​​the integrating capacitor array C is adjusted by the digital code word control switch; the input end of the integrator is connected to the reference voltage V REFP and V REFN, the output end is connected to the integrating capacitor array C; the output end of the integrator is connected to the input end of the static comparator, and the output end of the static comparator is connected to the digital logic circuit through a D flip-flop; the static comparator is a fully differential structure, and its positive input end is connected to the output end V of the integrator ON , the negative input terminal is connected to the output terminal V OP The digital logic circuit adjusts the digital code value of the integrating capacitor array C according to the output result of the comparator.

[0021] Furthermore, the working modes of the integrator include a differential amplification mode and an integrator mode.

[0022] Specifically, the input of the integrator includes four branches: V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2; switches S1 and S3 are driven by the same clock Control, switch S2 is controlled by the clock Control; the integrator is switched between the differential amplifier mode and the integrator mode by switching the switch.

[0023] In the differential amplifier mode, switches S1 and S3 are closed, and the operational amplifier works as a differential amplifier. IP Connect V REFP -R1-S1 branch, input terminal V IN Connect V REFN -R1-S1 branch; in integrator mode, switches S1 and S3 are open, switch S2 is closed, the operational amplifier works in integrator mode, and the input terminal V IP Connect V REFN -R1-S2 branch, input terminal V IN Connect V REFP -R1-S2 branch.

[0024] In integrator mode, the integrating capacitor array C is charged and discharged under the action of a constant differential current. The charge and discharge time is controlled by the frequency division of the system sampling clock. The integration process lasts for n system sampling clock cycles, where n is a preset integer. After the integration is completed, the differential output voltage of the operational amplifier is compared through a static comparator to determine whether the actual value of the integrating capacitor array C meets the designed time constant.

[0025] Furthermore, the output result of the static comparator is delayed after the integration is completed and latched by the D flip-flop at the rising edge of the clock; the output signal of the D flip-flop is sampled by the digital logic circuit and used to adjust the digital code value of the integrating capacitor array C.

[0026] In addition, the digital logic circuit adjusts the digital code value of the integrating capacitor array C through binary division; if the output result of the comparator is 0, the access area of ​​the integrating capacitor array C is reduced; if the output result of the comparator is 1, the access area of ​​the integrating capacitor array C is increased; after N cycles, N is the number of digital code bits of the integrating capacitor array C, and the calibrated time constant is finally obtained.

[0027] The following is a detailed description with reference to the accompanying drawings:

[0028] like Figure 1 As shown in Figure 1, the integrator in the calibration circuit is a replica of the integrator circuit in the sigma-delta modulator. It includes capacitors, resistors, and an operational amplifier, ensuring that its capacitor and resistor values ​​maintain a specific proportional relationship with the prototype circuit. In this design, the resistor value is fixed, while the integrating capacitor is designed to be adjustable, with the value of the capacitor connected to the integrator being adjusted by a switch controlled by a digital codeword.

[0029] First, configure the op amp in voltage amplifier mode and apply a specific input voltage to charge the integrating capacitor. Next, switch the amplifier to integrator mode and adjust the input voltage to ensure that the integrator capacitor charges and discharges at a constant current. The duration of the charge and discharge is controlled by dividing the system sampling clock. This allows both the system clock and the capacitors and resistors to participate in the calibration process, resulting in results that are more consistent with actual conditions.

[0030] The integrator's output is connected to a static comparator. After the integrating capacitor completes its charge and discharge cycles, the comparator outputs a comparison result, which is sampled by a D-type flip-flop and fed into a digital logic circuit for further processing. Finally, the digital logic circuit adjusts the capacitor array's code based on the comparator's output, and the process repeats. After multiple cycles, a stable capacitor code value is obtained, which is the final result of time constant calibration.

[0031] There are four branches at the integrator input, two sets of input reference voltages V REFP and V REFN The other end of the resistor R1 is connected to two sets of switches S1 and S2 respectively, forming V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2, four branches. V REFP -R1-S1, V REFN -R1-S2 two branches of switches S1, S2 and the other end of the operational amplifier input V IP Connected. V REFP -R1-S1, V REFP-R1-S2 two branches of switches S1, S2 and the other end of the operational amplifier input V IN At the input and output of the operational amplifier, V IP With V ON , and V IN With V OP Between them, a parallel path consisting of an integrating capacitor array C, a resistor R2, and a switch S3 is connected, wherein the resistor R2 is connected in series with the switch S3. Switches S1 and S3 are driven by the same clock. Control, switch S2 is controlled by the clock control.

[0032] The output of the integrator V OP and V ON The comparator's output is connected to the negative and positive inputs of the comparator, respectively. The comparator's output is connected to the input of a D-type flip-flop, whose clock input receives a signal from clock source CLKD. On the rising edge of CLKD, the system samples the comparator's output. The D-type flip-flop's output is further connected to a digital logic circuit, which processes the output and feeds back a digital code to control the capacitor array in the integrator.

[0033] like Figure 2 As shown in Figure 1, when switches S1 and S3 are closed, the operational amplifier works as a differential amplifier. IP Connect S1, R1 and V REFP , input terminal V IN Connect S1, R1 and V REFN Output voltage , so the difference in charge between the positive and negative integrating capacitors C at this time is .

[0034] It is worth noting that by appropriately increasing the resistance R1 and reducing the voltage The output voltage of the operational amplifier is limited to its output range. , ,in is a constant, so we get .

[0035] Next, after switches S1 and S3 are opened, switch S2 is closed. At this point, the operational amplifier operates in integrator mode, and R2 is disconnected from the operational amplifier input. IP Connect S2, R1 and V REFN , input terminal V IN Connect S2, R1 and V REFP A constant differential current flows through capacitor C. , after integration of n system sampling clock cycles, the differential output voltage of the operational amplifier is .

[0036] The known time constant is By adjusting the resistors R1 and R2, and the number of integrated clock cycles n, we can determine the values ​​m and n. ,now that Since m and n are fixed constants, the output differential voltage Approaching 0 In the present invention, only the capacitance is adjustable, so when the capacitance and resistance are affected by the manufacturing process, the designed time constant can be approached by adjusting the capacitance coding.

[0037] The output of the operational amplifier is connected to a static comparator. When the operational amplifier operates in differential amplification mode, , the comparator output remains at 0. During the integrator process, once The output of the comparator flips to 1. For a period of time after switch S2 is turned on, switch S1 is also in the open state. During this period of time, the output of the operational amplifier maintains the voltage value at the end of the integration to leave enough settling time for the comparator.

[0038] Since the static comparator has a certain delay, after the integration of the integrator is completed, there is a delay before the output of the comparator is latched into the output of the D flip-flop through the clock CLKD. O The output of the comparator does not change until the next rising edge of CLKD. The digital logic has enough time to process the output and feedback a new capacitance code value to start a new round of amplification, integration, and comparison. Approach .

[0039] The processing principle of digital logic is as follows: If the actual capacitance value is too large, then , get the final value of the integral , the output of the comparator is 0. After the digital logic detects the output 0, it changes the capacitance code value and reduces the integral capacitance value. On the contrary, if the actual capacitance value is too small, then , get the final value of the integral , the comparator output is 1. After detecting the output 1, the digital logic changes the capacitor code value, increasing the integral capacitor value. The feedback capacitor code value logic can be implemented using binary division. If the capacitor code value has N bits, the calibrated capacitor code value can be obtained after N cycles.

[0040] The time constant error of the calibration circuit is determined by the minimum unit capacitance of the capacitor array. The ideal time constant is , after calibration, the time constant with error is ,in is the minimum unit capacitance. Therefore, the relative error of the time constant is , it can be deduced that the maximum relative error rate is If the variation range of the capacitor array is to cover the 20% process deviation of the capacitor and resistor, we can get .therefore: hour, ; hour, ; hour, ; hour, To ensure that the time constant deviates less than 10% from the ideal value, the number of bits N in the capacitance code value needs to be greater than or equal to 4.

[0041] The calibration circuit of this invention abandons traditional clock-counting calibration methods and instead employs fixed-time integration and successive approximation techniques, eliminating the need for an additional high-frequency comparator clock. The integrator circuit completes integration within n system clock cycles and maintains the output state. A static comparator then outputs a 1-bit comparison result. The digital logic determines and adjusts the capacitance. This process is repeated multiple times, gradually bringing the integrator's time constant closer to the designed value.

[0042] This solution incorporates the three key parameters of the time constant—the system sampling clock, capacitance, and resistance—into the calibration process. These three parameters collectively determine the calibration result. Even with variations in the system clock period, this solution can still obtain the correct integration time constant through calibration. By adjusting the resistor ratio and integration time, the calibration result can achieve a more accurate time constant.

[0043] Compared to conventional calibration techniques, the present invention avoids current mirror ratio errors, the correlation of calibration errors with the counting clock, and comparison result errors caused by kickback noise in the dynamic comparator. Furthermore, it eliminates errors caused by parasitic capacitance of the integrating capacitor. In the differential amplification mode of the operational amplifier, the capacitor charging voltage is only related to the ratio of resistors R1 and R2. During the integrated circuit manufacturing process, although the absolute values ​​of the resistors or capacitors cannot be precisely controlled, the matching degree of the relative values ​​of the resistors and capacitors can be more accurately controlled, thereby enabling more precise management of the capacitor charging voltage.

[0044] In summary, this invention successfully achieves high-precision time constant calibration for a continuous-time sigma-delta modulator, with errors dependent only on the number of bits in the capacitor array and the comparator's offset voltage. By using the same operational amplifier and proportional capacitors and resistors as in the modulator circuit, the integration process is simulated to the greatest extent possible, thus reducing mismatch errors caused by the introduction of additional components and circuit structures.

[0045] The present invention uses multiples of the sigma-delta modulator's system sampling clock period as the calibration circuit's integration time, effectively avoiding the correlation between calibration error and calibration clock frequency in traditional calibration circuits. Even with errors in the system clock frequency, a relatively accurate time constant can still be obtained.

[0046] By adopting a fully differential amplifier structure, the integrated current only charges and discharges the capacitors across the input and output terminals, independent of parasitic capacitance, thus avoiding the errors caused by parasitic capacitance in traditional calibration circuits. In addition, the use of a static comparator instead of a traditional dynamic comparator effectively avoids erroneous comparison results caused by kickback noise in dynamic comparators.

[0047] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A time constant calibration circuit for a continuous-time sigma-delta modulator, characterized in that: Includes integrators, static comparators and digital logic circuits; The integrator is a copy of the integrator circuit in the sigma-delta modulator, including an input resistor R1, an integrating capacitor array C, a fixed resistor R2, an operational amplifier, and switches S1, S2, and S3; The access area of ​​the integrating capacitor array C is adjusted by a digital code word control switch; the input end of the integrator is connected to the reference voltage V REFP and V REFN , the output end is connected to the integrating capacitor array C; the output end of the integrator is connected to the input end of the static comparator, and the output end of the static comparator is connected to the digital logic circuit through a D flip-flop; the digital logic circuit adjusts the digital code value of the integrating capacitor array C according to the output result of the comparator; The working modes of the integrator include a differential amplification mode and an integrator mode; The input end of the integrator includes four branches: V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2; switches S1 and S3 are driven by the same clock Control, switch S2 is controlled by the clock Control; switching the integrator between the differential amplifier mode and the integrator mode is achieved by switching the switch; In differential amplifier mode, switches S1 and S3 are closed, and the operational amplifier works as a differential amplifier. IP Connect V REFP -R1-S1 branch, input terminal V IN Connect V REFN -R1-S1 branch; in integrator mode, switches S1 and S3 are open, switch S2 is closed, the operational amplifier works in integrator mode, and the input terminal V IP Connect V REFN -R1-S2 branch, input terminal V IN Connect V REFP -R1-S2 branch; In integrator mode, the integrating capacitor array C is charged and discharged under the action of a constant differential current. The charge and discharge time is controlled by the frequency division of the system sampling clock. The integration process lasts for n system sampling clock cycles, where n is a preset integer. After the integration is completed, the differential output voltage of the operational amplifier is compared through a static comparator to determine whether the actual value of the integrating capacitor array C meets the designed time constant.

2. A continuous-time sigma-delta modulator time constant calibration circuit according to claim 1, characterized in that: The output result of the static comparator is delayed after the integration is completed and latched by the D flip-flop at the rising edge of the clock; the output signal of the D flip-flop is sampled by the digital logic circuit to adjust the digital code value of the integrating capacitor array C.

3. A continuous-time sigma-delta modulator time constant calibration circuit according to claim 2, characterized in that: The digital logic circuit adjusts the digital code value of the integrating capacitor array C through a binary method; if the output result of the comparator is 0, the access area of ​​the integrating capacitor array C is reduced; if the output result of the comparator is 1, the access area of ​​the integrating capacitor array C is increased; after N cycles, where N is the number of digital code bits of the integrating capacitor array C, a calibrated time constant is finally obtained.

4. The time constant calibration circuit of a continuous-time sigma-delta modulator according to claim 1, wherein: The static comparator is a fully differential structure, and its positive input is connected to the output terminal V ON , the negative input terminal is connected to the output terminal V OP .

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