2-FSK signal frequency amplitude detection method based on FPGA

Abstract

The invention discloses a 2-FSK (Frequency Shift Keying) signal frequency amplitude detection method based on an FPGA (Field Programmable Gate Array), which relates to the field of communication systems and comprises the steps of signal acquisition, frequency analysis, amplitude spectrum conversion and amplitude estimation, frequency estimation, data output, signal preprocessing and frequency detection result calibration. In the acquisition step, signals are acquired by an eight-channel synchronous or sequential sampling technology; in the analysis step, frequencies are analyzed by a different-point FFT algorithm; in the conversion step, amplitude spectrums are obtained by processing spectrum conversion; in the estimation step, frequencies are calculated, verification and correction are carried out by a phase difference method; in the preprocessing step, a hardware filter is used to preprocess a signal, and in the calibration step, a detection result is calibrated and optimized according to a calibration formula. The method is high in detection precision, strong in real-time performance, high in detection speed, good in adaptability, low in cost, small in power consumption, beneficial to system integration and miniaturization and wide in application prospect in the field of communication and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of communication systems, and particularly to a method for detecting the frequency and amplitude of 2-FSK signals based on FPGA. Background Art

[0002] In modern communication systems, the 2-FSK (binary frequency shift keying) modulation technology is widely used in fields such as wireless communication, telemetry and remote control, and satellite communication due to its strong anti-interference ability and simple implementation. In these application scenarios, accurately detecting the frequency and amplitude of 2-FSK signals is crucial. For example, in wireless communication, the accurate detection of signal frequency and amplitude helps to achieve functions such as signal demodulation, synchronization, and power control, directly affecting the quality and reliability of communication.

[0003] However, the existing methods for detecting the frequency and amplitude of 2-FSK signals have many deficiencies. Traditional detection methods are mostly implemented based on software algorithms and rely on general-purpose processors for calculation, which results in slow detection speed and difficulty in meeting the real-time requirements of high-speed communication systems. Moreover, in a complex electromagnetic environment, these methods are easily affected by factors such as noise and interference, leading to a decrease in detection accuracy and an inability to accurately obtain the frequency and amplitude information of the signal. In addition, although some hardware-implemented detection methods have improved in speed, they have problems such as complex circuit structure, high cost, and high power consumption, which are not conducive to system integration and miniaturization.

[0004] At the same time, different application scenarios have different requirements for the detection accuracy and real-time performance of 2-FSK signals. For example, in high-precision measuring instruments, extremely high detection accuracy is required; while in real-time communication systems, more attention is paid to the real-time performance of detection. The existing detection methods are difficult to balance the diverse requirements of different scenarios and cannot flexibly adapt to various complex application environments. Therefore, it is of great practical significance to develop an efficient, accurate, and well-adaptive method for detecting the frequency and amplitude of 2-FSK signals. Summary of the Invention

[0005] The method for detecting the frequency and amplitude of 2-FSK signals based on FPGA proposed by the present invention is to solve the problems mentioned in the above prior art.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A method for detecting the frequency and amplitude of 2-FSK signals based on FPGA, including:

[0007] Signal acquisition step: Using eight-channel synchronous or sequential sampling technology, the signal is collected through an analog-to-digital converter ADC, the signal value is stored in a register, and an adaptive gain control circuit is used to adjust the ADC gain according to the input signal strength. The gain adjustment formula is V ref is the ADC reference voltage, Vmax is the estimated maximum amplitude value of the input signal;

[0008] Frequency analysis steps: Use the internal frequency detection module of the FPGA to analyze the sampled signal. For synchronous sampling, the 4096-point fast Fourier transform (FFT) algorithm is used with a resolution of 48.828 Hz; for sequential sampling, the 16384-point FFT algorithm is used with a resolution of 12.207 Hz. The spectrum interpolation algorithm is introduced, and the formula is X(n) is the original FFT spectrum, X interp (k) is the spectrum after interpolation, N is the number of points of the original FFT, and M is the interpolation multiple;

[0009] Amplitude spectrum conversion and amplitude estimation steps: Take the modulus of the complex spectrum after FFT operation and multiply by 2 1-N to obtain the amplitude spectrum. 2 N is the number of sampling points. The influence of spectrum leakage is processed by applying a window function, and the Hanning window is used n = 0, 1, …, N - 1, calculate the amplitude spectrum and extract the maximum value;

[0010] Frequency estimation steps: Calculate the frequency through the maximum value point of the amplitude spectrum, and use the phase difference method to verify and correct the frequency estimation result. Calculate the phase difference Δφ between signals in two adjacent sampling periods, and according to the formula obtain the corrected frequency. T s is the sampling period;

[0011] Data output steps: According to the return interval of the sampling mode, store the frequency and amplitude detection results of each channel in the internal result register of the FPGA. For synchronous sampling, it is every 100 milliseconds, and for sequential sampling, it is every 800 milliseconds. Transmit through the UART protocol network port, and use the compressed sensing technology combined with the Gaussian random matrix to compress and reconstruct the data.

[0012] Furthermore, it also includes:

[0013] Preprocessing steps: Use a hardware filter to perform filtering preprocessing on the 2-FSK signal to remove high-frequency noise and low-frequency interference. The filter cut-off frequency fc is set according to the center frequency and bandwidth of the 2-FSK signal, and the formula is where f max and f min are respectively the maximum and minimum values of the two carrier frequencies of the 2-FSK signal, and Δf is the signal bandwidth; An adaptive filter is used to adjust the coefficients in real time according to the statistical characteristics of the input signal. The adaptive filtering algorithm uses the least mean square (LMS) algorithm, and the coefficient update formula is W(n + 1) = W(n) + 2μe(n)X(n), where W(n) is the filter coefficient vector at the nth iteration, μ is the step factor, e(n) is the error signal, and X(n) is the input signal vector.

[0014] Further, it also includes:

[0015] Frequency detection result calibration step: Calibration coefficients at different frequencies and amplitudes are pre-stored inside the FPGA. According to the detected frequency and amplitude, the corresponding calibration coefficient k is found, and the detection result is calibrated. The calibration formula is f calibrated = k × f detected , A calibrated = k × A detected , where f calibrated , A calibrated are the calibrated frequency and amplitude, and f detected , A detected are the detected frequency and amplitude; The calibration coefficient is obtained through machine learning algorithm training. Using the sample data of 2-FSK signals with known frequencies and amplitudes, combined with the deep learning convolutional neural network CNN model for training, inputting frequency and amplitude data, outputting the calibration coefficient, and optimizing the model through training.

[0016] Further, for the clock jitter problem in the ADC sampling process in the signal acquisition step, a clock synchronization circuit is adopted to synchronize the sampling clock of the ADC. The phase jitter of the sampling clock is controlled within ±n picoseconds through a phase-locked loop PLL. The time-interleaved sampling technology is introduced, and multiple ADCs are used for parallel sampling. By controlling the sampling time interval of each ADC, the equivalent frequency of the sampling clock is reduced. The sampling time interval Δt is determined according to the sampling accuracy required by the system and the performance of the ADC.

[0017] Further, in the frequency analysis step, data normalization is adopted to handle the data overflow problem in the FFT operation. Before performing the FFT operation, the sampled data is divided by a constant M greater than the maximum value of the data. After the FFT operation, the result is multiplied by M again; A pipeline architecture design based on butterfly operation is adopted, and the FFT operation is decomposed into multiple cascaded butterfly operation units, and each butterfly operation unit completes a specific operation within one clock cycle.

[0018] Further, in the amplitude spectrum conversion and amplitude estimation step, a moving average filtering algorithm is adopted to process the amplitude spectrum. The amplitude spectrum is subjected to m-point moving average filtering to extract the maximum amplitude value. m is set according to the signal stability and noise level. Combining wavelet transform for multi-resolution analysis of the amplitude spectrum, and extracting amplitude features from different scale coefficients. The wavelet transform formula is W f (a, b) is the wavelet transform result, a is the scale parameter, b is the translation parameter, f(t) is the input signal, and ψ(t) is the wavelet basis function.

[0019] Furthermore, a Cyclic Redundancy Check (CRC) code is added in the data output step. According to the content of the data packet, the CRC code is calculated using the CRC generating polynomial and added to the end of the data packet. The receiving end determines the transmission status by verifying the CRC code; the multipath transmission technology is adopted, and the data is transmitted to the receiving end through different communication paths. The receiving end performs merging processing on the data packets, selects the correct data according to the CRC verification result, and the merging algorithm adopts the maximum likelihood merging criterion, and calculates the merging weights according to the signal-to-noise ratios of the received signals on each path.

[0020] Furthermore, the hardware filter uses a Butterworth low-pass filter, and the transfer function where n is the filter order and s k is the filter pole. The pole position is determined according to the set cut-off frequency f c and the filter order n; the genetic algorithm is introduced in the filter design to optimize the filter parameters. The genetic algorithm iteratively optimizes the filter poles and zeros through selection, crossover, and mutation operations.

[0021] Furthermore, the calibration coefficient is obtained through experiments. Under different environmental temperatures, humidities, and signal intensities, the 2-FSK signals with known frequencies and amplitudes are detected, and the deviations between the detection results and the true values are recorded. The functional relationship between the calibration coefficient and the frequency, amplitude, and environmental factors is obtained by fitting the deviation data and stored in the internal lookup table of the FPGA; the online learning algorithm is used to update the calibration coefficient according to the new detection data during the operation of the system. The online learning algorithm adopts the stochastic gradient descent method, calculates the gradient according to the newly detected data, and updates the calibration coefficient.

[0022] Furthermore, at the receiving end, when the CRC code is verified and a data packet error is found, the Automatic Repeat Request (ARQ) mechanism is adopted. The receiving end sends a retransmission request signal to the sending end, and the sending end retransmits the data packet until the receiving end correctly receives the data packet; the Forward Error Correction (FEC) technology is introduced. The data packet is encoded at the sending end, redundant information is added, and the receiving end uses the redundant information to correct the error data packet. The FEC encoding adopts convolutional encoding, and the data packet encoding and error correction are completed by designing appropriate generating polynomials and coding constraint lengths.

[0023] Compared with the existing technologies, the beneficial effects of the present invention are:

[0024] In terms of detection accuracy, through a series of innovative technologies such as adopting an adaptive gain control circuit, a spectrum interpolation algorithm, window function processing, and phase difference method correction, the detection accuracy of frequency and amplitude is effectively improved, and the frequency and amplitude information of the 2-FSK signal can be accurately obtained in a complex electromagnetic environment, meeting the requirements of high-precision measurement.

[0025] In terms of real-time performance, by leveraging the parallel processing capabilities of the FPGA and adopting a pipeline architecture to accelerate FFT operations, combined with multipath transmission and forward error correction techniques to improve data transmission efficiency, the detection time is significantly shortened, meeting the real-time requirements of high-speed communication systems. Compared with traditional software algorithm-based detection methods, the detection speed has been qualitatively improved.

[0026] In terms of adaptability, the introduction of adaptive filters and online learning algorithms enables the system to adjust parameters in real time according to different signal environments and working conditions, and the calibration coefficients can also be dynamically updated according to the actual situation, thus flexibly adapting to various complex application scenarios and taking into account the diverse requirements of different applications for detection accuracy and real-time performance.

[0027] In terms of cost and power consumption, this method is implemented based on the FPGA, with a relatively simple circuit structure, reducing hardware costs and power consumption, facilitating system integration and miniaturization, and conforming to the development trend of modern communication devices. In summary, the patented method of the present invention has obvious advantages in terms of detection accuracy, real-time performance, adaptability, cost, and power consumption, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic block diagram of a method for detecting the frequency and amplitude of 2-FSK signals based on FPGA proposed by the present invention;

[0029] Figure 2 It is a schematic diagram for comparing the frequency detection accuracy;

[0030] Figure 3 It is a schematic diagram for comparing the amplitude detection accuracy;

[0031] Figure 4 It is a schematic diagram showing the change of data transmission success rate with interference intensity. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0034] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "a plurality" is two or more, unless otherwise specifically defined. In addition, the terms "mounted", "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. The present invention will be further described in detail below with reference to the drawings.

[0035] Refer to Figures 1 to 4 : A method for detecting the frequency and amplitude of 2-FSK signals based on FPGA, comprising:

[0036] Signal acquisition step: Using eight-channel synchronous sampling or eight-channel sequential sampling technology, with the help of an analog-to-digital converter (ADC) with a sampling rate of 200 kHz, a sampling accuracy of 0.3 mv, and a sampling data bit width of 16 bits, the input 2-FSK signal is acquired. Each channel is configured with an independent ADC, and samples at a rate of 200 kHz according to the sampling mode, and stores the eight-channel sampling signal values in a register. At the same time, an adaptive gain control circuit is adopted to automatically adjust the gain of the ADC according to the input signal strength, so that the signal amplitude input to the ADC is always in the best quantization range, improving the sampling accuracy. The gain adjustment formula is where V ref is the reference voltage of the ADC, and V max is the estimated maximum amplitude value of the input signal.

[0037] Frequency analysis step: Using the internal frequency detection module of the FPGA to analyze the sampling signal. This module has synchronous and sequential sampling modes. In the synchronous sampling mode, a 4096-point fast Fourier transform (FFT) algorithm is adopted, and the frequency resolution Fres1 ≈48.828 Hz to meet the 48 Hz accuracy requirement; in the sequential sampling mode, a 16384-point FFT algorithm is adopted, and the frequency resolution Fres2≈12.207 Hz meets the 12 Hz accuracy requirement. On this basis, a spectrum interpolation algorithm is introduced to interpolate the spectrum after FFT transformation to further improve the frequency resolution. The interpolation formula is where X(n) is the original FFT spectrum, X interp (k) is the interpolated spectrum, N is the number of original FFT points, and M is the interpolation multiple.

[0038] Amplitude spectrum conversion and amplitude estimation steps: Take the modulus of the complex spectrum after FFT operation and multiply by 2 1-N (2 N is the number of sampling points) to obtain the amplitude spectrum. To suppress the influence of spectrum leakage on amplitude estimation, a window function processing is adopted, such as the Hanning window n = 0, 1, …, N - 1. After windowing, the amplitude spectrum calculation and the extraction of the maximum amplitude are performed to improve the accuracy of amplitude estimation.

[0039] Frequency estimation steps: Multiply the detection point number corresponding to the maximum amplitude point of the amplitude spectrum by the corresponding frequency resolution to obtain the signal frequency. At the same time, the phase difference method is used to verify and correct the frequency estimation result. For the signals of two adjacent sampling periods, calculate their phase difference According to the formula (Ts is the sampling period) to obtain the corrected frequency and ensure the reliability of frequency estimation.

[0040] Data output steps: Implement different data return intervals according to the sampling mode. Store the frequency and amplitude detection results of each channel in the internal result register of the FPGA, and encapsulate them into a data packet containing information such as eight-channel data indication bits, frequency values, and amplitude values. In the synchronous sampling mode, the data packet is transmitted via the UART protocol network port every 100 milliseconds; in the sequential sampling mode, it is transmitted every 800 milliseconds. During transmission, the compressed sensing technology is used to compress the data packet, reduce the data transmission volume, and improve the transmission efficiency. The compressed sensing measurement matrix uses a Gaussian random matrix, and the effective compression and accurate reconstruction of the data are realized by optimizing the measurement matrix and the reconstruction algorithm.

[0041] In the present invention, the following steps are further included:

[0042] Signal preprocessing steps: Before ADC sampling, use a hardware filter to filter the input 2-FSK signal to remove high-frequency noise and low-frequency interference in the signal. The filter cut-off frequency f c is set according to the center frequency and bandwidth of the 2-FSK signal. The formula is where f max and f minare the maximum and minimum values of the two carrier frequencies of the 2-FSK signal respectively, and Δf is the signal bandwidth. The filter uses an adaptive filter, and its coefficients are adjusted in real time according to the statistical characteristics of the input signal to adapt to different signal environments. The adaptive filtering algorithm uses the least mean square (LMS) algorithm, and the coefficient update formula is W(n + 1) = W(n) + 2μe(n)X(n), where W(n) is the filter coefficient vector at the nth iteration, μ is the step size factor, e(n) is the error signal, and X(n) is the input signal vector.

[0043] In the present invention, the following steps are further included:

[0044] Frequency detection result calibration step: Calibration coefficients at different frequencies and amplitudes are pre-stored inside the FPGA. According to the detected frequency and amplitude, the corresponding calibration coefficient k is found, and the detection result is calibrated. The calibration formula is f calibrated = k × f detected ,A calibrated = k × A detected ,where f calibrated 、A calibrated are the calibrated frequency and amplitude, and f detected 、A detected are the detected frequency and amplitude. The calibration coefficients are obtained through training with a machine learning algorithm. Using a large number of 2-FSK signal sample data with known frequencies and amplitudes, training is carried out in combination with a deep learning model such as a convolutional neural network (CNN). The input of the model is the detected frequency and amplitude data, and the output is the calibration coefficient. By continuously training and optimizing the model, the calibration accuracy is improved.

[0045] In the present invention, in order to overcome the clock jitter problem in the sampling process of the ADC (Analog-to-Digital Converter), a clock synchronization circuit and time-interleaved sampling technology are adopted, which involve rich technical details. In dealing with the clock jitter problem, the clock synchronization circuit plays a key role, and the Phase-Locked Loop (PLL) is the core component among them. The PLL is a closed-loop control system that can track the phase of the input signal. In this system, the input of the PLL is the sampling clock signal of the ADC, and its internal mainly includes a Phase Detector (PD), a Loop Filter (LF), a Voltage-Controlled Oscillator (VCO), etc. The Phase Detector is responsible for comparing the phase difference between the input clock signal and the output clock signal of the VCO, and converting this phase difference information into a voltage signal for output. The Loop Filter filters the voltage signal output by the Phase Detector, removes the high-frequency noise and interference components in it, and obtains a relatively smooth control voltage. This control voltage is used to adjust the oscillation frequency and phase of the Voltage-Controlled Oscillator, so that the phase of the clock signal output by the VCO gradually becomes consistent with the phase of the input clock signal. Through this feedback control mechanism of the PLL, the phase jitter of the sampling clock can be controlled within ±n picoseconds. A picosecond is an extremely small time unit. In high-speed signal sampling, even an extremely small clock phase jitter may cause the offset of the sampling point, thus seriously affecting the sampling accuracy. Controlling the phase jitter within such a small range can effectively ensure that the ADC samples the analog signal at the accurate moment, providing high-precision digital signals for subsequent signal processing. In addition, in order to further reduce the influence of clock jitter on the sampling accuracy, time-interleaved sampling technology is introduced. This technology uses multiple ADCs for parallel sampling. Specifically, multiple ADCs with similar performances are configured in the system, and each ADC samples the input analog signal at different time points. By precisely controlling the sampling time interval Δt of each ADC, the equivalent frequency of the sampling clock is reduced. For example, assuming that the sampling frequency of a single ADC is f, if N ADCs are used for time-interleaved sampling and the sampling time interval of each ADC is Δt, then the equivalent sampling frequency becomes f / N. The sampling time interval Δt is not set randomly. It needs to be determined according to the sampling accuracy required by the system and the performance of the ADC. The higher the sampling accuracy required by the system, the higher the control accuracy requirement for the sampling time interval of each ADC. Performance parameters such as the conversion time and settling time of the ADC need to be comprehensively considered. Through precise timing design and control circuits, it is ensured that each ADC samples at the appropriate time point, thereby effectively reducing the influence of clock jitter on the sampling accuracy and providing high-quality sampling data for the 2-FSK signal frequency and amplitude detection method based on FPGA.

[0046] In the present invention, for the purpose of ensuring the accuracy and efficiency of the operation in the frequency analysis step, data normalization processing and a pipeline architecture design based on butterfly operations are adopted for the FFT (Fast Fourier Transform) operation, which involve many key points. When dealing with the possible data overflow problem during the FFT operation, data normalization processing is an important measure. Before performing the FFT operation, it is necessary to first analyze the sampled data to determine its maximum value. Since the actual sampled data may have a large numerical range, if the FFT operation is directly performed, it is very easy to cause data overflow within the limited bit width representation inside the FPGA, resulting in incorrect operation results. Therefore, a constant M greater than the maximum value of the data is selected, and the sampled data is divided by M, so that the amplitude of the data can be reduced to a suitable range, reducing the risk of data overflow. After the FFT operation is completed, in order to restore the true amplitude of the data to ensure the accuracy of frequency and amplitude detection, the operation result needs to be multiplied by M again. Here, M acts as a scaling factor. Through the operations of division first and then multiplication, it not only avoids the overflow problem during the operation process but also does not change the essential characteristics of the data, enabling the subsequent analysis of the signal frequency and amplitude to be based on accurate data. In addition, to accelerate the FFT operation, a pipeline architecture design based on butterfly operations is adopted. The FFT operation can essentially be decomposed into a series of butterfly operations. The butterfly operation unit is the basic building block of the FFT operation, and it gets its name from the fact that its operation structure resembles a butterfly. In the pipeline architecture, the entire FFT operation is decomposed into multiple cascaded butterfly operation units. Each butterfly operation unit completes a specific operation within one clock cycle. In the first clock cycle, the data enters the first-stage butterfly operation unit for processing; in the second clock cycle, the result of the first-stage operation enters the second-stage butterfly operation unit, and at the same time, new data enters the first-stage butterfly operation unit, and so on. This pipeline operation method enables different levels of butterfly operation units to process data at different stages simultaneously, greatly improving the parallelism of the operation. Compared with the traditional non-pipeline architecture, the pipeline architecture avoids the time waste of waiting for the previous-stage operation to completely end before starting the next-stage operation, significantly improves the operation speed, and reduces the time required for the entire FFT operation. When implemented based on the FPGA, by using its programmable logic resources, this pipeline architecture can be flexibly implemented and optimized according to specific application requirements and resource conditions, so as to efficiently complete the frequency analysis of the 2-FSK signal and provide fast and accurate basic data for subsequent frequency and amplitude detection.

[0047] In the present invention, for the amplitude spectrum conversion and amplitude estimation steps to achieve high-precision amplitude estimation, the moving average filtering algorithm and wavelet transform technology are comprehensively utilized, involving many key details. When applying the moving average filtering algorithm, its core purpose is to reduce the noise interference in the amplitude spectrum, thereby providing a cleaner data basis for subsequent amplitude estimation. The specific operation process is to perform m-point moving average filtering on the amplitude spectrum. The so-called m-point moving average means that in the amplitude spectrum data sequence, m consecutive data points are successively taken, their average value is calculated, and the first data point among these m data points is replaced with this average value. Then the window slides backward by one data point, and the above calculation process is repeated until the entire amplitude spectrum data sequence is traversed. The value of m here is not arbitrarily set, but needs to be finely adjusted according to the signal stability and noise level. When the signal stability is good and the noise level is low, the value of m can be appropriately taken as a smaller value, which can process the data more quickly and retain the detailed features of the signal; while when the signal stability is poor and the noise interference is large, the value of m needs to be appropriately increased to enhance the filtering effect and more effectively smooth the noise. Generally speaking, the value range of m is 5 - 15. In practical applications, engineers need to determine the optimal value of m through a large number of experiments and data analyses, combined with the specific signal environment. After the filtering is completed, the maximum amplitude value is extracted from the processed amplitude spectrum. At this time, the obtained maximum value can more accurately reflect the true amplitude situation of the signal compared with that before filtering. In addition, to further improve the accuracy of amplitude estimation, this method also combines wavelet transform to perform multi-resolution analysis on the amplitude spectrum. Wavelet transform is a powerful signal processing tool that can decompose a signal into different scales and positions, thereby revealing the characteristics of the signal in different frequency bands. Its formula is In this formula, W f (a, b) represents the result of wavelet transform, which contains the information of the signal at different scales a and translation positions b; the scale parameter a determines the frequency range of analysis, a smaller value of a corresponds to the analysis of high-frequency components, and a larger value of a corresponds to the analysis of low-frequency components; the translation parameter b is used to locate the signal features on the time axis; f(t) is the input amplitude spectrum signal; ψ(t) is the wavelet basis function. Different wavelet basis functions have different characteristics and are suitable for different types of signal analysis. Common ones include Haar wavelet, Daubechies wavelet, etc. Through wavelet transform, the amplitude spectrum is decomposed into coefficients at different scales. From these coefficients at different scales, richer and more accurate amplitude features can be extracted. For example, the high-frequency scale coefficients may reflect the details and abrupt parts of the signal, while the low-frequency scale coefficients more reflect the overall trend and main components of the signal. Using the amplitude feature information at these multiple scales, the amplitude of the 2-FSK signal can be estimated more accurately, thereby significantly improving the accuracy of amplitude estimation and providing more reliable results for the frequency amplitude detection of 2-FSK signals based on FPGA.

[0048] In the present invention, in order to ensure the reliability of data transmission in the data output step, cyclic redundancy check (CRC) codes and multipath transmission techniques are employed, which involve many key technical details. Regarding the addition of CRC codes, first, its principle needs to be clarified. CRC codes are check codes generated through specific algorithms and are used to detect whether errors occur during data transmission. During specific operations, according to the actual data content in the data packet, a suitable CRC generation polynomial is selected. The generation polynomial is a binary sequence, and different generation polynomials are applicable to different application scenarios and data transmission requirements. For example, common ones such as CRC-16 and CRC-32 correspond to generation polynomials of different lengths. Using the selected generation polynomial, the data in the data packet is processed through modulo-2 division operations to calculate the CRC code. Modulo-2 division is different from ordinary arithmetic division. During the operation process, no borrow is generated, and only exclusive-OR operations are performed. The calculated CRC code is then added to the end of the data packet and transmitted together with the original data. After receiving the data packet, the receiving end will re-calculate the data (excluding the received CRC code part) in the data packet using the same CRC generation polynomial to obtain a new CRC code and compare it with the received CRC code. If the two are exactly the same, it indicates that the data packet has probably not had an error during transmission; if they are inconsistent, it is determined that the data packet has an error. In the application of multipath transmission technology, the system transmits the data packet to the receiving end through multiple different communication paths. These communication paths can be different physical lines or different signal propagation paths in a wireless communication environment. Due to the different transmission characteristics of each path, such as differences in signal attenuation levels and noise interference levels, the quality of the received data packets will also vary. After receiving multiple data packets, the receiving end will perform a merging process on them. Here, a merging algorithm based on the maximum likelihood merging criterion is adopted. This algorithm first calculates the merging weights according to the signal-to-noise ratios of the received signals on each path. The signal-to-noise ratio is an important indicator for measuring signal quality. The higher the signal-to-noise ratio, the more useful components there are relative to the noise components in the signal, and the higher the reliability of data transmission. Through specific mathematical formulas, the signal-to-noise ratios of each path are converted into merging weights. The higher the weight of a path, the greater the proportion of its data in the merging. Then, based on these weights, multiple data packets are merged, and the data with the highest reliability is selected from multiple versions of the data, thereby further improving the reliability of data transmission and ensuring the accuracy and stability of the 2-FSK signal frequency and amplitude detection method based on FPGA in the data output link.

[0049] In the present invention, a Butterworth low-pass filter is adopted for the hardware filter. The Butterworth low-pass filter is widely used due to its flat frequency response characteristic in the passband. Its transfer function is This formula has a clear physical meaning. Among them, n represents the order of the filter, which determines the complexity of the filter and the strength of the filtering effect. The higher the order, the stronger the signal screening ability of the filter, but at the same time, it will also increase the complexity of the circuit and the amount of calculation. s k are the poles of the filter, and the positions of these poles directly affect the frequency response characteristics of the filter. In practical applications, it is necessary to accurately determine the pole positions according to the set cut-off frequency f c and the filter order n. The cut-off frequency f c is an important parameter of the filter, which defines the boundary between the passband and the stopband of the filter. Signals below the cut-off frequency f c can pass through the filter relatively smoothly, while signals above f c will be significantly attenuated. Through specific mathematical calculation methods, combined with the cut-off frequency f c and the selected order n, the positions of the poles s k can be accurately calculated, so as to effectively filter the 2-FSK signal, remove the high-frequency noise and interference components in the signal, and make the subsequent frequency amplitude detection more accurate. In addition, in order to further improve the performance of the filter, a genetic algorithm is introduced in the filter design to optimize the filter parameters. The genetic algorithm is an optimization algorithm that draws on the natural selection and genetic mechanisms in the process of biological evolution. It continuously iteratively optimizes the poles and zeros of the filter through three main operations: selection, crossover, and mutation. The selection operation is to select individuals with better performance from the current population of filter parameters, just like organisms that adapt to the environment in nature are more likely to survive and reproduce. The crossover operation is to exchange and combine some parameters of the selected individuals to generate new parameter individuals, similar to the genetic recombination of organisms. The mutation operation is to randomly change the parameters of the new individuals with a small probability to increase the diversity of the population and avoid the algorithm falling into a local optimal solution. By continuously performing the selection, crossover, and mutation operations, the genetic algorithm can gradually adjust the poles and zeros of the filter, thereby minimizing the stopband attenuation and passband ripple of the filter. Excessive stopband attenuation may result in ineffective suppression of noise, while excessive passband ripple will cause distortion of the passed signal. The Butterworth low-pass filter optimized by the genetic algorithm can play a better filtering role in the frequency amplitude detection of 2-FSK signals and improve the performance of the entire detection system.

[0050] In the present invention, the initial acquisition of the calibration coefficient requires a large number of rigorous experimental processes. During the experimental stage, it is necessary to simulate a variety of different environmental conditions. For example, the environmental temperature can be set at multiple temperature nodes ranging from several degrees Celsius below zero to dozens of degrees Celsius above zero, and the humidity range can cover different levels from low humidity to high humidity. At the same time, for 2-FSK signals with different intensities, tests need to be carried out from weak signals to stronger signals. Under these different combinations of conditions, the 2-FSK signals with known accurate frequencies and amplitudes are detected. During the detection process, the deviation between each detection result and the true value is accurately recorded. These deviation data contain rich information, reflecting the relationship between environmental factors, signal characteristics, and detection errors. Subsequently, using professional data analysis methods, such as curve fitting algorithms, a functional relationship between the calibration coefficient and frequency, amplitude, and environmental factors (temperature, humidity, etc.) is obtained by fitting the deviation data. The establishment of this functional relationship can more accurately describe the internal connection between detection errors and various factors under different conditions. After obtaining the above functional relationship, it is stored in the look-up table inside the FPGA. The look-up table of the FPGA is a high-speed storage structure that can achieve fast data query and retrieval, facilitating the rapid acquisition of the corresponding calibration coefficient during the actual detection process to calibrate the detection result in real time. In order to make the calibration more suitable for the dynamic changes in the actual working environment, this method introduces an online learning algorithm. Specifically, the stochastic gradient descent method is adopted, which is an optimization algorithm widely used in the field of machine learning. During the operation of the system, every time a new set of detection data is obtained, calculations are carried out according to the principle of the stochastic gradient descent method. First, based on the new detection data and the current calibration coefficient, the error between the current detection result and the true value is calculated. Then, the gradient is calculated based on this error. The direction of the gradient reflects the direction of calibration coefficient adjustment to make the error change in the direction of decrease. Finally, the calibration coefficient is updated according to the calculated gradient. By continuously calculating and updating based on new data in this way, the calibration coefficient can adapt to the changes in the environment and signal characteristics in real time, thus significantly improving the accuracy and real-time performance of calibration and ensuring that the 2-FSK signal frequency and amplitude detection method based on FPGA can maintain a high detection accuracy under various complex conditions.

[0051] In the present invention, at the receiving end, the system will strictly check the received data packets using CRC (Cyclic Redundancy Check) codes. The CRC code is a check code generated through a specific algorithm. It is calculated based on the data content in the data packet and is transmitted together with the data packet. After receiving the data packet, the receiving end will recalculate the CRC code and compare it with the received CRC code. If the two are inconsistent, it is determined that an error has occurred during the transmission of the data packet. Once a data packet error is detected, the receiving end will adopt the Automatic Repeat reQuest (ARQ) mechanism. The ARQ mechanism is a classic data link layer protocol. It ensures the correct transmission of data by the receiving end sending a retransmission request signal to the sending end. In this method, the receiving end will explicitly send a retransmission request signal containing the identification of the error data packet to the sending end. After receiving this request, the sending end will re-locate and send the corresponding data packet. This process will continue until the receiving end correctly receives the data packet, thereby fundamentally ensuring the accuracy of data transmission. On this basis, to further improve the efficiency of data transmission, this method introduces Forward Error Correction (FEC) technology. At the sending end, the FEC technology will encode the data packets. Specifically, according to the principle of convolutional coding, by carefully designing appropriate generator polynomials and coding constraint lengths, redundant information is added to the original data packet. The generator polynomial is a mathematical expression used to define the convolutional coding rule, which determines the generation method of the redundant information; the coding constraint length determines the range of historical data participating in the coding. These redundant information are not added randomly, but have a specific mathematical relationship with the original data. At the receiving end, when receiving a data packet containing errors, using these pre-added redundant information and combining with a specific decoding algorithm, error correction processing is performed on the error data packet. In this way, many errors that originally required retransmission to correct can now be directly repaired locally, thus significantly reducing the number of retransmissions. In this way, both the accuracy of data transmission is ensured, and the efficiency of data transmission is greatly improved, making the 2-FSK signal frequency and amplitude detection system based on FPGA perform better in practical applications.

[0052] The above is only the preferred specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution of the present invention and its inventive concept, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.

Claims

1. A method for detecting the frequency and amplitude of 2-FSK signals based on FPGA, characterized in that It includes the following steps: Signal acquisition steps: Using eight-channel synchronous or sequential sampling technology, the signal is acquired through the analog-to-digital converter ADC, and the signal value is stored in the register. An adaptive gain control circuit is adopted to adjust the ADC gain according to the input signal strength, and the gain adjustment formula is V ref is the ADC reference voltage, V max is the estimated maximum amplitude value of the input signal; Frequency analysis steps: Use the internal frequency detection module of the FPGA to analyze the sampling signal. For synchronous sampling, the 4096-point Fast Fourier Transform (FFT) algorithm is used with a resolution of 48.828 Hz; for sequential sampling, the 16384-point FFT algorithm is used with a resolution of 12.207 Hz. Introduce the spectral interpolation algorithm, and the formula is where X(n) is the original FFT spectrum, and X interp (k) is the interpolated spectrum, N is the number of points of the original FFT, and M is the interpolation factor; Amplitude spectrum conversion and amplitude estimation steps: Take the modulus of the complex spectrum after FFT operation and multiply by 2 1-N Obtain the amplitude spectrum, 2 N is the number of sampling points. Deal with the influence of spectral leakage by applying a window function, and use a Hanning window Calculate the amplitude spectrum and extract the maximum value; Frequency estimation steps: Calculate the frequency through the maximum point of the amplitude spectrum, verify and correct the frequency estimation result using the phase difference method, calculate the phase difference Δφ between signals in two adjacent sampling periods, and obtain the corrected frequency according to the formula where T s is the sampling period; Data output step: According to the sampling mode return interval, store the detection results of each channel frequency and amplitude in the internal result register of the FPGA. Synchronous sampling is performed every 100 milliseconds, and sequential sampling is performed every 800 milliseconds. Transmit through the UART protocol network port, and use the compressed sensing technology to combine the Gaussian random matrix to compress and reconstruct the data.

2. The method for detecting the frequency and amplitude of a 2-FSK signal based on FPGA according to claim 1, wherein It also includes: Preprocessing step: Use a hardware filter to perform filtering preprocessing on the 2-FSK signal to remove high-frequency noise and low-frequency interference. The filter cut-off frequency fc is set according to the center frequency and bandwidth of the 2-FSK signal, and the formula is where f max and f min are respectively the maximum and minimum values of the two carrier frequencies of the 2-FSK signal, and Δf is the signal bandwidth; an adaptive filter is adopted to adjust the coefficients in real time according to the statistical characteristics of the input signal. The adaptive filtering algorithm adopts the least mean square LMS algorithm, and the coefficient update formula is W(n + 1) = W(n) + 2μe(n)X(n), where W(n) is the filter coefficient vector at the nth iteration, μ is the step factor, e(n) is the error signal, and X(n) is the input signal vector.

3. A 2-FSK signal frequency and amplitude detection method based on FPGA according to claim 1, characterized in that, It also includes: Frequency detection result calibration steps: Calibration coefficients at different frequencies and amplitudes are pre-stored inside the FPGA. According to the detected frequency and amplitude, the corresponding calibration coefficient k is found to calibrate the detection result. The calibration formula is f calibrated = k × f detected , A calibrated = k × A detected , where f calibrated , A calibrated are the calibrated frequency and amplitude, and f detected , A detected are the detected frequency and amplitude; The calibration coefficient is obtained through machine learning algorithm training. Using the 2-FSK signal sample data with known frequency and amplitude, combined with the deep learning convolutional neural network CNN model for training, inputting the frequency and amplitude data, outputting the calibration coefficient, and optimizing the model through training.

4. A 2-FSK signal frequency and amplitude detection method based on FPGA according to claim 1, characterized in that, For the signal acquisition step, a clock synchronization circuit is adopted for the clock jitter problem during the ADC sampling process to synchronize the sampling clock of the ADC. The phase jitter of the sampling clock is controlled within ±n picoseconds through the phase-locked loop PLL. The time-interleaved sampling technology is introduced, and multiple ADCs are used for parallel sampling. The equivalent frequency of the sampling clock is reduced by controlling the sampling time interval of each ADC. The sampling time interval Δt is determined according to the sampling accuracy required by the system and the performance of the ADC.

5. A 2-FSK signal frequency and amplitude detection method based on FPGA according to claim 1, characterized in that, For the frequency analysis step, data normalization is adopted to handle the data overflow problem in the FFT operation. Before the FFT operation, divide the sampling data by a constant M greater than the maximum value of the data. After the FFT operation, multiply the result by M. Adopt a pipeline architecture design based on butterfly operations, decompose the FFT operation into multiple cascaded butterfly operation units, and each butterfly operation unit completes a specific operation within one clock cycle.

6. A 2-FSK signal frequency and amplitude detection method based on FPGA according to claim 1, characterized in that, The amplitude spectrum conversion and amplitude estimation steps use a moving average filtering algorithm to process the amplitude spectrum. Perform m-point moving average filtering on the amplitude spectrum and extract the maximum amplitude. m is set according to the signal stability and noise level. Combine wavelet transform to perform multi-resolution analysis on the amplitude spectrum and extract amplitude features from different scale coefficients. The wavelet transform formula is W f (a, b) is the wavelet transform result, a is the scale parameter, b is the translation parameter, f(t) is the input signal, and ψ(t) is the wavelet basis function.

7. A method for detecting the frequency and amplitude of a 2-FSK signal based on FPGA according to claim 1, characterized in that, In the data output step, add a cyclic redundancy check CRC code. According to the content of the data packet, calculate the CRC code using the CRC generation polynomial and add it to the end of the data packet. The receiving end judges the transmission situation by verifying the CRC code. Adopt the multipath transmission technology, transmit through different communication paths to the receiving end, and the receiving end performs merging processing on the data packets. Select the correct data according to the CRC verification result. The merging algorithm adopts the maximum likelihood merging criterion, and calculates the merging weight according to the signal-to-noise ratio of the received signals on each path.

8. A method for detecting the frequency and amplitude of 2-FSK signals based on FPGA according to claim 2, characterized in that, The hardware filter uses a Butterworth low-pass filter, and the transfer function where n is the order of the filter and s k is the pole of the filter. The pole position is determined according to the set cut-off frequency f c and the filter order n. In the filter design, a genetic algorithm is introduced to optimize the filter parameters. The genetic algorithm iteratively optimizes the poles and zeros of the filter through selection, crossover, and mutation operations.

9. A 2-FSK signal frequency and amplitude detection method based on FPGA according to claim 3, characterized in that The calibration coefficient is obtained through experiments. Under different environmental temperatures, humidities, and signal intensities, detect the 2-FSK signal with known frequency and amplitude, record the deviation between the detection result and the true value, and fit the functional relationship between the calibration coefficient and frequency, amplitude, and environmental factors according to the deviation data, and store it in the internal look-up table of the FPGA; Use the online learning algorithm to update the calibration coefficient according to the new detection data during the operation of the system. The online learning algorithm adopts the stochastic gradient descent method, calculates the gradient according to the newly detected data, and updates the calibration coefficient.

10. A method for detecting the frequency and amplitude of 2-FSK signals based on FPGA according to claim 7, characterized in that, At the receiving end, when the CRC code is verified and a data packet error is found, adopt the automatic repeat request ARQ mechanism. The receiving end sends a retransmission request signal to the sending end, and the sending end retransmits the data packet until the receiving end correctly receives the data packet. Introduce the forward error correction FEC technology. Encode the data packet at the sending end and add redundant information. The receiving end uses the redundant information to correct the error data packet. The FEC encoding adopts convolutional coding, and completes the encoding and error correction of the data packet by designing a suitable generation polynomial and coding constraint length.

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