Field programmable logic gate array and pressure test method

Abstract

The embodiment of the invention provides a field programmable logic gate array and a pressure testing method, and the field programmable logic gate array comprises an internal memory and a network card, a segment is arranged in the internal memory, and the segment is used for storing a data packet used in a pressure test process; the data packet is stored in the segment; in a pressure test, the network card interacts with the processor through the segment. The technical scheme provided by the invention is used for solving the problem of low precision of the existing pressure test.

Description

Technical Field

[0001] This document relates to the field of network performance testing technology, and particularly to a field programmable gate array and a stress testing method. Background Art

[0002] Devices such as network devices and security devices that handle and forward traffic all require a network performance tester to simulate real traffic to achieve performance testing and stability testing. The network performance tester can generate and receive various types of data packets, thereby simulating various network communication traffic to achieve functional testing and stress testing of network devices and network security devices.

[0003] In order to accurately test the delay and throughput of data packets, traditional test instruments all use FPGA (Field Programmable Gate Array) to generate and send data packets. The data is generated and sent by the FPGA, and the CPU only plays a control role. The advantage of this mode is that the FPGA is self - contained, and all the generation, sending, receiving, and analysis of data packets are completed by the FPGA, and the CPU only conducts summary and report analysis.

[0004] Ordinary network cards do not strictly limit the data packet sending interval, making the data they send not uniform enough, and it is difficult to accurately test the throughput and microsecond - level delay. This will have an impact on the peak and valley of the device under test and the link, and ultimately affect the test effect. Summary of the Invention

[0005] In view of the above analysis, this application aims to provide a field programmable gate array and a stress testing method to improve the test accuracy.

[0006] In a first aspect, one or more embodiments of this specification provide a field programmable gate array, including an internal memory and a network card; Segments are set in the internal memory, and the segments are used to store data packets used in the stress testing process; In the stress testing, the network card interacts with the processor through the segments.

[0007] Further, the segments include: a first segment and a second segment; The processor sends a first data packet to the first segment through a preset first - segment interface; The processor obtains a second data packet from the second segment through a preset second - segment interface.

[0008] Further, the network card includes a first network card and a second network card; The first network card obtains the first data packet through the first - segment interface; The second network card sends a second data packet to the segment through the second segment interface.

[0009] In a second aspect, one or more embodiments of this specification provide a stress testing method based on network traffic simulation, which is characterized in that, based on the field programmable gate array described in any item of the first aspect, includes: Obtain a first data packet from the processor through a preset first segment; from the processor; Set a first timestamp for the first data packet, and send the first data packet containing the first timestamp to the device to be tested; Receive a second data packet returned by the device to be tested; Set a second timestamp for the returned second data packet, and store the second data packet containing the second timestamp in the second segment; Send a request message for obtaining data to the processor, so that the application program in the processor obtains the second data packet from the second segment.

[0010] Further, obtaining a data packet from the application program through the first segment includes: Detect whether the remaining space in the first segment is less than a first preset value; When it is less than the first preset value, write the data packet to the first segment.

[0011] Further, when there are multiple data packets, the method further includes: Uniformly set or set the sending interval between each of the data packets according to a preset rule.

[0012] Further, the transmission to the processor through the second segment includes: Detect whether the remaining space in the second segment is greater than a second preset value; When it is greater than the second preset value, send a request message to the processor.

[0013] Further, determine the sending interval of the data packet to be sent according to the remaining space in the second segment, so that the remaining space is greater than a third preset value.

[0014] In a third aspect, one or more embodiments of this specification provide a stress testing device based on network traffic simulation, including: an acquisition module, a first sending module, a receiving module, and a second sending module; The acquisition module is used to obtain a first data packet from the application program through a preset first segment; The first sending module is used to set a first timestamp for the first data packet, and send the first data packet containing the first timestamp to the device to be tested; The receiving module is configured to receive a second data packet returned by the device under test; The second sending module is configured to set a second timestamp for the returned second data packet, and store the second data packet containing the second timestamp in a second segment; send a request message for obtaining data to an internal memory, so that an application program in the internal memory obtains the second data packet from the second segment.

[0015] Further, the obtaining module is configured to detect whether the remaining space of the first segment is less than a preset value; when it is less than the preset value, obtain a data packet from the first segment.

[0016] Further, the apparatus further includes a setting module; The setting module is configured to uniformly set the sending intervals between the data packets.

[0017] Further, the second sending module is configured to detect whether the remaining space in the second segment is greater than a first preset value; when it is greater than the first preset value, send the data packet in the second segment to a processor.

[0018] In a fourth aspect, one or more embodiments of the present specification provide a storage medium, including: Instructions executable by a computer are stored, and the instructions executable by the computer, when executed, implement the method according to any one of the first aspect.

[0019] Compared with the prior art, the present application can at least achieve the following technical effects: In the prior art, in a stress test, data packets are sent by a processor. Since the state of the processor is unstable at each moment, the processor cannot send each data packet at a unified interval, resulting in a decrease in test accuracy. In the present application, by setting segments in an FPGA, the data packets in the test process can be concentrated together first, and then the sending intervals are uniformly arranged, thereby ensuring the test accuracy. In addition, an internal memory is built in the FPGA, so that the fetching interval of the returned data packet can be set according to the load condition of the application program, so as to facilitate parsing the data packet returned by the device under test, thereby enriching the evaluation dimension of the test result and improving the evaluation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in one or more embodiments of the present specification or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1A schematic diagram of an FPGA provided for one or more embodiments of this specification; Figure 2 A flowchart of a stress test method based on network traffic simulation provided for one or more embodiments of this specification; Figure 3 A schematic diagram of a stress test device based on network traffic simulation provided for one or more embodiments of this specification. Detailed implementation manners

[0022] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will clearly and completely describe the technical solutions in one or more embodiments of this specification with reference to the accompanying drawings in one or more embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this document.

[0023] The embodiments of this application provide a field programmable gate array, including: an internal memory and a network card; Segments are set in the internal memory, and the segments are used to store data packets used in the stress test process; In the stress test, the network card interacts with the processor through the segments.

[0024] It should be noted that the segment interface refers to the interface for receiving or sending segments. A segment, that is, a segment, is a memory management unit used to organize and access data in memory. This memory is physical memory specially designed for the FPGA.

[0025] Specifically, as Figure 1 shown, The segment includes: a first segment and a second segment; The first data packet sent by the processor to the first segment through a preset first segment interface; The processor obtains the second data packet from the second segment through a preset second segment interface.

[0026] The network card includes a first network card and a second network card; The first network card obtains the first data packet through the first segment interface; The second network card sends the second data packet through the second segment interface.

[0027] The embodiments of this application provide a stress test method based on network traffic simulation, based on the FPGA described in the foregoing embodiments, as Figure 2 shown, including the following steps: Step 1: Obtain a first data packet from the application through the first segment.

[0028] In the embodiment of the present application, the FPGA network card communicates with the application in the internal memory through a preset first segment. The application is responsible for generating the data packets required for testing and sending these data packets to the FPGA network card through the first segment. The test phase includes generating data packets and sending data packets. By setting the first segment, the generated data packets are stored together centrally, and the sending interval is uniformly set, so as to ensure that the data packets are sent evenly.

[0029] Step 2: Set a first timestamp for the data packet and send the first data packet containing the first timestamp to the device to be tested.

[0030] In the embodiment of the present application, after receiving the data packet, the FPGA network card will set a unique first timestamp for each data packet. The timestamp can be the value of a timestamp counter, which is updated in real time inside the FPGA. The purpose of setting the timestamp is to accurately record the sending time of the data packet for subsequent performance analysis. After setting the timestamp, the FPGA network card sends the data packet containing the timestamp to the device to be tested. The device to be tested can be a network device, a security device, or other devices that need to perform performance testing.

[0031] Step 3: Receive a second data packet returned by the device to be tested.

[0032] In the embodiment of the present application, after receiving the data packet, the device to be tested will perform corresponding processing. The processing process may include parsing, forwarding, storing, etc. of the data packet. After the processing is completed, the device to be tested will send the processing result (i.e., the returned data packet) to the FPGA.

[0033] Step 4: Set a second timestamp for the returned second data packet and store the second data packet containing the second timestamp in the second segment.

[0034] In the embodiment of the present application, the test phase includes receiving the returned data packet and sending the returned data packet. By setting the second segment, the returned data packets are stored together centrally, and the sending interval is uniformly set, so as to ensure that the data packets are sent evenly. In addition, the timing of sending the request information can be selected according to the running state of the application. For example, when the current application is running close to full load, the request information can be temporarily not sent.

[0035] Step 5: Send a request message for obtaining data to the processor, so that the application in the processor obtains the second data packet from the second segment.

[0036] In the embodiment of the present application, after the FPGA network card receives the returned data packet, it will also set a unique second timestamp for each data packet. After setting the timestamp, the FPGA network card sends the second data packet containing the timestamp to the application program in the internal memory through the second segment. After receiving the returned data packet, the application program will perform performance analysis based on the timestamp. The performance analysis may include the calculation and evaluation of indicators such as the delay, throughput, and packet loss rate of the data packet. Since segments are set in the FPGA, it is possible to choose to parse the data packet when the application program load is small, thereby improving the test efficiency.

[0037] It should be noted that in the embodiment of the present application, the first and the second are only used to distinguish the sent data packet and the returned data packet.

[0038] In the embodiment of the present application, the FPGA performs an operation of obtaining data packets once within a preset period. To further improve the efficiency of obtaining data packets, first, the remaining space of the first segment is detected. When the remaining space of the first segment is less than the preset value, the FPGA directly obtains the data packet from the first segment regardless of whether the current obtaining operation is within the preset period. This can ensure that the FPGA will not cause overflow or waste of the first segment when obtaining data packets. In addition, the capacity of the first segment can be dynamically adjusted. For example, in a small packet test scenario (such as a 64-byte data packet): the capacity of the first segment is 4KB, which supports fast writing. In a large packet test scenario (such as a 1500-byte data packet), the capacity of the first segment is extended to 16KB to reduce the frequent switching overhead.

[0039] Specifically, it is detected whether the remaining space of the first segment is less than the first preset value; When it is less than the first preset value, the data packet is obtained from the first segment.

[0040] Preferably, if the first segment frequently triggers the first threshold, the FPGA automatically expands the capacity of the first segment by 50%, with a maximum not exceeding the physical memory upper limit. When the utilization rate of the first segment is lower than the preset value, the capacity of the first segment is reduced.

[0041] In the embodiment of the present application, in order to improve the accuracy of the test, a mechanism for uniformly setting the data packet sending interval is adopted. When the processor generates data packets, it will calculate the sending interval between each data packet according to factors such as test requirements and the type and size of the data packet, and send the interval information to the FPGA.

[0042] When the FPGA sends data packets, it will uniformly or according to a certain rule set the sending interval between each data packet according to the received sending interval information or interval rule. This can ensure the stability of the data packet sending rate during the test, thereby improving the accuracy of the test.

[0043] For example, the Poisson distribution model is selected to calculate the transmission time interval of data packets, and this model is suitable for simulating the randomness of real network traffic. The uniform distribution model can also be selected, and this model is suitable for stability testing, and this time interval is a fixed value.

[0044] In the embodiment of the present application, the FPGA performs an operation of sending a request to the processor once within a preset period, so that the processor obtains data packets from the second segment of the FPGA. In order to further improve the efficiency of data packet transmission, first, the remaining space of the second segment is detected. When the remaining space of the second segment is less than a preset value, the FPGA directly sends request information to the CPU, regardless of whether the current transmission operation is within the preset period. This can ensure that the FPGA will not cause overflow or waste of the second segment when sending data packets. In addition, the capacity of the second segment can be dynamically adjusted. For example, in a small packet test scenario (such as a 64-byte data packet): the capacity of the second segment is 4KB, which supports fast writing. In a large packet test scenario (such as a 1500-byte data packet), the capacity of the second segment is expanded to 16KB, reducing the overhead of frequent switching.

[0045] The specific process of sending data packets to the processor is as follows: Detect whether the remaining space in the second segment is greater than a second preset value; When it is greater than the second preset value, the data packets in the second segment are sent to the processor.

[0046] Preferably, during the process of sending data packets to the processor, in order to prevent the data packets in the second segment from reaching the upper limit, the transmission interval of the data packets to be sent is determined according to the remaining space of the second segment, so that the remaining space is greater than a third preset value. For example, according to the current remaining space and the third preset value, based on the current transmission interval, it is calculated whether the second segment will be filled. If so, the transmission interval is reduced.

[0047] The embodiment of the present application provides a stress test device based on network traffic simulation, as Figure 3 shown, including: an acquisition module 301, a first sending module 302, a receiving module 303, and a second sending module 304; The acquisition module 301 is used to obtain data packets from the application program through a preset first segment; The first sending module 302 is used to set a first timestamp for the data packets and send the data packets containing the first timestamp to the device to be tested; The receiving module 303 is used to receive the data packets returned by the device to be tested; The second sending module 304 is used to set a second timestamp for the returned data packets and store the data packets containing the second timestamp in the second segment; send a request message for obtaining data to the internal memory, so that the application program in the internal memory obtains the second data packets from the second segment.

[0048] An embodiment of the present application provides a storage medium, including: For storing computer-executable instructions, which when executed implement the method described in any of the above embodiments.

[0049] The specific embodiments of the present specification have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0050] In the 1930s, it was obvious to distinguish whether an improvement in a technology was a hardware improvement (e.g., improvement in circuit structures such as diodes, transistors, switches, etc.) or a software improvement (improvement in method processes). However, with the development of technology, many improvements in method processes today can be regarded as direct improvements in hardware circuit structures. Almost all designers obtain the corresponding hardware circuit structures by programming the improved method processes into the hardware circuits. Therefore, it cannot be said that an improvement in a method process cannot be implemented with a hardware entity module. For example, a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can program by themselves to "integrate" a digital method on a piece of PLD without asking the chip manufacturer to design and fabricate a dedicated integrated circuit chip. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development and writing. The original code before compilation also has to be written in a specific programming language, which is called a hardware description language (HDL). And there is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones currently are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be clear that as long as the method process is slightly logically programmed with the above-mentioned several hardware description languages and programmed into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method process.

[0051] The controller can be implemented in any suitable manner. For example, the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of the controller include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, it is entirely possible to implement the same function by logically programming the method steps so that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as either software modules for implementing the method or structures within the hardware component.

[0052] The methods, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0053] For the convenience of description, when describing the above devices, they are described separately as various units according to their functions. Of course, when implementing the embodiments of this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0054] Those skilled in the art should understand that one or more embodiments of this specification can be provided as a method, method, or computer program product. Therefore, one or more embodiments of this specification can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0055] This specification is described with reference to the flowcharts and / or block diagrams of methods, apparatus (methods), and computer program products according to embodiments of the specification. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to produce a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices generate means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0056] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0057] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0058] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0059] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of computer-readable media.

[0060] A computer-readable medium includes both permanent and non-permanent, removable and non-removable media and can implement information storage by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information accessible by a computing device. As defined herein, a computer-readable medium does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0061] It should also be noted that the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0062] One or more embodiments of the present specification can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of the present specification can also be practiced in a distributed computing environment where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0063] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for method embodiments, since they are basically similar to method embodiments, they are described relatively simply, and reference can be made to the relevant parts of the method embodiments for the related content.

[0064] The above are only examples of this document and are not intended to limit this document. For those skilled in the art, this document may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this document shall be included within the scope of the claims of this document.

Claims

1. A field programmable gate array, characterized in that, Comprising: An internal memory and a network card; A segment is set in the internal memory, and the segment is used to store data packets used in the stress test process; In the stress test, the network card interacts with the processor through the segment.

2. The field programmable gate array according to claim 1, characterized in that The segment includes: a first segment and a second segment; The processor sends a first data packet to the first segment through a preset first segment interface; The processor obtains a second data packet from the second segment through a preset second segment interface.

3. The field programmable gate array according to claim 2, characterized in that The network card includes a first network card and a second network card; The first network card obtains the first data packet through the first segment interface; The second network card sends the second data packet through the second segment interface.

4. A stress testing method based on network traffic simulation, characterized in that, Based on the field programmable gate array according to any one of claims 1-3, comprising: Obtaining a first data packet from the processor through a preset first segment; Setting a first timestamp for the first data packet and sending the first data packet containing the first timestamp to the device to be tested; Receiving a second data packet returned by the device to be tested; Setting a second timestamp for the returned second data packet and storing the second data packet containing the second timestamp in the second segment; Sending a request message for obtaining data to the processor, so that the application program in the processor obtains the second data packet from the second segment.

5. The method according to claim 4, characterized in that Obtaining a data packet from the application program through the first segment includes: Detecting whether the remaining space of the first segment is less than a first preset value; When it is less than the first preset value, obtaining a data packet from the first segment.

6. The method according to claim 4, characterized in that There are multiple data packets, and the method further includes: Uniformly setting or setting the sending interval between each of the data packets according to a preset rule.

7. The method according to claim 4, characterized in that Transmitting to the processor through the second segment includes: Detecting whether the remaining space in the second segment is greater than a second preset value; When it is greater than the first preset value, sending a request message to the processor.

8. The method according to claim 7, characterized in that The method further includes: Determining the sending interval of the data packet to be sent according to the remaining space of the second segment, so that the remaining space is greater than a third preset value.

9. A pressure testing device based on network traffic simulation, characterized in that, Comprising: An acquisition module, a first sending module, a receiving module and a second sending module; The acquisition module is used to obtain a first data packet from the application program through a preset first segment; The first sending module is used to set a first timestamp for the first data packet and send the first data packet containing the first timestamp to the device to be tested; The receiving module is used to receive a second data packet returned by the device to be tested; The second sending module is used to set a second timestamp for the returned second data packet and store the second data packet containing the second timestamp in the second segment; Sending a request message for obtaining data to the internal memory, so that the application program in the internal memory obtains the second data packet from the second segment.

10. A storage medium, characterized in that, Comprising: For storing computer-executable instructions that, when executed, implement the method according to any one of claims 4-8.

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