Super-junction IGBT device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a super-junction IGBT (Insulated Gate Bipolar Translator) device and a preparation method thereof. The super-junction IGBT device comprises a current collection layer, a buffer layer, a voltage-withstanding layer and a top composite structure which are arranged in sequence, the top composite structure comprises a top base layer and a gate structure, the top base layer is provided with a groove, and the gate structure is formed in the groove; wherein the voltage-withstanding layer comprises first voltage-withstanding areas and second voltage-withstanding areas which are alternately distributed, and the second voltage-withstanding areas and the first voltage-withstanding areas are distributed in an interdigitated manner. According to the super-junction IGBT device, the second voltage-withstanding region and the first voltage-withstanding region are distributed in an interdigitated manner, and in the turn-off process of the device, the resistance of a carrier extraction path can be effectively increased by utilizing the second voltage-withstanding region and the first voltage-withstanding region which are distributed in the interdigitated manner, so that the current descending speed in the turn-off stage of the device is reduced, the turn-off voltage peak is inhibited, and the turn-off efficiency of the device is improved. And the problem of failure caused by overvoltage breakdown of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a superjunction IGBT device and a method for manufacturing the same. Background Art

[0002] A superjunction IGBT device is a new type of power semiconductor device that combines a superjunction (SJ) structure and an insulated gate bipolar transistor (IGBT) technology, and has N-column regions and P-column regions (i.e., a superjunction structure) arranged alternately in the transverse direction.

[0003] When the superjunction structure bears a reverse bias voltage, a transverse electric field will be generated at the PN junctions of the N-column regions and the P-column regions. During the device turn-off stage, the device is extremely prone to breakdown and failure. Summary of the Invention

[0004] An object of the present invention is to provide a superjunction IGBT device and a method for manufacturing the same. In the superjunction IGBT device manufactured by the manufacturing method, a second voltage withstand region and a first voltage withstand region form an interdigitated distribution. During the device turn-off process, the interdigitated second voltage withstand region and first voltage withstand region can be used to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate during the device turn-off stage, thereby suppressing the turn-off voltage spike and improving the problem of device overvoltage breakdown and failure.

[0005] Embodiments of the present invention may be implemented as follows: In a first aspect, the present invention provides a superjunction IGBT device, including: a collector layer, a buffer layer, a voltage withstand layer, and a top composite structure arranged in sequence; The top composite structure includes a top base layer and a gate structure. The top base layer has grooves, and the gate structure is formed in the grooves; wherein, The voltage withstand layer includes alternately distributed first voltage withstand regions and second voltage withstand regions, and the second voltage withstand regions and the first voltage withstand regions form an interdigitated distribution.

[0006] In an alternative embodiment, the first voltage withstand region includes a plurality of first long fingers and a plurality of first short fingers, and the second voltage withstand region includes a plurality of second long fingers and a plurality of second short fingers; along a first direction, the plurality of second long fingers and the plurality of second short fingers are arranged alternately in sequence, and the plurality of first long fingers and the plurality of first short fingers are arranged alternately in sequence; along a second direction, the plurality of second long fingers are arranged in one-to-one correspondence with the plurality of first short fingers, and the plurality of second short fingers are arranged in one-to-one correspondence with the plurality of first long fingers; wherein, the first direction and the second direction are distributed at an angle, and the collector layer, the buffer layer, the voltage withstand layer, and the top composite structure are arranged in sequence along the first direction.

[0007] In an alternative embodiment, the grooves extend into the second voltage withstand region, and the bottom of the gate structure is wrapped by the second voltage withstand region.

[0008] In an alternative embodiment, the gate structure includes polysilicon and a gate oxide layer wrapped around the outside of the polysilicon.

[0009] In an alternative embodiment, the gate structure further includes a gate conductor disposed on top of the polysilicon.

[0010] In an alternative embodiment, the top base layer includes a carrier storage region, a second base region, and a first base region and a source region; wherein, the carrier storage region and the second base region are sequentially disposed on a side of the voltage-resistant layer facing away from the buffer layer, the first base region and the source region are disposed on a side of the second base region facing away from the carrier storage region, and the source region is adjacent to the gate structure.

[0011] In an alternative embodiment, the superjunction IGBT device further includes an emitter conductor covering the tops of the source region and the first base region.

[0012] In an alternative embodiment, the superjunction IGBT device further includes a collector conductor disposed on a side of the collector layer facing away from the buffer layer.

[0013] In a second aspect, the present invention provides a method for manufacturing a superjunction IGBT device, and the method for manufacturing a superjunction IGBT device is used to manufacture the superjunction IGBT device according to any one of the foregoing embodiments; the method for manufacturing a superjunction IGBT device includes: Form a voltage-resistant layer on the substrate, wherein the voltage-resistant layer includes a first voltage-resistant region and a second voltage-resistant region, and the second voltage-resistant region and the first voltage-resistant region are formed in an interdigitated distribution; Form an epitaxial layer on the voltage-resistant layer and form trenches in the epitaxial layer; Form a gate structure in the trenches; Form a top base layer on the epitaxial layer.

[0014] In an alternative embodiment, when forming the trenches, extend the trenches into the second voltage-resistant region; Form a gate oxide layer in the trenches, and then backfill polysilicon in the gate oxide layer.

[0015] The beneficial effects of the superjunction IGBT device according to the embodiments of the present invention include: the superjunction IGBT device provided by the embodiments of the present invention has a second voltage-resistant region and a first voltage-resistant region formed in an interdigitated distribution. During the turn-off process of the device, the second voltage-resistant region and the first voltage-resistant region formed in an interdigitated distribution can be used to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate during the turn-off stage of the device, thereby suppressing the turn-off voltage spike and improving the problem that the device fails due to overvoltage breakdown.

[0016] The beneficial effects of the method for manufacturing a superjunction IGBT device according to an embodiment of the present invention include: The manufacturing method provided by the embodiment of the present invention can be used to manufacture a superjunction IGBT device in which a second breakdown voltage region and a first breakdown voltage region are distributed in an interdigitated manner. Since the second breakdown voltage region and the first breakdown voltage region are distributed in an interdigitated manner, during the turn-off process of the device manufactured by this method, the interdigitated second breakdown voltage region and first breakdown voltage region can be utilized to effectively increase the resistance of the carrier extraction path, so as to reduce the current fall speed during the turn-off stage of the device, thereby suppressing the turn-off voltage spike and improving the problem of device failure due to overvoltage breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 is a schematic structural diagram of a superjunction IGBT device according to an embodiment of the present invention; Figure 2 is a schematic structural diagram of a substrate according to an embodiment of the present invention; Figure 3 is a schematic diagram of forming a second short finger and a first long finger on the substrate according to an embodiment of the present invention; Figure 4 is a schematic diagram of alternately forming a first long finger and a first short finger, and alternately forming a second short finger and a second long finger on the substrate according to an embodiment of the present invention; Figure 5 is a schematic diagram of forming a first breakdown voltage region and a second breakdown voltage region in the substrate according to an embodiment of the present invention; Figure 6 is a schematic diagram of forming an epitaxial layer on a breakdown voltage layer according to an embodiment of the present invention; Figure 7 is a schematic diagram of forming a gate structure on the epitaxial layer according to an embodiment of the present invention; Figure 8 is a schematic diagram of forming a carrier storage region and a second base region on the epitaxial layer according to an embodiment of the present invention; Figure 9 is a schematic diagram of forming a first base region and a source region on the second base region according to an embodiment of the present invention; Figure 10 is a schematic diagram of forming a gate conductor and an emitter conductor according to an embodiment of the present invention; Figure 11 is a schematic diagram of thinning the substrate according to an embodiment of the present invention; Figure 12Schematic diagram of forming a buffer layer and a collector layer in an embodiment of the present invention.

[0019] Icons: 1 - collector conductor; 2 - gate conductor; 3 - emitter conductor; 10 - collector layer; 20 - buffer layer; 30 - first breakdown voltage region; 301 - first long finger; 302 - first short finger; 31 - second breakdown voltage region; 311 - second long finger; 312 - second short finger; 32 - carrier storage region; 40 - source region; 41 - first base region; 42 - second base region; 5 - gate structure; 50 - gate oxide layer; 51 - polysilicon; 100 - substrate; 101 - epitaxial layer; 200 - superjunction IGBT device. Detailed implementation manners

[0020] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the drawings herein can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0022] It should be noted that: like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0023] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the product of the present invention is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0024] In addition, if terms such as "first", "second", etc. are used only for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0025] It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0026] The superjunction IGBT device provided by the related art has N-column regions and P-column regions (i.e., superjunction structure) arranged alternately in the lateral direction.

[0027] The inventors' research found that when the superjunction structure bears a reverse bias voltage, a lateral electric field will be generated at the PN junctions of the N-column regions and P-column regions. Before breakdown, the entire N-column regions and P-column regions of the device are nearly completely depleted in the lateral direction. Therefore, during the device turn-off stage, the N-column regions and P-column regions arranged alternately in the lateral direction will be rapidly depleted in the lateral direction, and the carrier extraction speed in the device body is too fast, resulting in a relatively fast decline in the turn-off current of the device and a too large turn-off voltage spike, which is extremely likely to cause overvoltage breakdown of the device and failure.

[0028] In order to improve the above problems, the present embodiment provides a new superjunction IGBT device, which can reduce the decline speed of the device turn-off current, thereby reducing the turn-off voltage spike and improving the problem of overvoltage breakdown and failure of the device. The superjunction IGBT device of the present embodiment will be introduced in detail below with reference to the accompanying drawings.

[0029] Please refer to Figure 1 , the present embodiment provides a superjunction IGBT device 200, which includes a collector layer 10, a buffer layer 20, a breakdown voltage layer, and a top composite structure arranged in sequence; the top composite structure includes a top base layer and a gate structure 5, and the top base layer has grooves, and the gate structure 5 is formed in the grooves; wherein, the breakdown voltage layer includes second breakdown voltage regions 31 and first breakdown voltage regions 30 distributed alternately, and the second breakdown voltage regions 31 and the first breakdown voltage regions 30 are arranged in an interdigitated manner.

[0030] During the turn-off process of the superjunction IGBT device 200, the second breakdown voltage regions 31 and the first breakdown voltage regions 30 arranged in an interdigitated manner can be used to effectively increase the resistance of the carrier extraction path, so as to reduce the current decline speed during the device turn-off stage, thereby suppressing the turn-off voltage spike and improving the problem of overvoltage breakdown and failure of the device.

[0031] Furthermore, the second breakdown voltage regions 31 and the first breakdown voltage regions 30 are of the first conductivity type and the second conductivity type respectively, that is, the second breakdown voltage regions 31 are of the first conductivity type, and the first breakdown voltage regions 30 are of the second conductivity type; wherein, the first conductivity type can refer to one of N-type and P-type, and the second conductivity type can refer to the other of N-type and P-type.

[0032] The above-mentioned second breakdown voltage region 31 and the first breakdown voltage region 30 form an interdigital distribution, which may mean that both the second breakdown voltage region 31 and the first breakdown voltage region 30 have a structure with alternating long and short lengths; where the second breakdown voltage region 31 includes a plurality of second long fingers 311 and a plurality of second short fingers 312, and the first breakdown voltage region 30 includes a plurality of first long fingers 301 and a plurality of first short fingers 302; along the first direction a, the plurality of second long fingers 311 and the plurality of second short fingers 312 are alternately arranged in sequence, and the plurality of first long fingers 301 and the plurality of first short fingers 302 are alternately arranged in sequence; along the second direction b, the plurality of second long fingers 311 are arranged in one-to-one correspondence with the plurality of first short fingers 302, and the plurality of second short fingers 312 are arranged in one-to-one correspondence with the plurality of first long fingers 301; the length of the second long finger 311 along the second direction b is greater than the length of the second short finger 312 along the second direction b, and the length of the first long finger 301 along the second direction b is greater than the length of the first short finger 302 along the second direction b; where the first direction a and the second direction b are distributed at an angle, and the collector layer 10, the buffer layer 20, the breakdown voltage layer, and the top composite structure are arranged in sequence along the first direction a.

[0033] Since the length of the first short finger 302 is less than the length of the first long finger 301, and the length of the second short finger 312 is less than the length of the second long finger 311, therefore, the width (i.e., area) of at least part of the positions of the first breakdown voltage region 30 and the second breakdown voltage region 31 is reduced, that is, at least the widths of the first short finger 302 and the second short finger 312 are reduced; thus, the resistance corresponding to at least the first short finger 302 and the second short finger 312 increases; when the device is turned off, a larger resistance can be utilized to effectively slow down the carrier extraction speed, reduce the current drop speed during the device turn-off stage, thereby suppressing the turn-off voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0034] Optionally, the first direction a is perpendicular to the second direction b. Of course, in other embodiments, there may be a certain angle between the first direction a and the second direction b, for example: 0.5°, 1°, etc., which are not specifically limited herein.

[0035] Optionally, the breakdown voltage layer includes a plurality of first breakdown voltage regions 30 and a plurality of second breakdown voltage regions 31; where the two ends of the second long finger 311 of the second breakdown voltage region 31 protrude relative to the second short finger 312, the two ends of the first long finger 301 of a part of the first breakdown voltage region 30 protrude relative to the first short finger 302, and one end of the first long finger 301 of another part of the first breakdown voltage region 30 protrudes relative to the first short finger 302, and the other end of the corresponding first long finger 301 is flush with the first short finger 302.

[0036] Of course, in other embodiments, both ends of the second long finger 311 of a part of the second voltage-resistant region 31 protrude relative to the second short finger 312, and one end of the second long finger 311 of another part of the second voltage-resistant region 31 protrudes relative to the second short finger 312, and the other end of the corresponding second long finger 311 is flush with the second short finger 312.

[0037] The numbers of the second long fingers 311 and the second short fingers 312 of the second voltage-resistant region 31 can be selected as needed; in this embodiment, the second voltage-resistant region 31 includes 5 second long fingers 311 and 6 second short fingers 312. Along the first direction, both ends of the second voltage-resistant region 31 are second short fingers 312, and one of them is arranged on the buffer layer 20, and the other is used for arranging the top base layer.

[0038] Of course, in other embodiments, the number of the second long fingers 311 can also be 1, 2, 3, 4, 6, etc. Correspondingly, the number of the second short fingers 312 is one more or one less than that of the second long fingers 311.

[0039] Similarly, the numbers of the first long fingers 301 and the first short fingers 302 of the first voltage-resistant region 30 can be selected as needed; in this embodiment, the first voltage-resistant region 30 includes 6 first long fingers 301 and 5 first short fingers 302. Along the first direction, both ends of the first voltage-resistant region 30 are first long fingers 301, and one of them is arranged on the buffer layer 20, and the other is used for arranging the top base layer.

[0040] Of course, in other embodiments, the number of the first long fingers 301 can also be 1, 2, 3, 4, 6, etc. Correspondingly, the number of the first short fingers 302 is one more or one less than that of the second long fingers 311.

[0041] The inventor further studies and finds that during the turn-off process of the superjunction IGBT device 200, the electric field at the bottom of the trench of the top base layer is relatively high, which is extremely likely to cause the breakdown of the gate structure 5 at the bottom of the trench and lead to device failure.

[0042] To improve the above problems, please refer to Figure 1 , in this embodiment, the trench is extended into the second voltage-resistant region 31, and the bottom of the gate structure 5 is wrapped by the second voltage-resistant region 31. In this way, the electric field at the bottom of the trench can be reduced, the problem of the gate structure 5 being broken down by the high electric field can be improved, and the reliability of the device can be improved.

[0043] The depth of the trench can be set as needed. In this embodiment, the trench extends into the second short finger 312 connected to the top base layer and does not extend into the second long finger 311 connected to the second short finger 312.

[0044] Of course, in other embodiments, the trench extends into the second short finger 312 that is in contact with the top base layer, and further extends into the second long finger 311 that is in contact with the second short finger 312.

[0045] The gate structure 5 of this embodiment includes polysilicon 51 and a gate oxide layer 50 wrapped around the outside of the polysilicon 51; the bottom of the polysilicon 51 and the bottom of the gate oxide layer 50 are both disposed at the bottom of the trench extending into the second breakdown voltage region 31. In this way, when the device is turned off, the problem of device failure caused by gate oxide breakdown can be effectively improved.

[0046] Of course, in other embodiments, only the bottom of the gate oxide layer 50 may be disposed at the bottom of the trench extending into the second breakdown voltage region 31.

[0047] The gate structure 5 of this embodiment further includes a gate conductor 2 disposed on the top of the polysilicon 51.

[0048] Furthermore, the top base layer includes a carrier storage region 32, a second base region 42, as well as a first base region 41 and a source region 40; wherein, the carrier storage region 32 and the second base region 42 are sequentially disposed on the side of the breakdown voltage layer facing away from the buffer layer 20, and the carrier storage region 32 covers the second breakdown voltage region 31 and the first breakdown voltage region 30; the first base region 41 and the source region 40 are disposed on the side of the second base region 42 facing away from the carrier storage region 32, and the source region 40 is adjacent to the gate structure 5.

[0049] Still further, the superjunction IGBT device 200 further includes an emitter conductor 3 and a collector conductor 1, the emitter conductor 3 covers the tops of the source region 40 and the first base region 41; the collector conductor 1 is disposed on the side of the collector layer 10 facing away from the buffer layer 20.

[0050] Optionally, the buffer region, the polysilicon 51, the carrier storage region 32, and the source region 40 are all of the first conductivity type; the collector layer 10, the first base region 41, and the second base region 42 are all of the second conductivity type.

[0051] This embodiment also provides a method for manufacturing the above-mentioned superjunction IGBT device 200, which includes: Forming a breakdown voltage layer on the substrate 100, wherein the breakdown voltage layer includes a second breakdown voltage region 31 and a first breakdown voltage region 30, and the second breakdown voltage region 31 and the first breakdown voltage region 30 are formed in an interdigitated distribution; Forming an epitaxial layer 101 on the breakdown voltage layer, and forming a trench in the epitaxial layer 101; Forming a gate structure 5 in the trench; Forming a top base layer on the epitaxial layer 101.

[0052] The preparation method can be used to prepare a super junction IGBT device 200 in which the second voltage-resistant region 31 and the first voltage-resistant region 30 are distributed in a finger-like manner. Since the second voltage-resistant region 31 and the first voltage-resistant region 30 are distributed in a finger-like manner, the device prepared by the method can utilize the second voltage-resistant region 31 and the first voltage-resistant region 30 distributed in a finger-like manner during the shutdown process to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate in the shutdown stage of the device, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0053] Optionally, see Figure 2 , Figure 3 , Figure 4 and Figure 5 The method for forming a voltage-resistant layer includes: forming second short fingers 312 and second long fingers 311 alternately in sequence on a substrate 100 along a first direction, and when forming the second short fingers 312, forming first long fingers 301 that are distributed opposite to the second short fingers 312 along a second direction, and when forming the second long fingers 311, forming first short fingers 302 that are distributed opposite to the second long fingers 311 along the second direction. In this way, an interdigitated structure in which long and short fingers are crossed can be efficiently formed.

[0054] Optionally, see Figure 6 and Figure 7 When forming a trench in the epitaxial layer, the trench is extended to the second voltage-resistant region 31; a gate oxide layer 50 is formed in the trench, and polysilicon 51 is backfilled in the gate oxide layer 50 to form a gate structure 5. In this way, the bottom of the trench and the bottom of the gate structure 5 can be wrapped by the second voltage-resistant region 31, so as to reduce the electric field at the bottom of the trench, thereby improving the problem of gate oxide breakdown failure when the device is turned off.

[0055] Optionally, see Figure 8 and Figure 9 The preparation method of the top base layer includes: forming a carrier storage area 32 and a second base area 42 in sequence at a position where no groove is set in the epitaxial layer 101, and then forming a first base area 41 and a source area 40 distributed side by side in the second base area 42, and making the source area 40 adjacent to the gate structure 5.

[0056] Optionally, see Figure 10 The method for preparing the super junction IGBT device 200 also includes, after forming the top base layer, preparing a groove at the portion of the gate oxide layer 50 exposed from the top of the trench, and then preparing a gate conductor 2 at the groove, and making the gate conductor 2 contact the top of the polysilicon 51.

[0057] Optionally, see Figure 10, a method for manufacturing a super junction IGBT device 200 further includes, after forming the top base layer, forming an emitter conductor 3 on the tops of the first base region 41 and the source region 40.

[0058] Optionally, please refer to Figure 11 and Figure 12 , a method for manufacturing a super junction IGBT device 200 further includes: thinning one side of the substrate 100 away from the voltage withstand layer, sequentially disposing a buffer layer 20 and a collector layer 10 on the side of the substrate 100 away from the voltage withstand layer, and disposing a collector conductor 1 on the collector layer 10.

[0059] In summary, in the super junction IGBT device 200 of the present invention, the second voltage withstand region 31 and the first voltage withstand region 30 are formed in an interdigitated distribution. During the device turn-off process, the interdigitated second voltage withstand region 31 and first voltage withstand region 30 can be utilized to effectively increase the resistance of the carrier extraction path, so as to reduce the current fall speed during the device turn-off stage, thereby suppressing the turn-off voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0060] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A super junction IGBT device, characterized in that, include: A current collecting layer (10), a buffer layer (20), a voltage-resistant layer, and a top composite structure are arranged in sequence; The top composite structure comprises a top base layer and a gate structure (5), the top base layer having a groove, and the gate structure (5) is formed in the groove; wherein: The voltage-resistant layer comprises first voltage-resistant regions (30) and second voltage-resistant regions (31) which are alternately distributed, and the second voltage-resistant regions (31) and the first voltage-resistant regions (30) form an interdigitated distribution.

2. The superjunction IGBT device according to claim 1, wherein The first voltage-resistant region (30) includes a plurality of first long fingers (301) and a plurality of first short fingers (302), and the second voltage-resistant region (31) includes a plurality of second long fingers (311) and a plurality of second short fingers (312); along the first direction, the plurality of second long fingers (311) and the plurality of second short fingers (312) are arranged alternately in sequence, and the plurality of first long fingers (301) and the plurality of first short fingers (302) are arranged alternately in sequence; along the second direction, the plurality of second long fingers (311) and the plurality of first short fingers (302) are arranged in a one-to-one correspondence, and the plurality of second short fingers (312) and the plurality of first long fingers (301) are arranged in a one-to-one correspondence; wherein the first direction is distributed at an angle to the second direction, and the collector layer (10), the buffer layer (20), the voltage-resistant layer, and the top composite structure are arranged in sequence along the first direction.

3. The super junction IGBT device according to claim 1 or 2, characterized in that, The groove extends into the second voltage-resistant region (31), and the bottom of the gate structure (5) is wrapped by the second voltage-resistant region (31).

4. The superjunction IGBT device according to claim 3, characterized in that, The gate structure (5) comprises polysilicon (51) and a gate oxide layer (50) wrapped around the outside of the polysilicon (51).

5. The super junction IGBT device according to claim 4, wherein The gate structure (5) further comprises a gate conductor (2) arranged on top of the polysilicon (51).

6. The superjunction IGBT device according to claim 1 or 2, characterized in that, The top base layer comprises a carrier storage region (32), a second base region (42), and a first base region (41) and a source region (40); wherein the carrier storage region (32) and the second base region (42) are sequentially arranged on a side of the voltage-resistant layer away from the buffer layer (20), the first base region (41) and the source region (40) are arranged on a side of the second base region (42) away from the carrier storage region (32), and the source region (40) is adjacent to the gate structure (5).

7. The superjunction IGBT device according to claim 6, characterized in that, The super junction IGBT device further comprises an emitter conductor (3), wherein the emitter conductor (3) covers the top of the source region (40) and the first base region (41).

8. The superjunction IGBT device according to claim 1 or 2, characterized in that, The super junction IGBT device further comprises a collector conductor (1), wherein the collector conductor (1) is arranged on a side of the collector layer (10) facing away from the buffer layer (20).

9. A method for manufacturing a superjunction IGBT device, characterized in that, The method for preparing the super junction IGBT device is used to prepare the super junction IGBT device according to any one of claims 1 to 8; the method for preparing the super junction IGBT device comprises: A voltage-resistant layer is formed on a substrate (100), wherein the voltage-resistant layer comprises a first voltage-resistant region (30) and a second voltage-resistant region (31), and the second voltage-resistant region (31) and the first voltage-resistant region (30) are distributed in an interdigitated manner; An epitaxial layer (101) is formed on the pressure-resistant layer, and trenches are formed in the epitaxial layer (101). A gate structure (5) is formed in the trenches. A top base layer is formed on the epitaxial layer (101).

10. The manufacturing method of the super junction IGBT device according to claim 9, characterized in that, When forming the trenches, the trenches are extended into the second pressure-resistant region (31). A gate oxide layer (50) is formed in the trenches, and then polysilicon (51) is backfilled in the gate oxide layer (50).

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