Trench MOSFET manufacturing method

Abstract

The invention provides an improved Trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) manufacturing method, aiming at solving the problem of gaps generated by polysilicon filling in the traditional process and improving the performance and the yield of a device. The method comprises the steps of etching a groove on a silicon substrate, forming a gate oxide layer, performing polysilicon filling and etching twice, and performing chemical mechanical polishing (CMP) treatment. In addition, an oxide layer is formed on the surface of the polycrystalline silicon, a body and a source region are formed through ion implantation, and annealing treatment is carried out. According to the method, the accuracy of the groove structure and the stability of polycrystalline silicon filling are ensured by accurately controlling process parameters such as the depth of the groove, the thickness of the oxide layer and the film forming temperature of polycrystalline silicon, the problems of etching penetration and unstable electrical property are effectively avoided, and the electrical property and the consistency of the Trench MOSFET are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for manufacturing a Trench MOSFET (Trench Metal Oxide Semiconductor Field Effect Transistor). Background Art

[0002] In semiconductor processes, Trench MOSFET has become a mature technology. As a trench metal oxide field effect transistor, Trench MOSFET has a low on-resistance Rds(on) and gate-drain charge density, enabling lower conduction losses and switching losses, and at the same time having a faster switching speed. By adopting advanced trench technology and chip layout, it has the advantages of strong impact resistance, high output efficiency, and low cost, and can be widely applied to various application fields with a working frequency less than 100 kHz.

[0003] However, in the traditional Trench MOSFET process flow, there are obvious defects. Since the gate polysilicon is directly filled in the trench, voids in the polysilicon will occur during the seam formation process of the polysilicon. In the subsequent polysilicon etching process, there is a risk that these voids will be etched through. Once the etching through occurs, it will cause the product to have a leakage phenomenon, seriously affecting the performance and quality of the product. In addition, in the traditional Trench MOSFET process flow, the problem of polysilicon film formation rate and void generation restricts each other. When the polysilicon film formation rate is higher, it is easier to generate gaps during the seam formation process; while the film formation rate is lower, although the gaps will become smaller, the overall film formation time will be greatly extended, and the long-term thermal process will cause the doping of the epitaxial substrate to diffuse outward. This doping diffusion will make the electrical properties of the overall product unstable and unable to meet the strict requirements of high-performance semiconductor devices for stability and consistency.

[0004] In view of this, the present invention aims to provide an improved method for manufacturing Trench MOSFET to solve the problems of etching through and leakage caused by voids generated during polysilicon filling and the instability of product electrical properties in the prior art, thereby improving the performance and yield rate of Trench MOSFET. The present invention effectively overcomes the defects of the traditional process through innovative process steps and parameter optimization, and provides a new solution for the manufacture of high-performance Trench MOSFET. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing a Trench MOSFET to solve the problems of etching through and leakage caused by voids generated during polysilicon filling and the instability of product electrical properties in the prior art, and to improve the performance and yield rate of Trench MOSFET.

[0006] The manufacturing method of the Trench MOSFET provided by the present invention mainly includes the following steps: 1. Providing a silicon wafer with epitaxy and etching trenches: Select a silicon substrate with an epitaxial layer, and through photolithography and etching processes, etch the required trenches on the silicon epitaxial layer. The depth of the trenches is controlled within 0.5 to 1.0 um. The specific steps for forming the trenches are as follows: First, form a hard mask layer on the epitaxial layer, and then perform selective photolithography on the hard mask layer to accurately etch the area where the trenches need to be formed. 2. Thermally oxidizing to form a gate oxide layer: Form a gate oxide layer on the surface of the silicon wafer with etched trenches through a thermal oxidation process. The thickness of the gate oxide layer is controlled within 30 to 100 nm, and the process temperature is maintained at 800 to 1200 °C. 3. First filling of gate polysilicon: Adopt a suitable method such as chemical vapor deposition (CVD) to perform the first filling of gate polysilicon. The thickness of the first polysilicon film formation is 2 to times that of the second polysilicon film formation, and the film formation temperature of the first polysilicon is controlled at 580 °C. 4. Etching of gate polysilicon: Etch the gate polysilicon after the first filling, and adopt semiconductor dry etching technology to remove the excess polysilicon to prepare for subsequent processes. 5. Second filling of gate polysilicon: Perform the second filling of gate polysilicon, and the film formation temperature of the second polysilicon is 530 °C. 6. Grinding of gate polysilicon: Adopt chemical mechanical polishing (CMP) to process the polysilicon after the second filling and the substrate surface to be flush to ensure the flatness of the surface. 7. Thermally oxidizing to form an oxide layer: Once again, form an oxide layer on the polysilicon surface through a thermal oxidation process. The main component of this oxide layer is silicon oxide, and the thickness is controlled within 10 to 50 nm. 8. Body implantation and annealing treatment: Form a body region on both sides of the trenches through ion implantation, and perform annealing treatment at a temperature of 1000 °C to 1500 °C after the implantation is completed. 9. Source ion implantation and annealing treatment: Form a source in the corresponding region through ion implantation, and perform annealing treatment at a temperature of 1000 °C to 1500 °C after the implantation is completed.

[0007] Regarding claim 2, the substrate is a silicon substrate formed with a silicon epitaxial layer, and the trenches are formed inside the silicon epitaxial layer, with the depth controlled within 0.5 to 1.0 um. The steps for forming the trenches in the epitaxial layer include forming a hard mask layer on the epitaxial layer and performing selective photolithography on the mask layer to etch out the key trench regions.

[0008] Regarding claim 3, the gate oxide layer is realized through a thermal oxidation process, with the thickness controlled within 30 to 100 nm to ensure the electrical insulation performance and quality of the gate oxide layer. The process temperature is controlled within 800 to 1200 °C to avoid thermal damage to the silicon substrate.

[0009] For claim 4, the thickness of the first polysilicon film is 2 to 3 times that of the second polysilicon film, which reduces the voids in the polysilicon during subsequent etching processes, thereby reducing the risk of etching through. The deposition temperature of the first polysilicon is controlled at 580 °C, and the deposition temperature of the second polysilicon is 530 °C. While controlling the thickness and surface characteristics of the polysilicon layer, the flatness with the substrate is ensured.

[0010] For claim 5, the etching of the first polysilicon uses semiconductor dry etching, a process of removing materials using plasma or reactive gases in a vacuum or low-pressure environment, which provides high etching selectivity and precision and is suitable for fine etching after the first polysilicon filling to remove excess polysilicon material. The second polysilicon is processed by chemical mechanical polishing (CMP) to achieve global planarization of the polysilicon layer.

[0011] For claim 6, the main component of the oxide layer formed by thermal oxidation is silicon oxide, and the thickness is controlled within 10 to 50 nm, ensuring sufficient insulation performance and stable electrical characteristics, gate capacitance and threshold voltage. The main component of the oxide layer is silicon oxide, which is an insulating material widely used in semiconductor devices due to its good electrical insulation performance and chemical stability. The thickness of the oxide layer is strictly controlled between 10 and 50 nanometers.

[0012] Furthermore, precise control of the thickness range is crucial for ensuring the performance of the device. An oxide layer that is too thin cannot provide sufficient insulation performance, while an oxide layer that is too thick affects the electrical characteristics of the device, such as gate capacitance and threshold voltage. By precisely controlling the composition and thickness of the oxide layer, the method of the present invention can optimize the electrical performance of the Trench MOSFET, improve its switching speed and reduce leakage current, thereby enhancing the overall device performance and reliability.

[0013] For claim 7, the body and source regions are formed by ion implantation. Ion implantation is a technique of introducing dopants, usually impurity elements, into specific regions of a semiconductor material to change the electrical properties of that region. In a Trench MOSFET, the body and source regions need to have specific doping concentrations to ensure the normal operation of the device.

[0014] After each ion implantation, an annealing treatment is carried out in the temperature range of 1000 °C to 1500 °C. Annealing is a heat treatment process used to activate the implanted dopants and repair the lattice defects generated during the ion implantation process.

[0015] Furthermore, the steps are crucial for ensuring the correct distribution of dopants in the silicon substrate and improving the electrical performance of the device. The temperature range is sufficient to activate the dopants while avoiding thermal damage to the silicon substrate, and also helps to minimize the change in device size caused by high-temperature processing.

[0016] Regarding claim 8, it further clarifies the specific positions and formation methods of the body and source regions in the Trench MOSFET manufacturing method. The body and source regions are located on both sides of the trench. The layout is one of the key features of the Trench MOSFET structure, which helps to form an effective channel and control the flow of current. The body and source are formed by ion implantation. Using ion implantation technology can form the body and source regions with uniform doping concentration on both sides of the trench. By precisely controlling the energy and dose of ion implantation, the depth and concentration of dopants can be precisely controlled, thereby optimizing the electrical performance and reliability of the device.

[0017] Preferably, regarding claim 9, a semiconductor dry etching technique is used to form the trench. Dry etching is a process that uses plasma, reactive gas, or ion beam to remove materials in a vacuum or low-pressure environment, which can provide high selectivity and high precision etching and is suitable for precisely etching a trench with a depth control of 0.5 to 1.0 um on the silicon substrate. The advantage of dry etching is that it can achieve precise control of the etching profile and depth, which is crucial for forming a high-quality trench structure.

[0018] Furthermore, after the second polysilicon filling, chemical mechanical polishing (CMP) is used to process the filled polysilicon flush with the substrate surface. CMP is a planarization technique that combines chemical etching and mechanical polishing, which can achieve global planarization, ensure that the surface of the polysilicon layer is flat and consistent with the surface of the silicon substrate, and prepare for subsequent process steps such as forming a gate oxide layer and performing ion implantation, which can ensure the uniformity of subsequent processes and the performance of the device.

[0019] Regarding claim 10, after the ion implantation of the body and source regions is completed, annealing treatment is carried out in the temperature range of 1000°C to 1500°C. The body and source regions use the same annealing temperature range, ensuring the consistency of the annealing treatment. This consistency helps to ensure the performance uniformity and reliability of the entire Trench MOSFET device. The annealing process helps to repair the lattice defects introduced during the ion implantation process and improve the electrical performance and stability of the device.

[0020] The above technical solutions can achieve the following beneficial effects: Compared with the prior art, the present invention has the following advantages and positive effects: (1) The manufacturing method provided by the present invention effectively avoids the generation of gaps caused by the polysilicon film formation process by performing multiple film formations, first filling, etching, and second filling of the gate polysilicon, thereby avoiding the occurrence of etching penetration caused by subsequent polysilicon etching.

[0021] (2) The manufacturing method provided by the present invention clearly stipulates that the substrate is a silicon substrate formed with a silicon epitaxial layer, and strictly regulates the formation position of the trench in the silicon epitaxial layer, the depth of 0.5 to 1.0 um, and the formation steps, ensuring the accuracy of the trench structure.

[0022] (3) The manufacturing method provided by the present invention precisely controls the gate oxide layer and polysilicon film formation parameters, limits the thickness of the gate oxide layer to 30 to 100 nm and the formation process temperature to 800 to 1200 °C, ensuring that the performance of the oxide layer meets the device requirements. At the same time, the thickness ratio and different film formation temperatures of the first and second gate polysilicon film formations are clarified, ensuring the quality and stability of polysilicon filling.

[0023] (4) The manufacturing method provided by the present invention stipulates that the first polysilicon etching uses semiconductor dry etching, and the second polysilicon uses chemical mechanical polishing (CMP) for processing. This refined processing technology selection not only ensures the processing accuracy but also ensures the surface quality, improving the performance and yield of the final product.

[0024] (5) The manufacturing method provided by the present invention limits the composition and thickness of the oxide layer formed by thermal oxidation to meet the device performance requirements. The formation methods of the body and the source and the annealing treatment temperature range are clarified, ensuring the uniformity of impurity distribution and the activation effect, and further improving the electrical performance and stability of the device.

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art.

[0026] Figure 1 It is a structural illustration of the Trench MOSFET transistor provided by the present invention.

[0027] Figure 2 It is a step illustration of trench etching and forming a gate oxide layer in the transistor manufacturing of the present invention.

[0028] Figure 3 It is a step illustration of filling and etching the first gate polysilicon in the transistor manufacturing of the present invention.

[0029] Figure 4 It is a step illustration of filling and etching the second gate polysilicon in the transistor manufacturing of the present invention.

[0030] Figure 5 This is a step diagram for regenerating the oxide layer and forming the body and source in the fabrication of the transistors of the present invention.

[0031] Figure 6 This is a flowchart of a method for manufacturing a Trench MOSFET provided by the present invention.

[0032] In the figure: (1) epitaxial silicon wafer with trenches, (2) gate oxide layer, (3) first gate polysilicon, (4) second gate polysilicon, (5) regenerated gate oxide layer, (6) body, (7) source. Detailed implementation mode

[0033] The present invention will be further explained below in conjunction with the accompanying drawings and specific embodiments.

[0034] The implementation mode of the present invention relates to a method for manufacturing a Trench MOSFET. The finished structure of the Trench MOSFET transistor obtained is as Figure 1 shown, including an epitaxial silicon wafer with trenches (1), a gate oxide layer (2), a first gate polysilicon (3), a second gate polysilicon (4), a regenerated gate oxide layer (5), a body (6) and a source (7).

[0035] Example 1. Step 1, trench etching. In this step, first select an epitaxial silicon wafer with appropriate parameters. The epitaxial silicon wafer is obtained by growing a single-crystalline silicon layer on a silicon substrate. This silicon layer has better electrical properties and fewer defects. A hard mask layer is formed on the silicon epitaxial layer, and then photolithography and etching processes are carried out to accurately etch a trench with a depth of 0.6 μm. The formation of the trench is completed by forming a hard mask layer on the silicon epitaxial layer and then performing photolithography and etching processes. The formed structure is marked as (1) epitaxial silicon wafer with trenches in the accompanying drawings.

[0036] The depth and shape of the trench are crucial for the performance of the Trench MOSFET. If the trench is too shallow, the on-resistance of the device increases, while if the trench is too deep, the breakdown voltage of the device decreases. Accurately controlling the depth and shape of the trench is the key to manufacturing a high-performance Trench MOSFET.

[0037] Step 2, formation of the gate oxide layer. As Figure 2 shown, place the silicon wafer in a thermal oxidation device. At a temperature of 900 °C, a gate oxide layer (2) with a thickness of 50 nm is formed through a thermal oxidation process. This oxide layer covers the inner wall of the trench and the surface of the silicon wafer. The gate oxide layer is a key component in the MOSFET structure. As an insulating layer between the gate and the silicon substrate, it has an important impact on the electrical characteristics of the device.

[0038] The thickness and quality of the gate oxide layer have an important impact on the electrical characteristics of the device. An overly thin oxide layer leads to an increase in gate leakage current, while an overly thick oxide layer affects the switching speed of the device. Therefore, precisely controlling the thickness and quality of the gate oxide layer is the key to manufacturing high-performance Trench MOSFETs.

[0039] Step 3, first polysilicon filling. As Figure 3 shown, the first polysilicon filling (3) of the gate is carried out by CVD method, controlling the film formation temperature at 580 °C, and making the thickness of the first polysilicon film 2.5 times that of the subsequent second film formation. The purpose of this step is to provide sufficient material for the subsequent etching and filling processes, while reducing the voids in the polysilicon.

[0040] Polysilicon filling is a key step in the manufacturing process of Trench MOSFETs. As the gate material, the quality of polysilicon and the uniformity of filling have an important impact on the performance of the device. In the present invention, by controlling the film formation temperature and thickness ratio of polysilicon, the voids in polysilicon can be effectively reduced and the filling uniformity can be improved.

[0041] Step 4, first polysilicon etching. The polysilicon after the first filling is etched using semiconductor dry etching technology to remove the excess part and prepare for the subsequent processes. Dry etching provides high etching selectivity and precision, which helps to form an accurate polysilicon structure.

[0042] Dry etching is a commonly used etching technology in semiconductor manufacturing. It uses plasma or reactive gases to remove materials in a vacuum or low-pressure environment, with high selectivity and high precision. In the present invention, dry etching is used to remove the excess part after the first polysilicon filling and prepare for the subsequent polysilicon filling and CMP processes.

[0043] Step 5, second polysilicon filling. As Figure 4 shown, the second polysilicon filling (4) is carried out, and the film formation temperature is set at 530 °C. The purpose of this step is to further fill the trenches, reduce the voids, and prepare for the subsequent CMP process.

[0044] The second polysilicon filling is another key step in the manufacturing process of Trench MOSFETs. By precisely controlling the film formation temperature and thickness of the second polysilicon, the voids in polysilicon can be further reduced and the filling uniformity can be improved.

[0045] Step 6, chemical mechanical polishing. As Figure 4As shown, chemical mechanical polishing (CMP) is used to polish the polysilicon after the second filling so that it is flush with the substrate surface, ensuring the surface flatness. CMP is a key step to achieve global planarization and is crucial for the uniformity of subsequent processes and the performance of the device.

[0046] CMP is a planarization technology that combines chemical etching and mechanical polishing. Through the synergistic effect of chemical etching and mechanical polishing, global planarization of the polysilicon layer is achieved. In the present invention, CMP is used to make the polysilicon after the second filling flush with the substrate surface, providing a good foundation for subsequent process steps.

[0047] Step 7, formation of the regenerated oxide layer. As Figure 5 shown, thermal oxidation is carried out again to form a silicon oxide layer (5) with a thickness of 20 nm. The purpose of this step is to form a uniform oxide layer, providing a good foundation for subsequent ion implantation and annealing processes.

[0048] The regenerated oxide layer is another key component in the Trench MOSFET structure. It acts as an insulating layer between the gate and the polysilicon and has an important impact on the electrical characteristics of the device. In the present invention, by precisely controlling the thickness and quality of the regenerated oxide layer, the electrical characteristics of the device can be effectively improved.

[0049] Step 8, body (6) implantation and annealing treatment. The body (6) regions are formed on both sides of the trench by ion implantation, and then annealing treatment is carried out at a temperature of 1200 °C. Ion implantation provides precise doping control, while annealing treatment helps to activate the dopants and repair lattice defects. The body (6) region is a key component in the Trench MOSFET structure. It serves as the main body of the device and has an important impact on the electrical characteristics of the device. In the present invention, through ion implantation and annealing treatment, the doping concentration and distribution of the body (6) region can be precisely controlled, thereby improving the electrical characteristics of the device.

[0050] Step 9, source (7) ion implantation and annealing treatment. As Figure 5 shown, source ion implantation of the source (7) is carried out, and annealing treatment is carried out at a temperature of 1200 °C to complete the fabrication of the Trench MOSFET. The formation and annealing treatment of the source (7) are similar to those of the body (6) region, both aiming to ensure the correct distribution and activation of the dopants.

[0051] The source is another key component in the Trench MOSFET structure. It serves as the source part of the device and has an important impact on the electrical characteristics of the device. In the present invention, through ion implantation and annealing treatment, the doping concentration and distribution of the source region can be precisely controlled, thereby improving the electrical characteristics of the device.

[0052] Example 2. Step 1, trench etching. Select an epitaxial silicon wafer that meets the requirements and etch a trench (1) with a depth of 0.8 um. This step is similar to Example 1, but the trench depth is slightly different to meet the requirements of different device designs.

[0053] Step 2, gate oxide layer formation. Thermally oxidize at 850 °C to form a gate oxide layer (2) with a thickness of 40 nm. The temperature and thickness settings in this step are different from those in Example 1 to optimize the electrical characteristics of the device.

[0054] Step 3, first polysilicon filling and etching. The film formation temperature is 580 °C, and the thickness ratio is controlled. After dry etching, the excess part is removed. This step is similar to Example 1, but is fine-tuned according to specific process conditions and material characteristics.

[0055] Step 4, second polysilicon filling and polishing. Perform the second polysilicon filling (4) at a temperature of 530 °C. After CMP polishing, the polysilicon is flush with the substrate surface.

[0056] Step 5, regenerated oxide layer formation. Thermally oxidize to form an oxide layer (5) with a thickness of 15 nm.

[0057] Step 6, body (6) implantation and annealing treatment. After body implantation, anneal at 1100 °C.

[0058] Step 7, source (7) implantation and annealing treatment. After source (7) implantation, also anneal at 1100 °C.

[0059] Through the fabrication of the above different embodiments, the feasibility and stability of the fabrication method of the present invention under different parameter settings can be verified, effectively avoiding the problems of voids and etching penetration in the traditional process and improving the performance of the Trench MOSFET. At the same time, in actual production, the parameters of each step can be flexibly adjusted and optimized according to specific product requirements.

[0060] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A manufacturing method of a Trench MOSFET, comprising the following steps: A trench is etched in a silicon substrate with an epitaxial layer; A gate oxide layer is formed on the surface of the etched trench silicon wafer through a thermal oxidation process; the first filling of gate polysilicon is carried out by methods such as chemical vapor deposition (CVD); the gate polysilicon after the first filling is etched; the second filling of gate polysilicon is carried out; the polysilicon after the second filling is processed to be flush with the substrate surface by chemical mechanical polishing (CMP); a layer of oxide is formed on the polysilicon surface again through a thermal oxidation process; a body region is formed on both sides of the trench by ion implantation and annealing treatment is carried out; a source is formed in the corresponding region by ion implantation and annealing treatment is carried out.

2. The manufacturing method of the Trench MOSFET according to claim 1, wherein The substrate is a silicon substrate with a silicon epitaxial layer formed thereon, and the trench is formed inside the silicon epitaxial layer, and the depth is controlled to be 0.5 to 1.0 um. The steps of forming the trench in the epitaxial layer include forming a hard mask layer on the epitaxial layer and performing selective lithography on the mask layer to etch out the key region of the trench.

3. The manufacturing method of the Trench MOSFET according to claim 1, characterized in that, The gate oxide layer is realized through a thermal oxidation process, and the thickness is controlled to be 30 to 100 nm to ensure the electrical insulation performance and quality of the gate oxide layer. The process temperature is controlled to be 800 to 1200 °C to avoid thermal damage to the silicon substrate.

4. The manufacturing method of the Trench MOSFET according to claim 1, wherein, Among them, the thickness of the first polysilicon film formation is 2 - 3 times that of the second polysilicon film formation, reducing the voids of polysilicon in the subsequent etching process, thereby reducing the risk of etching through. The film formation temperature of the first polysilicon is controlled at 580 °C, and the film formation temperature of the second polysilicon is 530 °C. While controlling the thickness and surface characteristics of the polysilicon layer, the flatness with the substrate is ensured.

5. The manufacturing method of the Trench MOSFET according to claim 1, characterized in that, The etching of the first polysilicon adopts semiconductor dry etching, a process of removing materials by using plasma or reaction gas in a vacuum or low-pressure environment, providing high etching selectivity and accuracy, and is suitable for fine etching after the first polysilicon filling to remove excess polysilicon materials. The second polysilicon is processed by chemical mechanical polishing (CMP) to achieve global planarization of the polysilicon layer.

6. The manufacturing method of the Trench MOSFET according to claim 1, characterized in that, The oxide layer formed by thermal oxidation is mainly composed of silicon oxide, and the thickness is controlled to be 10 to 50 nm to ensure sufficient insulation performance and stable electrical characteristics, gate capacitance and threshold voltage.

7. The method for manufacturing a Trench MOSFET according to claim 1, wherein the body and the source are formed by ion implantation, and annealing treatment is carried out at a temperature of 1000 °C - 1500 °C after each implantation.

8. The method for manufacturing a Trench MOSFET according to claim 1, wherein the body and the source are located on both sides of the trench and are formed by ion implantation.

9. The method for manufacturing a Trench MOSFET according to claim 1, wherein the trench is formed by semiconductor dry etching, and the second polysilicon is made flush with the substrate by chemical mechanical polishing.

10. The manufacturing method of the Trench MOSFET according to claim 1, wherein the body implantation and annealing treatment are carried out at a temperature of 1000°C to 1500°C, and the source implantation and annealing treatment are also carried out at a temperature of 1000°C to 1500°C.

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