Fin field effect transistor and manufacturing method thereof
By setting a drift zone in a fin field effect transistor and using a heterojunction material design, the source-drain breakdown voltage and carrier mobility are improved, the problem of insufficient source-drain breakdown voltage in the prior art is solved, and higher power density and transistor density are achieved.
Patent Information
- Application Number
- CN202510499926.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-21
- Publication Date
- 2025-07-18
AI Technical Summary
The insufficient source-drain breakdown voltage of existing fin field effect transistors limits their application in BCD processes.
A drift region is set in a fin field effect transistor, and a compound semiconductor material is used as the drain region and the drift region, and an elemental semiconductor material is used as the body region to form a heterojunction, an gate structure covers the body region, and a three-dimensional conductive channel design is adopted.
The source-drain breakdown voltage is increased, the carrier mobility is improved, and the device's power density and transistor density are enhanced.
Smart Images
Figure CN120343950A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and particularly relates to a fin field-effect transistor and a manufacturing method thereof. Background Art
[0002] Modern power electronics technology requires the chip system to develop towards high frequency, integration, and intelligence. The BCD (Bipolar-CMOS-DMOS) process is the key to realizing this trend. The BCD process can fabricate bipolar, CMOS, and DMOS devices on the same chip, greatly reducing the chip area. Among them, DMOS is the key to improving the power and integration of BCD chips. Common DMOS devices include LDMOS and VDMOS devices. Regardless of the direction of the conduction current flow, the gate oxide layer of LDMOS and VDMOS processes is a planarized design similar to CMOS. To improve the current passing ability, it is necessary to increase the channel width, thereby occupying a larger wafer area and increasing the manufacturing cost.
[0003] The fin field-effect transistor of advanced processes changes the transistor conductive channel from a two-dimensional planar structure to a three-dimensional solid structure, improving the current passing ability. When the source-drain spacing is the same, the on-resistance of the device can be reduced by increasing the fin height and density, and there is no need to separately increase the fin width. However, the source-drain breakdown voltage of the fin field-effect transistor in related technologies is insufficient, restricting its application in the BCD process. Summary of the Invention
[0004] This application aims to at least solve one of the technical problems existing in the prior art. For this reason, this application provides a fin field-effect transistor and a manufacturing method thereof, which can improve the source-drain breakdown voltage and enhance the carrier mobility.
[0005] In a first aspect, this application provides a fin field-effect transistor, including:
[0006] A substrate;
[0007] A fin structure located on the substrate; the fin structure includes a first fin semiconductor structure and a second fin semiconductor structure connected along a first direction. The first fin semiconductor structure includes a drain region and a drift region, and the second fin semiconductor structure includes a body region and a source region. The drain region, the drift region, the body region, and the source region are sequentially connected along the first direction. Among them, the material of the first fin semiconductor structure includes a compound semiconductor material, the material of the second fin semiconductor structure includes an elemental semiconductor material, and the first fin semiconductor structure and the second fin semiconductor structure form a heterojunction;
[0008] The gate structure covers the upper surface of the body region and both side surfaces distributed along the second direction, and extends to the upper surface of the substrate, where the second direction is perpendicular to the first direction.
[0009] For the fin field-effect transistor according to the present application, a drift region is provided between the drain region and the body region to increase the source-drain breakdown voltage. The material of the first fin semiconductor structure includes a compound semiconductor material. The drain region and the drift region in the first fin semiconductor structure serve as a high-voltage withstand region, which can utilize the characteristics of high thermal conductivity, high bulk carrier mobility, and high breakdown voltage of the compound semiconductor material to increase the breakdown voltage of the device and improve the bulk carrier mobility. The material of the second fin semiconductor structure includes an elemental semiconductor material. A body region is provided in the second fin semiconductor structure, and a gate structure is provided at the body region to increase the channel mobility. Moreover, the fin field-effect transistor adopts a three-dimensional conductive channel design, enabling the device to have a higher power density and transistor density.
[0010] According to an embodiment of the present application, the compound semiconductor material includes any one of silicon carbide, gallium nitride, gallium oxide, and gallium arsenide, and the elemental semiconductor material includes any one of silicon and germanium.
[0011] According to an embodiment of the present application, the doping types of the drain region and the drift region are the same, and the doping concentration of the drain region is greater than that of the drift region.
[0012] According to an embodiment of the present application, the fin field-effect transistor further includes:
[0013] A field plate located on the upper surface of the drift region and both side surfaces distributed along the second direction, and extending to the upper surface of the substrate.
[0014] According to an embodiment of the present application, the gate structure includes a gate oxide layer and a gate;
[0015] The gate oxide layer covers the upper surface of the body region and both side surfaces distributed along the second direction, and extends to the upper surface of the substrate; the gate covers the gate oxide layer and extends to the upper surface of the substrate.
[0016] According to an embodiment of the present application, the gate also covers a part of the field plate.
[0017] According to an embodiment of the present application, the fin field-effect transistor further includes:
[0018] A protective layer covering the upper surface of the fin structure and both side surfaces distributed along the second direction, and covering the gate structure.
[0019] According to an embodiment of the present application, the fin field-effect transistor further includes:
[0020] An isolation structure is disposed on the substrate and is arranged around the peripheral side of the fin structure.
[0021] According to an embodiment of the present application, the fin field-effect transistor further includes:
[0022] A drain metal electrode is disposed on the drain region and is connected to the drain region;
[0023] A source metal electrode is disposed on the source region and is connected to the source region;
[0024] A gate metal electrode is disposed on the gate structure and is connected to the gate structure.
[0025] According to an embodiment of the present application, the substrate includes a substrate and a spacer layer;
[0026] The spacer layer is disposed on the substrate, the fin structure is disposed on the spacer layer, the gate structure covers the upper surface of the body region and the two side surfaces distributed along the second direction, and extends to the upper surface of the spacer layer.
[0027] In a second aspect, the present application provides a method for manufacturing a fin field-effect transistor, including:
[0028] Providing a substrate;
[0029] Forming a first fin semiconductor structure on the substrate, the first fin semiconductor structure including a drain region and a drift region connected along a first direction; wherein, the material of the first fin semiconductor structure includes a compound semiconductor material;
[0030] Forming a second fin semiconductor structure on the substrate and connected to the first fin semiconductor structure along the first direction, the second fin semiconductor structure including a body region and a source region connected along the first direction; wherein, the material of the second fin semiconductor structure includes an elemental semiconductor material, and the first fin semiconductor structure and the second fin semiconductor structure form a heterojunction;
[0031] Covering a gate structure on the upper surface of the body region and the two side surfaces distributed along the second direction, and the gate structure extends to the upper surface of the substrate, the second direction being perpendicular to the first direction.
[0032] According to an embodiment of the present application, the method further includes:
[0033] Covering a field plate on the upper surface of the drift region and the two side surfaces distributed along the second direction, and the field plate extends to the upper surface of the substrate.
[0034] According to an embodiment of the present application, the gate structure includes a gate oxide layer and a gate;
[0035] The gate structure covering the upper surface and two side surfaces distributed along the second direction of the body region includes:
[0036] Covering an initial gate oxide layer on the upper surface and two side surfaces distributed along the second direction of the body region, and the initial gate oxide layer extends to the upper surface of the substrate; the field plate and the initial gate oxide layer are formed simultaneously;
[0037] Performing a thinning process on the initial gate oxide layer to obtain the gate oxide layer;
[0038] Covering the gate on the gate oxide layer and part of the field plate, and the gate extends to the upper surface of the substrate.
[0039] One or more of the above technical solutions in the embodiments of the present application have at least one of the following technical effects:
[0040] A drift region is provided between the drain region and the body region to improve the source-drain breakdown voltage, and the material of the first fin-type semiconductor structure includes a compound semiconductor material. The drain region and the drift region in the first fin-type semiconductor structure serve as a high-voltage withstand region, which can utilize the characteristics of high thermal conductivity, high bulk carrier mobility, and high breakdown voltage of the compound semiconductor material to improve the breakdown voltage of the device and enhance the bulk carrier mobility. The material of the second fin-type semiconductor structure includes an elemental semiconductor material. A body region is provided in the second fin-type semiconductor structure, and a gate structure is provided at the body region to improve the channel mobility. Moreover, the fin field-effect transistor adopts a three-dimensional conductive channel design, making the device have a higher power density and transistor density.
[0041] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where:
[0043] Figure 1 is a schematic structural diagram of a fin field-effect transistor provided by an embodiment of the present application;
[0044] Figure 2 is one of the cross-sectional schematic diagrams of a fin field-effect transistor provided by an embodiment of the present application;
[0045] Figure 3 is another cross-sectional schematic diagram of a fin field-effect transistor provided by an embodiment of the present application;
[0046] Figure 4 It is the third cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiments of the present application;
[0047] Figure 5 It is a schematic flow chart of the manufacturing method of the fin field-effect transistor provided by the embodiments of the present application. Detailed implementation manners
[0048] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.
[0049] The fin field-effect transistor and its manufacturing method provided by the embodiments of the present application will be described below with reference to the accompanying drawings.
[0050] Figure 1 It is a schematic structural diagram of the fin field-effect transistor provided by the embodiments of the present application.
[0051] As Figure 1 shown, the fin field-effect transistor provided by the embodiments of the present application includes a substrate 1, a fin structure 2, and a gate structure 3.
[0052] The fin structure 2 is located on the substrate 1, that is, the fin structure 2 is located on one side of the substrate 1 along the thickness direction X. The fin structure 2 extends along a first direction Y on the substrate 1, and the first direction Y is perpendicular to the thickness direction X. The fin structure 2 constitutes a fin active region.
[0053] Combined with Figure 2 shown, Figure 2 is Figure 1 a cross-sectional schematic diagram at the dashed line AA' in. The fin structure 2 includes a first fin semiconductor structure 21 and a second fin semiconductor structure 22, and the first fin semiconductor structure 21 and the second fin semiconductor structure 22 are connected along the first direction Y. The heights of the first fin semiconductor structure 21 and the second fin semiconductor structure 22 along the thickness direction X may be the same, the widths of the first fin semiconductor structure 21 and the second fin semiconductor structure 22 along the second direction Z may be the same, and the lengths of the first fin semiconductor structure 21 and the second fin semiconductor structure 22 along the first direction Y may be the same or different. The second direction Z is perpendicular to the thickness direction X and the first direction Y respectively.
[0054] The materials of the first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 are both semiconductor materials, but the semiconductor materials of the first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 are different. The doping types of the first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 are opposite. For example, the first fin-type semiconductor structure 21 has a first doping type, and the first doping type can be P-type or N-type. The second fin-type semiconductor structure 22 has a second doping type, and the second doping type can be P-type or N-type. The first doping type is opposite to the second doping type. It should be noted that the fin field-effect transistor can be an N-type field-effect transistor or a P-type field-effect transistor. When the fin field-effect transistor is an N-type field-effect transistor, the first doping type is N-type and the second doping type is P-type; when the fin field-effect transistor is a P-type field-effect transistor, when the first doping type is P-type, the second doping type is N-type.
[0055] The first fin-type semiconductor structure 21 includes a drain region 211 and a drift region 212. The drain region 211 and the drift region 212 are connected along the first direction Y. The height of the drain region 211 along the thickness direction X and the height of the drift region 212 along the thickness direction X can be the same as the height of the first fin-type semiconductor structure 21 along the thickness direction X respectively. The width of the drain region 211 along the second direction Z and the width of the drift region 212 along the second direction Z can be the same as the width of the first fin-type semiconductor structure 21 along the second direction Z respectively. The sum of the lengths of the drain region 211 and the drift region 212 along the first direction Y can be the same as the length of the first fin-type semiconductor structure 21 along the first direction Y. The doping types of the drain region 211 and the drift region 212 are the same, and both have the first doping type.
[0056] The second fin-type semiconductor structure 22 includes a body region 221 and a source region 222. The body region 221 and the source region 222 are connected along the first direction Y, so that the drain region 211, the drift region 212, the body region 221, and the source region 222 are connected in sequence along the first direction Y. The height of the body region 221 along the thickness direction X and the height of the source region 222 along the thickness direction X can be the same as the height of the second fin-type semiconductor structure 22 along the thickness direction X respectively. The width of the body region 221 along the second direction Z and the width of the source region 222 along the second direction Z can be the same as the width of the second fin-type semiconductor structure 22 along the second direction Z respectively. The sum of the lengths of the body region 221 and the source region 222 along the first direction Y can be the same as the length of the second fin-type semiconductor structure 22 along the first direction Y. The doping types of the body region 221 and the source region 222 are the same, and both have the second doping type. Among them, the body region 221 is a heavily doped region and forms a channel. The doping concentration of the body region 211 can be 2E18 cm -3 . The source region 222 is a heavily doped region, and the doping concentration can be 1E20 cm -3 or 5E20 cm-3 。
[0057] The semiconductor materials of the first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 are different. The material of the first fin-type semiconductor structure 21 includes compound semiconductor materials, and the material of the second fin-type semiconductor structure 22 includes elemental semiconductor materials. The fin structure 2 combines the advantages of compound semiconductor materials and elemental semiconductor materials to improve the performance of the device. The first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 form a heterojunction to improve the reliability of the device.
[0058] Combined Figure 3 as shown Figure 3 is Figure 1 a cross-sectional schematic view at the dashed line BB' in the figure. The gate structure 3 covers the upper surface of the body region 221 (i.e., the surface of the body region 221 facing away from the substrate 1) and both side surfaces of the body region 211 distributed along the second direction Z, and extends to the upper surface of the substrate 1 (i.e., the surface of the substrate 1 close to the fin structure 2), that is, the gate structure 3 also covers a part of the upper surface of the substrate 1.
[0059] In this embodiment, a drift region 212 is added between the drain region 211 and the body region 221 to increase the breakdown voltage between the source and the drain. Moreover, the first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 use different semiconductor materials to form a heterojunction, improving the reliability of the device. The material of the first fin-type semiconductor structure 21 includes compound semiconductor materials. The drain region 211 and the drift region 212 in the first fin-type semiconductor structure 21 serve as high-voltage withstand regions, which can utilize the characteristics of high thermal conductivity, high bulk carrier mobility, and high breakdown voltage of the compound semiconductor materials, thereby increasing the breakdown voltage of the device and enhancing the bulk carrier mobility. The material of the second fin-type semiconductor structure 22 includes elemental semiconductor materials. A body region 221 is provided in the second fin-type semiconductor structure 22, and a gate structure 3 is provided at the body region 221 to increase the channel carrier mobility. Moreover, the fin field-effect transistor adopts a three-dimensional conductive channel design, making the device have a higher power density and transistor density.
[0060] In some embodiments, the compound semiconductor material includes any one of silicon carbide, gallium nitride, gallium oxide, and gallium arsenide, that is, the first fin-type semiconductor structure 21 may include any one of silicon carbide, gallium nitride, gallium oxide, and gallium arsenide. The elemental semiconductor material includes any one of silicon and germanium, that is, the material of the second fin-type semiconductor structure 22 includes any one of silicon and germanium. For example, the material of the first fin-type semiconductor structure 21 may include silicon carbide, and the material of the second fin-type semiconductor structure 22 may include silicon, such that the first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 form a heterojunction.
[0061] In this embodiment, the first fin-type semiconductor structure 21 is made of a compound semiconductor material such as silicon carbide or gallium nitride, which can utilize the characteristics of high thermal conductivity, high bulk carrier mobility, and high breakdown voltage of the compound semiconductor material. The drain region 211 and the drift region 212 are located in the first fin-type semiconductor structure 21, which can improve the breakdown voltage of the device and enhance the bulk carrier mobility. The second fin-type semiconductor structure 22 is made of an elemental semiconductor material such as silicon or germanium. The body region 221 is located in the second fin-type semiconductor structure 22, and the gate structure 3 covers the second fin-type semiconductor structure 22, which can improve the channel carrier mobility.
[0062] In some embodiments, the doping types of the drain region 211 and the drift region 212 are the same, and both the drain region 211 and the drift region 212 have the first doping type. The doping concentration of the drain region 211 is greater than that of the drift region 212. For example, the doping concentration of the drift region 212 is 1E17 cm -3 , and the doping concentration of the drain region 211 is 1.3E19 cm -3 or 3E19 cm -3 etc.
[0063] In this embodiment, the doping concentration of the drain region 211 is greater than that of the drift region 212, which can modulate the on-resistance of the drift region 212, thereby reducing the on-resistance of the device.
[0064] In some embodiments, as Figure 4 shown, Figure 4 is Figure 1 a cross-sectional schematic view at the dashed line CC' in
[0065] The fin field-effect transistor further includes a field plate 4. The field plate 4 is located on the upper surface of the drift region 212 (i.e., the surface of the drift region 212 facing away from the substrate 1) and on both side surfaces of the drift region 212 distributed along the second direction Z, and extends to the upper surface of the substrate 1, that is, the field plate 4 also covers a part of the upper surface of the substrate 1. The material of the field plate 4 may include silicon oxide, such as SiO2.
[0066] In some embodiments, as Figure 3As shown, the gate structure 3 includes a gate oxide layer 31 and a gate 32. The gate oxide layer 31 covers the upper surface of the body region 221 and both side surfaces of the body region 221 distributed along the second direction Z, and extends to the upper surface of the substrate 1, that is, the gate oxide layer 31 covers a part of the upper surface of the substrate 1. The extension length of the gate oxide layer 31 on the substrate 1 can be the same as the extension length of the field plate 4 on the substrate 1. The thickness of the gate oxide layer 31 is less than the thickness of the field plate 4. The material of the gate oxide layer 31 can be the same as the material of the field plate 4. Among them, the material of the gate oxide layer 31 can include dielectric materials such as SiO2, SiON, HfO2, etc.
[0067] The gate 32 covers the gate oxide layer 31 and extends to the upper surface of the substrate 1. The gate 32 can completely cover the gate oxide layer 31, and the extension length of the gate 32 on the substrate 1 can be greater than the extension length of the gate oxide layer 31 on the substrate 1, so that the gate 32 also covers a part of the upper surface of the substrate 1. The material of the gate 32 can include polysilicon or metal, etc. When the gate 32 is polysilicon, the doping concentration of the gate 32 can be 3E19 cm -3 .
[0068] In this embodiment, the material of the second fin-type semiconductor structure 22 includes elemental semiconductor materials such as silicon, and the gate oxide layer 31 (such as SiO2) covers the elemental semiconductor materials, improving the gate oxide reliability.
[0069] In some embodiments, the gate 32 also covers a part of the field plate 4.
[0070] Combined Figure 2 As shown, the gate 32 completely covers the gate oxide layer 31, covers a part of the field plate 4 (a part of the structure of the field plate 4 close to the gate oxide layer 31), and extends to the upper surface of the substrate 1. The extension length of the gate 32 on the substrate 1 can be greater than the extension length of the field plate 4 on the substrate 1, so that the gate 32 also covers a part of the upper surface of the substrate 1.
[0071] In this embodiment, the gate 32 also covers a part of the field plate 4, which can use the gate voltage to balance the high voltage at the drain end and improve the breakdown voltage characteristics of the device.
[0072] In some embodiments, as Figures 2 to 4 shown, the fin field effect transistor further includes a protective layer 5. The protective layer 5 covers the upper surface of the fin structure 2 (that is, the surface of the fin structure 2 facing away from the substrate 1) and both side surfaces of the fin structure 2 distributed along the second direction Z, and covers the gate structure 3 to protect the fin structure 2 and the gate structure 3.
[0073] When the fin field effect transistor further includes a field plate 4, the protective layer 5 also covers the field plate 4 to protect the field plate 4. Among them, the material of the protective layer 5 can include Si3N4, etc.
[0074] In some embodiments, Figure 3 and Figure 4 As shown, the fin field effect transistor also includes an isolation structure 6. The isolation structure 6 is located on the substrate 1 and is arranged around the circumference of the fin structure 2. The isolation structure 6 is used to isolate the fin field effect transistor from other transistors. The material of the isolation structure 6 may include BPSG (Boro-Phospho-Silicate Glass).
[0075] In some embodiments, the fin field effect transistor further includes a drain metal electrode 71, a source metal electrode 72, and a gate metal electrode 73. The drain metal electrode 71, the source metal electrode 72, and the gate metal electrode 73 may be located on the same side of the fin structure 2 (i.e., the side of the fin structure 2 facing away from the substrate 1). The drain metal electrode 71 is located on the drain region 211 and connected to the drain region 211. The source metal electrode 72 is located on the source region 222 and connected to the source region 222. The gate metal electrode 73 is located on the gate structure 3 and connected to the gate structure 3. Among them, the gate metal electrode 73 is located on the gate 32 in the gate structure 3 and connected to the gate 32.
[0076] In the case where the fin field effect transistor further includes a protective layer 5, the drain metal electrode 71, the source metal electrode 72 and the gate metal electrode 73 are respectively located on the side of the protective layer 5 away from the substrate 1. The drain metal electrode 71 penetrates the protective layer 5 and is connected to the drain region 211. The source metal electrode 72 penetrates the protective layer 5 and is connected to the source region 222. The gate metal electrode 73 penetrates the protective layer 5 and is connected to the gate 32 in the gate structure 3.
[0077] The materials of the drain metal electrode 71 , the source metal electrode 72 and the gate metal electrode 73 may all include metal materials such as tungsten.
[0078] In some embodiments, the base 1 includes a substrate 11, the fin structure 2 may be located on the substrate 11, and the gate structure 3 may cover the upper surface of the body region 221 and the two side surfaces of the body region 221 distributed along the second direction Z, and extend to the upper surface of the substrate 11 (the surface of the substrate 11 close to the fin structure 2). The gate oxide layer 31 in the gate structure 3 may cover the upper surface of the body region 221 and the two side surfaces of the body region 221 distributed along the second direction Z, and extend to the upper surface of the substrate 11. The gate 32 in the gate structure 3 may cover the gate oxide layer 31 and extend to the upper surface of the substrate 11.
[0079] The field plate 4 can cover the upper surface of the drift region 212 and both side surfaces of the drift region 212 distributed in the second direction Z, and extend to the upper surface of the substrate 11. The isolation structure 6 can be located on the substrate 11 and be disposed around the peripheral side of the fin structure 2.
[0080] Among them, the substrate 11 can be a silicon substrate or a silicon-on-insulator (SOI), or can also be a semiconductor substrate including other elements. The substrate 11 has a second doping type, that is, the doping type of the substrate 11 is opposite to that of the first fin semiconductor structure 21 and the same as that of the second fin semiconductor structure 22.
[0081] In some embodiments, the substrate 1 includes a substrate 11 and a spacer layer 12. The spacer layer 12 is located on the substrate 11, the fin structure 2 is located on the spacer layer 12, and the gate structure 3 covers the upper surface of the body region 221 and both side surfaces of the body region 221 distributed in the second direction Z, and extends to the upper surface of the spacer layer 12 (the surface of the spacer layer 12 close to the fin semiconductor structure side). Among them, the gate oxide layer 31 in the gate structure 3 can cover the upper surface of the body region 221 and both side surfaces of the body region 221 distributed in the second direction Z, and extend to the upper surface of the spacer layer 12. The gate 32 in the gate structure 3 can cover the gate oxide layer 31 and extend to the upper surface of the spacer layer 12.
[0082] The field plate 4 can cover the upper surface of the drift region 212 and both side surfaces of the drift region 212 distributed in the second direction Z, and extend to the upper surface of the spacer layer 12. The isolation structure 6 can be located on the spacer layer 12 and be disposed around the peripheral side of the fin structure 2. Among them, the material of the spacer layer 12 can include silicon oxide, etc.
[0083] According to the fin field effect transistor provided by the embodiments of the present application, a drift region 212 is arranged between the drain region 211 and the body region 221 to improve the source-drain breakdown voltage, and the material of the first fin semiconductor structure 21 includes a compound semiconductor material. The drain region 211 and the drift region 212 in the first fin semiconductor structure 21 serve as a high-voltage withstand region, which can exert the characteristics of high thermal conductivity, high bulk carrier mobility, and high breakdown voltage of the compound semiconductor material, improve the breakdown voltage of the device, and enhance the bulk carrier mobility. The material of the second fin semiconductor structure 22 includes an elemental semiconductor material. A body region 221 is arranged in the second fin semiconductor structure 22, and a gate structure 3 is arranged at the body region 221 to improve the channel mobility. Moreover, the fin field effect transistor adopts a three-dimensional conductive channel design, making the device have a higher power density and transistor density.
[0084] Correspondingly, the embodiments of the present application also provide a manufacturing method of a fin field effect transistor, which can manufacture the fin field effect transistor in the above embodiments.
[0085] Such as Figure 5As shown, the manufacturing method of the fin field-effect transistor provided by the embodiment of the present application includes steps 110 to 140.
[0086] Step 110: Provide a substrate.
[0087] In some embodiments, the substrate includes a substrate.
[0088] In some embodiments, as Figure 1 shown, the substrate 1 includes a substrate 11 and a spacer layer 12, and the spacer layer 12 is located on the substrate 11. For example, a thin film deposition process is used to form the spacer layer 12 on the substrate 11.
[0089] Among them, the substrate 11 can be a silicon substrate or silicon on insulator (SOI), or a semiconductor substrate including other elements. The substrate 11 has a second doping type, and the second doping type can be P-type or N-type.
[0090] Step 120: Form a first fin semiconductor structure on the substrate. The first fin semiconductor structure includes a drain region and a drift region connected along a first direction; wherein, the material of the first fin semiconductor structure includes a compound semiconductor material.
[0091] Combined with Figure 2 shown, first epitaxially grow a first fin semiconductor structure 21 on the substrate 1 as the matrix material of the drain region 211 and the drift region 212, and the drain region 211 and the drift region 212 are connected along the first direction Z. Among them, the doping concentration of the first fin semiconductor structure 21 can be 1E17 cm -3 . The first fin semiconductor structure 21 has a first doping type, and the first doping type can be P-type or N-type. The doping types of the drain region 211 and the drift region 212 are the same and both have the first doping type. The first doping type is opposite to the second doping type.
[0092] It should be noted that the fin field-effect transistor can be an N-type field-effect transistor or a P-type field-effect transistor. In the case where the fin field-effect transistor is an N-type field-effect transistor, the first doping type is N-type and the second doping type is P-type; in the case where the fin field-effect transistor is a P-type field-effect transistor, when the first doping type is P-type, the second doping type is N-type.
[0093] Then, through ion implantation (Implantation, IMP), the drain region 211 of the first fin semiconductor structure 21 is heavily doped. The doping concentration of the drain region 211 can be 1.3E19 cm -3 . The doping concentration of the drain region 211 is greater than that of the drift region 212, and the on-resistance of the drift region 212 can be modulated, thereby reducing the on-resistance of the device.
[0094] The material of the first fin-type semiconductor structure 21 includes a compound semiconductor material. The drain region 211 and the drift region 212 in the first fin-type semiconductor structure 21 serve as high-voltage withstand regions, which can utilize the characteristics of high thermal conductivity, high bulk carrier mobility, and high breakdown voltage of the compound semiconductor material, thereby improving the breakdown voltage of the device and enhancing the bulk carrier mobility.
[0095] In some embodiments, the compound semiconductor material includes any one of silicon carbide, gallium nitride, gallium oxide, and gallium arsenide, that is, the material of the first fin-type semiconductor structure 21 can include any one of silicon carbide, gallium nitride, gallium oxide, and gallium arsenide.
[0096] Step 130: Form a second fin-type semiconductor structure connected to the first fin-type semiconductor structure along a first direction on a substrate. The second fin-type semiconductor structure includes a body region and a source region connected along the first direction; wherein, the material of the second fin-type semiconductor structure includes an elemental semiconductor material, and the first fin-type semiconductor structure and the second fin-type semiconductor structure form a heterojunction.
[0097] Epitaxially grow the second fin-type semiconductor structure 22 on the substrate 1 as the matrix material of the body region 221 and the source region 222. The body region 221 and the source region 222 are connected along the first direction Z. The first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 are connected along the first direction Z, so that the drain region 211, the drift region 212, the body region 221, and the source region 222 are sequentially connected along the first direction Y. The second fin-type semiconductor structure 22 has a second doping type. The doping types of the body region 221 and the source region 222 are the same and both have the second doping type.
[0098] Then, through an ion implantation process, the body region 221 is heavily doped to form a channel in the body region 211. The doping concentration of the body region 211 can be 2E18 cm -3 .
[0099] The material of the second fin-type semiconductor structure includes an elemental semiconductor material. By providing the body region 221 in the second fin-type semiconductor structure 22, the carrier mobility of the channel is improved.
[0100] In some embodiments, the elemental semiconductor material includes any one of silicon and germanium, that is, the material of the second fin-type semiconductor structure 22 includes any one of silicon and germanium.
[0101] The semiconductor materials of the first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 are different. The first fin-type semiconductor structure 21 and the second fin-type semiconductor structure 22 form a heterojunction, which improves the reliability of the device.
[0102] Step 140: Cover the upper surface of the body region and the two side surfaces distributed along the second direction with a gate structure, and the gate structure extends to the upper surface of the substrate, where the second direction is perpendicular to the first direction.
[0103] Combined Figure 1 and Figure 3 As shown, the gate structure 3 covers the upper surface of the body region 221 (i.e., the surface of the body region 221 facing away from the substrate 1) and the two side surfaces of the body region 211 distributed along the second direction Z, and extends to the upper surface of the substrate 1 (i.e., the surface of the substrate 1 close to the fin structure 2), that is, the gate structure 3 also covers a part of the upper surface of the substrate 1.
[0104] In some embodiments, the manufacturing method of the fin field-effect transistor further includes:
[0105] Cover the upper surface of the drift region and the two side surfaces distributed along the second direction with a field plate, and the field plate extends to the upper surface of the substrate.
[0106] As Figure 2 and Figure 4 shown, by using a thin film deposition process, a field plate 4 is formed on the upper surface of the drift region 212 and the two side surfaces of the drift region 212 distributed along the second direction Z, and the field plate 4 also extends to the upper surface of the substrate 1. Among them, the material of the field plate 4 may include silicon oxide, such as SiO2.
[0107] In this embodiment, setting the field plate 4 at the drift region 212 can reduce the surface electric field and further improve the source-drain breakdown voltage.
[0108] In some embodiments, as Figure 2 and Figure 3 shown, the gate structure 3 includes a gate oxide layer 31 and a gate 32.
[0109] Covering the upper surface of the body region and the two side surfaces distributed along the second direction with a gate structure in Step 140 includes:
[0110] Cover the upper surface of the body region and the two side surfaces distributed along the second direction with an initial gate oxide layer, and the initial gate oxide layer extends to the upper surface of the substrate; the field plate and the initial gate oxide layer are formed simultaneously;
[0111] Thin the initial gate oxide layer to obtain the gate oxide layer;
[0112] Cover the gate on the gate oxide layer and a part of the field plate, and the gate extends to the upper surface of the substrate.
[0113] While forming the field plate 4, an initial gate oxide layer is formed. The initial gate oxide layer covers the upper surface of the body region 221 and the two side surfaces of the body region 221 distributed along the second direction Z, and extends to the upper surface of the substrate 1.
[0114] Then, the initial gate oxide layer is etched to thin the initial gate oxide layer, and the gate oxide layer 32 is obtained. The material of the gate oxide layer 31 can be the same as that of the field plate 4. For example, the material of the gate oxide layer 31 can include SiO2. The material of the gate oxide layer 31 can also include dielectric materials such as SiON and HfO2. The material of the second fin-type semiconductor structure 22 includes elemental semiconductor materials such as silicon. The gate oxide layer 31 (such as SiO2) covers the elemental semiconductor material to improve the gate oxide reliability.
[0115] Then, a gate 32 is formed on the gate oxide layer 31 by a thin film deposition process. The gate 32 covers the gate oxide layer 31 and extends to the upper surface of the substrate 1. The material of the gate 32 can include polysilicon or metal, etc. It should be noted that when the gate 32 is polysilicon, after the gate 32 is formed, the gate 32 also needs to be heavily doped. The doping concentration of the heavily doped gate 32 can be 3E19 cm -3 .
[0116] In some embodiments, the gate 32 also covers a part of the field plate 4. The gate 32 can completely cover the gate oxide layer 31, cover a part of the field plate 4 (a part of the structure of the field plate 4 close to the gate oxide layer 31), and extend to the upper surface of the substrate 1 to improve the breakdown voltage characteristics of the device.
[0117] In some embodiments, the method for manufacturing the fin field effect transistor further includes:
[0118] Form a protective layer that covers the upper surface of the fin structure and both side surfaces of the fin structure distributed along the second direction, and covers the gate structure.
[0119] By using a thin film deposition process and an etching process, a protective layer 5 is formed on the upper surface of the fin structure 2, both side surfaces of the fin structure 2 distributed along the second direction Z, and the surface of the gate structure 3 to protect the fin structure 2 and the gate structure 3. Among them, the material of the protective layer 5 can include Si3N4, etc.
[0120] It should be noted that openings need to be reserved in the protective layer 5 to expose the drain region 211, the source region 222, and the gate structure 3.
[0121] In some embodiments, the method for manufacturing the fin field effect transistor further includes:
[0122] Heavily dope the source region 222.
[0123] By using an ion implantation process, the source region 222 is heavily doped. The doping concentration of the heavily doped source region 222 can be 5E19 cm -3 .
[0124] In some embodiments, the method for manufacturing the fin field-effect transistor further includes:
[0125] Form a drain metal electrode connected to the drain region on the drain region, form a source metal electrode connected to the source region on the source region, and form a gate metal electrode connected to the gate structure on the gate structure.
[0126] Adopt a thin-film deposition process to respectively form a drain metal electrode 71 connected to the drain region 211, a source metal electrode 72 connected to the source region 222, and a gate metal electrode 73 connected to the gate 32 in the gate structure 3 on the drain region 211, the source region 222, and the gate structure 3. Among them, the materials of the drain metal electrode 71, the source metal electrode 72, and the gate metal electrode 73 can all include metal materials such as tungsten.
[0127] In some embodiments, the method for manufacturing the fin field-effect transistor further includes:
[0128] Form an isolation structure on the substrate, and the isolation structure is disposed around the peripheral side of the fin structure.
[0129] Adopt a thin-film deposition process to form an isolation structure 6 disposed around the peripheral side of the fin structure 2 on the substrate 1. The isolation structure 6 is used to isolate the fin field-effect transistor from other transistors. Among them, the material of the isolation structure 6 can include BPSG.
[0130] It should be noted that the subsequent back-end metal interconnection process can be continued, which will not be elaborated in detail here.
[0131] According to the method for manufacturing the fin field-effect transistor provided by the embodiments of the present application, a drift region 212 is provided between the drain region 211 and the body region 221 to improve the source-drain breakdown voltage, and the material of the first fin semiconductor structure 21 includes a compound semiconductor material. The drain region 211 and the drift region 212 in the first fin semiconductor structure 21 serve as a high-voltage withstand region, which can utilize the characteristics of the compound semiconductor material such as high thermal conductivity, high bulk carrier mobility, and high breakdown voltage to improve the breakdown voltage of the device and enhance the bulk carrier mobility. The material of the second fin semiconductor structure 22 includes an elemental semiconductor material. A body region 221 is provided in the second fin semiconductor structure 22, and a gate structure 3 is provided at the body region 221 to improve the channel mobility. Moreover, the fin field-effect transistor adopts a three-dimensional conductive channel design, enabling the device to have a higher power density and transistor density.
[0132] The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same type, and the number of objects is not limited. For example, the first object can be one or more.
[0133] In the description of this application, "a plurality" means two or more.
[0134] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0135] Although the embodiments of this application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of this application, and the scope of this application is defined by the claims and their equivalents.
Claims
1. A fin field-effect transistor, characterized in that Comprising: A substrate; A fin structure located on the substrate; The fin structure includes a first fin semiconductor structure and a second fin semiconductor structure connected along a first direction. The first fin semiconductor structure includes a drain region and a drift region, and the second fin semiconductor structure includes a body region and a source region. The drain region, the drift region, the body region, and the source region are sequentially connected along the first direction. Among them, the material of the first fin semiconductor structure includes a compound semiconductor material, the material of the second fin semiconductor structure includes an elemental semiconductor material, and the first fin semiconductor structure and the second fin semiconductor structure form a heterojunction; A gate structure covering the upper surface and two side surfaces distributed along a second direction of the body region and extending to the upper surface of the substrate. The second direction is perpendicular to the first direction.
2. The fin field effect transistor according to claim 1, wherein The compound semiconductor material includes any one of silicon carbide, gallium nitride, gallium oxide, and gallium arsenide, and the elemental semiconductor material includes any one of silicon and germanium.
3. The fin field-effect transistor according to claim 1, wherein The doping types of the drain region and the drift region are the same, and the doping concentration of the drain region is greater than that of the drift region.
4. The fin field effect transistor according to claim 1, characterized in that, The fin field effect transistor further includes: A field plate located on the upper surface and two side surfaces distributed along the second direction of the drift region and extending to the upper surface of the substrate.
5. The fin field effect transistor according to claim 4, characterized in that, The gate structure includes a gate oxide layer and a gate; The gate oxide layer covers the upper surface and two side surfaces distributed along the second direction of the body region and extends to the upper surface of the substrate; the gate covers the gate oxide layer and extends to the upper surface of the substrate.
6. The fin field effect transistor according to claim 5, characterized in that, The gate also covers a part of the field plate.
7. The fin field-effect transistor according to claim 1, wherein The fin field effect transistor further includes: A protective layer covering the upper surface and two side surfaces distributed along the second direction of the fin structure and covering the gate structure.
8. The fin field effect transistor according to claim 1, characterized in that, The fin field effect transistor further includes: An isolation structure located on the substrate and disposed around the peripheral side of the fin structure.
9. The fin field effect transistor according to claim 1, wherein The fin field effect transistor further includes: A drain metal electrode located on the drain region and connected to the drain region; A source metal electrode located on the source region and connected to the source region; A gate metal electrode located on the gate structure and connected to the gate structure.
10. The fin field effect transistor according to any one of claims 1-9, characterized in that The substrate includes a substrate and a spacer layer; The spacer layer is located on the substrate, the fin structure is located on the spacer layer, the gate structure covers the upper surface and two side surfaces distributed along the second direction of the body region and extends to the upper surface of the spacer layer.
11. A manufacturing method of a fin field effect transistor, characterized in that Comprising: Providing a substrate; Forming a first fin semiconductor structure on the substrate. The first fin semiconductor structure includes a drain region and a drift region connected along a first direction. Among them, the material of the first fin semiconductor structure includes a compound semiconductor material; Form a second fin-type semiconductor structure on the substrate, which is connected to the first fin-type semiconductor structure in a first direction. The second fin-type semiconductor structure includes a body region and a source region connected in the first direction. Among them, the material of the second fin-type semiconductor structure includes elemental semiconductor material, and a heterojunction is formed between the first fin-type semiconductor structure and the second fin-type semiconductor structure. Cover a gate structure on the upper surface and two side surfaces distributed in a second direction of the body region, and the gate structure extends to the upper surface of the substrate. The second direction is perpendicular to the first direction.
12. The manufacturing method of the fin field-effect transistor according to claim 11, wherein The method further includes: Cover field plates on the upper surface and two side surfaces distributed in the second direction of the drift region, and the field plates extend to the upper surface of the substrate.
13. The manufacturing method of the fin field effect transistor according to claim 12, characterized in that, The gate structure includes a gate oxide layer and a gate. The covering the gate structure on the upper surface and two side surfaces distributed in the second direction of the body region includes: Cover an initial gate oxide layer on the upper surface and two side surfaces distributed in the second direction of the body region, and the initial gate oxide layer extends to the upper surface of the substrate. The field plates and the initial gate oxide layer are formed simultaneously. Thin the initial gate oxide layer to obtain the gate oxide layer. Cover the gate on the gate oxide layer and part of the field plates, and the gate extends to the upper surface of the substrate.