Image sensing device

Abstract

An image sensing apparatus includes: a transmission signal output node coupled to output an electrical signal; a pull-up driver configured to pull up a voltage level of the transfer signal output node to a first charge pump voltage based on a pull-up control signal applied to the pull-up driver; a first pull-down driver configured to pull down a voltage level of the transfer signal output node at a first pull-down speed based on a first pull-down control signal applied to the first pull-down driver; a switching circuit configured to selectively connect the transmission signal output node to the pull-up driver or the first pull-down driver based on a switching control signal applied to the switching circuit; and a second pull-down driver coupled to the transmission signal output node and configured to pull down the voltage level of the transmission signal output node at a second pull-down speed different from the first pull-down speed based on a second pull-down control signal.

Description

Technical Field

[0001] The technologies and implementations disclosed in this patent document generally relate to image sensing devices including transfer transistors of pixels. Background Art

[0002] Image sensors are used in electronic devices to convert optical images into electrical signals. With the recent development of the automotive, medical, computer, and communication industries, the demand for highly integrated and high-performance image sensors has increased rapidly in various electronic devices such as digital cameras, portable video cameras, personal communication systems (PCS), video game consoles, surveillance cameras, medical micro cameras, robots, etc. Summary of the Invention

[0003] Various embodiments of the disclosed technologies relate to image sensing devices capable of improving the overflow characteristics that may occur in the transfer transistors of pixels.

[0004] According to an embodiment of the disclosed technology, an image sensing device may include: a transfer signal output node coupled to output an electrical signal; a pull-up driver configured to pull up the voltage level of the transfer signal output node to a first charge pump voltage based on a pull-up control signal applied to the pull-up driver; a first pull-down driver configured to pull down the voltage level of the transfer signal output node at a first pull-down speed based on a first pull-down control signal applied to the first pull-down driver; a switching circuit configured to selectively connect the transfer signal output node to the pull-up driver or the first pull-down driver based on a switching control signal applied to the switching circuit; and a second pull-down driver coupled to the transfer signal output node and configured to pull down the voltage level of the transfer signal output node at a second pull-down speed different from the first pull-down speed based on a second pull-down control signal.

[0005] According to another embodiment of the disclosed technology, an image sensing device may include: a photoelectric conversion element configured to generate photo charges by photoelectrically converting incident light; a floating diffusion node configured to receive and accumulate photo charges from the photoelectric conversion element; a transfer transistor coupled to the photoelectric conversion element and the floating diffusion node and configured to transfer the photo charges generated by the photoelectric conversion element to the floating diffusion node based on a transfer signal; and a row driver configured to generate the transfer signal and provide the transfer signal to the transfer transistor, wherein the row driver is configured to change the pull-down speed at which the transfer signal is pulled down from a first charge pump voltage to a second charge pump voltage.

[0006] It should be understood that both the above general description and the following detailed description of the disclosed technologies are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features and advantageous aspects of the disclosed technology will become apparent when considered in conjunction with the following detailed description with reference to the accompanying drawings.

[0008] Figure 1 FIG. is a schematic diagram illustrating an exemplary structure of an image sensing device based on some implementations of the disclosed technology.

[0009] Figure 2 FIG. is an illustration of some implementations based on the disclosed technology Figure 1 circuit diagram of an exemplary structure of a unit pixel formed in the pixel array shown.

[0010] Figure 3 FIG. is an illustration of some implementations based on the disclosed technology for enabling Figure 1 circuit diagram of an exemplary structure of a circuit for the row driver shown to generate a transmission signal.

[0011] Figure 4 FIG. is an illustration of some implementations based on the disclosed technology applied to Figure 1 timing diagram of an example of a control signal for the row driver shown.

[0012] Figure 5 FIG. is an example of a graph illustrating how the falling slope changes when the transmission signal is pulled down based on some implementations of the disclosed technology.

[0013] Figure 6 FIG. is an illustration of some implementations based on the disclosed technology for enabling Figure 1 circuit diagram of another exemplary structure of a circuit for the row driver shown to generate / output a transmission signal. DETAILED DESCRIPTION

[0014] This patent document provides implementations and examples of an image sensing device that can be used to fundamentally solve one or more technical or engineering problems and alleviate limitations or drawbacks encountered in some other image sensing devices. Some implementations of the disclosed technology present examples of an image sensing device that can improve spillback characteristics that may occur in the transfer transistors of pixels. Recognizing the above problems, the disclosed technology provides various implementations of an image sensing device that can improve spillback characteristics that may occur in the transfer transistors of pixels.

[0015] Reference will now be made in detail to some embodiments, examples of which are illustrated in the accompanying drawings. As far as possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. In the following description, detailed descriptions of related known structures or functions incorporated herein will be omitted to avoid obscuring the subject matter.

[0016] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the disclosed technology.

[0017] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0018] Referring to Figure 1 , the image sensing device may include a pixel array 100, a row driver 200, a correlated double sampler (CDS) 300, an analog-to-digital converter (ADC) 400, an output buffer 500, a column driver 600, and a timing controller 700. Figure 1 The components of the illustrated image sensing device are discussed only as examples, and this patent document covers many other variations, substitutions, modifications, changes, and alterations. In this patent document, the term "pixel" may be used to represent an image sensing pixel configured to detect incident light to generate an electrical signal carrying an image in the incident light.

[0019] The pixel array 100 may include a plurality of unit pixels (PX) arranged in rows and columns. In one example, the plurality of unit pixels (PX) may be arranged in a two-dimensional (2D) pixel array including rows and columns. The plurality of unit pixels (PX) may convert incident light into an electrical signal (pixel signal) on a unit pixel basis and may output the electrical signal (pixel signal). Each unit pixel (PX) may include a photoelectric conversion element that generates photo charges by photoelectrically converting incident light. The photoelectric conversion element may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0020] The pixel array 100 may receive drive signals (e.g., row selection signals, reset signals, transmit (or transfer) signals, etc.) from the row driver 200. Once the drive signals are received, the unit pixels may be activated to perform operations corresponding to the row selection signals, reset signals, and transmit signals.

[0021] The row driver 200 can activate the pixel array 100 based on control signals provided by a controller circuit such as the timing controller 700 to perform certain operations on unit pixels in corresponding rows. In some implementations, the row driver 200 can selectively arrange one or more unit pixels in one or more rows of the pixel array 100. The row driver 200 can generate row selection signals to select one or more rows from among a plurality of rows.

[0022] The row driver 200 can operate the unit pixels by providing a reset signal and a transmission signal to the unit pixels of the selected row. When generating the transmission signal, the row driver 200 can gradually change the falling slope (pull-down speed) of the transmission signal while the transmission signal is being pulled down. As a result, the row driver 200 can improve the feedthrough characteristics that may occur in the transmission transistor. The pixel signals generated by the unit pixels arranged in the selected row can be output to the correlated double sampler (CDS) 300.

[0023] The correlated double sampler (CDS) 300 can use correlated double sampling to remove undesired offset values of the unit pixels. In one example, the correlated double sampler (CDS) 300 can remove the undesired offset values of the unit pixels by comparing the output voltages of the pixel signals (of the unit pixels) obtained before and after the optical charges generated by incident light are accumulated in the sensing node (i.e., the floating diffusion (FD) node). As a result, the CDS 300 can obtain pixel signals generated only by incident light without introducing noise. In some implementations, once receiving a clock signal from the timing controller 700, the CDS 300 can sequentially sample and hold the voltage levels of the reference signals and pixel signals provided to each of a plurality of column lines from the pixel array 100. That is, the CDS 300 can sample and hold the voltage levels of the reference signals and pixel signals corresponding to each column line of the pixel array 100. In some implementations, the CDS 300 can transmit the reference signals and pixel signals of each column line to the ADC 400 as correlated double sampling (CDS) signals based on control signals from the timing controller 700.

[0024] The ADC 400 is used to convert the analog CDS signal received from the CDS 300 into a digital signal. In some implementations, the ADC 400 can be implemented as a ramp comparison type ADC. The analog-to-digital converter (ADC) 400 can compare the ramp signal received from the timing controller 700 with the CDS signal received from the CDS 300, and thereby can output a comparison signal indicating the comparison result between the ramp signal and the CDS signal. The analog-to-digital converter (ADC) 400 can count the level transition time of the comparison signal in response to the ramp signal received from the timing controller 700, and can output a count value indicating the counted level transition time to the output buffer 500.

[0025] The output buffer 500 can temporarily store the column-based image data provided from the ADC 400 based on the control signal of the timing controller 700.

[0026] Once receiving the control signal from the timing controller 700, the column driver 600 can select the column of the output buffer 500 and sequentially output the image data temporarily stored in the selected column of the output buffer 500. In some implementations, once receiving the address signal from the timing controller 700, the column driver 600 can generate a column selection signal based on the address signal and can use the column selection signal to select the column of the output buffer 500.

[0027] The timing controller 700 can generate signals for controlling the operations of the row driver 200, the ADC 400, the output buffer 500, and the column driver 600. The timing controller 700 can provide the clock signal required for the operations of the respective components of the image sensing device, the control signal for timing control, and the address signal for selecting a row or a column to the row driver 200, the column driver 600, the ADC 400, and the output buffer 500.

[0028] In some implementations, the timing controller 700 can include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0029] Figure 2 is a circuit diagram exemplifying the example structure of the unit pixel (PX) formed in the Figure 1 shown pixel array 100.

[0030] Referring to Figure 2 , the unit pixel (PX) of the pixel array 110 can include a photoelectric conversion element PD, a transfer transistor T1, a reset transistor T2, a driving transistor T3, and a selection transistor T4.

[0031] The photoelectric conversion element PD can generate and accumulate photo - charges corresponding to incident light. For example, the photoelectric conversion element PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof, but is not limited thereto.

[0032] The transfer transistor T1 can transfer the photo - charges accumulated in the photoelectric conversion element PD to the floating diffusion node FD based on the transfer signal TX. For example, the transfer transistor T1 can include an NMOS transistor that receives the transfer signal TX through its gate terminal and is connected to the floating diffusion node FD through its source / drain terminal.

[0033] The floating diffusion node FD can receive and accumulate the photo - charges generated by the photoelectric conversion element PD. The driving transistor T3 can be controlled based on the amount of photo - charges accumulated in the floating diffusion node FD.

[0034] The reset transistor T2 can periodically reset the floating diffusion node FD. When the reset signal RX is enabled and the reset transistor T2 is turned on, the first pixel power supply voltage (VDDPX) is transferred to the floating diffusion node FD. Thus, the photo - charges accumulated in the floating diffusion node FD can be discharged, enabling the floating diffusion node FD to be reset. For example, the reset transistor T2 can include an NMOS transistor that receives the reset signal RX through its gate terminal and is connected to the floating diffusion node FD and the first pixel power supply voltage (VDDPX) node.

[0035] The driving transistor T3 can be a source - follower buffer amplifier or include a source - follower buffer amplifier that generates a source - drain current proportional to the charge amount of the floating diffusion node FD. The driving transistor T3 can amplify the potential change at the floating diffusion node FD, and the amplified signal can be output to the output line (column line) through the selection transistor T4. For example, the driving transistor T3 can include an NMOS transistor that is connected to the floating diffusion node (FD) through the gate terminal of the NMOS transistor and is connected to the first pixel power supply voltage (VDDPX) node and the selection transistor T4.

[0036] The selection transistor T4 can output the pixel signal (PXOUT) to the column line based on the row selection signal SX. For example, the selection transistor T4 can include an NMOS transistor that receives the row selection signal SX through the gate terminal of the NMOS transistor and is connected to the driving transistor T3 and the column line.

[0037] Figure 3 Illustrates some implementations based on the disclosed technology for enabling Figure 1The circuit diagram of an example structure of a circuit that the line driver 200 shown in can generate a transmission signal.

[0038] Referring to Figure 3 , the line driver 200 may include a pull-up driver 210, a pull-up / pull-down switching circuit 220, a first pull-down driver 230, and a second pull-down driver 240.

[0039] The pull-up driver 210 may pull up the voltage of the transmission signal output node (OUT) to a preset positive charge pump (PCP) voltage (VPCP) level based on a pull-up control signal (TXB). When the pull-up / pull-down switching circuit 220 is turned on and the pull-up driver 210 is connected to the transmission signal output node (OUT), the pull-up control signal (TXB) may be activated, thereby operating the pull-up driver 210. For example, the pull-up control signal (TXB) may be a signal having a phase opposite to the phase of the transmission signal (TX) to be generated.

[0040] The pull-up driver 210 may include a switching element P1 connected to the pull-up / pull-down switching circuit 220 and a PCP voltage (VPCP) node. For example, the switching element P1 may include a PMOS transistor that receives the pull-up control signal (TXB) through the gate terminal of the PMOS transistor and is connected to the PCP voltage (VPCP) node and the pull-up / pull-down switching circuit 220.

[0041] The pull-up / pull-down switching circuit 220 may selectively connect the transmission signal output node (OUT) to the pull-up driver 210 or the first pull-down driver 230 based on a switching control signal (IDLE). For example, when the switching control signal (IDLE) is at a low level, the pull-up / pull-down switching circuit 220 may connect the pull-up driver 210 to the transmission signal output node (OUT), and when the switching control signal (IDLE) is at a high level, the pull-up / pull-down switching circuit 220 may connect the first pull-down driver 230 to the transmission signal output node (OUT).

[0042] The pull-up / pull-down switching circuit 220 may include a first switching element P2 connected to the pull-up driver 210 and the transmission signal output node (OUT), and a second switching element N1 connected to the first pull-down driver 230 and the transmission signal output node (OUT). For example, the first switching element P2 may include a first transistor, such as a PMOS transistor, which receives a switching control signal (IDLE) through the gate terminal of the PMOS transistor and is connected to the pull-up driver 210 and the transmission signal output node (OUT), while the second switching element N1 may include a second transistor, such as an NMOS transistor, which receives the switching control signal (IDLE) through the gate terminal of the NMOS transistor and is connected to the first pull-down driver 230 and the transmission signal output node (OUT). The switching control signal (IDLE) may transition from a high level to a low level before a predetermined time from a specific time when the pull-up control signal (TXB) transitions to a low level, and may transition to a high level when the pull-up control signal (TXB) is at a low level.

[0043] The first pull-down driver 230 may pull down the voltage of the transmission signal output node (OUT) to the second pixel power supply voltage (VSSPX) level along a first falling slope (e.g., a first pull-down speed) based on a first pull-down control signal (TX_NCP) applied to the first pull-down driver 230. In an implementation, the first pull-down control signal (TX_NCP) may be a signal having a phase opposite to that of the pull-up control signal (TXB).

[0044] The first pull-down driver 230 may include switching elements (N21, N22, N23) connected in series along a first current path Ipath 1 between the pull-up / pull-down switching circuit 220 and the negative charge pump (NCP) voltage (VNCP) node. For example, each of the switching elements (N21, N22, N23) may include an NMOS transistor, which receives the first pull-down control signal (TX_NCP) through the gate terminal of the NMOS transistor and is connected in series between the NCP voltage (VNCP) node and the pull-up / pull-down switching circuit 220.

[0045] The NMOS transistors (N21, N22, N23) may be formed to have the same size. For example, the NMOS transistors (N21, N22, N23) may have substantially the same channel resistance.

[0046] Although this embodiment has disclosed an example case where the first pull - down driver 230 includes three NMOS transistors (N21, N22, N23) connected in series, the scope of this embodiment is not limited thereto, and it should be noted that the number of such NMOS transistors within the first pull - down driver 230 can vary according to how the first falling slope is determined.

[0047] The second pull - down driver 240 can be directly connected to the transmission signal output node (OUT), for example, via a wire connected to the transmission signal output node (OUT), and there is no switching circuit between the second pull - down driver and the transmission signal output node. The second pull - down driver 240 can pull down the voltage of the transmission signal output node (OUT) to the NCP voltage (VNCP) level based on the second pull - down control signal (TXB_NCP) fed or applied to the second pull - down driver 240 and the first pixel power supply voltage (VDDPX). Here, the second falling slope can be a slope that changes faster than the first falling slope. That is to say, the second pull - down driver 240 can pull down the transmission signal output node (OUT) at a higher speed than the pull - down operation of the first pull - down driver 230. The second pull - down control signal (TXB_NCP) can be a signal having a phase opposite to that of the first pull - down control signal (TX_NCP).

[0048] The second pull - down driver 240 can include switching elements (N31, N32) connected in series between the transmission signal output node (OUT) and the NCP voltage (VNCP) node along the second current path Ipath2. For example, the switching elements N31 and N32 can each include an NMOS transistor. The NMOS transistor N31 can be connected to the transmission signal output node (OUT) and the NMOS transistor N32, and can receive the first pixel power supply voltage (VDDPX) through the gate terminal of the NMOS transistor N31.

[0049] Since the first pixel power supply voltage (VDDPX) is a positive (+) voltage, the NMOS transistor N31 can remain conducting. The NMOS transistor N32 can be connected to the NMOS transistor N31 and the NCP voltage (VNCP) node, and can receive the second pull - down control signal (TXB_NCP) through the gate terminal of the NMOS transistor N32.

[0050] The NMOS transistors (N31, N32) can be formed to have the same size as the NMOS transistors (N21, N22, N23) of the first pull-down driver 230. For example, each of the NMOS transistors (N31, N32) can have a channel resistance substantially the same as that of each of the NMOS transistors (N21, N22, N23). In this design, the total resistance of the second current path Ipath 2 between the transmission signal output node (OUT) and the bottom terminal of the VNCP of the second pull-down driver 240 having two NMOS transistors in series is less than the total resistance of the first current path Ipath 1 between the transmission signal output node (OUT) and the bottom terminal of the VNCP of the first pull-down driver 230 having three NMOS transistors in series.

[0051] The pull-down speed of the transmission signal output node (OUT) can be determined based on the resistance of each current path (Ipath1, Ipath 2) between the transmission signal output node (OUT) and the NCP voltage (VNCP) node. In the present embodiment, since the channel resistance of the current path (Ipath1) is greater than that of the current path (Ipath2), the pull-down speed of the first pull-down driver 230 is less than that of the second pull-down driver 240.

[0052] The control signals (TXB, IDLE, TX_NCP, TXB_NCP) can be provided from the timing controller 700.

[0053] Figure 4 illustrates some implementations based on the disclosed technology applied to Figure 1 the timing diagram of an example of the control signal of the row driver 200 shown. Figure 5 is a diagram illustrating how the falling slope changes when the transmission signal is pulled down based on some implementations of the disclosed technology.

[0054] Referring to Figure 4 and Figure 5 , at the timing point (t0), the pull-up driver 210 and the first pull-down driver 230 may not operate, and only the second pull-down driver 240 may operate. In this case, the transmission signal output node (OUT) can be changed to the NCP voltage (VNCP) level by the second pull-down driver 240. Therefore, the transmission signal (TX) can reach the NCP voltage (VNCP) level.

[0055] Thereafter, at the timing point (t1), when the switching control signal (IDLE) changes to a low level and the PMOS transistor P2 is turned on, the pull-up / pull-down switching circuit 220 can connect the pull-up driver 210 to the transmission signal output node (OUT).

[0056] Thereafter, at a timing point (t2), the pull-up control signal (TXB) and the second pull-down control signal (TXB_NCP) may transition from a high level to a low level, and the first pull-down control signal (TX_NCP) may transition from a low level to a high level.

[0057] As a result, the NMOS transistor N32 of the second pull-down driver 240 is turned off, the pull-down operation stops, and the PMOS transistor P1 of the pull-up driver 210 is turned on, so that the transmission signal output node (OUT) can be pulled up to the PCP voltage (VPCP) level by the pull-up driver 210. At this time, since the NMOS transistor N1 of the pull-up / pull-down switching circuit 220 remains off, the first pull-down driver 230 may not operate. Therefore, the transmission signal TX can transition from the NCP voltage (VNCP) level to the PCP voltage (VPCP) level.

[0058] Thereafter, at a timing point (t3), the switching control signal (IDLE) may transition to a high level. For example, the switching control signal (IDLE) may transition to a high level first before the second pull-down control signal (TXB_NCP) transitions to a high level again. As a result, although the pull-up driver 210 is still operating, the connection between the pull-up driver 210 and the transmission signal output node (OUT) is cut off by the pull-up / pull-down switching circuit 220, and the first pull-down driver 230 is connected to the transmission signal output node (OUT), so that the transmission signal output node (OUT) can be pulled down by the first pull-down driver 230 according to a first falling slope.

[0059] At this time, since the first pull-down driver 230 has a plurality of NMOS transistors (N21, N22, N23) connected in series, the channel resistance of the current path (Ipath1) through the first pull-down driver 230 is greater than the channel resistance of the current path (Ipath2) through the second pull-down driver 240. Therefore, the transmission signal output node (OUT) can be pulled down more slowly compared to the case of pulling down by the second pull-down driver 240.

[0060] Thereafter, at a timing point (t4), the first pull-down control signal (TX_NCP) transitions to a low level, and the second pull-down control signal (TXB_NCP) transitions to a high level, so that the transmission signal output node (OUT) can be quickly pulled down by the second pull-down driver 240 according to a second falling slope.

[0061] For example, in Figure 5During the period from t3 to t4 as shown, the transmission signal (TX) can be slowly pulled down to the second pixel power supply voltage (VSSPX) by the first pull-down driver 230 along a first falling slope. After passing through the timing point (t4), the transmission signal (TX) can be quickly pulled down to the NCP voltage (VNCP) level by the second pull-down driver 240 along a second falling slope as compared to when the transmission signal is pulled down by the first pull-down driver 230. In an implementation, the pull-down speed at which the transmission signal is pulled down has different values in the period from t3 to t4 and the period after t4.

[0062] As described above Figure 2 As shown, while the optical charges converted and accumulated in the photoelectric conversion element PD are transferred to the floating diffusion node FD through the transfer transistor T1, the transmission signal (TX) changes to the NCP voltage (VNCP) level too quickly, such that a spillover phenomenon may occur, in which not all of the optical charges present in the channel region of the transfer transistor T1 are transferred to the floating diffusion node FD, but some of the optical charges return to the photoelectric conversion element PD.

[0063] However, according to the current embodiment, while the transmission signal (TX) is being pulled down to the NCP voltage (VNCP) level, the transmission signal (TX) is controlled to be slowly pulled down for a predetermined period only in an initial pull-down stage, rather than being immediately quickly pulled down to the NCP voltage (VNCP) level, such that the occurrence of the spillover phenomenon can be minimized.

[0064] Figure 6 is a circuit diagram illustrating another exemplary structure of a circuit for enabling the Figure 1 row driver shown to output a transmission signal based on some implementations of the disclosed technology.

[0065] Referring to Figure 6 , the row driver 200' can include a pull-up driver 210, a pull-up / pull-down switching circuit 220, a first pull-down driver 230, a second pull-down driver 240, and a third pull-down driver 250.

[0066] Unlike Figure 3 the row driver 200 shown, Figure 6 the row driver 200' in Figure 3 can further include a third pull-down driver 250. The following description will focus on the construction and operation of the third pull-down driver 250. In addition, the same reference numerals are given to the components identical to those of the row driver 200 in

[0067] The third pull-down driver 250 can be selectively connected in parallel with the first pull-down driver 230 based on a third pull-down control signal (EN), such that the third pull-down driver 250 can pull down the voltage of the transmission signal output node (OUT) together with the first pull-down driver 230. The third pull-down control signal (EN) can be selectively activated to increase the pull-down speed of the transmission signal output node (OUT). For example, the third pull-down control signal (EN) can be selectively activated to a high level at the timing point (t3) shown in Figure 4 The timing point (t3) is shown.

[0068] The third pull-down driver 250 can include NMOS transistors (N41, N42, N43, N44) connected in series between the transmission signal output node (OUT) and the NCP voltage (VNCP) node along a third current path Ipath3. Additionally, the third pull-down driver 250 can include an NMOS transistor N45 that is connected to the gate terminals of the NMOS transistors (N42, N43, N44) and the gate terminals of the NMOS transistors (N21, N22, N23) of the first pull-down driver 230.

[0069] For example, when the third pull-down control signal (EN) is activated to a high level at the timing point (t3) shown in Figure 4 The timing point (t3) is shown, the NMOS transistor N41 is turned on, and the NMOS transistor N45 is also turned on, such that the first pull-down control signal (TX_NCP) can also be applied to the gate terminals of the NMOS transistors (N42, N43, N44). As a result, during the time period from t3 to t4, the first pull-down driver 230 and the third pull-down driver 250 are simultaneously driven, and the transmission signal output node (OUT) can be pulled down faster compared to another case where only the first pull-down driver 230 is driven. Therefore, in an implementation, the third pull-down driver 250 operates together with the first pull-down driver 230 to pull down the transmission signal, and the pull-down speed at which the transmission signal is pulled down increases compared to a case where the first pull-down driver 230 operates without the third pull-down driver 250.

[0070] The third pull-down driver 250 may pull down the transmission signal output node (OUT) at the same pull-down speed as the first pull-down driver 230. The speed at which the first pull-down driver 230 and the third pull-down driver 250 pull down the transmission signal output node (OUT) may be less than the speed at which the second pull-down driver 240 pulls down the transmission signal output node (OUT). The third pull-down driver 250 may pull down the transmission signal output node (OUT) at a pull-down speed different from that of the first pull-down driver 230. In this case, the speed at which the first pull-down driver 230 and the third pull-down driver 250 pull down the transmission signal output node (OUT) may be less than the speed at which the second pull-down driver 240 pulls down the transmission signal output node (OUT).

[0071] In some implementations, the NMOS transistors (N41, N42, N43, N44) of the third pull-down driver 250 may be formed to have the same dimensions as the NMOS transistors (N21, N22, N23) of the first pull-down driver 230. For example, each NMOS transistor (N41, N42, N43, N44) may have a channel resistance substantially the same as that of each NMOS transistor (N21, N22, N23).

[0072] In some other implementations, the NMOS transistors (N41, N42, N43, N44) of the third pull-down driver 250 may also be formed to have different dimensions from the NMOS transistors (N21, N22, N23) of the first pull-down driver 230.

[0073] It can be clearly seen from the above description that an image sensing device based on some implementations of the disclosed technology can improve the overflow characteristics that may occur in the transfer transistors of pixels.

[0074] Embodiments of the disclosed technology may provide various effects that can be directly or indirectly recognized through the above patent documents.

[0075] Although some exemplary embodiments have been described, it should be understood that various modifications or enhancements to the disclosed embodiments and other embodiments can be designed based on the content described and / or illustrated in this patent document.

[0076] Cross-reference to related applications

[0077] This patent document claims the priority and benefit of Korean Patent Application No. 10-2024-0006816, filed on January 16, 2024, the entire content of which is incorporated herein by reference as part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device comprising: A transmission signal output node, the transmission signal output node being coupled to output an electrical signal; A pull-up driver, the pull-up driver pulling up the voltage level of the transmission signal output node to a first charge pumping voltage based on a pull-up control signal applied to the pull-up driver; A first pull-down driver, the first pull-down driver pulling down the voltage level of the transmission signal output node at a first pull-down speed based on a first pull-down control signal applied to the first pull-down driver; A switching circuit, the switching circuit selectively connecting the transmission signal output node to the pull-up driver or the first pull-down driver based on a switching control signal applied to the switching circuit; And A second pull-down driver, the second pull-down driver being coupled to the transmission signal output node and pulling down the voltage level of the transmission signal output node at a second pull-down speed different from the first pull-down speed based on a second pull-down control signal.

2. The image sensing device according to claim 1, wherein, The second pull-down driver: Pulls down the transmission signal output node to a second charge pumping voltage at a speed higher than the first pull-down speed.

3. The image sensing device according to claim 2, wherein, The first pull-down driver: Pulls down the transmission signal output node to a voltage level between the first charge pumping voltage and the second charge pumping voltage.

4. The image sensing device according to claim 3, wherein, The second pull-down driver: Pulls down the transmission signal output node, which has been pulled down by the first pull-down driver, to the second charge pumping voltage.

5. The image sensing device according to claim 1, wherein, The switching circuit includes: A first switching element, the first switching element being connected to the pull-up driver and the transmission signal output node, and receiving the switching control signal through a gate terminal of the first switching element; and A second switching element, the second switching element being connected to the first pull-down driver and the transmission signal output node, and receiving the switching control signal through a gate terminal of the second switching element.

6. The image sensing device according to claim 5, wherein, The pull-up driver includes: A third switching element, the third switching element being connected to the first switching element and the first charge pumping voltage node, and receiving the pull-up control signal through a gate terminal of the third switching element.

7. The image sensing device according to claim 5, wherein, The first pull-down driver includes: A plurality of fourth switching elements, the plurality of fourth switching elements being connected in series between the second switching element and the second charge pumping voltage node, and commonly receiving the first pull-down control signal through gate terminals of the plurality of fourth switching elements.

8. The image sensing device according to claim 1, wherein The second pull-down driver includes: A fifth switching element, the fifth switching element having a terminal connected to the transmission signal output node, and receiving a pixel power supply voltage through a gate terminal of the fifth switching element; and A sixth switching element, the sixth switching element being connected to the fifth switching element and the second charge pumping voltage node, and receiving the second pull-down control signal through a gate terminal of the sixth switching element.

9. The image sensing device according to claim 1, the image sensing device further comprising: A third pull-down driver that is selectively connected in parallel with the first pull-down driver based on a third pull-down control signal and, together with the first pull-down driver, pulls down the voltage level of the transmission signal output node.

10. The image sensing device according to claim 9, wherein, The third pull-down driver includes: A seventh switching element having one terminal connected to the transmission signal output node and receiving the third pull-down control signal through a gate terminal of the seventh switching element; and A plurality of eighth switching elements connected in series between the seventh switching element and a second charge pumping voltage node and receiving the first pull-down control signal through gate terminals of the plurality of eighth switching elements.

11. The image sensing device according to claim 10, further comprising: A ninth switching element that selectively transmits the first pull-down control signal to gate terminals of the plurality of eighth switching elements based on the third pull-down control signal.

12. The image sensing device according to claim 9, wherein, The third pull-down driver: Pulls down the voltage level of the transmission signal output node at the first pull-down speed.

13. An image sensing device, comprising: A photoelectric conversion element that generates photo charges by photoelectrically converting incident light; A floating diffusion node that receives and accumulates the photo charges from the photoelectric conversion element; A transfer transistor coupled to the photoelectric conversion element and the floating diffusion node and transferring the photo charges generated by the photoelectric conversion element to the floating diffusion node based on a transmission signal; And A row driver that generates the transmission signal and supplies the transmission signal to the transfer transistor, wherein the row driver changes a pull-down speed at which the transmission signal is pulled down from a first charge pumping voltage to a second charge pumping voltage.

14. The image sensing device according to claim 13, wherein, The row driver includes: A pull-up driver that pulls up the voltage level of a transmission signal output node to the first charge pumping voltage based on a pull-up control signal; and A pull-down driver that gradually pulls down the voltage level of the transmission signal output node at different pull-down speeds based on a first pull-down control signal and a second pull-down control signal.

15. The image sensing device according to claim 14, wherein, The pull-down driver includes: A first pull-down driver that pulls down the voltage level of the transmission signal output node to a pixel power supply voltage level at a first pull-down speed based on the first pull-down control signal; and A second pull-down driver that pulls down the transmission signal output node, which has been pulled down to the pixel power supply voltage level, to the second charge pumping voltage at a second pull-down speed higher than the first pull-down speed based on the second pull-down control signal.

16. The image sensing device according to claim 15, further comprising: A third pull-down driver that is selectively connected in parallel with the first pull-down driver based on a third pull-down control signal and that, together with the first pull-down driver, pulls down the transmission signal output node.

17. The image sensing device according to claim 15, the image sensing device further comprising: A switching circuit that selectively connects either the pull-up driver or the first pull-down driver to the transmission signal output node based on a switching control signal.

18. The image sensing device according to claim 15, wherein, The resistance of a first current path through the first pull-down driver is greater than the resistance of a second current path through the second pull-down driver.

19. The image sensing device according to claim 16, wherein, The first pull-down driver and the third pull-down driver pull down the transmission signal output node at a third pull-down speed that is greater than the first pull-down speed and less than the second pull-down speed.

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