Image sensor

Abstract

An image sensor includes: a top layer including a first front bonding pad under a first substrate, a first front bonding plug connected to the first front bonding pad, and a first shielding structure separated from the first front bonding pad in a first horizontal direction; an intermediate layer under and bonded to the top layer, the intermediate layer including a second front bonding pad over the second substrate, a second front bonding plug connected to the second front bonding pad, and a second shielding structure separated from the second front bonding pad in the first horizontal direction; and a bottom layer below the intermediate layer and bonded to the intermediate layer, in which a vertical height of a top surface of the first shielding structure is higher than a vertical height of a top surface of the first front bonding pad.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0005567, filed with the Korean Intellectual Property Office on January 12, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The disclosure relates to an image sensor, and more particularly, to an image sensor capable of improving coupling occurring due to miniaturization of the image sensor. Background Art

[0003] An image sensor that captures an image and converts the image into an electrical signal is used in electronic devices for ordinary consumers (such as digital cameras, mobile phone cameras, and camcorders), and is also used in cameras mounted on automobiles, security devices, and robots. As image sensors are becoming smaller, there is a need to improve coupling occurring due to miniaturization of the image sensor. Summary of the Invention

[0004] Provided is an image sensor capable of improving coupling occurring due to miniaturization of the image sensor.

[0005] Also provided is an image sensor having improved electrical characteristics and reliability.

[0006] Also provided is an image sensor having an increased integration density.

[0007] The disclosure is not limited to the above-mentioned content and will be clearly understood by those skilled in the art from the following description.

[0008] According to one aspect of the disclosure, an image sensor includes: a top layer including a first substrate having a first front surface and a first rear surface opposite to the first front surface, a first front bonding pad on the first front surface, a first front bonding plug connected to the first front bonding pad and extending in a vertical direction toward the first front surface, and a first shielding structure separated from the first front bonding pad in a first horizontal direction; an intermediate layer below the top layer and bonded to the top layer, the intermediate layer including a second substrate having a second front surface and a second rear surface opposite to the second front surface, a second front bonding pad on the second front surface, a second front bonding plug connected to the second front bonding pad and extending in a vertical direction toward the second front surface, and a second shielding structure separated from the second front bonding pad in the first horizontal direction; and a bottom layer below the intermediate layer and bonded to the intermediate layer, the bottom layer including a third substrate and transistors on the third substrate, wherein a vertical height of a top surface of the first shielding structure is higher than a vertical height of a top surface of the first front bonding pad.

[0009] According to one aspect of the disclosure, an image sensor includes: a top layer including a first substrate having a first front surface and a first rear surface opposite the first front surface, a first front bonding pad on the first front surface, a first front bonding plug connected to the first front bonding pad and extending in a vertical direction toward the first front surface, and a first shielding structure including a first portion separated from the first front bonding pad in a first horizontal direction and a second portion separated from the first front bonding plug in the first horizontal direction; a middle layer below the top layer and bonded to the top layer, the middle layer including a second substrate having a second front surface and a second rear surface opposite the second front surface, a second front bonding pad on the second front surface, a second front bonding plug connected to the second front bonding pad and extending in a vertical direction toward the second front surface, and a second shielding structure including a third portion separated from the second front bonding pad in the first horizontal direction and a fourth portion separated from the second front bonding plug in the first horizontal direction; and a bottom layer below the middle layer and bonded to the middle layer, the bottom layer including a third substrate and transistors on the third substrate, wherein the first shielding structure and the second shielding structure extend in a second horizontal direction intersecting the first horizontal direction.

[0010] According to one aspect of the disclosure, an image sensor includes: a top layer including a first substrate having a first front surface and a first rear surface opposite the first front surface, a color filter and a lens sequentially stacked on the first rear surface, a pixel isolation layer penetrating the first substrate, a first transistor on the first front surface of the first substrate, a first contact plug connected to the first transistor, a first wiring layer below the first contact plug and connected to the first contact plug, a first front bonding plug below the first wiring layer and connected to the first wiring layer, a first front bonding pad below the first front bonding plug and in contact with the first front bonding plug, and a first shielding structure separated from the first front bonding pad in a first horizontal direction; a middle layer below the top layer and bonded to the top layer, the middle layer including a second substrate having a second front surface and a second rear surface opposite the second front surface, a second transistor on the second front surface, a second contact plug connected to the second transistor, a second wiring layer above the second contact plug and connected to the second contact plug, a second front bonding plug above the second wiring layer and connected to the second wiring layer, a second front bonding pad above the second front bonding plug and in contact with the second front bonding plug, and a second shielding structure separated from the second front bonding pad in the first horizontal direction; and a bottom layer below the middle layer and bonded to the middle layer, the bottom layer including a third substrate and transistors on the third substrate, wherein a vertical height of a top surface of the first shielding structure is higher than a vertical height of a top surface of the first front bonding pad. Description of the Drawings

[0011] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram of an image sensor according to an embodiment.

[0013] Figure 2 is a circuit diagram of an image sensor according to an embodiment.

[0014] Figure 3 is a schematic cross-sectional view showing the structure of an image sensor according to an embodiment.

[0015] Figure 4 is Figure 3 an enlarged view of region PP1 in

[0016] Figure 5 is a schematic plan view showing the structure of an image sensor according to an embodiment.

[0017] Figure 6 is a schematic plan view showing the structure of an image sensor according to an embodiment.

[0018] Figure 7 is a schematic cross-sectional view showing the structure of an image sensor according to an embodiment.

[0019] Figure 8 is Figure 7 an enlarged view of region PP2 in

[0020] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 are cross-sectional views showing a method of manufacturing an image sensor according to an embodiment. Figure 3 of Detailed Description of Embodiments

[0021] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. An embodiment may have only one implementation manner or may be implemented in combination with one or more embodiments. Therefore, the disclosure is not limited to one embodiment.

[0022] As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. For clarity, the drawings may be exaggerated and the drawings are not drawn to scale. Although terms including ordinal numbers (such as, "first", "second", etc.) may be used for convenience of description, the disclosure is not limited to the above terms.

[0023] In the following description, throughout the specification, the same reference numerals denote the same elements. As used herein, a plurality of "units", a plurality of "modules", a plurality of "components", and a plurality of "blocks" may be implemented as a single component, or a single "unit", a single "module", a single "component", and a single "block" may include a plurality of components.

[0024] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly or indirectly connected to that other element.

[0025] In addition, when a component "includes" or "comprises" an element, unless there is a specific description to the contrary, the component may also include other elements without excluding other elements.

[0026] Throughout the specification, when a component is "on" another component, this includes not only the case where the component is in contact with the other component, but also the case where there is another component between the two components.

[0027] As used herein, the expressions "at least one of a, b, or c" and "at least one of a, b, and c" indicate: "only a", "only b", "only c", "both a and b", "both a and c", "both b and c", and "all of a, b, and c".

[0028] Regarding any method or process described herein, for ease of description, identification codes may be used, but are not intended to indicate the order of each step or operation. Unless the context clearly indicates otherwise, each step or operation may be implemented in an order different from the order shown. Unless the disclosed context clearly indicates otherwise, one or more steps or operations may be omitted.

[0029] Figure 1 is a block diagram of an image sensor 100 according to an embodiment.

[0030] The image sensor 100 may include a pixel array 110, a row driver 120, a ramp signal generator 130, a count number generator 140, an analog-to-digital converter (ADC) circuit 150, a data output circuit 180, and a timing controller 190. The image sensor 100 may also include a signal processor 195. The configuration including the ADC circuit 150 and the data output circuit 180 may be referred to as a readout circuit.

[0031] The pixel array 110 may include a plurality of row lines RL and a plurality of column lines CL. The pixel array 110 may include a plurality of pixels PX, and the plurality of pixels PX are connected to the plurality of row lines RL and the plurality of column lines CL and are arranged in a matrix. The pixel PX may include an active pixel sensor (APS).

[0032] Each pixel PX may include at least one photoelectric conversion element, may sense light by using the photoelectric conversion element, and may generate an image signal as an electrical signal converted from the sensed light. For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, a pinned photodiode, etc.

[0033] Each pixel PX may sense light in a specific spectrum. For example, a part of the pixel PX may convert light in the red spectrum into an electrical signal, convert light in the green spectrum into an electrical signal, or convert light in the blue spectrum into an electrical signal. However, the disclosure is not limited thereto. At least a part of the pixel PX may convert light in the white spectrum into an electrical signal.

[0034] For example, at least a part of the pixel PX may convert light in a color spectrum different from the red spectrum, the green spectrum, the blue spectrum, and the white spectrum into an electrical signal. For example, at least a part of the pixel PX may convert light in the yellow spectrum, the cyan spectrum, or the magenta spectrum into an electrical signal.

[0035] A color filter that transmits light in a specific spectrum may be disposed above each pixel PX. The color sensed by each pixel PX may be determined by the color filter. However, the disclosure is not limited thereto. In one or more embodiments, a specific photoelectric conversion element may convert light in a specific wavelength band into an electrical signal according to the level of an electrical signal applied thereto.

[0036] In one or more embodiments, each pixel PX may have a dual conversion gain. The dual conversion gain includes a low conversion gain and a high conversion gain. Here, the conversion gain is the ratio at which the charge accumulated in the floating diffusion node is converted into a voltage. The charge generated by the photoelectric conversion element may be transferred to the floating diffusion node and accumulated in the floating diffusion node, and the charge in the floating diffusion node may be converted into a voltage according to the conversion gain. The conversion gain may vary with the capacitance of the floating diffusion node. The conversion gain may decrease when the capacitance of the floating diffusion node increases, and increase when the capacitance of the floating diffusion node decreases.

[0037] The row driver 120 may drive the pixel array 110 row by row. The row driver 120 may decode a row control signal (e.g., an address signal) generated by the timing controller 190. The row driver 120 may select at least one row line among the row lines RL of the pixel array 110 in response to the decoded row control signal.

[0038] For example, the row driver 120 may generate a selection signal for selecting one of a plurality of rows. The selection signal may be sent to the pixel array 110 via the row line RL. The pixel array 110 may output a pixel signal (e.g., a pixel voltage) from the selected row, which is selected by the selection signal from the row driver 120. The pixel signal may include a reset signal and an image signal. The row driver 120 may send a control signal to the pixel array 110. The control signal may be a signal for outputting the pixel signal. Each pixel PX may output a pixel signal by operating in response to the control signal.

[0039] Under the control of the timing controller 190, the ramp signal generator 130 may generate a ramp signal RAMP (e.g., a ramp voltage) that increases or decreases at a specific slope. The ramp signal RAMP may be provided to each of a plurality of correlated double sampling (CDS) circuits 160 of the ADC circuit 150.

[0040] Under the control of the timing controller 190, the count code generator 140 may generate a count code CCD. The count code CCD may be provided to a plurality of counter circuits 170. In one or more embodiments, the count code generator 140 may include a Gray code generator. The count code generator 140 may generate a plurality of code values having a resolution corresponding to the set number of bits as the count code CCD. For example, when a 10-bit code is set, the count code generator 140 may generate a count code CCD including 1024 code values in ascending or descending order.

[0041] The ADC circuit 150 may include a CDS circuit 160 and a counter circuit 170. The ADC circuit 150 may convert the pixel signal received from the pixel array 110 into a pixel value corresponding to a digital signal. The pixel signal received via each column line CL may be converted into a pixel value corresponding to a digital signal by the CDS circuit 160 and the counter circuit 170.

[0042] The CDS circuit 160 may compare the pixel signal received via the column line CL with the ramp signal RAMP and output the result of the comparison as a comparison signal. When the level of the ramp signal RAMP is equal to the level of the pixel signal, the CDS circuit 160 may output a comparison signal that changes from a first level (e.g., logic high) to a second level (e.g., logic low). The level transition time of the comparison signal may be determined according to the level of the pixel signal.

[0043] The CDS circuit 160 may sample the pixel signal provided from the pixel PX by using the CDS method. The CDS circuit 160 may sample the reset signal received as the pixel signal, compare the reset signal with the ramp signal RAMP, and generate a comparison signal based on the reset signal. Thereafter, the CDS circuit 160 may sample the image signal related to the reset signal, compare the image signal with the ramp signal RAMP, and generate a comparison signal based on the image signal.

[0044] The counter circuit 170 may count the level transition time of the comparison signal output from the CDS circuit 160 and output a count value. In one or more embodiments, the counter circuit 170 may include a latch circuit and an arithmetic circuit. The latch circuit may receive the count code CCD from the count code generator 140 and the comparison signal from the CDS circuit 160, and latch the code value of the count code CCD at the level transition time of the comparison signal.

[0045] The latch circuit may latch the code value corresponding to the reset signal. For example, the latch circuit may latch the reset value and the code value corresponding to the image signal. For example, the latch circuit may latch the image signal value. The arithmetic circuit may perform an operation on the reset value and the image signal value to generate an image signal value having the reset level of the pixel PX removed from the image signal value. The counter circuit 170 may output the image signal value having the reset level removed from the image signal value as the pixel value.

[0046] In one embodiment, the image sensor 100 may include the count code generator 140 and the counter circuit 170, and the counter circuit 170 may include a circuit that latches the code value of the count code CCD received from the count code generator 140, but the disclosure is not limited thereto.

[0047] In one or more embodiments, the image sensor 100 may not include the count code generator 140, and the counter circuit 170 may include an arithmetic circuit and an up counter that sequentially increases the count value based on the count clock signal provided from the timing controller 190, or may include an up-down counter or a bitwise inversion counter.

[0048] The data output circuit 180 may temporarily store the pixel values output from the ADC circuit 150 and then output the pixel values. The data output circuit 180 may include a plurality of column memories 181 and a column decoder 182. Each column memory 181 may store the pixel values received from the counter circuit 170. In one or more embodiments, each column memory 181 may be included in the counter circuit 170. The plurality of pixel values respectively stored in the column memories 181 may be output as image data IDT under the control of the column decoder 182.

[0049] The timing controller 190 may output control signals to each of the line driver 120, the ramp signal generator 130, the count code generator 140, the ADC circuit 150, and the data output circuit 180. Thus, the timing controller 190 may control the operations or timings of the line driver 120, the ramp signal generator 130, the count code generator 140, the ADC circuit 150, and the data output circuit 180.

[0050] The signal processor 195 may perform noise reduction, gain tuning, waveform shaping, interpolation, white balance, gamma processing, edge enhancement, binning, etc. on the image data IDT. In one or more embodiments, the signal processor 195 may be provided in a processor external to the image sensor 100.

[0051] Figure 2 is a circuit diagram of the image sensor 100 according to an embodiment.

[0052] Referring to Figure 2 , the image sensor 100 (e.g., each pixel in the image sensor 100) may include a photodiode PD, a transfer transistor TX, a floating diffusion node FD, a conversion gain transistor DCG, a reset transistor RX, a source follower transistor SF, and a selection transistor SEL.

[0053] The transfer transistor TX, the conversion gain transistor DCG, the reset transistor RX, the source follower transistor SF, and the selection transistor SEL may respectively include a transfer gate TG, a conversion gain gate, a reset gate, a source follower gate SFG, and a selection gate.

[0054] In one or more embodiments, the transfer gate TG may include a vertical gate. In one or more embodiments, each of the conversion gain gate, the reset gate, the source follower gate SFG, and the selection gate may include a flat gate.

[0055] The photodiode PD may generate charges in proportion to the amount of incident light. The photodiode PD may generate negatively charged electrons and positively charged holes in response to the incident light.

[0056] There may be multiple photodiodes PD. The multiple photodiodes PD may share a floating diffusion node FD, a reset transistor RX, a conversion gain transistor DCG, a source follower transistor SF, and a selection transistor SEL. Setting one photodiode PD or eight photodiodes PD is only an example, and the number of photodiodes PD is not limited thereto. A transfer transistor TX may be between the photodiode PD and the floating diffusion node FD, and may transfer the charge generated in the photodiode PD to the floating diffusion node FD.

[0057] The transfer transistor TX may include a transfer gate TG, a drain connected to the photodiode PD, and a source connected to the floating diffusion node FD. The conversion gain transistor DCG may include a conversion gain gate, a source connected to the drain of the reset transistor RX, and a drain connected to the floating diffusion node FD.

[0058] The conversion gain transistor DCG may change the capacitance of the floating diffusion node FD according to a conversion gain signal.

[0059] When the conversion gain transistor DCG is turned on, the capacitance of the floating diffusion node FD may increase, such that the image sensor 100 may operate in a low conversion gain mode. Conversely, when the conversion gain transistor DCG is turned off, the capacitance of the floating diffusion node FD may decrease, such that the image sensor 100 may operate in a high conversion gain mode. The reset transistor RX may include a reset gate, a source connected to the power supply voltage Vpix, and a drain connected to the source of the conversion gain transistor DCG.

[0060] When the reset transistor RX is turned on according to a reset control signal and the conversion gain transistor DCG is turned on according to a conversion gain signal, the floating diffusion node FD may be reset based on the power supply voltage Vpix. Specifically, the charge accumulated in the floating diffusion node FD may be discharged, such that the floating diffusion node FD may be reset. At this time, a reset signal corresponding to the voltage level of the floating diffusion node FD may be output. The source follower gate SFG of the source follower transistor SF may be electrically connected to the floating diffusion node FD.

[0061] The source of the source follower transistor SF may be electrically connected to the source of the selection transistor SEL. The drain of the source follower transistor SF may be electrically connected to the power supply voltage Vpix. The potential of the floating diffusion node FD may change according to the amount of charge accumulated in the floating diffusion node FD. The source follower transistor SF may amplify the change in the potential of the floating diffusion node FD and output the amplified result to the source of the selection transistor SEL.

[0062] The source of the selection transistor SEL may be electrically connected to the source of the source follower transistor SF.

[0063] The drain of the select transistor SEL may be electrically connected to the output voltage line Vout.

[0064] Figure 3 is a schematic cross-sectional view showing the structure of an image sensor according to an embodiment. Figure 4 is Figure 3 an enlarged view of the region PP1 in Figure 3 The image sensor EX1 of Figure 1 may be an exemplary embodiment of the image sensor 100 of Figure 3 and Figure 4 Referring to Figure 1 the image sensor EX1 may include

[0065] The image sensor EX1 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The intermediate layer 300 and the top layer 200 may be sequentially stacked on the bottom layer 400.

[0066] The image sensor EX1 may be composed of three layers, in which the intermediate layer 300 and the top layer 200 are stacked on the bottom layer 400. The image sensor EX1 may be composed of three layers, in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are joined to each other. Hereinafter, the transistor may include a planar transistor, a multi-bridge channel (MBC) transistor, a gate-all-around (GAA) transistor, or a fin field-effect transistor (FET).

[0067] The top layer 200 may include a first substrate 201, a pixel isolation layer 217, a color filter 219, a lens 221, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first via plug 209, a first front bonding pad (landing pad), a first front bonding plug 213, a first shielding structure 230, a first insulating layer 215, and a first passivation layer 216.

[0068] The first substrate 201 may include a silicon substrate.

[0069] The first substrate 201 may include a first front surface 201f and a first rear surface 201b opposite to the first front surface 201f. A photodiode ( Figure 2 PD in

[0070] The color filter 219 and the lens 221 may be sequentially stacked on the first rear surface 201b of the first substrate 201. Although a plurality of lenses 221 are shown as being separated from each other in Figure 3 , the lenses 221 may be integrally formed. This may vary according to the design of the image sensor EX1 to be manufactured. The pixel isolation layer 217 may be disposed inside the first substrate 201.

[0071] The pixel isolation layer 217 may isolate Figure 1 the plurality of pixels PX in

[0072] from each other. The pixel isolation layer 217 may penetrate the first substrate 201. The pixel isolation layer 217 may include at least two materials. For example, the pixel isolation layer 217 may include an insulating material and a semiconductor material having a refractive index different from that of the first substrate 201. For example, the semiconductor material may include a polysilicon film doped with impurities or a silicon germanium film doped with impurities. The impurities doped in the polysilicon film or the silicon germanium film may include, for example, boron, phosphorus, or arsenic. For example, the insulating material may include silicon oxide. In another example, the pixel isolation layer 217 may include a metal film instead of a semiconductor material. The fence pattern 220 may be disposed on the pixel isolation layer 217.

[0073] For example, the fence pattern 220 may be vertically stacked with the pixel isolation layer 217. However, this is only an example, and the fence pattern 220 may not be vertically stacked with the pixel isolation layer 217. The fence pattern 220 may be between a pair of color filters 219 adjacent to each other in the first horizontal direction D1. Figure 1 The fence pattern 220 may separate the plurality of color filters 219 from each other. For example, the color filters 219 may be physically and optically separated from each other by the fence pattern 220. In a plan view, the fence pattern 220 may surround

[0074] each pixel PX in

[0075] For example, the fence pattern 220 may surround each color filter 219. The fence pattern 220 may include a first fence component 220a and a second fence component 220b on the first fence component 220a.

[0076] For example, the first fence component 220a and the second fence component 220b may have a rectangular cross section. The first fence component 220a may be used as a barrier layer.

[0077] For example, the second barrier member 220 b may include an organic material. The second barrier member 220 b may include a material having a low refractive index and may have an insulating property. The first transistor 203 may be disposed on the first front surface 201 f of the first substrate 201 .

[0078] The first source region and the first drain region of the first transistor 203 may be arranged in the first substrate 201, but for convenience, Figure 3 The first source region and the first drain region of the first transistor 203 are omitted. The first contact plug 207 and the first wiring layer 205 may be connected to the first transistor 203 .

[0079] The first contact plug 207 may include a conductive metal. For example, the first contact plug 207 may include tungsten. There may be a plurality of first wiring layers 205. Two different first wiring layers 205 among the plurality of first wiring layers 205 may be at different vertical heights. In other words, the plurality of first wiring layers 205 may form a multilayer structure. The first wiring layer 205 may be connected to the first via plug 209.

[0080] The first via plug 209 may connect at least two first wiring layers 205 at different vertical heights to each other. The first front bonding pad 211 may be at the bottom of the roof layer 200.

[0081] The first front bonding pad 211 may be connected to the first front bonding plug 213. The first front bonding plug 213 may extend in the vertical direction D3 and be connected to the first wiring layer 205. For example, the first front bonding plug 213 may extend in the vertical direction D3 toward the first front surface 201f of the first substrate 201. Here, the first horizontal direction D1 is defined as a direction parallel to the first front surface 201f of the first substrate 201, the second horizontal direction D2 is defined as a direction parallel to the first front surface 201f of the first substrate 201 and intersecting the first horizontal direction D1, and the vertical direction D3 is defined as a direction perpendicular to the first front surface 201f of the first substrate 201.

[0082] For example, the first front bonding pad 211 and the first front bonding plug 213 may be integrally formed.

[0083] In other words, no boundary may be observed between the first front bonding pad 211 and the first front bonding plug 213. The first front bonding pad 211 may be electrically connected to the first transistor 203 through the first front bonding plug 213, the first wiring layer 205, the first via plug 209, and the first contact plug 207.

[0084] For example, the first front bonding pad 211 may be electrically connected to Figure 2The floating diffusion node FD therein. For example, the floating diffusion node FD may be inside the first substrate 201. The first wiring layer 205 may have a first thickness T1.

[0085] The first via plug 209 may have a second thickness T2. The first front bonding pad 211 may have a third thickness T3. The first front bonding plug 213 may have a fourth thickness T4. The first thickness T1 may correspond to the length of the first wiring layer 205 in the vertical direction D3.

[0086] The second thickness T2 may correspond to the length of the first via plug 209 in the vertical direction D3. The third thickness T3 may correspond to the length of the first front bonding pad 211 in the vertical direction D3. The fourth thickness T4 may correspond to the length of the first front bonding plug 213 in the vertical direction D3. The third thickness T3 of the first front bonding pad 211 may be smaller than the first thickness T1 of the first wiring layer 205.

[0087] The fourth thickness T4 of the first front bonding plug 213 may be larger than the second thickness T2 of the first via plug 209. The first shielding structure 230 may be disposed beside the first front bonding pad 211.

[0088] The first shielding structure 230 may be separated from the first front bonding pad 211 in the first horizontal direction D1. The first shielding structure 230 may be between two first front bonding pads 211 adjacent to each other along the first horizontal direction D1. The first shielding structure 230 may extend toward the first front surface 201f of the first substrate 201 in the vertical direction D3. For example, the first shielding structure 230 may protrude upward from the bottom surface 215b of the first insulating layer 215 toward the first substrate 201. The first shielding structure 230 may be separated from the first front bonding pad 211, the first front bonding plug 213, the first wiring layer 205, and the first via plug 209. The first shielding structure 230 may include a first part and a second part, the first part being separated from the first front bonding pad 211 in the first horizontal direction D1, and the second part being separated from the first front bonding plug 213 in the first horizontal direction D1.

[0089] The first part of the first shielding structure 230 may be disposed at the same vertical height as the first front bonding pad 211. The second part of the first shielding structure 230 may be disposed at the same vertical height as the first front bonding plug 213. The first part and the second part of the first shielding structure 230 may be integrally formed. The first shielding structure 230 may be vertically stacked with the pixel isolation layer 217.

[0090] In a plan view, the first shielding structure 230 may be stacked with the pixel isolation layer 217. The bottom surface 230b of the first shielding structure 230 may be coplanar with the bottom surface 211b of the first front bonding pad 211.

[0091] The vertical height of the top surface 230a of the first shielding structure 230 may be higher than the vertical height of the top surface 211a of the first front bonding pad 211. The vertical height of the top surface 230a of the first shielding structure 230 may be lower than the vertical height of the top surface 213a of the first front bonding plug 213. The first shielding structure 230 may have a fifth thickness T5.

[0092] The fifth thickness T5 may correspond to the length of the first shielding structure 230 in the vertical direction D3. The fifth thickness T5 of the first shielding structure 230 may be greater than the third thickness T3 of the first front bonding pad 211. The fifth thickness T5 of the first shielding structure 230 may be less than or equal to the sum of the third thickness T3 of the first front bonding pad 211 and the fourth thickness T4 of the first front bonding plug 213. For example, the fifth thickness T5 of the first shielding structure 230 may be different from the fourth thickness T4 of the first front bonding plug 213. For example, the fifth thickness T5 of the first shielding structure 230 may be less than or equal to the fourth thickness T4 of the first front bonding plug 213. For example, the fifth thickness T5 of the first shielding structure 230 may be greater than the fourth thickness T4 of the first front bonding plug 213. In Figure 4 In the cross-sectional view, the width of the first shielding structure 230 in the first horizontal direction D1 may be smaller than the width of the first front bonding pad 211 in the first horizontal direction D1.

[0093] The width of the first shielding structure 230 in the first horizontal direction D1 may be less than or substantially equal to the width of the first front bonding plug 213 in the first horizontal direction D1. The first wiring layer 205, the first via plug 209, the first front bonding pad 211, the first front bonding plug 213, and the first shielding structure 230 may include the same material.

[0094] The first wiring layer 205, the first via plug 209, the first front bonding pad 211, the first front bonding plug 213, and the first shielding structure 230 may include a conductive metal. For example, the first wiring layer 205, the first via plug 209, the first front bonding pad 211, the first front bonding plug 213, and the first shielding structure 230 may include copper. The first insulating layer 215 may be disposed on the first front surface 201f of the first substrate 201.

[0095] The first wiring layer 205, the first contact plug 207, the first via plug 209, and the first front bonding plug 213 may be arranged inside the first insulating layer 215. The first insulating layer 215 may surround a portion of the first shielding structure 230. The first shielding structure 230 may also extend downward from the bottom surface 215b of the first insulating layer 215 in the vertical direction D3. The first front bonding pad 211 may be disposed below the bottom surface 215b of the first insulating layer 215. The vertical height of the bottom surface 215b of the first insulating layer 215 may be higher than the vertical heights of the bottom surface 211b of the first front bonding pad 211 and the bottom surface 230b of the first shielding structure 230.

[0096] The first insulating layer 215 may include silicon oxide. The first passivation layer 216 may be disposed on the bottom surface 215 b of the first insulating layer 215 .

[0097] The first passivation layer 216 may surround the side surface of the first front bonding pad 211. The bottom surface of the first passivation layer 216 may be coplanar with the bottom surface 211b of the first front bonding pad 211 and the bottom surface 230b of the first shielding structure 230. The first passivation layer 216 may include silicon oxynitride. The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a backbonding through via 317, a second wiring layer 305, a second contact plug 307, a second via plug 309, a second front bonding pad 311, a second front bonding plug 313, a second shielding structure 330, a second insulating layer 315, and a second passivation layer 316.

[0098] The first front bonding pad 211 of the roof layer 200 may be bonded to the second front bonding pad 311 of the middle layer 300 .

[0099] The first passivation layer 216 of the roof layer 200 may be bonded to the second passivation layer 316 of the intermediate layer 300. The roof layer 200 and the intermediate layer 300 may have an interface FF where the front surface F of the roof layer 200 is bonded to the front surface F of the intermediate layer 300. The second substrate 301 may include a silicon substrate.

[0100] The second substrate 301 may include a second front surface 301f and a second rear surface 301b opposite to the second front surface 301f. The second transistor 303 may be disposed on the second front surface 301f of the second substrate 301. The second source region and the second drain region of the second transistor 303 may be disposed in the second substrate 301, but for convenience, the second source region and the second drain region of the second transistor 303 are shown in FIG. Figure 3 The second source region and the second drain region of the second transistor 303 are omitted. A through via hole VHO may be disposed inside the second substrate 301 to penetrate from the second front surface 301 f of the second substrate 301 to the second rear surface 301 b of the second substrate 301 .

[0101] A post-bonding through-via 317 insulated from the second substrate 301 by a second insulating layer 315 may be disposed in the through-via VHO. The second contact plug 307 and the second wiring layer 305 may be connected to the second transistor 303.

[0102] The second contact plug 307 may include a conductive metal. For example, the second contact plug 307 may include tungsten. The second contact plug 307 and the second wiring layer 305 may be connected to the second pre-bonding pad 311 and the post-bonding through-via 317. There may be a plurality of second wiring layers 305.

[0103] Two different second wiring layers 305 among the plurality of second wiring layers 305 may be at different vertical heights. In other words, the plurality of second wiring layers 305 may form a multi-layer structure. The second wiring layer 305 may be connected to the second via plug 309.

[0104] The second via plug 309 may connect at least two second wiring layers 305 at different vertical heights to each other. The second pre-bonding pad 311 may be at the top of the intermediate layer 300.

[0105] The second pre-bonding pad 311 may be connected to the second pre-bonding plug 313. The second pre-bonding plug 313 may extend in the vertical direction D3 and be connected to the second wiring layer 305. For example, the second pre-bonding plug 313 may extend in the vertical direction D3 toward the second front surface 301f of the second substrate 301. For example, the second pre-bonding pad 311 and the second pre-bonding plug 313 may be integrally formed.

[0106] In other words, the boundary between the second pre-bonding pad 311 and the second pre-bonding plug 313 may not be observable. The second pre-bonding pad 311 may be electrically connected to the second transistor 303 through the second pre-bonding plug 313, the second wiring layer 305, the second via plug 309, and the second contact plug 307.

[0107] For example, the second pre-bonding pad 311 may be electrically connected to Figure 2 the source-follower gate of the source-follower transistor SF in. The second wiring layer 305 may have a sixth thickness T6.

[0108] The second via plug 309 may have a seventh thickness T7. The second pre-bonding pad 311 may have an eighth thickness T8. The second pre-bonding plug 313 may have a ninth thickness T9. The sixth thickness T6 may correspond to the length of the second wiring layer 305 in the vertical direction D3.

[0109] The seventh thickness T7 may correspond to the length of the second via plug 309 in the vertical direction D3. The eighth thickness T8 may correspond to the length of the second front bonding pad 311 in the vertical direction D3. The ninth thickness T9 may correspond to the length of the second front bonding plug 313 in the vertical direction D3. The eighth thickness T8 of the second front bonding pad 311 may be smaller than the sixth thickness T6 of the second wiring layer 305.

[0110] The ninth thickness T9 of the second front bonding plug 313 may be larger than the seventh thickness T7 of the second via plug 309. The second shielding structure 330 may be disposed beside the second front bonding pad 311.

[0111] The second shielding structure 330 may be separated from the second front bonding pad 311 in the first horizontal direction D1. The second shielding structure 330 may be between two second front bonding pads 311 adjacent to each other along the first horizontal direction D1. The second shielding structure 330 may extend toward the second front surface 301f of the second substrate 301 in the vertical direction D3. The second shielding structure 330 may be separated from the second front bonding pad 311, the second front bonding plug 313, the second wiring layer 305, and the second via plug 309. The second shielding structure 330 may include a third portion and a fourth portion. The third portion is separated from the second front bonding pad 311 in the first horizontal direction D1, and the fourth portion is separated from the second front bonding plug 313 in the first horizontal direction D1.

[0112] The third portion of the second shielding structure 330 may be disposed at the same vertical height as the second front bonding pad 311. The fourth portion of the second shielding structure 330 may be disposed at the same vertical height as the second front bonding plug 313. The third portion and the fourth portion of the second shielding structure 330 may be integrally formed. The second shielding structure 330 may be vertically stacked with the pixel isolation layer 217.

[0113] In a plan view, the second shielding structure 330 may be stacked with the pixel isolation layer 217. The top surface 330a of the second shielding structure 330 may be coplanar with the top surface 311a of the second front bonding pad 311.

[0114] The vertical height of the bottom surface 330b of the second shielding structure 330 may be lower than the vertical height of the bottom surface 311b of the second front bonding pad 311. The vertical height of the bottom surface 330b of the second shielding structure 330 may be higher than the vertical height of the bottom surface 313b of the second front bonding plug 313. The second shielding structure 330 may have a tenth thickness T10.

[0115] The tenth thickness T10 may correspond to the length of the second shielding structure 330 in the vertical direction D3. The tenth thickness T10 of the second shielding structure 330 may be greater than the eighth thickness T8 of the second front bonding pad 311. The tenth thickness T10 of the second shielding structure 330 may be smaller than the sum of the eighth thickness T8 of the second front bonding pad 311 and the ninth thickness T9 of the second front bonding plug 313. For example, the width of the second shielding structure 330 in the first horizontal direction D1 may be substantially the same as the width of the first shielding structure 230 in the first horizontal direction D1.

[0116] In Figure 4 the cross-sectional view of, the width of the second shielding structure 330 in the first horizontal direction D1 may be smaller than the width of the second front bonding pad 311 in the first horizontal direction D1.

[0117] The width of the second shielding structure 330 in the first horizontal direction D1 may be less than or substantially equal to the width of the second front bonding plug 313 in the first horizontal direction D1. The second shielding structure 330 may be in contact with the first shielding structure 230.

[0118] Specifically, at least a part of the top surface 330a of the second shielding structure 330 may be in contact with at least a part of the bottom surface 230b of the first shielding structure 230. The second shielding structure 330 may be connected to the first shielding structure 230. The second wiring layer 305, the second via plug 309, the second front bonding pad 311, the second front bonding plug 313, and the second shielding structure 330 may include the same material.

[0119] The second wiring layer 305, the second via plug 309, the second front bonding pad 311, the second front bonding plug 313, and the second shielding structure 330 may include a conductive metal. For example, the second wiring layer 305, the second via plug 309, the second front bonding pad 311, the second front bonding plug 313, and the second shielding structure 330 may include copper. The second insulating layer 315 may be disposed on the second front surface 301f of the second substrate 301.

[0120] The second wiring layer 305, the second contact plug 307, the second via plug 309, and the second front bonding plug 313 may be disposed inside the second insulating layer 315. The second insulating layer 315 may surround a part of the second shielding structure 330. The second shielding structure 330 may further extend upward from the top surface 315a of the second insulating layer 315 in the vertical direction D3. The second front bonding pad 311 may be disposed above the top surface 315a of the second insulating layer 315. The vertical height of the top surface 315a of the second insulating layer 315 may be lower than the vertical heights of the top surface 311a of the second front bonding pad 311 and the top surface 330a of the second shielding structure 330.

[0121] The second insulating layer 315 may include silicon oxide. The second passivation layer 316 may be disposed on the top surface 315a of the second insulating layer 315.

[0122] The second passivation layer 316 may surround the side surface of the second front bonding pad 311. The top surface of the second passivation layer 316 may be coplanar with the top surface 311a of the second front bonding pad 311 and the top surface 330a of the second shielding structure 330. The second passivation layer 316 may include silicon oxynitride. The bottom layer 400 may include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, third contact plugs 407, a third front bonding pad 411, third via plugs 406, and a third insulating layer 415.

[0123] The back bonding through hole 317 of the intermediate layer 300 may be bonded to the third front bonding pad 411 of the bottom layer 400.

[0124] The second insulating layer 315 and the second substrate 301 of the intermediate layer 300 may be bonded to the third insulating layer 415 of the bottom layer 400. The intermediate layer 300 and the bottom layer 400 may have an interface B-F, at which the back surface B of the intermediate layer 300 is bonded to the front surface F of the bottom layer 400. The third substrate 401 may include a silicon substrate.

[0125] The third substrate 401 may include a third front surface 401f and a third back surface 401b opposite to the third front surface 401f. The third transistors 403 may be disposed on the third front surface 401f of the third substrate 401. The third source regions and the third drain regions of the third transistors 403 may be disposed in the third substrate 401, but for convenience, the third source regions and the third drain regions of the third transistors 403 are omitted. Figure 3 The third contact plugs 407 and the third wiring layer 405 may be connected to the third transistors 403.

[0126] The third contact plugs 407 may include a metal layer (e.g., a tungsten layer). The third wiring layer 405 may be connected to the third front bonding pad 411 through the third via plugs 406. The third contact plugs 407 and the third wiring layer 405 may be connected to the third front bonding pad 411. The third front bonding pad 411, the third wiring layer 405, and the third via plugs 406 may include a conductive metal. For example, the third front bonding pad 411, the third wiring layer 405, and the third via plugs 406 may include copper. In the image sensor EX1, the first front bonding pad 211 of the top layer 200 may be bonded to the second front bonding pad 311 of the intermediate layer 300, and the top layer 200 and the intermediate layer 300 may have an interface F-F, at which the front surface F of the top layer 200 is bonded to the front surface F of the intermediate layer 300.

[0127] In the image sensor EX1, the post-bonding vias 317 of the intermediate layer 300 can be bonded to the third pre-bonding pads 411 of the bottom layer 400.

[0128] The intermediate layer 300 and the bottom layer 400 can have an interface B-F, at which the rear surface B of the intermediate layer 300 is bonded to the front surface F of the bottom layer 400. When the vertical height of the top surface 230a of the first shielding structure 230 is lower than the vertical height of the top surface 211a of the first pre-bonding pad 211, it may be difficult to prevent coupling between two first pre-bonding plugs 213 adjacent to each other in the first horizontal direction D1.

[0129] The coupling can be enhanced with the miniaturization of the image sensor EX1. According to the disclosure, the image sensor EX1 can include a bottom layer 400, an intermediate layer 300, and a top layer 200 stacked in sequence.

[0130] The top layer 200 can include a first pre-bonding pad 211 at the bottom of the top layer 200, a first pre-bonding plug 213 connected to the first pre-bonding pad 211 and extending upward in the vertical direction D3, and a first shielding structure 230 between two first pre-bonding pads 211 adjacent to each other in the first horizontal direction D1. The vertical height of the top surface 230a of the first shielding structure 230 can be higher than the vertical height of the top surface 211a of the first pre-bonding pad 211. The intermediate layer 300 can include a second pre-bonding pad 311 on the top of the intermediate layer 300, a second pre-bonding plug 313 connected to the second pre-bonding pad 311 and extending downward in the vertical direction D3, and a second shielding structure 330 between two second pre-bonding pads 311 adjacent to each other in the first horizontal direction D1.

[0131] The vertical height of the bottom surface 330b of the second shielding structure 330 can be lower than the vertical height of the bottom surface 311b of the second pre-bonding pad 311. Therefore, coupling may not occur between two first pre-bonding plugs 213 adjacent to each other in the first horizontal direction D1.

[0132] For these reasons, the electrical characteristics and reliability of the image sensor EX1 can be improved. In Figure 4 the cross-sectional view, the width of the first shielding structure 230 in the first horizontal direction D1 can be smaller than the width of the first pre-bonding pad 211 in the first horizontal direction D1.

[0133] The width of the first shielding structure 230 in the first horizontal direction D1 can be less than or substantially equal to the width of the first pre-bonding plug 213 in the first horizontal direction D1. In Figure 4 the cross-sectional view, the width of the second shielding structure 330 in the first horizontal direction D1 can be smaller than the width of the second pre-bonding pad 311 in the first horizontal direction D1.

[0134] The width of the second shielding structure 330 in the first horizontal direction D1 may be less than or substantially equal to the width of the second front bonding plug 313 in the first horizontal direction D1. Accordingly, the space occupied by the first shielding structure 230 and the second shielding structure 330 can be minimized. For these reasons, the integration density of the image sensor EX1 can be increased.

[0135] Figure 5 is a schematic plan view showing the structure of an image sensor according to an embodiment. Specifically, Figure 5 is a plan view showing the planar layout relationship between the first front bonding pad 211 and the first shielding structure 230 described with reference to Figure 3 and Figure 4 or the planar layout relationship between the second front bonding pad 311 and the second shielding structure 330 described with reference to Figure 3 and Figure 4 The redundant descriptions given above with reference to Figure 5 are omitted from the following description. Referring to Figure 3 and Figure 4 The first front bonding pad 211 and the second front bonding pad 311 may have a rectangular planar shape. Figure 5 However, this is merely an example. The first front bonding pad 211 and the second front bonding pad 311 may have various planar shapes (such as circular, elliptical, polygonal, and annular). There may be a plurality of first front bonding pads 211.

[0136] There may be a plurality of second front bonding pads 311. The first front bonding pads 211 may be two-dimensionally arranged in the first horizontal direction D1 and the second horizontal direction D2. The second front bonding pads 311 may be two-dimensionally arranged in the first horizontal direction D1 and the second horizontal direction D2. One of the first front bonding pads 211 may be stacked with one of the second front bonding pads 311 in the vertical direction D3.

[0137] The first front bonding pad 211 may be stacked with the first front bonding plug 213 in the vertical direction D3. The second front bonding pad 311 may be stacked with the second front bonding plug 313 in the vertical direction D3. The first shielding structure 230 may be between two first front bonding pads 211 adjacent to each other along the first horizontal direction D1.

[0138] There may be a plurality of first shielding structures 230. The first shielding structure 230 may extend in the second horizontal direction D2. The second shielding structure 330 may be between two second front bonding pads 311 adjacent to each other along the first horizontal direction D1. There may be a plurality of second shielding structures 330. The second shielding structure 330 may extend in the second horizontal direction D2. One of the first shielding structures 230 may be stacked with one of the second shielding structures 330 in the vertical direction D3.

[0139] There may be a plurality of first shielding structures 230. The first shielding structure 230 may extend in the second horizontal direction D2. The second shielding structure 330 may be between two second front bonding pads 311 adjacent to each other along the first horizontal direction D1. There may be a plurality of second shielding structures 330. The second shielding structure 330 may extend in the second horizontal direction D2. One of the first shielding structures 230 may be stacked with one of the second shielding structures 330 in the vertical direction D3.

[0140] Figure 6 is a schematic plan view showing the structure of an image sensor according to an embodiment.

[0141] Specifically, Figure 6 is a plan view showing the planar layout relationship between the first front bonding pad 211 and the first shielding structure 230 that has been described with reference to Figure 3 and Figure 4 or the planar layout relationship between the second front bonding pad 311 and the second shielding structure 330 that has been described with reference to Figure 3 and Figure 4 The redundant descriptions given above with reference to Figure 6 are omitted from the following description. Referring to Figure 3 and Figure 4 , the first front bonding pad 211 and the second front bonding pad 311 may have a rectangular planar shape. Figure 6 However, this is merely an example. The first front bonding pad 211 and the second front bonding pad 311 may have various planar shapes (such as circular, oval, polygonal, and annular). There may be multiple first front bonding pads 211.

[0142] There may be multiple second front bonding pads 311. The first front bonding pad 211 may be two-dimensionally arranged in a first horizontal direction D1 and a second horizontal direction D2. The second front bonding pad 311 may be two-dimensionally arranged in the first horizontal direction D1 and the second horizontal direction D2. One of the first front bonding pads 211 may be stacked with one of the second front bonding pads 311 in a vertical direction D3.

[0143] The first front bonding pad 211 may be stacked with the first front bonding plug 213 in the vertical direction D3. The second front bonding pad 311 may be stacked with the second front bonding plug 313 in the vertical direction D3. In the plan view, the first shielding structure 230 may surround the first front bonding pad 211.

[0144] In the plan view, the first shielding structure 230 may surround the first front bonding plug 213. In the plan view, the first shielding structure 230 may have a grid shape. The first shielding structure 230 may extend in the first horizontal direction D1 and the second horizontal direction D2. In the plan view, the second shielding structure 330 may surround the second front bonding pad 311.

[0145] In the plan view, the second shielding structure 330 may surround the second front bonding plug 313. In the plan view, the second shielding structure 330 may have a grid shape. The second shielding structure 330 may extend in the first horizontal direction D1 and the second horizontal direction D2.

[0146] In the plan view, the second shielding structure 330 may surround the second front bonding plug 313. In the plan view, the second shielding structure 330 may have a grid shape. The second shielding structure 330 may extend in the first horizontal direction D1 and the second horizontal direction D2.

[0147] Figure 7is a schematic cross-sectional view showing the structure of an image sensor according to an embodiment. Figure 8 is Figure 7 an enlarged view of the region PP2 in Figure 7 and Figure 8 The above reference Figure 3 and Figure 4 gives redundant descriptions which are omitted herein. Referring to Figure 7 and Figure 8 the image sensor EX2 may include a bottom layer 400, an intermediate layer 300, and a top layer 200 that are sequentially stacked.

[0148] The top layer 200 may include a first substrate 201, a pixel isolation layer 217, a color filter 219, a lens 221, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first via plug 209, a first front bonding pad 211, a first front bonding plug 213, a first shielding structure 230, a first insulating layer 215, and a first passivation layer 216.

[0149] The vertical height of the top surface 230a of the first shielding structure 230 may be higher than the vertical height of the top surface 213a of the first front bonding plug 213.

[0150] The first front bonding pad 211 may have a third thickness T3.

[0151] The first front bonding plug 213 may have a fourth thickness T4. The first shielding structure 230 may have a fifth thickness T5. The fifth thickness T5 of the first shielding structure 230 may be greater than the sum of the third thickness T3 of the first front bonding pad 211 and the fourth thickness T4 of the first front bonding plug 213. The fifth thickness T5 of the first shielding structure 230 may be different from the fourth thickness T4 of the first front side bonding plug 213. The fifth thickness T5 of the first shielding structure 230 may be greater than the fourth thickness T4 of the first front bonding plug 213. The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a back bonding through via 317, a second wiring layer 305, a second contact plug 307, a second via plug 309, a second front bonding pad 311, a second front bonding plug 313, a second shielding structure 330, a second insulating layer 315, and a second passivation layer 316.

[0152] The vertical height of the bottom surface 330b of the second shielding structure 330 may be lower than the vertical height of the bottom surface 313b of the second front bonding plug 313.

[0153] The second front bonding pad 311 may have an eighth thickness T8.

[0154] The second front bonding plug 313 may have a ninth thickness T9. The second shielding structure 330 may have a tenth thickness T10. The tenth thickness T10 of the second shielding structure 330 may be greater than the sum of the eighth thickness T8 of the second front bonding pad 311 and the ninth thickness T9 of the second front bonding plug 313.

[0155] Figures 9 to 15 is a cross-sectional view showing a method of manufacturing Figure 3 the image sensor EX1 according to an embodiment. The redundant descriptions referred to above Figure 3 and Figure 4 are brief, or the redundant descriptions referred to above are omitted from the following Figures 9 to 15 description. Figure 3 and Figure 4 given.

[0156] Referring to Figure 9 , a first substrate 201 may be provided. The first substrate 201 may include a first front surface 201f and a first back surface 201b opposite to the first front surface 201f. A pixel isolation layer 217 may be formed in the first substrate 201. A plurality of first transistors 203 may be formed on the first front surface 201f of the first substrate 201. A first contact plug 207, a first wiring layer 205, and a first via plug 209 may be formed to connect to each first transistor 203. A first insulating layer 215 may be formed on the first front surface 201f of the first substrate 201 to cover the first contact plug 207, the first wiring layer 205, and the first via plug 209. A first passivation film 216a may be formed on the first insulating layer 215.

[0157] A protective insulating layer ILD may be formed on the first passivation film 216a. The first passivation film 216a may include silicon oxynitride. The protective insulating layer ILD may include silicon oxide. A first mask pattern PM1 may be formed on the protective insulating layer ILD.

[0158] The first mask pattern PM1 may include a first opening OP1 exposing at least a part of the top surface of the protective insulating layer ILD. There may be a plurality of first openings OP1.

[0159] Referring to Figure 10 , a first etching process ET1 may be performed on the protective insulating layer ILD, the first passivation film 216a, and the first insulating layer 215 by using the first mask pattern PM1 as an etching mask. The first etching process ET1 may use dry etching. Due to the first etching process ET1, a first hole H1 and a second hole H2 may be formed to penetrate the protective insulating layer ILD and the first passivation film 216a.

[0160] The first hole H1 and the second hole H2 may each further penetrate a part of the first insulating layer 215. However, the first hole H1 and the second hole H2 may not expose the first wiring layer 205. Each of the first hole H1 and the second hole H2 may be stacked with at least one of the first openings OP1 in the vertical direction D3. There may be a plurality of first holes H1 and a plurality of second holes H2.

[0161] Referring to Figure 11 , the first mask pattern PM1 in Figure 10 may be removed. Subsequently, a sacrificial film SL filling the first hole H1 and the second hole H2 may be formed. The sacrificial film SL may cover the top surface of the protective insulating layer ILD. The sacrificial film SL may include a polymer material. A second mask pattern PM2 may be formed on the sacrificial film SL.

[0162] The second mask pattern PM2 may include a second opening OP2 exposing at least a part of the top surface of the sacrificial film SL. The second opening OP2 may be stacked with the first hole H1 in the vertical direction D3. The width of the second opening OP2 in the first horizontal direction D1 may be larger than the width of the first hole H1 in the first horizontal direction D1. The second opening OP2 may not be stacked with the second hole H2 in the vertical direction D3. Referring to Figure 12 , a second etching process ET2 may be performed on the sacrificial film SL by using the second mask pattern PM2 as an etching mask.

[0163] The second etching process ET2 may use dry etching. Due to the second etching process ET2, a part of the sacrificial film SL may be removed.

[0164] The removed part of the sacrificial film SL may correspond to the part of the sacrificial film SL stacked with the second opening OP2 in the vertical direction D3. Due to the second etching process ET2, the part of the sacrificial film SL filling the first hole H1 may be removed. Due to the second etching process ET2, the part of the sacrificial film SL on the protective insulating layer ILD may be removed. When a part of the sacrificial film SL is removed by the second etching process ET2, a third opening OP3 may be formed in the sacrificial film SL.

[0165] The width of the third opening OP3 in the first horizontal direction D1 may be substantially the same as the width of the second opening OP2 in the first horizontal direction D1. The width of the third opening OP3 in the first horizontal direction D1 may be larger than the width of the first hole H1 in the first horizontal direction D1. Due to the second etching process ET2, the thickness of the second mask pattern PM2 may be reduced. However, the second mask pattern PM2 may not be completely removed but may be partially retained.

[0166] Referring to Figure 13 , by using Figure 12The second mask pattern PM2 in [[MASK]] is used as an etching mask to perform a third etching process ET3 on the protective insulating layer ILD, the first passivation film 216a, and the first insulating layer 215.

[0167] The third etching process ET3 can use dry etching. Each of the protective insulating layer ILD, the first passivation film 216a, and the first insulating layer 215 can be partially removed by the third etching process ET3, thereby forming a third hole H3.

[0168] At the vertical height where the protective insulating layer ILD overlaps with the first passivation film 216a in the vertical direction D3, the width of the third hole H3 in the first horizontal direction D1 can be substantially the same as the width of the third opening OP3 in the first horizontal direction D1. As a part of the first insulating layer 215 is further etched by the third etching process ET3, at least a part of the first wiring layer 205 can be exposed.

[0169] Subsequently, the second mask pattern PM2 can be removed.

[0170] Referring to Figure 14 , the sacrificial film SL can be removed, and a conductive film PCL can be formed to fill the second hole H2 and the third hole H3.

[0171] A conductive film PCL can also be formed on the top surface of the protective insulating layer ILD. The conductive film PCL can contact the first wiring layer 205 through the third hole H3. Referring to Figure 15 , a Figure 14 planarization process can be performed on the conductive film PCL, the protective insulating layer ILD, and the first passivation film 216a in [[MASK]].

[0172] For example, the planarization process can include chemical mechanical polishing (CMP). Due to the planarization process, a first front bonding pad 211, a first front bonding plug 213, and a first shielding structure 230 can be formed from the conductive film PCL in [[MASK]]. The protective insulating layer ILD can be completely removed by the planarization process. Due to the planarization process, a first passivation layer 216 can be formed from the first passivation film 216a. Returning to refer to Figure 14 Figure 3 , the first substrate 201 in [[MASK]] can be inverted. A color filter 219 and a lens 221 can be formed on the first rear surface 201b of the first substrate 201. Figure 15

[0173]

[0174] Therefore, the top layer 200 can be formed. The intermediate layer 300 can be prepared separately from the top layer 200.

[0174] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a back-bonding through via 317, a second wiring layer 305, a second contact plug 307, a second via plug 309, a second front-bonding pad 311, a second front-bonding plug 313, a second shielding structure 330, a second insulating layer 315, and a second passivation layer 316. The second substrate 301 may include a second front surface 301f and a second back surface 301b opposite to the second front surface 301f.

[0175] A through via VHO may be formed inside the second substrate 301 to penetrate from the second front surface 301f of the second substrate 301 to the second back surface 301b of the second substrate 301. A back-bonding through via 317 insulated from the second substrate 301 by the second insulating layer 315 may be formed in the through via VHO. The second transistors 303 may be formed on the second front surface 301f of the second substrate 301.

[0176] The second contact plugs 307, the second wiring layer 305, and the second via plugs 309 may be formed to connect to each of the second transistors 303. The second insulating layer 315 may be formed on the second front surface 301f of the second substrate 301 to cover the second contact plugs 307, the second wiring layer 305, and the second via plugs 309. The second front-bonding pad 311, the second front-bonding plug 313, the second shielding structure 330, and the second passivation layer 316 of the intermediate layer 300 may be formed by a method similar to the method of forming the first front-bonding pad 211, the first front-bonding plug 213, the first shielding structure 230, and the first passivation layer 216 described above with reference to Figures 9 to 15 The second front-bonding pad 311, the second front-bonding plug 313, the second shielding structure 330, and the second passivation layer 316 of the intermediate layer 300 may be formed by a method similar to the method of forming the first front-bonding pad 211, the first front-bonding plug 213, the first shielding structure 230, and the first passivation layer 216 described above with reference to

[0177] Subsequently, the first front-bonding pad 211 of the top layer 200 may be bonded to the second front-bonding pad 311 of the intermediate layer 300.

[0178] When the first front-bonding pad 211 and the second front-bonding pad 311 include copper, a copper pad (e.g., the first front-bonding pad 211) may be bonded to a copper pad (e.g., the second front-bonding pad 311). The bottom layer 400 may be prepared separately from the top layer 200 and the intermediate layer 300.

[0179] The bottom layer 400 may include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, a third contact plug 407, a third front-bonding pad 411, a third via plug 406, and a third insulating layer 415. The back-bonding through via 317 of the intermediate layer 300 may be bonded to the third front-bonding pad 411 of the bottom layer 400.

[0180] The second insulating layer 315 and the second substrate 301 of the intermediate layer 300 may be bonded to the third insulating layer 415 of the bottom layer 400. When the post-bonding vias 317 and the third pre-bonding pads 411 include copper, a copper via (e.g., the post-bonding via 317) may be bonded to a copper pad (e.g., the third pre-bonding pad 411). As a result, an Figure 3 image sensor EX1 may be manufactured.

[0181] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: A top layer, comprising: A first substrate, comprising a first front surface and a first back surface opposite to the first front surface, A first front bonding pad, below the first front surface, A first front bonding plug, connected to the first front bonding pad and extending in a vertical direction towards the first front surface, and A first shielding structure, separated from the first front bonding pad in a first horizontal direction; An intermediate layer, below the top layer and bonded to the top layer, the intermediate layer comprising: A second substrate, comprising a second front surface and a second back surface opposite to the second front surface, A second front bonding pad, above the second front surface, A second front bonding plug, connected to the second front bonding pad and extending in a vertical direction towards the second front surface, and A second shielding structure, separated from the second front bonding pad in a first horizontal direction; and A bottom layer, below the intermediate layer and bonded to the intermediate layer, the bottom layer comprising: a third substrate and transistors on the third substrate, Wherein, the vertical height of the top surface of the first shielding structure is higher than the vertical height of the top surface of the first front bonding pad.

2. The image sensor according to claim 1, wherein, The vertical height of the bottom surface of the second shielding structure is lower than the vertical height of the bottom surface of the second front bonding pad.

3. The image sensor according to claim 1, wherein, The width of the first shielding structure in the first horizontal direction is smaller than the width of the first front bonding pad in the first horizontal direction.

4. The image sensor according to claim 1, wherein, The width of the first shielding structure in the first horizontal direction is smaller than the width of the first front bonding plug in the first horizontal direction.

5. The image sensor according to claim 1, wherein The top layer further comprises: A first wiring layer and a second wiring layer, wherein the first wiring layer and the second wiring layer are between the first substrate and the first front bonding plug, the first wiring layer and the second wiring layer are at different vertical heights, and the first wiring layer is connected to the first front bonding plug; and A first via plug, connecting the first wiring layer to the second wiring layer, and Wherein, the length of the first front bonding plug in the vertical direction is larger than the length of the first via plug in the vertical direction.

6. The image sensor according to claim 1, wherein, The length of the first shielding structure in the vertical direction is larger than the sum of the length of the first front bonding pad in the vertical direction and the length of the first front bonding plug in the vertical direction.

7. The image sensor according to claim 1, wherein, The vertical height of the top surface of the first shielding structure is higher than the vertical height of the top surface of the first front bonding plug.

8. The image sensor according to claim 1, wherein, The top layer further comprises: a first wiring layer, between the first substrate and the first front bonding plug, Wherein, the first wiring layer is connected to the first front bonding plug, and Wherein, the length of the first front bonding pad in the vertical direction is smaller than the length of the first wiring layer in the vertical direction.

9. The image sensor according to claim 1, wherein, The top layer further comprises: a floating diffusion node, inside the first substrate, and Wherein, the first front bonding pad, the first front bonding plug, the second front bonding pad and the second front bonding plug are connected to the floating diffusion node.

10. The image sensor according to claim 1, wherein, The top layer further comprises: A first insulating layer, surrounding the first front bonding plug and covering the top surface of the first front bonding pad and a first part of the side surface of the first shielding structure; and A first passivation layer, below the first insulating layer, and Wherein, the first passivation layer surrounds a second part of the side surface of the first front bonding pad and the side surface of the first shielding structure.

11. The image sensor according to claim 10, wherein, The first shielding structure protrudes upward from the bottom surface of the first insulating layer towards the first substrate, and Wherein, the bottom surface of the first shielding structure is coplanar with the bottom surface of the first passivation layer.

12. The image sensor according to claim 10, wherein, The intermediate layer further comprises: A second insulating layer that surrounds a second front bonding plug and covers a bottom surface of a second front bonding pad and a first portion of a side surface of a second shielding structure; and A second passivation layer on the second insulating layer, wherein the second passivation layer surrounds a side surface of the second front bonding pad and a second portion of the side surface of the second shielding structure, and wherein a first shielding structure is in contact with the second shielding structure.

13. An image sensor, comprising: A top layer, comprising: A first substrate including a first front surface and a first back surface opposite to the first front surface, A first front bonding pad below the first front surface, A first front bonding plug connected to the first front bonding pad and extending in a vertical direction toward the first front surface, and A first shielding structure including a first portion separated from the first front bonding pad in a first horizontal direction and a second portion separated from the first front bonding plug in the first horizontal direction; An intermediate layer below the top layer and bonded to the top layer, the intermediate layer comprising: A second substrate including a second front surface and a second back surface opposite to the second front surface, A second front bonding pad above the second front surface, A second front bonding plug connected to the second front bonding pad and extending in a vertical direction toward the second front surface, and A second shielding structure including a third portion separated from the second front bonding pad in the first horizontal direction and a fourth portion separated from the second front bonding plug in the first horizontal direction; and A bottom layer below the intermediate layer and bonded to the intermediate layer, the bottom layer comprising: a third substrate and transistors on the third substrate, wherein the first shielding structure and the second shielding structure extend in a second horizontal direction intersecting the first horizontal direction.

14. The image sensor according to claim 13, wherein, Viewed from a planar perspective, the first shielding structure surrounds the first front bonding pad and the first front bonding plug.

15. The image sensor according to claim 13, wherein, Viewed from a planar perspective, the first shielding structure has a grid shape.

16. The image sensor according to claim 13, wherein, The first front bonding pad and the first front bonding plug are integrally formed.

17. The image sensor according to any one of claims 13 to 16, wherein, The length of the first shielding structure in the vertical direction is greater than the length of the first front bonding plug in the vertical direction.

18. An image sensor, comprising: A top layer, comprising: A first substrate including a first front surface and a first back surface opposite to the first front surface, A color filter and a lens sequentially stacked on the first back surface, A pixel isolation layer penetrating the first substrate, A first transistor on a first front surface of the first substrate, A first contact plug connected to the first transistor, A first wiring layer below the first contact plug and connected to the first contact plug, A first front bonding plug below the first wiring layer and connected to the first wiring layer, A first front bonding pad below the first front bonding plug and in contact with the first front bonding plug, and A first shielding structure separated from the first front bonding pad in a first horizontal direction; An intermediate layer below the top layer and bonded to the top layer, the intermediate layer comprising: A second substrate including a second front surface and a second back surface opposite to the second front surface, A second transistor on the second front surface, A second contact plug connected to the second transistor, A second wiring layer above the second contact plug and connected to the second contact plug, A second front bonding plug above the second wiring layer and connected to the second wiring layer, A second front bonding pad, above the second front bonding plug and in contact with the second front bonding plug; and A second shielding structure, separated from the second front bonding pad in a first horizontal direction; and A bottom layer, below the intermediate layer and bonded to the intermediate layer, the bottom layer including: a third substrate and transistors on the third substrate, wherein, the vertical height of the top surface of the first shielding structure is higher than the vertical height of the top surface of the first front bonding pad.

19. The image sensor according to claim 18, wherein, The vertical height of the bottom surface of the second shielding structure is lower than the vertical height of the bottom surface of the second front bonding pad.

20. The image sensor according to claim 18, wherein, The width of the first shielding structure in the first horizontal direction is smaller than the width of the first front bonding pad in the first horizontal direction.

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