Solar cell with double-sided selective passivation contact structure and preparation method thereof

Abstract

The invention discloses a solar cell with a double-sided selective passivation contact structure and a preparation method of the solar cell. The preparation method comprises the following steps: forming a PN junction on the front surface of a silicon wafer through high-temperature boron diffusion, and forming a boron-doped P-type polycrystalline silicon layer in a grid line region on the PN junction of the silicon wafer in a PECVD in-situ doping mode in combination with mechanical mask patterning; and forming a phosphorus-doped N-type polycrystalline silicon layer in a grid line region on the back surface of the silicon wafer in a PECVD in-situ doping mode in combination with mechanical mask patterning. Selective passivation contact structures are realized in grid line areas on the front surface and the back surface of the silicon wafer; and cleaning the silicon wafer, depositing a protective layer and preparing an electrode to prepare the battery. A selective passivation contact structure of a polycrystalline silicon interdigital grid line pattern is realized on two sides of a silicon wafer by adopting a PECVD in-situ technology and a mechanical mask mode. Contact resistance of the battery can be reduced, and open-circuit voltage, short-wave response and conversion efficiency of the battery can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell with a double-sided selective passivation contact structure prepared by a tube-type PECVD method and a preparation method thereof. Background Art

[0002] At present, the crystalline silicon cell market is mainly dominated by N-type TOPCon cells. Traditional TOPcon cells are mostly prepared by low-pressure chemical vapor deposition (LPCVD). This is a classic preparation method. Years of development have made this technology highly mature. Its process is simple and easy to prepare. However, as a vapor deposition technology, even when two silicon wafers are stacked together for processing, deposition products will still be formed on the other side and the side, that is, "wrap-around plating" occurs. Since the materials deposited on both sides of the cell have completely opposite properties, the wrap-around plating will cause leakage and a decline in cell properties. Therefore, if LPCVD is to be used to prepare a double-sided N-type TOPCon structure cell, it is necessary to repeatedly prepare and remove masks, which makes the preparation process cumbersome, time-consuming, and costly. In addition, for the traditional high-temperature diffusion method of preparing N-type TOPCon cells, due to the high boron diffusion temperature, large minority carrier lifetime recombination, difficult doping, and high sheet resistance after diffusion, the contact resistance in the metal region is large, and the cell conversion efficiency is not ideal.

[0003] How to overcome the defects of the existing technology in the preparation of cells, such as cumbersome process, high cost, high contact resistance, and low conversion efficiency, is a problem that needs to be solved as soon as possible in this field. Summary of the Invention

[0004] In order to solve the technical problems of the cumbersome process, high cost, high contact resistance, and low conversion efficiency in the preparation of N-type TOPCon cells in the existing technology, the present invention proposes a solar cell with a double-sided selective passivation contact structure prepared by a tube-type PECVD method and a preparation method thereof.

[0005] To solve the above technical problems, a preparation method of a solar cell with a double-sided selective passivation contact structure prepared by PECVD provided by the present invention is as follows:

[0006] Step 1: Process the front side of the silicon wafer

[0007] Clean and texture both sides of the N-type silicon wafer to form a pyramidal textured surface structure;

[0008] Form a PN junction and a boron-silicon glass layer on the front side of the silicon wafer by high-temperature boron diffusion; polish the front and back sides of the silicon wafer to remove the boron-silicon glass layer on the front side, and the back side becomes a polished surface;

[0009] A mask region and a non-mask region are formed on the front PN junction of the silicon wafer by in-situ PECVD combined with mechanical mask patterning, and a gate-line-shaped tunneling oxide layer, a boron-doped amorphous silicon layer, and a silicon oxide protective layer are prepared in the non-mask region;

[0010] The silicon wafer is subjected to high-temperature annealing, and boron atoms in the boron-doped amorphous silicon layer enter the activated state, causing the boron-doped amorphous silicon layer to crystallize to form a boron-doped P-type polycrystalline silicon layer, that is, a selective passivation contact structure is realized in the gate-line region on the front of the silicon wafer; at the same time, a borosilicate glass layer is also generated on the front of the silicon wafer;

[0011] Step 2: Process the back of the silicon wafer

[0012] A mask region and a non-mask region are formed on the back of the silicon wafer by in-situ PECVD combined with mechanical mask patterning, and a gate-line-shaped tunneling oxide layer, a phosphorus-doped amorphous silicon, and a silicon oxide protective layer are prepared in the non-mask region;

[0013] The silicon wafer is subjected to high-temperature annealing, and phosphorus atoms in the phosphorus-doped amorphous silicon layer enter the activated state, causing the phosphorus-doped amorphous silicon layer to crystallize to form a phosphorus-doped N-type polycrystalline silicon layer, that is, a selective passivation contact structure is realized in the gate-line region on the back of the silicon wafer; at the same time, a phosphosilicate glass layer is also generated on the back of the silicon wafer;

[0014] Step 3: Clean the silicon wafer, deposit a protective layer, and prepare electrodes

[0015] Remove the borosilicate glass layer and the silicon oxide protective layer on the front of the silicon wafer, and remove the phosphosilicate glass layer and the silicon oxide protective layer on the back of the silicon wafer;

[0016] Prepare an aluminum oxide layer on the front of the silicon wafer; prepare a silicon nitride layer, or a silicon nitride layer and a silicon oxide layer outside the aluminum oxide layer;

[0017] Prepare a silicon oxide layer and a silicon nitride layer on the back of the silicon wafer;

[0018] Prepare electrodes on the front and back of the silicon wafer by screen printing and sintering technology to obtain the N-type TOPCon battery of the present invention.

[0019] Preferably, the gate-line-shaped pattern in the non-mask region is an interdigitated gate-line-shaped pattern.

[0020] Preferably, in step 1, boron doping is carried out at a temperature of 820 °C - 910 °C; the temperature is raised to 1000 °C - 1100 °C for oxidation annealing to form the PN junction on the front of the silicon wafer.

[0021] Preferably, in step 1, the high-temperature annealing is carried out at 930 °C for 30 min, so that the boron-doped amorphous silicon layer crystallizes to form a boron-doped P-type polycrystalline silicon layer.

[0022] Preferably, in step 2, high-temperature annealing is carried out at 920 °C for 25 min, so that the phosphorus-doped amorphous silicon layer is crystallized to form a phosphorus-doped N-type polycrystalline silicon layer.

[0023] Another preparation method of a solar cell with a double-sided selective passivation contact structure prepared by PECVD provided by the present invention comprises the following steps:

[0024] Step 1: Deposit and process both sides of the silicon wafer

[0025] Clean and texture both sides of the N-type silicon wafer to form a pyramidal textured surface structure;

[0026] Form a PN junction and a layer of borosilicate glass on the front side of the silicon wafer by high-temperature boron diffusion; polish both the front and back sides of the silicon wafer to remove the borosilicate glass on the front side, and the back side becomes a polished surface;

[0027] Form a mask area and a non-mask area on the PN junction on the front side of the silicon wafer by PECVD in-situ method combined with mechanical mask patterning, and prepare a gate-line-shaped tunneling oxide layer, a boron-doped amorphous silicon layer and a silicon oxide protection layer in the non-mask area, and there is no amorphous silicon layer in the non-gate-line area;

[0028] Form a mask area and a non-mask area on the back side of the silicon wafer by PECVD in-situ method combined with mechanical mask patterning, and prepare a gate-line-shaped tunneling oxide layer, a phosphorus-doped amorphous silicon and a silicon oxide protection layer in the non-mask area, and there is no amorphous silicon layer in the non-gate-line area;

[0029] Step 2: Anneal the silicon wafer at high temperature at one time

[0030] Anneal the silicon wafer at high temperature. Boron atoms in the boron-doped amorphous silicon layer on the front side of the silicon wafer enter the activated state, so that the boron-doped amorphous silicon layer is crystallized to form a boron-doped P-type polycrystalline silicon layer, and a selective passivation contact structure is realized in the gate-line area on the front side of the silicon wafer; meanwhile, a layer of borosilicate glass is also generated on the front side of the silicon wafer;

[0031] Phosphorus atoms in the phosphorus-doped amorphous silicon layer on the back side of the silicon wafer enter the activated state, so that the phosphorus-doped amorphous silicon layer is crystallized to form a phosphorus-doped N-type polycrystalline silicon layer, and a selective passivation contact structure is realized in the gate-line area on the back side of the silicon wafer; meanwhile, a layer of phosphosilicate glass is also generated on the back side of the silicon wafer;

[0032] Step 3: Clean the silicon wafer, deposit a protection layer and prepare electrodes

[0033] Remove the borosilicate glass layer and the silicon oxide protection layer on the front side of the silicon wafer, and remove the phosphosilicate glass layer and the silicon oxide protection layer on the back side of the silicon wafer;

[0034] Prepare an alumina layer on the front side of the silicon wafer; prepare a silicon nitride layer, or a silicon nitride layer and a silicon oxide layer outside the alumina layer;

[0035] Prepare a silicon oxide layer and a silicon nitride layer on the back side of the silicon wafer;

[0036] Prepare electrodes on the front and back sides of the silicon wafer by screen printing and sintering technology to obtain the N-type TOPCon battery of the present invention.

[0037] Preferably, the grid-like pattern in the non-mask area is a finger-like grid pattern.

[0038] Preferably, in step 1, boron doping is carried out at a temperature of 820 °C - 910 °C; the temperature is raised to 1000 °C - 1100 °C for oxidation annealing to form the PN junction on the front side of the silicon wafer.

[0039] Preferably, in step 2, the high-temperature annealing is carried out at 925 °C for 35 min to form the boron-doped P-type polysilicon layer; the phosphorus-doped N-type polysilicon layer is formed.

[0040] The present invention also provides an N-type TOPCon battery with a double-sided selective passivation contact structure prepared by the above preparation method.

[0041] The technical effects achieved by the present invention are as follows:

[0042] The present invention uses the PECVD in-situ doping technology and mechanical mask patterning method to realize the selective passivation contact structure of the P-type amorphous silicon finger-like grid pattern on the front side (light-receiving side) of the silicon wafer, that is, to realize local boron heavy doping at the front grid line position, form a boron-doped P-type polysilicon layer, reduce the sheet resistance of the electrode area, and thus reduce the contact resistance of the battery. The non-grid line area is lightly doped and there is no amorphous silicon layer, which improves the open-circuit voltage and short-wave response, and finally improves the conversion efficiency of the battery.

[0043] Use the PECVD in-situ doping technology and mechanical mask patterning method to realize the selective passivation contact structure of the N-type amorphous silicon finger-like grid pattern on the back side (backlight side) of the silicon wafer. That is, to realize local phosphorus heavy doping at the back grid line position, reduce the sheet resistance of the electrode area, the non-grid line area is lightly doped and there is no amorphous silicon layer, further reduce the parasitic absorption of the battery, thereby reducing the contact resistance and back surface minority carrier recombination of the battery, increasing the short-circuit current, and finally improving the conversion efficiency of the battery. Description of the Drawings

[0044] Figure 1 It is a process flow schematic diagram of Example 1;

[0045] Figure 2 It is a process flow schematic diagram of Example 2;

[0046] Figure 3 It is a structural schematic diagram of the N-type TOPCon battery prepared by the preparation method of the present invention;

[0047] Figure 4 It is the light illumination I-V test curve graph of the TOPCon cell with the highest efficiency in the embodiment.

[0048] Among them Figure 3 : 100 is an N-type silicon wafer, 101 is a PN junction, 102 is a tunneling oxide layer, 103 is an interdigitated boron-doped P-type polysilicon layer, 104 is an interdigitated phosphorus-doped N-type polysilicon layer, 105 is an aluminum oxide layer, 106 is a silicon oxide layer, 107 is a silicon nitride layer, and 108 is a metal grid line. Specific implementation manners

[0049] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the present invention and do not constitute a limitation to the present invention.

[0050] Embodiment 1:

[0051] Please refer to Figure 1 、 Figure 3 as shown. A preparation method of an N-type TOPCon cell adopting a PECVD to prepare a double-sided selective passivation contact structure is provided by the present invention. The preparation method is as follows:

[0052] I. Processing the front side of the silicon wafer

[0053] An N-type silicon wafer 100 with a resistivity of 0.9 Ω·cm is used as a substrate. A trough cleaning device is adopted to remove the damaged layer and clean and texture both sides of the silicon wafer 100 to form an inverted pyramid-shaped light trapping structure.

[0054] The silicon wafer 100 is loaded into a quartz boat by means of a high-temperature boron diffusion method and sent into a diffusion furnace tube, and boron doping is carried out at a temperature of 820°C - 910°C; then the temperature is raised to 1000°C - 1100°C for oxidation annealing, so that boron atoms diffuse into the silicon wafer 100 and a PN junction 101 (also called a p+ emitter) is generated on the front side (light-receiving surface) of the silicon wafer 100. At the same time, a new BSG (boron silicate glass) layer is deposited on the surface, and the BSG layer can protect the diffusion surface in subsequent cleaning processes.

[0055] A trough polishing device is adopted to form a polished surface on the front side and the back side of the silicon wafer 100. That is, the newly deposited BSG on the front side is removed, and at the same time, the textured surface on the back side disappears and becomes a polished surface.

[0056] A mask area and a non-mask area are formed on the PN junction on the front side of the silicon wafer 100 by means of a PECVD in-situ doping technology and mechanical mask patterning, and a tunneling oxide layer 102 of an interdigitated grid line and a boron-doped amorphous silicon and silicon oxide protection layer are prepared in the non-mask area, that is:

[0057] Insert the silicon wafer into a graphite boat and send it into a furnace tube for discharge oxidation at 430 °C for 200 s. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 10000 W, and the pulse duty ratio is 20:1500. Oxidatively grow a 3-nm-thick SiOx layer on the polished surface of the front side of the silicon wafer. Subsequently, continue to introduce 2700 sccm of SiH4, 5000 sccm of H2, and 1000 sccm of TMB / BC3 into the furnace tube to deposit a 150-nm-thick boron-doped amorphous silicon layer. The deposition time is 650 s, the power is 12000 W, the pulse duty ratio is 30:450, and the pressure is 3100 mtorr. Finally, deposit a 30-nm-thick SiOx protective layer. The SiH4 flow rate is 1500 sccm, the N2O flow rate is 7500 sccm, the power is 9000 W, the pulse duty ratio is 30:600, and the time is 90 s. There is no amorphous silicon layer in the non-grid line area.

[0058] High-temperature annealing: The above-mentioned silicon wafer enters high-temperature annealing at 930 °C for 30 min, so that the first layer (the innermost layer close to the PN junction on the front side of the silicon wafer) of SiOx forms a tunneling oxide layer 102; under the action of high temperature, the boron atoms in the second layer of boron-doped amorphous silicon change from the non-activated state to the activated state, and the boron-doped amorphous silicon crystallizes to form doped polycrystalline silicon, that is, a finger-like boron-doped P-type polycrystalline silicon layer 103 is formed, that is, a passivated contact structure is realized in the grid line area on the front side of the silicon wafer; at the same time, a layer of BSG is generated on the front side of the silicon wafer by boron atoms and the silicon body. The third layer of silicon oxide deposited finally is a protective layer to protect the tunneling oxide layer and the boron-doped polycrystalline silicon layer inside, which will be removed later.

[0059] II. Process the back side of the silicon wafer

[0060] Form a mask area and a non-mask area on the polished surface of the back side of the silicon wafer 100 by PECVD in-situ doping technology and mechanical mask patterning, and prepare a tunneling oxide layer 102, a phosphorus-doped amorphous silicon 104, and a silicon oxide protective layer of finger-like grid lines in the non-mask area:

[0061] Insert the silicon wafer into a graphite boat and send it into the furnace tube for discharge oxidation at 430 °C for 90 s. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 10000 W, and the pulse switch ratio is 20:1500. A 1-nm-thick SiOx layer is oxidized and grown on the polished surface of the back of the silicon wafer. Subsequently, 2700 sccm of SiH4, 5000 sccm of H2, and 200 sccm of PH3 are continuously introduced into the furnace tube to deposit a 10-nm-thick phosphorus-doped amorphous silicon layer. The deposition time is 120 s, the power is 12000 W, the pulse switch ratio is 30:450, and the pressure is 3100 mtorr. Next, evacuate, and then 12000 sccm of N2O is continuously introduced into the furnace tube for discharge oxidation for 95 s to form a silicon oxide layer with a thickness of about 0.7 nm. After the next vacuuming, 2700 sccm of SiH4, 10000 sccm of H2, and 1000 sccm of PH3 are introduced into the furnace tube to deposit a 100-nm-thick phosphorus-doped amorphous silicon layer. The deposition time is 680 s, the power is 12500 w, and the pulse switch ratio is 30:360. Finally, a 20-nm-thick SiOx silicon oxide protective layer is deposited. The SiH4 flow rate is 1600 sccm, the N2O flow rate is 8000 sccm, the power is 10000 W, the pulse switch ratio is 30:600, and the time is 60 s. The above process deposits five layers: the first layer (innermost layer) is a 1-nm-thick SiOx, the second layer is a 10-nm-thick phosphorus-doped amorphous silicon, the third layer is a 0.7-nm-thick SiOx silicon oxide layer, the fourth layer is a 100-nm-thick phosphorus-doped amorphous silicon, and the fifth layer is a 20-nm-thick SiOx protective layer. There is no amorphous silicon layer in the non-grid line area.

[0062] High-temperature annealing: The silicon wafer enters high-temperature annealing at 920 °C for 25 min, so that the SiOx in the first layer (the innermost layer close to the back of the silicon wafer) forms a tunneling oxide layer 102; under the action of high temperature, the phosphorus atoms in the second layer of phosphorus-doped amorphous silicon change from the non-activated state to the activated state, and the amorphous silicon crystallizes to form doped polycrystalline silicon, that is, a finger-like phosphorus-doped polycrystalline silicon layer is formed; the SiOx in the third layer forms a new tunneling oxide layer; the fourth layer of phosphorus-doped amorphous silicon forms a new finger-like phosphorus-doped polycrystalline silicon layer. The above four layers constitute a stacked structure in which the tunneling oxide layer and the finger-like phosphorus-doped polycrystalline silicon layer are spaced apart - a finger-like phosphorus-doped N-type polycrystalline silicon layer 104. At the same time, PSG (phosphosilicate glass) is formed from phosphine and nitrous oxide; the fifth layer of SiOx is a protective layer.

[0063] III. Silicon wafer cleaning, deposition of protective layer and preparation of metal gate line 108

[0064] Use an HF tank to remove the SiOx protective layer on the front and back of the silicon wafer 100, and use a batch-type RCA cleaning equipment to remove the BSG layer on the front and the PSG layer on the back of the silicon wafer 100.

[0065] Using an ALD atomic layer deposition equipment, an alumina passivation layer 105 is deposited on the front side of the silicon wafer at a temperature of 200 °C. For example, it is fabricated using the ALD atomic layer deposition equipment of Shenzhen Jiejia Weichuang Co., Ltd.

[0066] A silicon nitride layer 107, or a silicon nitride layer and a silicon oxide layer, is prepared on the front side of the silicon wafer under the condition of 450 °C.

[0067] A silicon oxide layer 106 and a silicon nitride layer 107 are prepared on the periphery of the back side of the silicon wafer under the condition of 450 °C.

[0068] Electrodes are prepared by using the conventional screen printing and sintering technology, that is, metal grid lines 108 are prepared, and finally the N-type TOPCon cell described in the present invention is obtained.

[0069] Example 2:

[0070] Please refer to Figure 2 、 Figure 3 As shown. Another preparation method of an N-type TOPCon cell with a double-sided selective passivation contact structure prepared by PECVD provided by the present invention is as follows:

[0071] I. Deposition processing is carried out on the front side of the silicon wafer

[0072] An N-type silicon wafer 100 with a resistivity of 1.2 Ω·cm is used as a substrate, and a damage layer removal and cleaning and texturing are carried out on both sides of the silicon wafer 100 by using a tank cleaning equipment to form an inverted pyramid-shaped light trapping structure.

[0073] The silicon wafer 100 is loaded into a quartz boat by the high-temperature boron diffusion method and sent into a diffusion furnace tube, and boron doping is carried out at a temperature of 820 °C - 910 °C; then it is heated to 1000 °C - 1100 °C for oxidation annealing, so that boron atoms diffuse into the silicon wafer 100 and a PN junction 101 (also called a p+ emitter) is generated on the front side (light-receiving surface) of the silicon wafer 100, and a new BSG (boron silicon glass) layer is deposited on the surface. The BSG layer can protect the diffusion surface in the subsequent cleaning process.

[0074] A polishing surface is formed on the front side and the back side of the silicon wafer 100 by using a tank polishing equipment. That is, the newly deposited BSG layer on the front side is removed, and at the same time, the textured surface on the back side disappears and becomes a polishing surface.

[0075] A mask region and a non-mask region are formed on the PN junction by the PECVD in-situ doping technology and the mechanical mask patterning method, and a tunneling oxide layer 102 of finger-shaped grid lines and a boron-doped amorphous silicon and silicon oxide protection layer are prepared in the non-mask region, that is:

[0076] Insert the silicon wafer into the graphite boat and send it into the furnace tube for discharge oxidation at 430 °C for 200 s. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 10000 W, and the pulse duty ratio is 20:1500. A 3-nm-thick SiOx layer is grown by oxidation on the polished surface of the silicon wafer. Subsequently, 2700 sccm of SiH4, 5000 sccm of H2, and 1000 sccm of TMB / BC3 are continuously introduced into the furnace tube to deposit a 150-nm-thick boron-doped amorphous silicon layer. The deposition time is 650 s, the power is 12000 W, the pulse duty ratio is 30:450, and the pressure is 3100 mtorr. Finally, a 30-nm SiOx mask protection layer is deposited. The SiH4 flow rate is 1500 sccm, the N2O flow rate is 7500 sccm, the power is 9000 W, the pulse duty ratio is 30:600, and the time is 90 s. There is no amorphous silicon layer in the non-grid line area.

[0077] II. Perform deposition processing on the back side of the silicon wafer

[0078] Form a mask area and a non-mask area on the polished back surface of the silicon wafer 100 by PECVD in-situ doping technology and mechanical mask patterning, and prepare a tunneling oxide layer 102, a phosphorus-doped amorphous silicon 104, and a silicon oxide protection layer with interdigitated grid lines in the non-mask area:

[0079] Insert the silicon wafer into the graphite boat and send it into the furnace tube for discharge oxidation at 430 °C for 90 s. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 10000 W, and the pulse switch ratio is 20:1500. A 1-nm-thick SiOx layer is grown by oxidation on the polished surface of the silicon wafer. Subsequently, continue to introduce 2700 sccm of SiH4, 5000 sccm of H2, and 200 sccm of PH3 into the furnace tube to deposit a 10-nm-thick phosphorus-doped amorphous silicon layer. The deposition time is 120 s, the power is 12000 W, the pulse switch ratio is 30:450, and the pressure is 3100 mtorr. Next, evacuate, and then continue to introduce 12000 sccm of N2O into the furnace tube for discharge oxidation for 95 s to form a silicon oxide layer with a thickness of about 0.7 nm. After evacuating again, introduce 2700 sccm of SiH4, 10000 sccm of H2, and 1000 sccm of PH3 into the furnace tube to deposit a 100-nm-thick phosphorus-doped amorphous silicon layer. The deposition time is 680 s, the power is 12500 w, the pulse switch ratio is 30:360. Finally, deposit a 20-nm-thick SiOx silicon oxide protective layer. The SiH4 flow rate is 1600 sccm, the N2O flow rate is 8000 sccm, the power is 10000 W, the pulse switch ratio is 30:600, and the time is 60 s. The above process deposits five layers: the first layer (innermost layer) is a 1-nm-thick SiOx, the second layer is a 10-nm-thick phosphorus-doped amorphous silicon, the third layer is a 0.7-nm-thick silicon oxide layer, the fourth layer is a 100-nm-thick phosphorus-doped amorphous silicon, and the fifth layer is a 20-nm-thick SiOx protective layer. There is no amorphous silicon layer in the non-grid line area.

[0080] III. High-temperature annealing of the silicon wafer 100 at one time

[0081] Put the silicon wafer into high-temperature annealing at 925 °C for 35 min, so that the first layer (the innermost layer close to the PN junction on the front side of the silicon wafer) of SiOx on the front side of the silicon wafer forms a tunneling oxide layer 102; in the second layer of boron-doped amorphous silicon, under the action of high temperature, boron atoms change from the non-activated state to the activated state, and the boron-doped amorphous silicon crystallizes to form doped polycrystalline silicon, that is, a finger-like boron-doped P-type polycrystalline silicon layer 103 is formed; at the same time, a layer of BSG is generated on the front side of the silicon wafer by boron atoms and the silicon body. The third layer of silicon oxide deposited finally is a protective layer to protect the tunneling oxide layer and the boron-doped polycrystalline silicon layer inside, and then it will be removed later.

[0082] Meanwhile, the first layer of SiOx (the innermost layer close to the back surface of the silicon wafer) on the back surface of the silicon wafer forms the tunneling oxide layer 102; under the action of high temperature, the phosphorus atoms in the second layer of phosphorus-doped amorphous silicon change from the non-activated state to the activated state, and the amorphous silicon crystallizes to form doped polysilicon, that is, a finger-shaped phosphorus-doped polysilicon layer is formed; the SiOx in the third layer forms a new tunneling oxide layer; the fourth layer of phosphorus-doped amorphous silicon forms a new finger-shaped phosphorus-doped polysilicon layer. The above four layers constitute a stacked structure in which the tunneling oxide layer and the finger-shaped phosphorus-doped polysilicon layer are spaced apart from each other - the finger-shaped phosphorus-doped N-type polysilicon layer 104. Meanwhile, PSG (phosphosilicate glass) is formed from phosphine and nitrous oxide; the fifth layer of SiOx is a protective layer.

[0083] IV. Silicon Wafer Cleaning, Deposition of Protective Layer and Fabrication of Metal Gate Line 108

[0084] Use an HF tank to remove the SiOx mask protective layer on the front and back surfaces of the silicon wafer 100, and use a batch-type RCA cleaning equipment to remove the BSG layer on the front surface and the PSG layer on the back surface of the silicon wafer 100.

[0085] Use an ALD atomic layer deposition equipment to deposit an aluminum oxide passivation layer 105 on the front surface of the silicon wafer at a temperature of 200 °C. For example, use the ALD atomic layer deposition equipment of Shenzhen Jiejiaweichuang Co., Ltd. to fabricate.

[0086] Prepare a silicon nitride layer 107 on the front surface of the silicon wafer at 450 °C, or a silicon nitride layer and a silicon oxide layer.

[0087] Prepare a silicon oxide layer 106 and a silicon nitride layer 107 on the back surface of the silicon wafer at 450 °C.

[0088] Use the conventional screen printing and sintering technology to prepare the electrodes, that is, to fabricate the metal gate line 108, and finally obtain the N-type TOPCon battery described in the present invention.

[0089] As Figure 3 shown, the present invention also provides an N-type TOPCon battery with a double-sided selective passivation contact structure prepared by the above preparation method.

[0090] In the preparation of the solar cell of the present invention, the finger-shaped grid line amorphous silicon can be deposited on the front or back side of the silicon wafer, and then high-temperature annealing is carried out separately; or after the finger-shaped grid line amorphous silicon is deposited on the front and back sides of the silicon wafer respectively, high-temperature annealing is carried out on the front and back sides of the silicon wafer at one time. The present invention adopts the PECVD in-situ doping technology and the mechanical mask patterning method to realize the selective passivation contact structure of the P-type amorphous silicon finger-shaped grid line pattern on the front side (light-receiving surface) of the silicon wafer, forming a finger-shaped boron-doped P-type polysilicon layer, reducing the sheet resistance of the electrode region, and thus reducing the contact resistance of the battery. The non-grid line region is lightly doped and there is no amorphous silicon layer, improving the open-circuit voltage and short-wave response, and finally improving the conversion efficiency of the battery. The PECVD in-situ doping technology and the mechanical mask patterning method are adopted to realize the selective passivation contact structure of the N-type amorphous silicon finger-shaped grid line pattern on the back side (backlight surface) of the silicon wafer. That is, local phosphorus heavy doping is realized at the position of the back grid line, forming a finger-shaped phosphorus-doped N-type polysilicon layer, reducing the sheet resistance of the electrode region, the non-grid line region is lightly doped and there is no amorphous silicon layer, further reducing the parasitic absorption of the battery, thus reducing the contact resistance and the back minority carrier recombination of the battery, increasing the short-circuit current, and finally improving the conversion efficiency of the battery.

[0091] Comparative Example 1:

[0092] A traditional low-pressure chemical vapor deposition (LPCVD) is used to prepare an N-type TOPcon battery. Using an N-type silicon wafer as the substrate, the damage layer on both sides of the silicon wafer is removed and the wafer is cleaned and textured first to form an inverted pyramid-shaped light-trapping structure. A PN junction is formed on the front side of the silicon wafer; boron-doped amorphous silicon is prepared on the front-side PN junction of the silicon wafer by the LPCVD method, and then high-temperature annealing is carried out to obtain boron-doped P-type polysilicon; then phosphorus-doped amorphous silicon is prepared on the back side of the silicon wafer by the LPCVD method, and then high-temperature annealing is carried out to obtain phosphorus-doped N-type polysilicon. After cleaning the front and back sides of the silicon wafer, protective layers are prepared respectively. Finally, the electrodes are prepared by using the conventional screen printing and sintering technology. A traditional N-type TOPCon battery is prepared.

[0093] Next, the performance of the batteries of Example 1, Example 2 and Comparative Example 1 of the present invention is detected.

[0094] In the photovoltaic IV test, the commonly used test method is the variable load method, also known as the scan method (ScanMethod). This method measures the current and voltage output by the photovoltaic cell by changing the size of the load, so as to obtain the IV characteristic curve. The specific steps are as follows:

[0095] 1. Apply certain light conditions and temperature conditions to ensure the consistency and repeatability of the test environment.

[0096] 2. Use a test device to perform current-voltage scanning on the photovoltaic cell through a variable load, gradually increasing the voltage from zero to a certain value, then gradually decreasing it back to zero voltage, and finally increasing it to negative voltage.

[0097] 3. Measure the current and voltage values at each voltage point to obtain the IV characteristic curve.

[0098] 4. Calculate the key parameters of the photovoltaic cell based on the measured current and voltage values, such as open-circuit voltage (Voc), short-circuit current (Isc), maximum power point (MPP), etc.

[0099] 5. Test method

[0100] (1) Voc: The open-circuit voltage refers to the potential difference between the positive and negative electrodes when there is no current passing through the cell;

[0101] Calculation method: Multiply adjacent current values in the current array pairwise. When the result is less than or equal to zero, it indicates that the I-V line intersects the horizontal axis. At this time, the value in the corresponding voltage array is the open-circuit voltage.

[0102] (2) Isc: The short-circuit current is the current in the case of short-circuit of the positive and negative electrodes. Multiply adjacent voltage values in the current array pairwise. When the result is less than or equal to zero, it indicates that the I-V line intersects the horizontal axis. At this time, the value in the corresponding current array is the short-circuit current.

[0103] The open-circuit voltage (Voc) and short-circuit current (Isc) can be directly measured values

[0104] (3) Rs: Series resistance In any actual solar cell, there exists a series resistance, whose sources include the resistance of the positive grid metal grid line, the front and back metal-semiconductor contact resistances, the resistance of the front diffusion layer, the base region bulk resistance, and the resistance of the back electrode metal layer.

[0105] (4) FF: Fill factor The output power at any operating point on the volt-ampere characteristic curve of the photovoltaic cell is equal to the rectangular area corresponding to that point. Among them, only one point is the output maximum power, called the optimal operating point. The voltage and current at this point are called the optimal operating voltage Vmpp and the optimal operating current Impp, respectively.

[0106] FF = Impp * Vmpp / (Isc * Voc)

[0107] (5) Maximum power Pmpp = Isc * Voc * FF.

[0108] (6) Conversion efficiency η = Pmpp / (Pin * S) = Voc * Isc * FF / (Pin * S)

[0109] Where:

[0110] Pin is the incident optical power per unit area in W / m2. The standard optical intensity of Pin refers to: under the spectral AM1.5 and test temperature of 25 degrees Celsius, it is 1000 w / m2;

[0111] S is the area of a single battery cell in m2.

[0112] (7) Short - circuit current density Jsc, calculation formula:

[0113] Jsc = AIsc (unit: mA / cm 2 )

[0114] Where:

[0115] Isc: Short - circuit current (unit: mA)

[0116] A: Effective light - receiving area of the battery (unit: cm 2 )

[0117] Table 1

[0118] Detection items Example 1 Example 2 Comparative example Short-circuit current density (Jsc) 42.31 42.5 39.78 Fill factor (FF) 85.16％ 84 81.62 Open-circuit voltage (Voc) 738.7 mV 72.5 702.6 Conversion efficiency (η) 26.62 25.83 22.81

[0119] According to the detection data of Examples 1 and 2 and Comparative Example 1, as Figure 4 shown, applying the above formula to calculate the performance parameters of the battery, as shown in Table 1, the Examples of the present invention have a short - circuit current density (Jsc), fill factor (FF), open - circuit voltage (Voc) and conversion efficiency (η) all higher than those of the batteries prepared by the prior art. Therefore, through the technical improvement of the present invention, the performance of the TOPCon battery has been improved well.

[0120] The above is only the specific implementation manner of the present invention. It should be noted that any modifications, equivalent substitutions and changes made within the spirit and framework of the concept of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a solar cell with a double-sided selective passivation contact structure by PECVD, comprising the following steps: Step 1: Process the front side of the silicon wafer Clean and texturize both sides of the N-type silicon wafer; Form a PN junction and a borosilicate glass layer on the front side of the silicon wafer by high-temperature boron diffusion; polish the front and back sides of the silicon wafer to remove the borosilicate glass layer on the front side, and the back side becomes a polished surface; Form a mask area and a non-mask area on the PN junction on the front side of the silicon wafer by PECVD in-situ combined with mechanical mask patterning, and prepare a gate-like tunneling oxide layer, a boron-doped amorphous silicon layer, and a silicon oxide protection layer in the non-mask area; Anneal the silicon wafer at a high temperature to crystallize the boron-doped amorphous silicon layer to form a boron-doped P-type polycrystalline silicon layer, and achieve a selective passivation contact structure in the gate line area on the front side of the silicon wafer; a boride glass layer is also formed on the front side of the silicon wafer; Step 2: Process the back side of the silicon wafer Form a mask area and a non-mask area on the back side of the silicon wafer by PECVD in-situ combined with mechanical mask patterning, and prepare a gate-like tunneling oxide layer, a phosphorus-doped amorphous silicon, and a silicon oxide protection layer in the non-mask area; Anneal the silicon wafer at a high temperature to crystallize the phosphorus-doped amorphous silicon layer to form a phosphorus-doped N-type polycrystalline silicon layer, and achieve a selective passivation contact structure in the gate line area on the back side of the silicon wafer; a phosphide glass layer is also formed on the back side of the silicon wafer; Step 3: Clean the silicon wafer, deposit a protection layer, and prepare electrodes Remove the borosilicate glass layer and the silicon oxide protection layer on the front side of the silicon wafer, and remove the phosphide glass layer and the silicon oxide protection layer on the back side of the silicon wafer; Prepare an alumina layer on the front side of the silicon wafer; prepare a silicon nitride layer, or a silicon nitride layer and a silicon oxide layer outside the alumina layer; Prepare a silicon oxide layer and a silicon nitride layer on the back side of the silicon wafer; Prepare electrodes on the front and back sides of the silicon wafer by screen printing and sintering technology to obtain the N-type TOPCon battery.

2. The preparation method according to claim 1, characterized in that, The gate-like pattern in the non-mask area is a finger-like gate-like pattern.

3. The preparation method according to claim 1, characterized in that, In the step 1, boron doping is carried out at a temperature of 820 °C - 910 °C; the temperature is raised to 1000 °C - 1100 °C for oxidation annealing to form the PN junction on the front side of the silicon wafer.

4. The preparation method according to claim 1, characterized in that, In the step 1, the high-temperature annealing is carried out at 930 °C for 30 min to crystallize the boron-doped amorphous silicon layer to form a boron-doped P-type polycrystalline silicon layer.

5. The preparation method according to claim 1, wherein In the step 2, the high-temperature annealing is carried out at 920 °C for 25 min to crystallize the phosphorus-doped amorphous silicon layer to form a phosphorus-doped N-type polycrystalline silicon layer.

6. A method for preparing a solar cell with a double-sided selective passivation contact structure by PECVD, comprising the following steps: Step 1: Deposit and process both sides of the silicon wafer Clean and texturize both sides of the N-type silicon wafer; Form a PN junction and a layer of borosilicate glass on the front side of the silicon wafer by high-temperature boron diffusion; polish the front and back sides of the silicon wafer to remove the borosilicate glass on the front side, and the back side becomes a polished surface; Form a mask area and a non-mask area on the PN junction on the front side of the silicon wafer by PECVD in-situ combined with mechanical mask patterning, and prepare a gate-like tunneling oxide layer, a boron-doped amorphous silicon layer, and a silicon oxide protection layer in the non-mask area; A mask region and a non-mask region are formed on the back side of the silicon wafer by an in-situ PECVD method combined with mechanical mask patterning, and a gate-line-shaped tunneling oxide layer, a phosphorus-doped amorphous silicon, and a silicon oxide protective layer are prepared in the non-mask region; Step 2: Perform a one-time high-temperature annealing on the silicon wafer The silicon wafer is subjected to high-temperature annealing, so that the boron-doped amorphous silicon layer is crystallized to form a boron-doped P-type polycrystalline silicon layer, and a selective passivation contact structure is realized in the gate-line region on the front side of the silicon wafer; a boron-silicate glass layer is also formed on the front side of the silicon wafer; At the same time, the phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is crystallized to form a phosphorus-doped N-type polycrystalline silicon layer, and a selective passivation contact structure is realized in the gate-line region on the back side of the silicon wafer; a phosphorus-silicate glass layer is also formed on the back side of the silicon wafer; Step 3: Clean the silicon wafer, deposit a protective layer, and prepare electrodes Remove the boron-silicate glass layer and the silicon oxide protective layer on the front side of the silicon wafer, and remove the phosphorus-silicate glass layer and the silicon oxide protective layer on the back side of the silicon wafer; Prepare an aluminum oxide layer on the front side of the silicon wafer; prepare a silicon nitride layer, or a silicon nitride layer and a silicon oxide layer outside the aluminum oxide layer; Prepare a silicon oxide layer and a silicon nitride layer on the back side of the silicon wafer; Prepare electrodes on the front and back sides of the silicon wafer by using a screen printing and sintering technique to obtain the N-type TOPCon battery.

7. The preparation method according to claim 6, wherein The gate-line-shaped pattern in the non-mask region is an interdigital gate-line pattern.

8. The preparation method according to claim 6, characterized in that, In the step 1, boron doping is performed at a temperature of 820 °C - 910 °C; the temperature is raised to 1000 °C - 1100 °C for oxidation annealing, and the PN junction is formed on the front side of the silicon wafer.

9. The preparation method according to claim 6, characterized in that, In the step 2, the high-temperature annealing is performed at 925 °C for 35 min to form the boron-doped P-type polycrystalline silicon layer; the phosphorus-doped N-type polycrystalline silicon layer is formed.

10. A solar cell with a double-sided selective passivation contact structure, characterized in that, A solar cell with the double-sided selective passivation contact structure prepared by the preparation method according to claim 1 or claim 6.

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