Selective contact structure back junction solar cell and preparation method thereof

Abstract

The invention discloses a selective contact structure back junction solar cell and a preparation method thereof. The preparation method comprises the following steps: forming a PN junction in the back surface of a silicon wafer in a PECVD (Plasma Enhanced Chemical Vapor Deposition) in-situ doping mode, and forming a boron-doped P-type polysilicon layer on the back surface of the silicon wafer; forming a mask region and a non-mask region on the front surface of the silicon wafer in a PECVD (Plasma Enhanced Chemical Vapor Deposition) in-situ doping mode in combination with mechanical mask patterning, forming a phosphorus-doped N-type polycrystalline silicon layer in an interdigital grid line region of the non-mask region, and realizing a selective passivation contact structure in a grid line region on the back surface of the silicon wafer; and cleaning the silicon wafer, depositing a protective layer and preparing an electrode to prepare the battery. And the PN junction is formed on the back surface of the silicon wafer through the PECVD in-situ doping technology, so that the cost can be reduced. A selective passivation contact structure of an N-type amorphous silicon interdigital grid line pattern is realized on the front surface of a silicon wafer by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) in-situ technology and a mechanical mask mode. Contact resistance of the battery can be reduced, and open-circuit voltage, short-wave response and conversion efficiency of the battery can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back-junction solar cell with a selective passivation contact structure prepared by a tube-type PECVD method and a preparation method thereof. Background Art

[0002] At present, the crystalline silicon cell market is mainly dominated by N-type TOPCon cells. Traditional TOPcon cells are mostly prepared by low-pressure chemical vapor deposition (LPCVD). This is a classic preparation method. Years of development have made this technology highly mature. Its process is simple and easy to prepare. However, as a vapor deposition technology, even if two silicon wafers are stacked together for processing, deposition products will still be deposited on the other side and the side, that is, "wrap-around plating" occurs. Since the material properties of the deposits on both sides of the cell are completely opposite, the so-called wrap-around plating will cause leakage and a decline in cell properties. Therefore, if LPCVD is to be used to prepare a double-sided N-type TOPCon structure cell, the mask must be repeatedly prepared and removed, which makes the preparation process cumbersome, time-consuming, and costly. In addition, the existing technology prepares N-type TOPCon cells by high-temperature boron diffusion, that is, boron is diffused into the cell on the front side of the cell to form a PN junction. Therefore, the upper part of the cell is P and the lower part is N. Because the boron diffusion temperature is high, the minority carrier lifetime recombination is large, the doping difficulty is high, and the sheet resistance after diffusion is high, resulting in a large contact resistance in the metal region and an unsatisfactory cell conversion efficiency.

[0003] How to overcome the defects of the existing technology in preparing cells, such as cumbersome process, high cost, high contact resistance, and low conversion efficiency, is a problem that needs to be solved as soon as possible in this field. Summary of the Invention

[0004] In order to solve the technical problems of the existing technology in preparing solar cells, such as cumbersome process, high cost, high contact resistance, and low conversion efficiency, the present invention proposes a back-junction solar cell with a selective passivation contact structure prepared by a tube-type PECVD method and a preparation method thereof.

[0005] To solve the above technical problems, a preparation method of a back-junction solar cell with a selective contact structure prepared by PECVD provided by the present invention comprises the following steps:

[0006] Step 1, process the back side of the silicon wafer

[0007] Remove the damaged layer on both sides of the N-type silicon wafer and polish both sides;

[0008] Prepare a tunneling oxide layer and a boron-doped amorphous silicon layer on the back side of the silicon wafer by PECVD in-situ doping method;

[0009] The silicon wafer is subjected to high-temperature annealing, and the boron atoms in the boron-doped amorphous silicon layer enter the activated state, forming a PN junction inside the back surface of the silicon wafer. The surface of the silicon wafer is the tunneling oxide layer, and the boron-doped amorphous silicon layer crystallizes to form a boron-doped P-type polycrystalline silicon layer; meanwhile, a borosilicate glass layer is also formed on the back surface of the silicon wafer.

[0010] The borosilicate glass layer on the back surface of the silicon wafer and the boron-doped polycrystalline silicon layer plated around to the front surface of the silicon wafer are removed, and the front surface of the silicon wafer is subjected to texturing cleaning to form a pyramidal textured surface structure.

[0011] Step 2: Process the front surface of the silicon wafer

[0012] By means of PECVD in-situ doping combined with mechanical mask patterning, a mask region and a non-mask region are formed on the textured surface of the front surface of the silicon wafer, and a gate-line-shaped tunneling oxide layer, phosphorus-doped amorphous silicon, and silicon oxide protection layer are prepared in the non-mask region.

[0013] The silicon wafer is subjected to high-temperature annealing, and the phosphorus atoms in the phosphorus-doped amorphous silicon layer enter the activated state, causing the phosphorus-doped amorphous silicon layer to crystallize to form a phosphorus-doped N-type polycrystalline silicon layer, that is, a selective passivation contact structure is realized in the gate-line region on the back surface of the silicon wafer; meanwhile, a phosphorus-silicate glass layer (PSG) is also formed in the gate-line region on the front surface of the silicon wafer.

[0014] Step 3: Clean the silicon wafer, deposit a protection layer, and prepare electrodes

[0015] The borosilicate glass layer on the back surface of the silicon wafer is removed, and the phosphorus-silicate glass layer and the silicon oxide protection layer on the front surface of the silicon wafer are removed.

[0016] A silicon oxide layer and a silicon nitride layer are prepared on the front surface of the silicon wafer.

[0017] A silicon nitride layer is prepared outside the boron-doped P-type polycrystalline silicon layer on the back surface of the silicon wafer.

[0018] Electrodes are prepared on the front and back surfaces of the silicon wafer to obtain the N-type TOPCon battery of the present invention.

[0019] Preferably, in step 1, the high-temperature annealing is carried out at 920°C - 1050°C for 30 min.

[0020] Preferably, in step 2, the high-temperature annealing is carried out at 920°C for 35 min.

[0021] Preferably, the gate-line-shaped pattern in the non-mask region in step 2 is an interdigitated gate-line-shaped pattern.

[0022] Another preparation method of a back-junction solar cell using PECVD to prepare a selective contact structure provided by the present invention is as follows:

[0023] Step 1: Process the back and front sides of the silicon wafer.

[0024] Remove the damaged layer and perform double-sided polishing on both sides of the N-type silicon wafer.

[0025] Prepare a tunneling oxide layer and a boron-doped amorphous silicon layer on the back side of the silicon wafer by PECVD in-situ doping.

[0026] Remove the boron-doped amorphous silicon layer deposited on the front side of the silicon wafer and perform cleaning and texturing on the front side of the silicon wafer.

[0027] Form a mask area and a non-mask area on the textured surface of the front side of the silicon wafer by PECVD in-situ doping combined with mechanical mask patterning, and prepare a gate-line-shaped tunneling oxide layer, phosphorus-doped amorphous silicon, and silicon oxide protection layer in the non-mask area.

[0028] Step 2: Perform a one-time high-temperature annealing on the silicon wafer.

[0029] Perform high-temperature annealing on the silicon wafer. Boron atoms in the boron-doped amorphous silicon layer on the back side of the silicon wafer enter the activated state, forming a PN junction inside the back side of the silicon wafer. The surface of the silicon wafer is the tunneling oxide layer, and the boron-doped amorphous silicon layer crystallizes to form a boron-doped P-type polycrystalline silicon layer. At the same time, a boron silicate glass layer (BSG) is also formed on the back side of the silicon wafer.

[0030] At the same time, phosphorus atoms in the phosphorus-doped amorphous silicon layer on the front side of the silicon wafer enter the activated state, causing the phosphorus-doped amorphous silicon layer to crystallize to form a phosphorus-doped N-type polycrystalline silicon layer, realizing a selective passivation contact structure in the gate-line area on the front side of the silicon wafer. At the same time, a phosphorus silicate glass layer (PSG) is also formed on the front side of the silicon wafer.

[0031] Step 3: Clean the silicon wafer, deposit a protection layer, and prepare electrodes.

[0032] Remove the BSG layer on the back side of the silicon wafer and the PSG layer and SiOx protection layer on the front side of the silicon wafer.

[0033] Prepare a silicon oxide layer and a silicon nitride layer on the front side of the silicon wafer.

[0034] Prepare a silicon nitride layer outside the boron-doped P-type polycrystalline silicon layer on the back side of the silicon wafer.

[0035] Prepare electrodes on the front and back sides of the silicon wafer to obtain the N-type TOPCon cell of the present invention.

[0036] Preferably, the gate-line-shaped pattern in the non-mask area in Step 1 is a finger-shaped gate-line-shaped pattern.

[0037] Preferably, in Step 2, perform the high-temperature annealing at 925 °C for 35 min to form the boron-doped P-type polycrystalline silicon layer; form the phosphorus-doped N-type polycrystalline silicon layer.

[0038] The present invention also provides a back-junction solar cell with a selective contact structure prepared by the above preparation method.

[0039] The technical effects achieved by the present invention are as follows:

[0040] By using the PECVD (Plasma Enhanced Chemical Vapor Deposition) plasma-enhanced chemical vapor deposition technology, that is, the in-situ doping technology, a boron-doped amorphous silicon layer is prepared on the back (backlight side) of the TOPCon cell, and then by heating, the boron atoms in the boron-doped amorphous silicon layer diffuse into the silicon wafer and form a PN junction with the phosphorus originally existing in the silicon wafer. That is, the present invention transfers the PN junction to the back of the cell and replaces the traditional high-temperature diffusion method to prepare the PN junction on the front of the cell, which can at least reduce the cost.

[0041] At the same time, a selective passivation contact structure of N-type amorphous silicon finger-shaped grid lines is realized on the front (light-receiving side) of the silicon wafer by using the PECVD in-situ doping technology and the mechanical mask patterning method. That is, by high-temperature annealing, the phosphorus atoms are activated, and the amorphous silicon is converted into phosphorus-doped N-type polycrystalline silicon, realizing local phosphorus heavy doping at the position of the front grid lines, reducing the sheet resistance of the electrode area, thereby reducing the contact resistance and minority carrier recombination of the cell and improving the short-wave response. The non-grid line area is lightly doped without an amorphous silicon layer, further reducing the parasitic absorption of the cell. The non-grid line area is passivated with silicon oxide to increase the short-circuit current, and then the short-circuit current, open-circuit voltage and fill factor of the cell are improved, and finally the conversion efficiency of the cell is increased. Description of the Drawings

[0042] Figure 1 It is a process flow schematic diagram of Example 1;

[0043] Figure 2 It is a process flow schematic diagram of Example 2;

[0044] Figure 3 It is a structure schematic diagram of an N-type TOPCon cell prepared by the preparation method of the present invention;

[0045] Figure 4 It is a light illumination I-V test curve graph of the highest-efficiency TOPCon cell of Comparative Example 1;

[0046] Figure 5 It is a light illumination I-V test curve graph of the highest-efficiency TOPCon cell of the Example.

[0047] Wherein Figure 3 : 100 is an N-type silicon wafer, 101 is a tunneling oxide layer, 102 is a boron-doped P-type polycrystalline silicon layer, 103 is a finger-shaped phosphorus-doped N-type polycrystalline silicon layer, 104 is an aluminum oxide layer, 105 is a silicon nitride layer, and 106 is a metal grid line. Detailed implementation manners

[0048] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the present invention and do not limit the present invention.

[0049] Embodiment 1:

[0050] Please refer to Figure 1 、 Figure 3 as shown. A preparation method of a selective passivated contact structure back-junction N-type TOPCon cell prepared by PECVD provided by the present invention is as follows:

[0051] I. Processing the back surface of the silicon wafer

[0052] An N-type silicon wafer 100 with a resistivity of 0.9 Ω·cm is used as a substrate, and a slot cleaning device is used to remove the damaged layer and polish both sides of the silicon wafer 100;

[0053] A tunneling oxide layer 101 and a boron-doped amorphous silicon layer are prepared on the back surface of the silicon wafer 100 by PECVD in-situ doping method, that is:

[0054] The silicon wafer 100 is inserted into a graphite boat and sent into a furnace tube for discharge oxidation at 430 °C for 200 s, with a nitrous oxide flow rate of 10000 sccm, a pressure of 1800 mtorr, a discharge power of 10000 W, and a pulse switch ratio of 20:1500. A 1-3 nm thick SiOx tunneling oxide layer 101 is grown by oxidation on the polished surface of the silicon wafer 100.

[0055] Subsequently, continue to introduce nitrous oxide into the furnace tube with a flow rate of 8000 sccm, silane flow rate of 1800 sccm, boron trichloride flow rate of 300 sccm, pressure of 1800 mtorr, discharge power of 12000 W, and pulse switch ratio of 30:600, and deposit a 100 nm thick boron-doped amorphous silicon layer on the back surface of the silicon wafer.

[0056] The silicon wafer is annealed at a high temperature of 920 °C - 1050 °C for 30 min. Under the action of high temperature, boron atoms in the boron-doped amorphous silicon layer are transformed from a non-activated state to an activated state, and a PN junction (not shown in the figure) is formed inside the back surface of the silicon wafer. The outer surface of the back surface of the silicon wafer is the tunneling oxide layer 101, and the boron-doped amorphous silicon layer crystallizes to form a boron-doped P-type polycrystalline silicon layer 102; at the same time, a boron-silicate glass (BSG) layer is also formed on the front surface of the silicon wafer, and the BSG layer can protect the diffusion surface in subsequent cleaning processes.

[0057] Use a chain device to remove the BSG on the back surface of the silicon wafer, and use a slot cleaning device to remove the boron-doped polycrystalline silicon layer deposited on the front surface of the silicon wafer and perform texturing cleaning on the front surface to form a pyramidal textured surface structure.

[0058] II. Processing the front side of the silicon wafer

[0059] A mask region and a non-mask region are formed on the textured surface of the front side of the silicon wafer 100 by means of in-situ doping by PECVD in combination with mechanical mask patterning, and a tunneling oxide layer 101 of finger-shaped gate lines, a phosphorus-doped amorphous silicon, and a silicon oxide protective layer are prepared in the non-mask region, that is:

[0060] Insert the silicon wafer 100 into a graphite boat and send it into the furnace tube for discharge oxidation at 400 - 500 °C for 90 s. A 1 - 2 nm thick SiOx is grown in the non-mask region. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 10000 W, and the pulse duty ratio is 20:1500. Then evacuate, and then continue to introduce 2700 sccm SiH4, 5000 sccm H2, and 200 sccm PH3 into the furnace tube to deposit a 10 nm phosphorus-doped amorphous silicon. The deposition time is 120 s, the power is 12000 W, the pulse duty ratio is 30:450, and the pressure is 3100 mtorr. Evacuate again, and then continue to introduce 12000 sccm N2O into the furnace tube for discharge oxidation for 95 s to form a silicon oxide layer with a thickness of about 0.7 nm. After the next evacuation, introduce 2700 sccm SiH4, 10000 sccm H2, and 1000 sccm PH3 into the furnace tube to deposit a 100 nm phosphorus-doped amorphous silicon. The deposition time is 680 s, the power is 12500 w, and the pulse duty ratio is 30:360. Finally, deposit a 20 nm SiOx silicon oxide protective layer. The SiH4 flow rate is 1600 sccm, the N2O flow rate is 8000 sccm, the power is 10000 W, the pulse duty ratio is 30:600, and the time is 60 s. The above process deposits five layers: the first layer (the innermost layer) is a 1 - 2 nm thick SiOx, the second layer is a 10 nm phosphorus-doped amorphous silicon, the third layer is a 0.7 nm SiOx silicon oxide layer, the fourth layer is a 100 nm phosphorus-doped amorphous silicon, and the fifth layer is a 20 nm SiOx protective layer. There is no amorphous silicon layer in the non-gate line region.

[0061] The silicon wafer 100 is subjected to high-temperature annealing at 920 °C for 35 min, so that the SiOx in the first layer (the innermost layer in contact with the front side of the silicon wafer) forms a tunneling oxide layer 101; under the action of high temperature, the phosphorus atoms in the second layer of phosphorus-doped amorphous silicon change from the non-activated state to the activated state, and the amorphous silicon crystallizes to form doped polycrystalline silicon, that is, a finger-like phosphorus-doped polycrystalline silicon layer is formed; the SiOx in the third layer forms a new tunneling oxide layer; the fourth layer of phosphorus-doped amorphous silicon forms a new finger-like phosphorus-doped polycrystalline silicon layer. The above four layers constitute a stacked structure in which the tunneling oxide layer and the finger-like phosphorus-doped polycrystalline silicon layer are spaced apart from each other - a finger-like phosphorus-doped N-type polycrystalline silicon layer 103. That is, a selective passivation contact structure is realized in the gate line area on the front side of the silicon wafer; at the same time, a phosphosilicate glass (PSG) layer is also generated in the non-mask (gate line) area on the front side of the silicon wafer; the fifth layer of SiOx is a protective layer.

[0062] Step 3: Cleaning the silicon wafer, depositing a protective layer, and fabricating electrodes

[0063] The BSG layer on the back side of the silicon wafer is removed by using a chain-type and tank-type RCA cleaning device, and the PSG layer and the silicon oxide protective layer on the front side of the silicon wafer are removed.

[0064] A silicon oxide layer 104 and a silicon nitride layer 105 are prepared on the front side of the silicon wafer by using PECVD under the condition of 400 - 550 °C.

[0065] A silicon nitride layer 105 is prepared on the outside of the boron-doped P-type polycrystalline silicon layer 102 on the back side of the silicon wafer by using PECVD under the condition of 400 - 550 °C.

[0066] Electrodes 106 are fabricated on the front and back sides of the silicon wafer by using screen printing and sintering technology, and the N-type TOPCon battery of the present invention is obtained.

[0067] Example 2:

[0068] Please refer to Figure 2 、 Figure 3 as shown. Another preparation method of a selective passivation contact structure back-junction N-type TOPCon battery provided by the present invention is as follows:

[0069] 1. Processing the back side and the front side of the silicon wafer

[0070] An N-type silicon wafer 100 with a resistivity of 1.0 Ω·cm is used as a substrate, and a damage layer is removed from both sides of the silicon wafer 100 and both sides are polished by using a tank-type cleaning device;

[0071] A tunneling oxide layer 101 and a boron-doped amorphous silicon layer are prepared on the back side of the silicon wafer 100 by using PECVD in-situ doping method, that is:

[0072] Insert the silicon wafer 100 into a graphite boat and send it into the furnace tube for discharge oxidation at 400°C - 500°C for 200 s. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 10000 W, and the pulse switch ratio is 20:1500. A SiOx tunneling oxide layer 101 with a thickness of 1 - 3 nm is grown by oxidation on the polished surface of the silicon wafer 100.

[0073] Then, perform glow discharge for 60 s. The silane flow rate is 1500 sccm, the N2O flow rate is 7500 sccm, the pressure is 1600 mttor, the discharge power is 10000 W, and the pulse switch ratio is 30:660. After evacuation, continue the discharge for 600 s. The nitrogen flow rate is 12500 sccm, the boron trichloride flow rate is 100 sccm, the pressure is 1700 mtorr, the discharge power is 13000 W, and the pulse switch ratio is 30:600. Deposit a boron source on the front side of the silicon wafer. Subsequently, continue to introduce nitrous oxide into the furnace tube with a flow rate of 8000 sccm, a pressure of 1800 mtorr, a discharge power of 12000 W, and a pulse switch ratio of 30:600. Finally, form a boron-doped silicon oxide layer with a thickness of 100 nm.

[0074] Use a chain-type device and a tank-type cleaning device to remove the boron-doped amorphous silicon layer deposited on the front side of the silicon wafer and perform cleaning and texturing on the front side of the silicon wafer to form a pyramidal texture structure.

[0075] By means of PECVD in-situ doping combined with mechanical mask patterning, a mask region and a non-mask region are formed on the textured surface of the front side of the silicon wafer 100, and a tunneling oxide layer 101, a phosphorus-doped amorphous silicon, and a silicon oxide protective layer with finger-like gate lines are prepared in the non-mask region, that is:

[0076] Insert the silicon wafer 100 into a graphite boat and send it into the furnace tube. Perform discharge oxidation at 400 - 500 °C for 90 s to grow a 1 - 2 nm thick SiOx layer in the non - masked area. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 10000 W, and the pulse - on / off ratio is 20:1500. Then evacuate, and then continue to introduce 2700 sccm of SiH4, 5000 sccm of H2, and 200 sccm of PH3 into the furnace tube to deposit a 10 nm thick phosphorus - doped amorphous silicon layer. The deposition time is 120 s, the power is 12000 W, the pulse - on / off ratio is 30:450, and the pressure is 3100 mtorr. Evacuate again, and then continue to introduce 12000 sccm of N2O into the furnace tube for discharge oxidation for 95 s to form a silicon oxide layer with a thickness of about 0.7 nm. After the next evacuation, introduce 2700 sccm of SiH4, 10000 sccm of H2, and 1000 sccm of PH3 into the furnace tube to deposit a 100 nm thick phosphorus - doped amorphous silicon layer. The deposition time is 680 s, the power is 12500 w, the pulse - on / off ratio is 30:360. Finally, deposit a 20 nm thick SiOx silicon oxide protective layer. The SiH4 flow rate is 1600 sccm, the N2O flow rate is 8000 sccm, the power is 10000 W, the pulse - on / off ratio is 30:600, and the time is 60 s. The above process deposits five layers: the first layer (innermost layer) is a 1 - 2 nm thick SiOx layer, the second layer is a 10 nm thick phosphorus - doped amorphous silicon layer, the third layer is a 0.7 nm thick silicon oxide layer, the fourth layer is a 100 nm thick phosphorus - doped amorphous silicon layer, and the fifth layer is a 20 nm thick SiOx protective layer. There is no amorphous silicon layer in the non - gate - line area.

[0077] Step 2: Perform a one - time high - temperature annealing on the silicon wafer

[0078] Perform high - temperature annealing on the silicon wafer at 925 °C for 35 min. Under the action of high temperature, the boron atoms in the boron - doped amorphous silicon layer on the back of the silicon wafer enter the activated state, and a PN junction (not shown in the figure) is formed inside the back of the silicon wafer. The surface of the silicon wafer is the tunneling oxide layer 101, and the boron - doped amorphous silicon layer crystallizes to form a boron - doped P - type polycrystalline silicon layer 102; at the same time, a boron - silicon glass layer (BSG) is also formed on the back of the silicon wafer; the BSG layer can protect the diffusion surface in the subsequent cleaning process.

[0079] Meanwhile, the SiOx of the first layer (the innermost layer in contact with the front side of the silicon wafer) on the front side of the silicon wafer 100 forms a tunneling oxide layer 101; under the action of high temperature, the phosphorus atoms in the second layer of phosphorus-doped amorphous silicon change from the non-activated state to the activated state, and the amorphous silicon crystallizes to form doped polysilicon, that is, a finger-like phosphorus-doped polysilicon layer is formed; the SiOx of the third layer forms a new tunneling oxide layer; the fourth layer of phosphorus-doped amorphous silicon forms a new finger-like phosphorus-doped polysilicon layer. The above four layers constitute a stacked structure in which the tunneling oxide layer and the finger-like phosphorus-doped polysilicon layer are spaced apart from each other - a finger-like phosphorus-doped N-type polysilicon layer 103. That is, a selective passivation contact structure is realized in the gate line area on the front side of the silicon wafer; meanwhile, a phosphosilicate glass (PSG) layer is also formed in the non-masked (gate line) area on the front side of the silicon wafer; the fifth layer of SiOx is a protective layer.

[0080] Step 3: Cleaning the silicon wafer, depositing a protective layer, and fabricating electrodes

[0081] Use a chain and batch RCA cleaning equipment to remove the BSG layer on the back side of the silicon wafer, and remove the PSG layer and the silicon oxide protective layer on the front side of the silicon wafer.

[0082] Use PECVD to deposit a silicon oxide layer 104 and a silicon nitride layer 105 on the front side of the silicon wafer at 400 - 550 °C.

[0083] Use PECVD to deposit a silicon nitride layer 105 on the outside of the boron-doped P-type polysilicon layer 102 on the back side of the silicon wafer at 400 - 550 °C.

[0084] Fabricate electrodes 106 on the front and back sides of the silicon wafer by screen printing and sintering technology to obtain the N-type TOPCon cell of the present invention.

[0085] As Figure 3 shown, the present invention provides a solar cell fabricated by the above fabrication method.

[0086] The present invention forms a PN junction on the back of a TOPCon cell through PECVD in-situ doping technology, replacing the traditional way of preparing a PN junction on the front of the cell by high-temperature boron diffusion, which can reduce production costs. Finger-shaped grid line amorphous silicon is deposited on the front of the cell and annealed at high temperature to form phosphorus-doped N-type polycrystalline silicon; alternatively, after preparing a boron-doped amorphous silicon layer on the back of the silicon wafer and depositing finger-shaped grid line amorphous silicon on the front, the front and back of the silicon wafer are annealed at high temperature at one time to form a PN junction on the back of the cell and phosphorus-doped N-type polycrystalline silicon on the front of the cell. The present invention adopts PECVD in-situ doping technology and mechanical mask patterning to realize a selective passivation contact structure of N-type amorphous silicon finger-shaped grid line patterns on the front (light-receiving surface) of the silicon wafer. That is, local phosphorus heavy doping is realized at the position of the front grid lines to form a finger-shaped phosphorus-doped N-type polycrystalline silicon layer, reducing the sheet resistance of the electrode area and thus reducing the contact resistance of the cell. The non-grid line area is lightly doped and there is no amorphous silicon layer, improving the open-circuit voltage and short-wave response, and finally improving the conversion efficiency of the cell.

[0087] Comparative Example 1:

[0088] A traditional low-pressure chemical vapor deposition (LPCVD) is used to prepare an N-type TOPcon cell. Using an N-type silicon wafer as the substrate, the damage layer on both sides of the silicon wafer is first cleaned. Boron atoms are diffused into the front of the cell through high-temperature diffusion to generate a PN junction on the front of the cell, and then phosphorus-doped N-type polycrystalline silicon is prepared on the back of the silicon wafer by the LPCVD method. After cleaning the front and back of the silicon wafer, protective layers are prepared respectively. Finally, electrodes are prepared by conventional screen printing and sintering technology to obtain a traditional N-type TOPCon cell.

[0089] Next, the cells of Example 1 and 2 of the present invention and Comparative Example 1 are subjected to performance testing.

[0090] In photovoltaic IV testing, the commonly used testing method is the variable load method, also known as the scan method (ScanMethod). This method measures the current and voltage output by the photovoltaic cell by changing the size of the load, thereby obtaining the IV characteristic curve. The specific steps are as follows:

[0091] 1. Apply certain light conditions and temperature conditions to ensure the consistency and repeatability of the test environment.

[0092] 2. Use the test equipment to perform a current-voltage scan on the photovoltaic cell through a variable load, gradually increasing from zero voltage to a certain voltage value, then gradually decreasing to zero voltage, and finally increasing to a negative voltage.

[0093] 3. Measure the current and voltage values at each voltage point to obtain the IV characteristic curve.

[0094] 4. Calculate the key parameters of the photovoltaic cell based on the measured current and voltage values, such as open-circuit voltage (Voc), short-circuit current (Isc), maximum power point (MPP), etc.

[0095] 5. Test method

[0096] (1) Voc: The open-circuit voltage refers to the potential difference between the positive and negative electrodes when there is no current passing through the cell;

[0097] Calculation method: Multiply adjacent current values in the current array pairwise. When the result is less than or equal to zero, it indicates that the I-V curve intersects the horizontal axis. At this time, the value in the corresponding voltage array is the open-circuit voltage.

[0098] (2) Isc: The short-circuit current is the current in the case of short-circuit between the positive and negative electrodes. Multiply adjacent voltage values in the current array pairwise. When the result is less than or equal to zero, it indicates that the I-V curve intersects the horizontal axis. At this time, the value in the corresponding current array is the short-circuit current.

[0099] The open-circuit voltage (Voc) and short-circuit current (Isc) can be directly measured values

[0100] (3) Rs: Series resistance. In any actual solar cell, there is a series resistance, whose sources are the resistance of the front grid metal grid line, the front and back metal-semiconductor contact resistances, the resistance of the front diffusion layer, the base region bulk resistance, and the resistance of the back electrode metal layer.

[0101] (4) FF: Fill factor. The output power at any operating point on the volt-ampere characteristic curve of the photovoltaic cell is equal to the rectangular area corresponding to that point. Among them, there is only one point with the maximum output power, called the optimal operating point. The voltage and current at this point are called the optimal operating voltage Vmpp and the optimal operating current Impp, respectively.

[0102] FF = Impp * Vmpp / (Isc * Voc)

[0103] (5) Maximum power Pmpp = Isc * Voc * FF.

[0104] (6) Conversion efficiency η = Pmpp / (Pin * S) = Voc * Isc * FF / (Pin * S)

[0105] Where:

[0106] Pin is the incident light power per unit area in W / m2. The standard light intensity of Pin refers to: under the conditions of spectral AM1.5 and a test temperature of 25 degrees Celsius, it is 1000 w / m2;

[0107] S is the area of the cell monomer in m2.

[0108] (7) Short-circuit current density Jsc, calculation formula:

[0109] Jsc = AIsc (unit: mA / cm 2 )

[0110] Wherein:

[0111] Isc: short - circuit current (unit: mA)

[0112] A: effective light - receiving area of the battery (unit: cm 2 )

[0113] Table 1

[0114] Test items Example 1 Example 2 Comparative example Short-circuit current density (Jsc) 41.99 43 39.78 Fill factor (FF) 85.16％ 83 81.62 Open-circuit voltage (Voc) 738.7 mV 730 702.6 Conversion efficiency (η) 24.84 25.3 22.81

[0115] According to the detection data of Example 1, Example 2 and Comparative Example 1, as Figure 4 , 5 shown, applying the above formula to calculate the performance parameters of the battery, as shown in Table 1, the short - circuit current density (Jsc), fill factor (FF), open - circuit voltage (Voc) and conversion efficiency (η) of the examples of the present invention are all higher than those of the batteries prepared by the prior art. Therefore, through the technical improvement of the present invention, the performance of the TOPCon battery has been improved well.

[0116] The above is only the specific implementation manner of the present invention. It should be noted that any modification, equivalent replacement and change made within the spirit and framework of the concept of the present invention should be included in the protection scope of the present invention.

Claims

1. A preparation method of a back-contact solar cell with a selective contact structure prepared by PECVD, the steps are as follows: Step 1: Process the back surface of the silicon wafer Remove the damaged layer and polish both sides of the N-type silicon wafer; Prepare a tunneling oxide layer and a boron-doped amorphous silicon layer on the back surface of the silicon wafer by in-situ doping of PECVD; Anneal the silicon wafer at a high temperature, form a PN junction inside the back surface of the silicon wafer, the surface of the silicon wafer is the tunneling oxide layer, and the boron-doped amorphous silicon layer crystallizes to form a boron-doped P-type polycrystalline silicon layer; at the same time, a borosilicate glass layer is also generated on the back surface of the silicon wafer; Remove the borosilicate glass layer on the back surface of the silicon wafer and the boron-doped polycrystalline silicon layer deposited on the front surface of the silicon wafer, and perform texturing cleaning on the front surface of the silicon wafer; Step 2: Process the front surface of the silicon wafer Form a mask area and a non-mask area on the textured surface of the front surface of the silicon wafer by in-situ doping of PECVD combined with mechanical mask patterning, and prepare a grid-like tunneling oxide layer, phosphorus-doped amorphous silicon and silicon oxide protective layer in the non-mask area; Anneal the silicon wafer at a high temperature, the phosphorus-doped amorphous silicon layer crystallizes to form a phosphorus-doped N-type polycrystalline silicon layer, and a selective passivation contact structure is realized in the grid line area on the back surface of the silicon wafer; at the same time, a phosphosilicate glass layer is also generated in the grid line area on the front surface of the silicon wafer; Step 3: Clean the silicon wafer, deposit a protective layer and prepare electrodes Remove the borosilicate glass layer on the back surface of the silicon wafer, remove the phosphosilicate glass layer and the silicon oxide protective layer on the front surface of the silicon wafer; Prepare a silicon oxide layer and a silicon nitride layer on the front surface of the silicon wafer; Prepare a silicon nitride layer outside the boron-doped P-type polycrystalline silicon layer on the back surface of the silicon wafer; Prepare electrodes on the front and back surfaces of the silicon wafer to obtain the N-type TOPCon battery of the present invention.

2. The preparation method according to claim 1, characterized in that, The grid-like pattern in the non-mask area in Step 2 is a finger-like grid-like pattern.

3. The preparation method according to claim 1, characterized in that, In Step 1, the high-temperature annealing is carried out at 920 °C - 1050 °C for 30 min.

4. The preparation method according to claim 1, wherein, In Step 2, the high-temperature annealing is carried out at 920 °C for 35 min.

5. A preparation method of a back-contact solar cell with a selective contact structure prepared by PECVD, the steps are as follows: Step 1: Process the front and back surfaces of the silicon wafer Remove the damaged layer and polish both sides of the N-type silicon wafer; Prepare a tunneling oxide layer and a boron-doped amorphous silicon layer on the back surface of the silicon wafer by in-situ doping of PECVD; Remove the boron-doped amorphous silicon layer deposited on the front surface of the silicon wafer and clean and texture the front surface of the silicon wafer; Form a mask area and a non-mask area on the textured surface of the front surface of the silicon wafer by in-situ doping of PECVD combined with mechanical mask patterning, and prepare a grid-like tunneling oxide layer, phosphorus-doped amorphous silicon and silicon oxide protective layer in the non-mask area; Step 2: Anneal the silicon wafer at a high temperature at one time Anneal the silicon wafer at a high temperature, form a PN junction inside the back surface of the silicon wafer, the surface of the silicon wafer is the tunneling oxide layer, and the boron-doped amorphous silicon layer crystallizes to form a boron-doped P-type polycrystalline silicon layer; at the same time, a borosilicate glass layer is also generated on the back surface of the silicon wafer; At the same time, the phosphorus-doped amorphous silicon layer on the front surface of the silicon wafer crystallizes to form a phosphorus-doped N-type polycrystalline silicon layer, and a selective passivation contact structure is realized in the grid line area on the front surface of the silicon wafer; at the same time, a phosphosilicate glass layer is also generated on the front surface of the silicon wafer; Step 3: Wafer cleaning, deposition of protective layer and preparation of electrodes Remove the BSG layer on the back of the wafer and the PSG layer and SiOx protective layer on the front of the wafer; Prepare a silicon oxide layer and a silicon nitride layer on the front of the wafer; Prepare a silicon nitride layer outside the boron-doped P-type polysilicon layer on the back of the wafer; Prepare electrodes on the front and back of the wafer to obtain the N-type TOPCon cell of the present invention.

6. The preparation method according to claim 5, characterized in that, The grid-like pattern in the non-mask area in Step 1 is an interdigitated grid-like pattern.

7. The preparation method according to claim 5, characterized in that, In Step 2, perform the high-temperature annealing at 925 °C for 35 min to form the boron-doped P-type polysilicon layer; form the phosphorus-doped N-type polysilicon layer.

8. A back-contact solar cell with a selective contact structure, characterized in that The back-junction solar cell with the selective contact structure is obtained by using the preparation method as described in Claim 1 or Claim 5.

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