Preparation method of sliced solar cell and sliced solar cell

Abstract

The invention discloses a preparation method of a slice solar cell and the slice solar cell, and relates to the technical field of solar cell manufacturing, and the method comprises the steps: forming p + emitters which are arranged at intervals on a first main surface of a silicon substrate, and a slice region located between every two adjacent p + emitters; under the condition that the temperature ranges from 900 DEG C to 1100 DEG C, oxide layers are prepared on the p + emitting electrode and the slice area, and part of doping elements in the p + emitting electrode are diffused towards the corresponding oxide layer above the p + emitting electrode so as to reduce the doping concentration of the p + emitting electrode; and removing the oxide layer by a wet process. According to the embodiment of the invention, the oxide layer is further prepared after the p + emitter is prepared in the non-slicing region, and part of doped elements in the p + emitter are diffused to the corresponding oxide layer above the p + emitter, so that the doping concentration of the p + emitter is reduced, auger recombination is reduced, the open-circuit voltage of the solar cell is effectively improved, and the performance of the solar cell is improved. And meanwhile, deep repair of the silicon substrate is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell manufacturing, and in particular, to a method for preparing a sliced solar cell and a sliced solar cell. Background Art

[0002] In the preparation process of the existing sliced solar cells, the process of preparing an emitter on the first main surface of a silicon substrate is usually achieved only through one-time boron diffusion. However, since the emitter concentration obtained after one-time boron diffusion is relatively high, Auger recombination is increased and the minority carrier lifetime is reduced. Generally, an oxidation source absorption (boron diffuses into the oxide layer) process can be adopted subsequently to reduce the emitter concentration. However, the BSG layer formed on the surface after one-time boron diffusion will affect the oxidation source absorption process, resulting in the inability to effectively reduce the emitter concentration. In addition, after the emitter is prepared, in order to avoid the pn junction in the sliced area during the slicing process from affecting the silicon substrate, a laser process is required to cooperate with an alkali solution cleaning to remove the pn junction in the sliced area on the first main surface of the silicon substrate. However, the high-energy laser in this process is likely to damage the silicon substrate. Summary of the Invention

[0003] In view of this, the present invention provides a method for preparing a sliced solar cell and a sliced solar cell. By further preparing an oxide layer after preparing a p+ emitter in a non-sliced area, part of the doping elements in the p+ emitter can diffuse into the corresponding oxide layer above it, thereby reducing the doping concentration of the p+ emitter, further reducing Auger recombination, and effectively improving the open-circuit voltage of the solar cell. At the same time, the silicon substrate corresponding to the sliced area can undergo lattice recrystallization under high-temperature conditions, realizing further repair of the silicon substrate.

[0004] To solve the above technical problems, the present invention provides the following technical solutions:

[0005] In a first aspect, the present invention provides a method for preparing a sliced solar cell, including: Step 1, forming spaced-apart p+ emitters on the first main surface of a silicon substrate and a sliced area located between every two adjacent p+ emitters; Step 2, preparing an oxide layer on the p+ emitter and the sliced area under the condition that the temperature is 900 °C to 1100 °C, wherein part of the doping elements in the p+ emitter diffuse into the corresponding oxide layer above it to reduce the doping concentration of the p+ emitter; Step 3, removing the oxide layer by a wet process.

[0006] Optionally, step 1 includes: step 11, performing boron diffusion treatment on the first main surface of the silicon substrate to form a p+ emitter and a first silicon glass layer of p-type doping elements laminated on the p+ emitter; step 12, using a laser process to turn the p+ emitter and the first silicon glass layer of p-type doping elements corresponding to the slicing area into a molten state, and using an alkaline solution to clean the slicing area to obtain p+ emitters arranged at intervals, and making the thickness of the silicon substrate corresponding to the slicing area less than the thickness of the silicon substrate corresponding to the p+ emitter; step 13, using an acid solution with a first concentration to remove the remaining first silicon glass layer 100 of p-type doping elements on the p+ emitter; wherein, the volume fraction of the acid solution with the first concentration is 10% - 60%.

[0007] Optionally, step 11 further includes: simultaneously forming a p+ emitter and a first silicon glass layer of p-type doping elements by plating around on the second main surface of the silicon substrate;

[0008] After step 12 and before step 13, it further includes: etching one side to sequentially remove the first silicon glass layer of p-type doping elements and the p+ emitter plated around on the second main surface of the silicon substrate.

[0009] Optionally, step 2 further includes: forming an undoped oxide layer on the second main surface of the silicon substrate while forming the oxide layer; before step 3, it further includes: using an acid solution with a second concentration to remove the undoped oxide layer.

[0010] Optionally, the oxide layer includes a first oxide layer corresponding to the p+ emitter and a second oxide layer corresponding to the slicing area; wherein, the first oxide layer contains doping elements diffused from the p+ emitter, and the second oxide layer does not contain doping elements diffused from the p+ emitter.

[0011] Optionally, after step 2 and before step 3, it further includes: sequentially forming a tunneling oxide layer, an n-type doping layer, and a first silicon glass layer of n-type doping elements from the inside to the outside on the second main surface of the silicon substrate, and simultaneously forming a plating-around structure on the outside of the first oxide layer and the second oxide layer; wherein, the plating-around structure includes: a first plating-around structure corresponding to the first oxide layer and a second plating-around structure corresponding to the second oxide layer.

[0012] Optionally, the doping concentration of the p-type doping elements in the p+ emitter formed in step 1 is 1×10 18 atom / cm 3 ~1×10 20 atom / cm 3 ; and / or, after step 2, the doping concentration of the doping elements in the p+ emitter is 1×10 17atoms / cm 3 ~1×10 19 atoms / cm 3 。

[0013] Optionally, the laser process uses a green picosecond pulsed laser with a wavelength of 200 nm to 600 nm. Among them, the pulse width of the green picosecond pulsed laser is 1 ps to 50 ps, the laser power is 20 W to 100 W, and the single pulse energy is 50 mJ to 200 mJ.

[0014] In a second aspect, the present invention provides a sliced solar cell, including: a silicon substrate; p+ emitters arranged at intervals on the first main surface of the silicon substrate; and a sliced area located between every two adjacent p+ emitters; wherein, the p+ emitter is obtained by diffusing part of the doping elements into the oxide layer prepared above it to reduce the doping concentration.

[0015] The technical solution of the present invention has the following beneficial effects: By further preparing an oxide layer after preparing the p+ emitter in the non-sliced area, part of the doping elements in the p+ emitter can diffuse into the corresponding oxide layer above it, thereby reducing the doping concentration of the p+ emitter, and further reducing Auger recombination, effectively improving the open-circuit voltage of the solar cell. At the same time, the silicon substrate corresponding to the sliced area can undergo lattice recrystallization under high-temperature conditions, realizing further repair of the silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings are used to better understand the present invention and do not constitute an improper limitation to the present invention. Among them:

[0017] Figure 1 is a schematic flow chart of a method for preparing a sliced solar cell according to an embodiment of the present invention;

[0018] Figure 2 is a schematic flow chart of the specific process for forming the p+ emitter and the sliced area according to an embodiment of the present invention;

[0019] Figure 3 is a schematic cross-sectional structure diagram of the silicon substrate obtained after step S201 according to an embodiment of the present invention;

[0020] Figure 4 is a schematic cross-sectional structure diagram of the silicon substrate obtained after step S202 according to an embodiment of the present invention;

[0021] Figure 5 is a schematic cross-sectional structure diagram of the silicon substrate obtained after step S203 according to an embodiment of the present invention;

[0022] Figure 6It is a schematic cross-sectional structure diagram of a silicon substrate obtained after step S2021 according to an embodiment of the present invention;

[0023] Figure 7 It is a schematic cross-sectional structure diagram of a silicon substrate obtained after step S2022 according to an embodiment of the present invention;

[0024] Figure 8 It is a schematic cross-sectional structure diagram of a silicon substrate obtained after step S102 according to an embodiment of the present invention;

[0025] Figure 9 It is a schematic cross-sectional structure diagram of a silicon substrate obtained after removing the undoped oxide layer according to an embodiment of the present invention;

[0026] Figure 10 It is a schematic cross-sectional structure diagram of a silicon substrate with a back structure according to an embodiment of the present invention;

[0027] Figure 11 It is a schematic cross-sectional structure diagram of a silicon substrate when the edge of the wrap plating structure is located outside the first oxide layer according to an embodiment of the present invention;

[0028] Figure 12 It is a specific process flow diagram of step S103 when the edge of the wrap plating structure is located outside the first oxide layer according to an embodiment of the present invention;

[0029] Figure 13 It is a schematic cross-sectional structure diagram of a silicon substrate when the edge of the wrap plating structure is located outside the second oxide layer according to an embodiment of the present invention;

[0030] Figure 14 It is a specific process flow diagram of step S103 when the edge of the wrap plating structure is located outside the second oxide layer according to an embodiment of the present invention;

[0031] Figure 15 It is a schematic cross-sectional structure diagram of a silicon substrate obtained after step S1203 or step S1403 according to an embodiment of the present invention;

[0032] Figure 16 It is a specific process flow diagram for preparing a passivation and antireflection layer and a metal electrode according to an embodiment of the present invention;

[0033] Figure 17 It is a schematic cross-sectional structure diagram of a silicon substrate obtained by a method for manufacturing a sliced solar cell according to an embodiment of the present invention;

[0034] Figure 18 It is an enlarged structure diagram of region A according to an embodiment of the present invention.

[0035] The reference numerals are as follows:

[0036] 1 - Silicon substrate; 2 - p+ emitter; 3 - Oxide layer; 31 - First oxide layer; 32 - Second oxide layer; 4 - Undoped oxide layer; 5 - Tunneling oxide layer; 6 - n-type doped layer; 7 - n-type doped element first silicon glass layer; 8 - First passivation and antireflection layer; 9 - Second passivation and antireflection layer; 10 - First metal electrode; 11 - Second metal electrode;

[0037] 100 - p-type doped element first silicon glass layer; 200 - First wrap plating structure; 300 - Second wrap plating structure. Detailed implementation mode

[0038] For the convenience and clear description of the preparation method of the solar cell and the solar cell of the present invention, the following makes an explanation of the exemplary embodiments of the present invention in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to help understanding, and they should be regarded as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted below.

[0039] In an embodiment of the present invention, as Figure 1 shown, this embodiment provides a preparation method of a sliced solar cell, and the preparation method may include the following steps:

[0040] Step S101, forming spaced-apart p+ emitters 2 and sliced regions located between every two adjacent p+ emitters 2 on the first main surface of the silicon substrate 1;

[0041] Step S102, preparing an oxide layer 3 on the p+ emitter 2 and the sliced region under the condition that the temperature is 900 °C to 1100 °C, wherein a part of the doped elements in the p+ emitter 2 diffuse into the corresponding oxide layer 3 above it to reduce the doping concentration of the p+ emitter 2;

[0042] Step S103, removing the oxide layer 3 by a wet process.

[0043] Among them, the first main surface can be understood as the front surface of the silicon substrate 1 (hereinafter referred to as the front surface). The process of preparing the oxide layer 3 is realized by continuously introducing oxygen to the surface of the silicon substrate 1 at 900 °C to 1100 °C. Specifically, the time for introducing oxygen can be 50 min to 70 min, such as 50 min, 60 min, 70 min, etc., and preferably 60 min. In the embodiment of the present invention, this process can achieve two effects simultaneously:

[0044] (1) Regarding the p+ emitter 2, since the solubility of the p-type doping element in the oxide layer is higher than that in the silicon substrate, the p-type doping element will diffuse from the silicon substrate into the oxide layer under high temperature. Therefore, by laminating the oxide layer 3 outside the p+ emitter 2, the doping concentration of the p-type element in the p+ emitter 2 can be effectively reduced, while reducing Auger recombination and increasing the open-circuit voltage of the solar cell.

[0045] (2) Regarding the silicon substrate 1 in the sliced area, since the sliced area is actually achieved through the cooperation of the laser process and the alkali solution cleaning, the silicon substrate 1 in the sliced area has laser damage. However, the silicon substrate 1 in the sliced area can achieve the process of lattice recrystallization under high temperature, thereby effectively repairing the bulk damage inside the silicon substrate 1 in the sliced area and improving the cell efficiency of the solar cell.

[0046] It should be noted that the oxide layer 3 prepared in step S102 of the present invention does not exist in the final solar cell structure. Its purpose of setting is only to achieve the corresponding technical effects during the preparation process. Therefore, a simple and efficient process should be used to remove it as much as possible to avoid complex process flows and increased material costs. Specifically, in step S103 of the embodiment of the present invention, a simple wet process can be used to remove the oxide layer 3, and there is no need for the laser process that will damage the silicon substrate. It is not only simple to operate, but also will not repeatedly damage the silicon substrate, and at the same time, it is inexpensive, which can effectively reduce the material usage cost.

[0047] In an optional embodiment, the p+ emitter 2 and the sliced area formed in step S101 can be prepared according to the Figure 2 process shown, as Figure 2 shown, including:

[0048] Step S201, performing boron diffusion treatment on the first main surface of the silicon substrate 1 to form the p+ emitter 2 and the first silicon glass layer 100 of the p-type doping element laminated on the p+ emitter 2;

[0049] Step S202, using the laser process to turn the p+ emitter 2 and the first silicon glass layer 100 of the p-type doping element corresponding to the sliced area into a molten state, and using the alkali solution to clean the sliced area to obtain the p+ emitter 2 arranged at intervals, and making the thickness of the silicon substrate 1 corresponding to the sliced area less than the thickness of the silicon substrate 1 corresponding to the p+ emitter 2;

[0050] Step S203, using the acid solution with the first concentration to remove the remaining first silicon glass layer 100 of the p-type doping element on the p+ emitter 2, where the volume fraction of the acid solution with the first concentration is 10% - 60%.

[0051] In the embodiment of the present invention, first, boron diffusion treatment is performed on the front surface of the silicon substrate 1 to form a whole-layer p+ emitter 2 and a first silicon glass layer 100 of p-type doping elements. Then, through a laser process and chemical etching respectively, a stacked structure is obtained in which the sliced area is the exposed silicon substrate 1 and the non-sliced area is provided with the p+ emitter 2. Exemplarily, the cross-sectional structure of the silicon substrate obtained in steps S201 to S203 is as Figures 3 to 5 shown, where Figure 3 FIG. Figure 3 shows a schematic cross-sectional structure of the silicon substrate obtained after step S201, Figure 4 FIG. Figure 4 shows a schematic cross-sectional structure of the silicon substrate obtained after step S202, Figure 5 FIG. Figure 5 shows a schematic cross-sectional structure of the silicon substrate obtained after step S203. Specifically, in Figure 4 FIG. Figure 4 , H is used to represent the thickness difference between the sliced area of the silicon substrate 1 and the area corresponding to the p+ emitter. It can be understood that the thickness difference is formed because when the p+ emitter 2 and the first silicon glass layer 100 of p-type doping elements in the sliced area are transformed into a molten state by the laser process, the alkali solution can directly contact the front surface of the sliced area of the silicon substrate 1, etching the surface of the silicon substrate 1 in the sliced area. Further, for the specific value setting of the thickness difference H, it can be set according to actual performance requirements. In the embodiment of the present invention, by making the surfaces of the silicon substrate 1 corresponding to the sliced area and the silicon substrate 1 corresponding to the p+ emitter 2 not in the same plane, the situation that the remaining p+ emitter 2 in the sliced area redistributes to the silicon substrate 1 during the process of preparing the oxide layer 3 in step S102 is avoided, the problem of possible p-type doping element residues in the sliced area is eliminated, and the effect of completely removing the pn junction in the sliced area is achieved.

[0052] For the specific parameters of the laser process in step S202, in an optional embodiment, for the type of laser emitter, a green picosecond pulsed laser is preferably used. The wavelength of the laser process is 200 nm to 600 nm, such as 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, etc.; the laser power of the laser process is 20 W to 100 W, such as 20 W, 40 W, 60 W, 80 W, 100 W, etc.; the single-pulse energy of the laser process is 50 mJ to 200 mJ, such as 50 mJ, 100 mJ, 150 mJ, 200 mJ, etc.; the pulse width of the laser process is 1 ps to 50 ps, such as 1 ps, 10 ps, 25 ps, 40 ps, 50 ps, etc. According to actual requirements, an infrared laser can also be selected, and the present invention does not make specific limitations on this, as long as it can provide the energy to transform the p+ emitter 2 and the first silicon glass layer 100 of p-type doping elements corresponding to the sliced area into a molten state.

[0053] For the boron diffusion process in step S201, actually, a p+ emitter 2 and a first silicon glass layer 100 doped with p-type doping elements are also formed by edge plating on the back surface of the silicon substrate 1 synchronously, that is Figure 3 the structure of the back surface part of the silicon substrate 1 shown in the figure. Therefore, step S201 further includes: synchronously forming a p+ emitter 2 and a first silicon glass layer 100 doped with p-type doping elements by edge plating on the second main surface of the silicon substrate 1. The second main surface can be understood as the back surface of the silicon substrate 1 (hereinafter referred to as the back surface). The edge plating structure on the back surface will affect the preparation of the n-type doped layer on the back surface of the subsequent silicon substrate 1, so it needs to be removed. That is, after step S202 and before step S203, it further includes: sequentially etching and removing the first silicon glass layer 100 doped with p-type doping elements and the p+ emitter 2 plated on the back surface of the silicon substrate 1. Specifically, it may include:

[0054] Step S2021, cleaning the first silicon glass layer 100 doped with p-type doping elements plated on the second main surface of the silicon substrate 1 with an acid solution of a first concentration;

[0055] Step S2022, synchronously cleaning the part of the silicon substrate 1 corresponding to the slicing area and the p+ emitter 2 plated on the second main surface of the silicon substrate 1 with an alkali solution.

[0056] Among them, the alkali solution in step S2022 can be cleaned by means of tank cleaning, that is, while etching the silicon substrate 1 in the front slicing area, the exposed p+ emitter 2 on the back surface of the silicon substrate 1 can also be removed. Specifically, the cross-sectional structure of the silicon substrate obtained in step S2021 is as Figure 6 shown. At this time, only the plated p+ emitter 2 remains on the back surface of the silicon substrate 1, and further through step S2022, Figure 7 the schematic diagram of the cross-sectional structure of the silicon substrate shown is obtained. Comparing Figure 6 and Figure 7 it can be seen that in the embodiment of the present invention, during the cleaning process with the alkali solution in step S2022, while actually etching the surface of the silicon substrate 1 in the slicing area, the plated p+ emitter 2 on the back surface of the silicon substrate 1 is removed, killing two birds with one stone.

[0057] Next, taking Figure 8 as an example, the structure of the silicon substrate obtained in step S102 will be specifically described. As Figure 8As shown, after step S102, an oxide layer 3 is formed above the p+ emitter 2 and the silicon substrate 1 in the slicing area respectively. As described above, in the embodiment of the present invention, the part of the oxide layer 3 corresponding to the p+ emitter 2 and the part corresponding to the silicon substrate 1 in the slicing area achieve different technical effects respectively. Therefore, in an optional embodiment, the oxide layer 3 includes: a first oxide layer 31 corresponding to the p+ emitter 2 and a second oxide layer 32 corresponding to the slicing area; wherein, the first oxide layer 31 contains doping elements diffused from the p+ emitter 2, and the second oxide layer 32 does not contain doping elements diffused from the p+ emitter 2. In order to clearly show the changes in the p+ emitter 2 and the oxide layer 3 after step S102, in Figure 8 the first oxide layer 31 corresponding to the slicing area and the second oxide layer 32 corresponding to the p+ emitter 2 are represented by different filling patterns, and since some of the p-type doping elements in the p+ emitter 2 diffuse into the oxide layer 3 above it, the doping concentration of the p-type doping elements in the p+ emitter 2 decreases. Therefore, in Figure 8 different filling colors are used to represent different concentrations of the p+ emitter 2.

[0058] In an optional embodiment, the doping concentration of the p-type doping elements in the p+ emitter 2 formed in step S101 is 1×10 18 atom / cm 3 ~1×10 20 atom / cm 3 , for example 1×10 18 atom / cm 3 , 1×10 19 atom / cm 3 , 1×10 20 atom / cm 3 and so on. After step S102, the doping concentration of the doping elements in the p+ emitter 2 is 1×10 17 atom / cm 3 ~1×10 19 atom / cm 3 , for example 1×10 17 atom / cm 3 , 1×10 18 atom / cm 3 , 1×10 19 atom / cm 3 and so on. It can be seen that the doping concentration of the doping elements in the p+ emitter 2 is effectively reduced by the oxide layer 3 prepared in step S102.

[0059] In the actual preparation process, still taking Figure 8For example, in an optional embodiment, step S102 further includes: while forming the oxide layer 3, a non-doped oxide layer 4 is formed on the second main surface of the silicon substrate 1. Since the non-doped oxide layer 4 formed on the back surface does not actually achieve additional technical effects for the present invention and will affect the subsequent preparation of the n-type doped layer on the back surface of the silicon substrate 1, before step S103, it further includes: removing the non-doped oxide layer 4 by using an acid solution with a second concentration, where the volume fraction of the acid solution with the second concentration is 2% to 8%. Exemplarily, the cross-sectional structure of the silicon substrate after removing the non-doped oxide layer 4 is as Figure 9 shown, that is, before step S103, the actually formed cross-sectional structure only has the oxide layer 3 on the front surface of the silicon substrate 1.

[0060] It should be noted here that the second oxide layer 32 corresponding to the sliced area and the non-doped oxide layer 4 formed on the back surface of the silicon substrate 1 are both oxide structures without p-type doping elements, and they are essentially the same. Therefore, in Figure 8 they are represented by the same filling pattern. In the embodiment of the present invention, since the non-doped oxide layer 4 formed on the back surface of the silicon substrate 1 does not contain doping elements, a relatively low concentration of the acid solution is required to completely remove it. Therefore, the volume fraction of the acid solution with the second concentration can be set to 2% to 8%, such as 2%, 3%, 4%, 5%, 7%, etc., and preferably 2%. Thus, an acid solution with a lower concentration than the prior art can be used to remove the oxide layer on the back surface, achieving the effect of cost reduction.

[0061] Since when preparing the back surface structure of the silicon substrate 1, some structures may be plated around to the front surface of the silicon substrate 1 to affect the front surface structure of the silicon substrate 1, the embodiment of the present invention selects to preferentially prepare the back surface structure of the silicon substrate 1 before step S103. In this way, while removing the front surface plating structure, the removal of the front surface oxide layer 3 can be achieved synchronously without an additional removal process, greatly simplifying the process flow.

[0062] Specifically, for the preparation process of the back surface structure of the silicon substrate 1, after step S102 and before step S103, it includes: sequentially forming a tunneling oxide layer 5, an n-type doped layer 6, and an n-type doped element first silicon glass layer 7 from the inside to the outside on the second main surface of the silicon substrate 1, and simultaneously forming a plating structure on the outside of the first oxide layer 31 and the second oxide layer 32; where the plating structure includes: a first plating structure 200 corresponding to the first oxide layer 31 and a second plating structure 300 corresponding to the second oxide layer 32. Exemplarily, the cross-sectional structure of the prepared silicon substrate is as Figure 10As shown, during the preparation of the back structure, the tunneling oxide layer 5, the n-type doped layer 6, and the first silicon glass layer 7 of the n-type doped element are also simultaneously deposited around the front surface of the silicon substrate 1. Regarding the specific widths of the tunneling oxide layer 5, the n-type doped layer 6, and the first silicon glass layer 7 of the n-type doped element deposited around the front surface of the silicon substrate 1, Figure 10 it is only for illustration and does not represent the actual deposition width of the tunneling oxide layer 5, the n-type doped layer 6, and the first silicon glass layer 7 of the n-type doped element. The present invention does not make specific limitations in this regard. It should be noted that since the deposition process is from the periphery of the silicon substrate 1 to the front surface of the silicon substrate 1, a deposited structure will be formed in the edge region (including the first oxide layer 31 and the second oxide layer 32) on the front surface of the silicon substrate 1. In Figure 10 only the second deposited structure 300 is marked outside the second oxide layer 32 on both sides as an example, which does not represent the actual deposited structure. It can be understood that the number and the setting positions of the first oxide layer 31 and the second oxide layer 32 can both be adjusted according to the actual situation.

[0063] In an optional embodiment, the first deposited structure 200 includes a silicon glass layer, an n-type doped layer 6, and the first silicon glass layer 7 of the n-type doped element stacked from the inside to the outside; wherein, the silicon glass layer includes at least one of the following: the second silicon glass layer of the p-type doped element, the mixed silicon glass layer co-doped with the n-type doped element and the p-type doped element, and the stacked structure composed of the second silicon glass layer of the p-type doped element and the mixed silicon glass layer; the second deposited structure 300 includes the tunneling oxide layer 5, the n-type doped layer 6, and the first silicon glass layer 7 of the n-type doped element stacked from the inside to the outside on the outside of the second oxide layer 32. It should be noted that during the preparation of the back tunneling oxide layer 5, the tunneling oxide layer 5 will also be deposited around the front surface of the silicon substrate 1. However, due to the diffusion of the doped element under high-temperature conditions, the boron element in the first oxide layer 31 will diffuse into the tunneling oxide layer 5, so a second silicon glass layer of the p-type doped element will be stacked outside the first oxide layer 31. Further, since the non-slice region for preparing the p+ emitter 2 can itself be a textured structure, resulting in uneven deposition of the n-type doped layer 6 outside the first oxide layer 31, during the diffusion process of the doped element when preparing the n-type doped layer 6, some n-type doped elements will pass through the n-type doped layer 6 and form a mixed silicon glass layer with the first oxide layer 31 outside the p+ emitter 2.

[0064] In a further optional embodiment, for the case where the edge of the deposited structure is located outside the first oxide layer 31, a mixed silicon glass layer is formed outside the first oxide layer 31 corresponding to the edge of the deposited structure; and / or, n-type doped elements are diffused in the first oxide layer 31 corresponding to the edge of the deposited structure. Exemplarily, it can be as shown in Figure 11 the A region in and Figure 18 as shown, wherein,Figure 18 is Figure 11 an enlarged view of region A in []. This is because during the actual preparation process, the tunneling oxide layer 5 and the intrinsic polysilicon layer are deposited through a single pipe. Therefore, after the diffusion of the n-type doping element, the widths of the silicon glass layer and the n-type doping layer 6 are the same. However, the n-type doping element is deposited through another pipe, which may result in a different width of the diffusion region of the n-type doping element from the region formed by the tunneling oxide layer 5 and the intrinsic polysilicon layer (usually wider than the width of the tunneling oxide layer 5). Therefore, during the diffusion process of the n-type doping element, the n-type element may diffuse into the region where the intrinsic polysilicon layer is not formed, that is, a mixed silicon glass layer is formed outside the exposed partial region in the first oxide layer 31 ( Figure 18 the white region in []), or directly diffuse into the first oxide layer 31.

[0065] Furthermore, in the case where a mixed silicon glass layer is formed outside the first oxide layer 31 corresponding to the edge of the plating-around structure, step S103 can be as Figure 12 shown, and specifically includes:

[0066] Step S1201, using an acid solution with a third concentration to etch the n-type doped element first silicon glass layer 7 outside the first oxide layer 31 and outside the second oxide layer 32 and the mixed silicon glass layer outside the first oxide layer 31 on one side;

[0067] Step S1202, using an alkaline solution to remove the n-type doping layer 6 outside the first oxide layer 31 and outside the second oxide layer 32;

[0068] Step S1203, using an acid solution with a fourth concentration to simultaneously remove the silicon glass layer, the first oxide layer 31, the second oxide layer 32, and the n-type doped element first silicon glass layer 7 outside the second main surface.

[0069] Among them, although both step S1201 and step S1203 use an acid solution to remove the silicon glass layer including the doped element, in step S1201, it is one-sided etching, while in step S1203, it is trough etching, and the etching processes of the two are different. Therefore, the concentration selection of the acid solution is also different. In an optional embodiment, the volume fraction of the acid solution with the third concentration is 5% - 20%, such as 5%, 6%, 8%, 10%, 12%, 15%, 18%, 20%, etc., and the volume fraction of the acid solution with the fourth concentration is 15% - 28%, such as 15%, 17%, 20%, 23%, 24%, 25%, 28%, etc.

[0070] Similarly, in another alternative embodiment, in the case where the edge of the plating-around structure is located outside the second oxide layer 32, an n-type doped element second silicon glass layer is further formed outside the second oxide layer 32 corresponding to the edge of the plating-around structure; and / or, the second oxide layer 32 corresponding to the edge of the plating-around structure is doped with an n-type doping element. Exemplarily, as shown in the B region of Figure 13 . It can be understood that the widths of the plating-around on both sides of the silicon substrate 1 may be the same or different. Therefore, the plating-around structures on both sides of the silicon substrate 1 may be the same or different, and the present invention does not make specific limitations in this regard.

[0071] In a further alternative embodiment, in the case where an n-type doped element second silicon glass layer is further formed outside the second oxide layer 32 corresponding to the edge of the plating-around structure, step S103 may be as shown in Figure 14 and specifically includes:

[0072] Step S1401, using an acid solution with a third concentration to etch the n-type doped element first silicon glass layer 7 outside the first oxide layer 31 and outside the second oxide layer 32 and the n-type doped element second silicon glass layer outside the second oxide layer 32 on one side;

[0073] Step S1402, using an alkaline solution to remove the n-type doped layer 6 outside the first oxide layer 31 and outside the second oxide layer 32;

[0074] Step S1403, using an acid solution with a fourth concentration to synchronously remove the silicon glass layer, the first oxide layer 31, the second oxide layer 32, and the n-type doped element first silicon glass layer 7 outside the second main surface.

[0075] It can be understood that regardless of which of the above situations, the cross-sectional structure of the silicon substrate finally obtained after removing the plating-around structure is the same, and is the structure shown in Figure 15 . Specifically, Figure 15 shows a schematic cross-sectional structure diagram of the silicon substrate obtained after step S1203 or step S1403.

[0076] In a further alternative embodiment, it is also necessary to prepare a passivation and antireflection layer on the front and back surfaces of the silicon substrate 1 by atomic layer deposition, and print metal electrodes on the front and back surfaces of the silicon substrate 1. That is, after step S103, as shown in Figure 16 , it further includes:

[0077] Step S1601, preparing a first passivation and antireflection layer 8 and a second passivation and antireflection layer 9 on the front and back surfaces of the silicon substrate 1 respectively;

[0078] Step S1602: Prepare a first metal electrode 10 and a second metal electrode 11 on the front and back surfaces of the silicon substrate 1 respectively. Among them, the first metal electrode 10 penetrates through the first passivation and antireflection layer 8 and is electrically connected to the p+ emitter 2, and the second metal electrode 11 penetrates through the second passivation and antireflection layer 9 and is electrically connected to the n-type doped layer 6.

[0079] Exemplarily, the cross-sectional structure of the silicon substrate obtained after step S1602 is as Figure 17 shown. For the process of preparing the first passivation and antireflection layer 8 and the second passivation and antireflection layer 9 in step S1601, they can be deposited by atomic layer deposition or plasma-enhanced chemical vapor deposition at corresponding temperatures. Specifically, the deposition temperature of atomic layer deposition can be 300°C to 400°C, such as 300°C, 320°C, 350°C, 380°C, 400°C, etc., and the deposition temperature of plasma-enhanced chemical vapor deposition can be 500°C to 600°C, such as 500°C, 550°C, 600°C, etc.

[0080] In an alternative embodiment, the thickness of the first passivation and antireflection layer 8 is 20 nm to 180 nm, such as 20 nm, 80 nm, 100 nm, 180 nm, etc., and the thickness of the second passivation and antireflection layer 9 is slightly thicker than that of the first passivation and antireflection layer 8, being 25 nm to 200 nm, such as 25 nm, 50 nm, 100 nm, 150 nm, 200 nm, etc.

[0081] In summary, in the preparation method of the sliced solar cell provided by the embodiment of the present invention, by further preparing an oxide layer after preparing the p+ emitter in the non-sliced area, part of the doping elements in the p+ emitter can diffuse into the corresponding oxide layer above it, thereby reducing the doping concentration of the p+ emitter, reducing Auger recombination, and effectively improving the open-circuit voltage of the solar cell. At the same time, the silicon substrate corresponding to the sliced area can also undergo lattice recrystallization under high-temperature conditions, achieving deep repair of the silicon substrate.

[0082] Still taking Figure 17 as an example, the structure of the sliced solar cell prepared by the above preparation method provided by the embodiment of the present invention will be specifically described. As Figure 17 shown, the sliced solar cell provided by the present invention includes: a silicon substrate 1; p+ emitters 2 arranged at intervals on the first main surface of the silicon substrate 1; and a sliced area located between every two adjacent p+ emitters 2. Among them, the p+ emitter 2 is obtained by reducing the doping concentration by diffusing part of the doping elements into the oxide layer 3 prepared above it. Among them, as described above, the oxide layer 3 only exists during the preparation process and does not exist in the final structure of the solar cell. Therefore, there is no identification of the oxide layer 3 in Figure 17 .

[0083] In an optional embodiment, the difference H between the thickness of the silicon substrate 1 corresponding to the slicing area and the thickness of the silicon substrate 1 corresponding to the p+ emitter 2 is 2μm to 15μm. By setting the thickness difference between the slicing area and the non-slicing area, the p+ emitter 2 in the non-slicing area will not be laterally redistributed to the slicing area during the preparation process, that is, the pn junction in the slicing area is completely removed, which is more conducive to the implementation of the subsequent slicing process.

[0084] In an optional embodiment, the sliced solar cell provided by the present invention further includes: a tunneling oxide layer 5, an n-type doping layer 6 and a second passivation anti-reflection layer 9 stacked from the inside to the outside on the second main surface of the silicon substrate 1; and a first passivation anti-reflection layer 8 arranged outside the p+ emitter 2 and the sliced area. The tunneling oxide layer can be silicon oxide with a thickness of 0.5nm to 3nm, such as 0.5nm, 1nm, 2nm, 3nm, etc. The thickness of the n-type doping layer 6 can be 30nm to 200nm, such as 30nm, 80nm, 100nm, 150nm, 200nm, etc. Furthermore, the doping concentration of the doping element in the n-type doping layer 6 can be 1x10 20 atom / cm 3 ~1ⅹ10 21 atom / cm 3 , for example 1 x 10 20 atom / cm 3 5 x 10 20 atom / cm 3 8ⅹ10 20 atom / cm 3 1 x 10 21 atom / cm 3 wait.

[0085] In an optional embodiment, the materials of the first passivation anti-reflection layer 8 and the second passivation anti-reflection layer 9 may be the same or different. Specifically, the first passivation anti-reflection layer 8 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride, and the second passivation anti-reflection layer 9 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum nitride.

[0086] In addition, a first metal electrode 10 and a second metal electrode 11 are respectively provided on the front and back sides of the silicon substrate 1; wherein the first metal electrode 10 penetrates the first passivation anti-reflection layer 8 and is electrically connected to the p+ emitter 2, and the second metal electrode 11 penetrates the second passivation anti-reflection layer 9 and is electrically connected to the n-type doping layer 6. For the material of the first metal electrode 10 and the second metal electrode 11, conventional electrode materials such as silver and copper can be selected, and the present invention does not specifically limit this.

[0087] In summary, for the solar cell provided by an embodiment of the present invention, by further preparing an oxide layer after preparing a p+ emitter in a non-sliced area, part of the doping elements in the p+ emitter can diffuse into the corresponding oxide layer above it, thereby reducing the doping concentration of the p+ emitter, reducing Auger recombination, and effectively improving the open-circuit voltage of the solar cell. At the same time, the silicon substrate corresponding to the sliced area can undergo lattice recrystallization under high-temperature conditions, achieving further repair of the silicon substrate.

[0088] Embodiment

[0089] A method for preparing a sliced solar cell includes:

[0090] Step a: Using an n-type silicon substrate as a silicon substrate, placing it in a texturing solution for texturing treatment;

[0091] Step b: Diffusing boron elements on the front surface of the silicon substrate 1 to form a p+ emitter 2 and a borosilicate glass layer BSG laminated outside the p+ emitter 2 on the front surface of the silicon substrate 1, and forming a p+ emitter 2 and a borosilicate glass layer BSG laminated outside the p+ emitter 2 by edge plating on the back surface in a partial area;

[0092] Step c: Processing the p+ emitter 2 and the borosilicate glass layer BSG in the sliced area using a laser process; the laser is a green picosecond pulsed laser with a wavelength of 500 nm, a power of 50 W, a pulse width of 25 ps, and a single pulse energy of 150 mJ;

[0093] Step d: Removing the borosilicate glass layer BSG formed by edge plating on the back surface using a hydrofluoric acid solution with a volume fraction of 25%;

[0094] Step e: Synchronously cleaning the sliced area on the front surface of the silicon substrate 1 and the p+ emitter 2 formed by edge plating on the back surface using a NaOH alkaline solution to etch the sliced area, and forming a thickness difference H of 10 μm between the sliced area of the silicon substrate 1 and the p+ emitter 2;

[0095] Step f: Removing the borosilicate glass layer BSG on the p+ emitter 2 using a hydrofluoric acid solution with a volume fraction of 25%;

[0096] Step g: Under an oxygen-containing condition, forming a BSG (first oxide layer 31) outside the p+ emitter 2, forming a second oxide layer 32 outside the sliced area, and simultaneously forming an undoped oxide layer 4 on the back surface of the silicon substrate. The preparation temperature is 950 °C and the time is 60 min;

[0097] Step h: Removing the undoped oxide layer 4 on one side of the back surface of the silicon substrate using a hydrofluoric acid solution with a volume fraction of 5%;

[0098] Step i, a tunneling oxide layer 5, an n-type doped layer 6, and a phosphosilicate glass layer PSG are sequentially prepared from the inside to the outside on the back surface of the silicon substrate 1 by plasma enhanced chemical vapor deposition (PECVD) and annealing, and a wrap-around structure is simultaneously formed on the first oxide layer 31, the second oxide layer 32, and the outside; wherein, the thickness of the tunneling oxide layer is 2 nm, and the thickness of the n-type doped layer is 100 nm;

[0099] Step j, a wrap-around structure, the first oxide layer 31, the second oxide layer 32, and the phosphosilicate glass layer PSG on the back surface of the silicon substrate 1 are removed in sequence by using a hydrofluoric acid solution with a volume fraction of 15%, an alkali solution, and a hydrofluoric acid solution with a volume fraction of 23% on the front surface of the silicon substrate 1;

[0100] Step k, an alumina layer with a thickness of 5 nm is prepared on the front surface of the silicon substrate 1 at 200 °C by atomic layer deposition (ALD), and a silicon nitride layer is deposited on the front and back surfaces of the silicon substrate 1 respectively by PECVD at 550 °C, a pressure of 255 Pa, and a radio frequency power of 10,000 W, to obtain a first passivation and antireflection layer 8 composed of an alumina layer and a silicon nitride layer on the front surface, and a second passivation and antireflection layer 9 composed of a silicon nitride layer on the back surface, wherein, the thickness of the first passivation and antireflection layer 8 on the front surface of the silicon substrate 1 is 95 nm, and the thickness of the second passivation and antireflection layer 9 on the back surface of the silicon substrate 1 is 100 nm;

[0101] Step l, a first metal electrode 10 and a second metal electrode 11 are respectively prepared on the front and back surfaces of the silicon substrate 1 by screen printing; wherein, the first metal electrode 10 penetrates through the first passivation and antireflection layer 8 and is electrically connected to the p+ emitter 2, and the second metal electrode 11 penetrates through the second passivation and antireflection layer 9 and is electrically connected to the n-type doped layer 6.

[0102] Comparative Example 1

[0103] A preparation method of a sliced solar cell, including:

[0104] Step a, using an n-type silicon substrate as a silicon substrate, and placing it in a texturing solution for texturing treatment;

[0105] Step b, boron element diffusion is carried out on the front surface of the silicon substrate 1 to form a p+ emitter 2 and a borosilicate glass layer BSG stacked outside the p+ emitter on the front surface of the silicon substrate, and a p+ emitter 2 and a borosilicate glass layer BSG stacked outside the p+ emitter are formed by wrap-around plating in a partial area on the back surface;

[0106] Step c: Under an oxygen - passing condition, an oxide layer 3 is prepared outside the borosilicate glass layer BSG on the front side of the silicon substrate 1. After the boron element in the original borosilicate glass layer BSG diffuses into the oxide layer 3, a new layer of borosilicate glass layer BSG is formed outside the original borosilicate glass layer BSG, and simultaneously a new layer of borosilicate glass layer BSG is formed by side - plating outside the borosilicate glass layer BSG on the back side of the silicon substrate 1. The preparation temperature is 950 °C and the time is 60 min.

[0107] Step d: The borosilicate glass layer BSG and the p+ emitter in the sliced area are processed using a laser process. The laser is a green - light picosecond pulsed laser with a wavelength of 500 nm, a power of 50 W, a pulse width of 25 ps, and a single - pulse energy of 150 mJ.

[0108] Step e: The borosilicate glass layer BSG on the back side of the silicon substrate 1 is removed using a hydrofluoric acid solution with a volume concentration of 25%. Meanwhile, the sliced area on the front side of the silicon substrate 1 is cleaned using a NaOH alkaline solution, and the p+ emitter 2 plated on the back side of the silicon substrate 1 is removed. A thickness difference H of 10 μm is formed between the sliced area of the silicon substrate 1 and the p+ emitter.

[0109] Step f: The silicon substrate is heated at 900 °C to repair the damage of the silicon substrate in the sliced area.

[0110] Step g: Using plasma - enhanced chemical vapor deposition (PECVD) and annealing methods, a tunneling oxide layer 5, an n - type doped layer 6, and a phosphosilicate glass layer PSG are sequentially prepared from the inside to the outside on the back side of the silicon substrate 1, and a side - plating structure is simultaneously formed outside the BSG on the front side. Among them, the thickness of the tunneling oxide layer is 2 nm, and the thickness of the n - type doped layer is 100 nm.

[0111] Step h: The side - plating structure on the front side of the silicon substrate 1, the first oxide layer 31, the second oxide layer 32, and the phosphosilicate glass layer PSG on the back side of the silicon substrate 1 are removed using a hydrofluoric acid solution with a volume fraction of 15%, an alkaline solution, and a hydrofluoric acid solution with a volume fraction of 23% in sequence.

[0112] Step i: An aluminum oxide layer with a thickness of 5 nm is prepared on the front side of the silicon substrate 1 at 200 °C using atomic layer deposition (ALD). Using PECVD method, at 550 °C, a pressure of 255 Pa, and a radio - frequency power of 10000 W, a silicon nitride layer is deposited on the front and back sides of the silicon substrate 1 respectively, obtaining a first passivation and antireflection layer 8 composed of an aluminum oxide layer and a silicon nitride layer on the front side, and a second passivation and antireflection layer 9 composed of a silicon nitride layer on the back side. Among them, the thickness of the first passivation and antireflection layer 8 on the front side of the silicon substrate 1 is 95 nm, and the thickness of the second passivation and antireflection layer 9 on the back side of the silicon substrate 1 is 100 nm.

[0113] Step j: Prepare the first metal electrode 10 and the second metal electrode 11 on the front and back of the silicon substrate 1 respectively by screen printing. Among them, the first metal electrode 10 penetrates through the first passivation and antireflection layer 8 and is electrically connected to the p+ emitter 2, and the second metal electrode 11 penetrates through the third passivation and antireflection layer 9 and is electrically connected to the n-type doping layer 6.

[0114] Comparative Example 2

[0115] A preparation method of a sliced solar cell, comprising:

[0116] Step a: Use an n-type silicon substrate as the silicon substrate and place it in a texturing solution for texturing treatment.

[0117] Step b: Diffuse boron elements on the front of the silicon substrate 1 to form a p+ emitter 2 and a borosilicate glass layer BSG laminated outside the p+ emitter 2 on the front of the silicon substrate 1, and form a p+ emitter 2 and a borosilicate glass layer BSG laminated outside the p+ emitter 2 by edge plating in a partial area on the back.

[0118] Step c: Use a laser process to process the p+ emitter 2 and the borosilicate glass layer BSG in the sliced area. The laser is a green picosecond pulsed laser with a wavelength of 500 nm, a power of 50 W, a pulse width of 25 ps, and a single pulse energy of 150 mJ.

[0119] Step d: Under an oxygen passing condition, form a new borosilicate glass layer BSG (the first oxide layer 31) on the original borosilicate glass layer BSG, and form a second oxide layer 32 outside the sliced area, and simultaneously form a new borosilicate glass layer BSG outside the borosilicate glass layer BSG on the back of the silicon substrate 1. The preparation temperature is 950 °C and the time is 60 min.

[0120] Step e: Use a hydrofluoric acid solution with a volume fraction of 25% to remove the borosilicate glass layer BSG on the back.

[0121] Step f: Use a NaOH alkaline solution to simultaneously clean the sliced area on the front of the silicon substrate 1 and the p+ emitter 2 formed by edge plating on the back to etch the sliced area, and form a thickness difference H of 10 μm between the sliced area of the silicon substrate 1 and the p+ emitter 2.

[0122] Step g: Use plasma enhanced chemical vapor deposition (PECVD) and annealing to sequentially prepare a tunneling oxide layer 5, an n-type doping layer 6, and a phosphosilicate glass layer PSG from the inside to the outside on the back of the silicon substrate, and simultaneously form an edge plating structure outside the BSG (the first oxide layer 31) and the second oxide layer 32 on the front of the silicon substrate. Among them, the thickness of the tunneling oxide layer is 2 nm, and the thickness of the n-type doping layer is 100 nm.

[0123] Step h, sequentially remove the overplated structure, the first oxide layer 31, the second oxide layer 32 on the front of the silicon substrate 1, and the phosphosilicate glass layer PSG on the back of the silicon substrate 1 by using a hydrofluoric acid solution with a volume fraction of 15%, an alkali solution, and a hydrofluoric acid solution with a volume fraction of 23%;

[0124] Step i, use atomic layer deposition (ALD) to prepare a 5-nm alumina layer on the front of the silicon substrate 1 at 200 °C, and use PECVD to deposit silicon nitride layers on the front and back of the silicon substrate 1 at 550 °C, a pressure of 255 Pa, and a radio frequency power of 10,000 W, respectively, to obtain a first passivation and antireflection layer 8 composed of an alumina layer and a silicon nitride layer on the front, and a second passivation and antireflection layer 9 composed of a silicon nitride layer on the back. Among them, the thickness of the first passivation and antireflection layer 8 on the front of the silicon substrate 1 is 95 nm, and the thickness of the second passivation and antireflection layer 9 on the back of the silicon substrate 1 is 100 nm;

[0125] Step k, use screen printing to prepare a first metal electrode 10 and a second metal electrode 11 on the front and back of the silicon substrate 1, respectively; among them, the first metal electrode 10 penetrates the first passivation and antireflection layer 8 and is electrically connected to the p+ emitter 2, and the second metal electrode 11 penetrates the second passivation and antireflection layer 9 and is electrically connected to the n-type doping layer 6.

[0126] Comparative Example 3

[0127] A preparation method of a sliced solar cell, including:

[0128] Step a, use an n-type silicon substrate as a silicon substrate, and place it in a texturing solution for texturing treatment;

[0129] Step b, perform boron element diffusion on the front of the silicon substrate 1 to form a p+ emitter 2 and a borosilicate glass layer BSG laminated outside the p+ emitter 2 on the front of the silicon substrate, and form a p+ emitter and a borosilicate glass layer BSG laminated outside the p+ emitter by overplating in a partial area on the back;

[0130] Step c, under an oxygen-containing condition, prepare an oxide layer 3 outside the borosilicate glass layer BSG on the front of the silicon substrate 1. After the boron element in the original borosilicate glass layer BSG diffuses into the oxide layer 3, a new layer of borosilicate glass layer BSG is formed outside the original borosilicate glass layer BSG, and at the same time, a new layer of borosilicate glass layer BSG is formed by overplating outside the borosilicate glass layer BSG on the back of the silicon substrate 1; the preparation temperature is 950 °C and the time is 60 min;

[0131] Step d, use a hydrofluoric acid solution with a volume concentration of 25% to remove the borosilicate glass layer BSG on the back of the silicon substrate 1, and use an alkali solution to remove the p+ emitter overplated on the back of the silicon substrate;

[0132] Step e: The tunneling oxide layer 5, n-type doping layer 6, and phosphosilicate glass layer PSG are sequentially prepared from the inside to the outside on the back of the silicon substrate 1 by plasma-enhanced chemical vapor deposition (PECVD) and annealing, and a plating-around structure is simultaneously formed on the outside of the borosilicate glass layer BSG on the front side; among them, the thickness of the tunneling oxide layer is 2 nm, and the thickness of the n-type doping layer is 100 nm.

[0133] Step f: The plating-around structure, borosilicate glass layer BSG, and p+ emitter 2 in the sliced area are processed by a laser process; the laser is a green picosecond pulsed laser with a wavelength of 500 nm, a power of 50 W, a pulse width of 25 ps, and a single-pulse energy of 150 mJ.

[0134] Step g: The plating-around structure on the front of the silicon substrate, the borosilicate glass layer BSG, and the phosphosilicate glass layer PSG on the back of the silicon substrate are removed sequentially using a hydrofluoric acid solution with a volume fraction of 15%, an alkali solution, and a hydrofluoric acid solution with a volume fraction of 23%.

[0135] Step h: A 5-nm aluminum oxide layer is prepared on the front of the silicon substrate 1 at 200 °C by atomic layer deposition (ALD), and a silicon nitride layer is deposited on the front and back of the silicon substrate 1 at 550 °C, a pressure of 255 Pa, and a radio frequency power of 10,000 W by PECVD to obtain a first passivation and antireflection layer 8 composed of an aluminum oxide layer and a silicon nitride layer on the front, and a second passivation and antireflection layer 9 composed of a silicon nitride layer on the back. Among them, the thickness of the first passivation and antireflection layer 8 on the front of the silicon substrate 1 is 95 nm, and the thickness of the second passivation and antireflection layer 9 on the back of the silicon substrate 1 is 100 nm.

[0136] Step i: The first metal electrode 10 and the second metal electrode 11 are prepared on the front and back of the silicon substrate 1 by screen printing; among them, the first metal electrode 10 penetrates the first passivation and antireflection layer 8 and is electrically connected to the p+ emitter 2, and the second metal electrode 11 penetrates the third passivation and antireflection layer 9 and is electrically connected to the n-type doping layer 6.

[0137] The sliced solar cells prepared in the above examples and comparative examples are respectively subjected to performance tests, and the test results are shown in Tables 1 and 2:

[0138] Table 1: Electrical performance results

[0139]

[0140] Table 2: Boron element concentration results

[0141]

[0142] As can be seen from Table 1 and Table 2 above, there are also differences in the performance of the solar cells prepared with different execution sequences, which also shows that different process flows have different effects on reducing the p+ emitter concentration. Specifically, through J01 and J02 in Table 1, it can be seen that the solar cells prepared in the embodiments of the present invention effectively reduce the damage caused by the laser process, and compared with the solar cells prepared by changing the execution sequence of the corresponding steps in multiple comparative examples, the open-circuit voltage and fill factor are improved. Moreover, since the boron-silicate glass layer BSG was not removed before preparing the oxide layer in Comparative Examples 1-3, although the boron element in the p+ emitter could be appropriately extracted, compared with the embodiments, the presence of the boron-silicate glass layer BSG would reduce the extraction efficiency of the boron element. Therefore, the concentration of the p+ emitter in the embodiments is lower than that in Comparative Examples 1-3, and the passivation performance is also more excellent.

[0143] From the change in the boron element concentration in Table 2, it can be seen that the process of preparing the oxide layer in the embodiments of the present invention effectively increases the resistance, and on the basis of reducing the junction depth, reduces the surface concentration and peak concentration of the boron element, further reduces the Auger recombination, and effectively improves the open-circuit voltage of the solar cell.

[0144] The introduction provided in the above steps is only used to help understand the structure, method and core idea of the present invention. For those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A preparation method of a sliced solar cell, characterized in that, Including: Step 1: Form spaced-apart p+ emitters (2) and sliced regions located between every two adjacent p+ emitters (2) on the first main surface of the silicon substrate (1); Step 2: Prepare an oxide layer (3) on the p+ emitter (2) and the sliced region under the condition that the temperature is 900 °C to 1100 °C. Wherein, a part of the doping elements in the p+ emitter (2) diffuse into the corresponding oxide layer (3) above it to reduce the doping concentration of the p+ emitter (2); Step 3: Remove the oxide layer (3) by a wet process.

2. The preparation method according to claim 1, characterized in that, The said Step 1 includes: Step 11: Perform boron diffusion treatment on the first main surface of the silicon substrate (1) to form a p+ emitter (2) and a first silicon glass layer (100) of p-type doping elements stacked on the p+ emitter (2); Step 12: Use a laser process to turn the p+ emitter (2) and the first silicon glass layer (100) of p-type doping elements corresponding to the sliced region into a molten state, and use an alkaline solution to clean the sliced region to obtain spaced-apart p+ emitters (2), and make the thickness of the silicon substrate (1) corresponding to the sliced region less than the thickness of the silicon substrate (1) corresponding to the p+ emitter (2); Step 13: Use an acid solution with a first concentration to remove the remaining first silicon glass layer (100) of p-type doping elements on the p+ emitter (2); wherein, the volume fraction of the acid solution with the first concentration is 10% to 60%.

3. The preparation method according to claim 2, wherein, The said Step 11 further includes: Synchronously form a p+ emitter (2) and a first silicon glass layer (100) of p-type doping elements by circumferential plating on the second main surface of the silicon substrate (1); After the said Step 12 and before Step 13, it further includes: Successively remove the first silicon glass layer (100) of p-type doping elements and the p+ emitter (2) circumferentially plated on the second main surface of the silicon substrate (1).

4. The preparation method according to claim 1, wherein The said Step 2 further includes: While forming the oxide layer (3), form an undoped oxide layer (4) on the second main surface of the silicon substrate (1); Before the said Step 3, it further includes: Use an acid solution with a second concentration to remove the undoped oxide layer (4), wherein, the volume fraction of the acid solution with the second concentration is 2% to 8%.

5. The preparation method according to claim 1, wherein, The said oxide layer (3) includes: A first oxide layer (31) corresponding to the p+ emitter (2) and a second oxide layer (32) corresponding to the sliced region; Wherein, the first oxide layer (31) contains doping elements diffused from the p+ emitter (2), and the second oxide layer (32) does not contain doping elements diffused from the p+ emitter (2).

6. The preparation method according to claim 5, characterized in that, After the said Step 2 and before Step 3, it further includes: A tunneling oxide layer (5), an n-type doped layer (6), and a first silicon glass layer (7) of an n-type doping element are sequentially formed from the inside to the outside on the second main surface of the silicon substrate (1), and a plating-around structure is simultaneously formed outside the first oxide layer (31) and the second oxide layer (32); wherein, the plating-around structure includes: a first plating-around structure (200) corresponding to the first oxide layer (31) and a second plating-around structure (300) corresponding to the second oxide layer (32).

7. The manufacturing method according to claim 1, characterized in that The doping concentration of the p-type doping element in the p+ emitter (2) formed in the step 1 is 1×10 18 atom / cm 3 ~1×10 20 atom / cm 3 ; and / or After the step 2, the doping concentration of the doping element of the p+ emitter (2) is 1×10 17 atom / cm 3 ~1×10 19 atom / cm 3 .

8. The manufacturing method according to claim 2, characterized in that The laser process uses a green picosecond pulsed laser with a wavelength of 200 nm to 600 nm, wherein the pulse width of the green picosecond pulsed laser is 1 ps to 50 ps, the laser power is 20 W to 100 W, and the single pulse energy is 50 mJ to 200 mJ.

9. A sliced solar cell, characterized in that, including: a silicon substrate (1); p+ emitters (2) arranged at intervals on the first main surface of the silicon substrate (1); and, a slicing region located between every two adjacent p+ emitters (2); wherein, the p+ emitter (2) is obtained by reducing the doping concentration by diffusing a part of the doping element into the oxide layer (3) above it. Preferably, it further includes: The difference H between the thickness of the silicon substrate (1) corresponding to the slicing region and the thickness of the silicon substrate (1) corresponding to the p+ emitter (2) is 2 μm to 15 μm.

10. The sliced solar cell according to claim 9, wherein It further includes: a tunneling oxide layer (5), an n-type doped layer (6), and a second passivation and antireflection layer (9) stacked from the inside to the outside on the second main surface of the silicon substrate (1); and, a first passivation and antireflection layer (8) provided outside the p+ emitter (2) and the slicing region.

Images