A back contact solar cell

Abstract

The present application relates to a kind of back contact solar cell, it is related to solar cell technical field, back contact solar cell includes: silicon base, back surface includes first area, second area and intersection area, first area is higher than second area, intersection area includes step;First area is sequentially stacked with first carrier collection layer and first conductive layer from the surface of silicon base to outside;Second area is sequentially stacked with second carrier collection layer and second conductive layer from the surface of silicon base to outside, second conductive layer does not extend to the step face of step;Intersection area includes third intersection area located on the step face and extending to the edge of step face, second carrier collection layer extends from second area to third intersection area, and the surface of third intersection area is provided with second carrier collection layer, and third intersection area is not provided with first carrier collection layer.The cell has excellent anti-creeping effect and photoelectric conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back-contact solar cell. Background Art

[0002] In recent years, heterojunction back contact (HBC) solar cells have become a research hotspot in the photovoltaic field due to their advantages such as high open-circuit voltage, low temperature coefficient, and no front-side shading loss. The back side of an HBC cell typically features alternating n-type and p-type regions, with carrier separation achieved through a localized metal contact.

[0003] A back-contact solar cell provided by prior art includes a silicon substrate, the back side of which includes a first region, a second region, and an intersection region between the first and second regions. The first region is provided with a first carrier collection layer and a first conductive layer, the second region is provided with a second carrier layer and a second conductive layer, and the intersection region is provided with a stacked first and second carrier collection layers. The first and second conductive layers both extend to the intersection region and are separated. However, such back-contact solar cells are prone to leakage. Summary of the Invention

[0004] Based on this, the present invention provides a back-contact solar cell to solve the problem that the existing back-contact solar cells are prone to leakage.

[0005] The present invention provides a back-contact solar cell comprising:

[0006] A silicon substrate, wherein the back surface includes a first region, a second region, and an intersection region between the first region and the second region, the first region is higher than the second region, and the intersection region includes a step;

[0007] The first region is provided with a first carrier collection layer and a first conductive layer stacked in sequence from the surface of the silicon substrate outward;

[0008] The second region is provided with a second carrier collection layer and a second conductive layer stacked sequentially from the surface of the silicon substrate outward, and the second conductive layer does not extend to the step surface of the step;

[0009] The intersection region includes a third intersection region located on the step surface and extending to the edge of the step surface, the second carrier collection layer extends from the second region to the third intersection region, and the second carrier collection layer is provided on the surface of the third intersection region, and the first carrier collection layer is not provided in the third intersection region.

[0010] In one embodiment, the width of the third intersection region is 0.01-10 μm.

[0011] In one embodiment, the intersection region also includes a fourth intersection region located between the third intersection region and the second region, the fourth intersection region includes the side of the step surface, the second carrier collection layer covers the side of the step surface, and an isolation groove is formed between the second conductive layer and the second carrier collection layer located on the side of the step surface.

[0012] In one embodiment, the width of the fourth intersection region is 30-90 μm.

[0013] In one embodiment, the intersection region further includes a second intersection region connected to the third intersection region and extending to the first region;

[0014] The second intersection region is provided with the first carrier collection layer and the second carrier collection layer stacked in sequence from the surface of the silicon substrate outward.

[0015] In one embodiment, the width of the second intersection region is 30-90 μm.

[0016] In one embodiment, the intersection region further includes a first intersection region disposed between the first region and the second intersection region, wherein the first intersection region is provided with the first carrier collection layer, the second carrier collection layer and the first conductive layer stacked in sequence from the surface of the silicon substrate outward.

[0017] In one embodiment, the width of the first intersection region is 50-150 μm.

[0018] In one embodiment, the second carrier collection layer includes a stacked first intrinsic hydrogenated silicon-containing layer and a second doped silicon layer in a direction away from the silicon substrate, and the second doped silicon layer is connected to the second conductive layer;

[0019] The first carrier collection layer includes a stacked tunneling passivation layer and a first doped silicon layer in a direction away from the silicon substrate, and the first doped silicon layer is connected to the first conductive layer.

[0020] In one embodiment, the thickness of the first intrinsic hydrogenated silicon-containing layer is 1-10 nm;

[0021] And / or, the material of the second doped silicon layer includes at least one of amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide and silicon carbide;

[0022] And / or, the second doped silicon layer includes one layer or a stack of at least two of an amorphous silicon layer, a microcrystalline silicon layer, a nanocrystalline silicon layer, a silicon oxide layer, and a silicon carbide layer;

[0023] And / or, the thickness of the second doped silicon layer is 1-50 nm;

[0024] And / or, the thickness of the tunnel passivation layer is 0.5 nm to 3 nm;

[0025] And / or, the thickness of the first doped silicon layer is 20-100 nm;

[0026] And / or, the material of the first conductive layer and the second conductive layer includes at least one of a metal oxide containing a doping element and a metal nitride containing a doping element, wherein the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, cadmium oxide, and titanium nitride, the metal nitride includes titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, and fluorine;

[0027] The first conductive layer and the second conductive layer are single-layer film layers or multi-layer stacked film layers.

[0028] In one embodiment, there is a height difference between the first region and the second region, and the height difference is less than 20 μm.

[0029] In one embodiment, the back-contact solar cell further includes: a first electrode electrically connected to the first conductive layer, and a second electrode electrically connected to the second conductive layer.

[0030] In one embodiment, the back-contact solar cell further includes: a passivation layer and an anti-reflection layer stacked sequentially from the front surface of the silicon substrate outward.

[0031] In one embodiment, the silicon substrate is an n-type silicon substrate;

[0032] The first doped silicon layer is an n-type doped silicon layer, and the second doped silicon layer is a p-type doped silicon layer.

[0033] Compared with the prior art, the present invention has at least the following beneficial effects:

[0034] The back-contact solar cell provided by the present invention is provided with only the second carrier collection layer on the third intersection region, i.e., the step surface. Compared with the prior art in which the first carrier collection layer and the second carrier collection layer are completely stacked in the intersection region, the stacking area of ​​the first carrier collection layer and the second carrier collection layer is reduced, and the risk of leakage caused by electrical conduction between the first carrier collection layer and the second carrier collection layer is reduced. Since the second conductive layer does not extend to the step surface, the horizontal spacing between the first conductive layer and the second conductive layer is increased, so that horizontal isolation is formed between the two, avoiding the problem of leakage caused by electrical conduction between the first conductive layer and the second conductive layer. In addition, the first carrier collection layer and the first conductive layer provided in the first region form a height difference with the second carrier collection layer and the second conductive layer provided in the second region due to the step, which forms a vertical isolation between the two, avoiding the problem of leakage. It can be seen that by reducing the stacking area between the first carrier collection layer and the second carrier collection layer, and by horizontally isolating and vertically isolating the first conductive layer and the second conductive layer, the back-contact solar cell provided by the embodiment of the present invention has an excellent anti-leakage effect, which is beneficial to improving the photoelectric conversion efficiency of the back-contact solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the structure of a back-contact solar cell in one embodiment.

[0036] The reference numerals in the drawings of the specification include:

[0037] 100-silicon substrate; 110-step; 120-protrusion;

[0038] 200 - first carrier collection layer; 210 - tunneling passivation layer; 220 - first doped silicon layer;

[0039] 310 - first conductive layer; 320 - first electrode;

[0040] 400 - second carrier collection layer; 410 - first intrinsic hydrogenated silicon-containing layer; 420 - second doped silicon layer;

[0041] 510 - second conductive layer; 520 - second electrode;

[0042] 600-passivation layer;

[0043] 700-anti-reflection layer;

[0044] 800-isolation tank;

[0045] A-first area; A1-enhanced passivation area;

[0046] B-Second area;

[0047] C1-first intersection zone; C2-second intersection zone; C3-third intersection zone; C4-fourth intersection zone. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0049] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention.

[0050] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so that people familiar with this technology can understand and read them. They are not used to limit the conditions under which the present invention can be implemented. Any structural modifications, changes in proportional relationships, or adjustments in size should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0051] Terms such as "upper," "lower," "left," "right," "center," "longitudinal," "transverse," "horizontal," "inner," "outer," "radial," and "circumferential" used in this specification to indicate positions or locations are based on those shown in the accompanying drawings and are intended solely for ease of description. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

[0052] As described in the background, a back-contact solar cell provided by prior art includes a silicon substrate, the back side of which includes a first region, a second region, and an intersection region between the first and second regions. The first region includes a first carrier collection layer and a first conductive layer, the second region includes a second carrier collection layer and a second conductive layer, and the intersection region includes a stacked first and second carrier collection layers, with the first and second conductive layers extending to and separated from each other in the intersection region. The first and second carrier collection layers have opposite conductivity types. The first carrier collection layer includes a tunneling passivation layer and a first doped silicon layer disposed on the surface of the tunneling passivation layer. The second carrier collection layer includes an intrinsic hydrogenated silicon layer and a second doped silicon layer disposed on the surface of the intrinsic hydrogenated silicon layer. When the first and second carrier collection layers are stacked, with the intrinsic hydrogenated silicon layer located between the first and second doped silicon layers, the intrinsic hydrogenated silicon layer is relatively thin and has limited passivation effect. This can easily lead to electrical conduction between the stacked first and second doped silicon layers, causing leakage in the solar cell.

[0053] In addition, since both the first conductive layer and the second conductive layer extend to the intersection area, the width of the intersection area is very small in actual applications. Due to process errors or other reasons, there is often conduction between the first conductive layer and the second conductive layer, causing leakage problems in the back-contact solar cell.

[0054] It should be noted that when there is electrical conduction between the first doped silicon layer and the second doped silicon layer, or when there is electrical conduction between the first conductive layer and the second conductive layer, the output current of the back contact solar cell will be reduced, that is, leakage problem will occur.

[0055] In order to solve the above problems, an embodiment of the present invention provides a back-contact solar cell, comprising:

[0056] The back surface of the silicon substrate 100 includes a first region A, a second region B, and an intersection region C between the first region A and the second region B. The first region A is higher than the second region B. The intersection region C includes a step 110.

[0057] The first region A is formed by sequentially stacking a first carrier collection layer 200 and a first conductive layer 310 from the surface of the silicon substrate 100 outwards;

[0058] The second region B is provided with a second carrier collection layer 400 and a second conductive layer 510 stacked sequentially from the surface of the silicon substrate 100 outwards, and the second conductive layer 510 does not extend to the step surface of the step 110;

[0059] The intersection region C includes a third intersection region C3 located on the step surface and extending to the edge of the step surface. The second carrier collection layer 400 extends from the second region B to the third intersection region C3, and the surface of the third intersection region C3 is provided with a second carrier collection layer 400. The first carrier collection layer 200 is not provided in the third intersection region C3.

[0060] It should be noted that the third intersection region C3 is a region between a portion of the intersection region C connected to the first region A and a side surface of the step 110 .

[0061] In the back-contact solar cell provided by the present embodiment, only the second carrier collection layer 400 is disposed on the third intersection region C3, also known as the step surface. Compared to prior art methods in which the first and second carrier collection layers 200 and 400 are fully stacked at the intersection region, this reduces the stacking area of ​​the first and second carrier collection layers 200 and 400, thereby reducing the risk of leakage caused by electrical conduction between the first and second carrier collection layers 200 and 400. Because the second conductive layer 510 does not extend onto the step surface, this increases the horizontal spacing between the first and second conductive layers 310 and 510, creating horizontal isolation and preventing leakage caused by electrical conduction between the first and second conductive layers 310 and 510. Furthermore, the height difference between the first and second carrier collection layers 200 and 310 located in the first region A and the second and second carrier collection layers 400 and 510 located in the second region B due to the step 110 creates vertical isolation between the two, preventing leakage. It can be seen that by reducing the stacking area between the first carrier collection layer 200 and the second carrier collection layer 400, and by horizontally isolating and vertically isolating the first conductive layer 310 and the second conductive layer 510, the back-contact solar cell provided by the embodiment of the present invention has an excellent anti-leakage effect, which is beneficial to improving the photoelectric conversion efficiency of the back-contact solar cell.

[0062] In an embodiment of the present invention, the silicon substrate 100 is a doped silicon substrate. For example, the silicon substrate can be an n-type doped silicon substrate, or it can be a p-type doped silicon substrate. The n-type doping element can be phosphorus (P) or arsenic (As), and the p-type doping element can be boron or gallium (Ga). The silicon substrate 100 is in the form of a silicon sheet and includes a front surface and a back surface, which are arranged relative to each other along the thickness direction of the silicon substrate 100. In this embodiment, the front surface direction and the back surface direction of the silicon substrate 100 are defined based on the light-facing surface and the back surface of the silicon substrate 100. For example, the light-facing surface of the silicon substrate 100 is defined as the front surface, and the back surface of the silicon substrate 100 is defined as the back surface.

[0063] See also Figure 1A passivation layer 600 and an anti-reflection layer 700 are sequentially stacked from the front surface of the silicon substrate 100 outward. The passivation layer 600 includes a second intrinsic hydrogenated silicon-containing layer. For example, the passivation layer 600 can be a single second intrinsic hydrogenated silicon-containing layer, or a stack of the second intrinsic hydrogenated silicon-containing layer and an n-type doped silicon layer. The thickness of the second intrinsic hydrogenated silicon-containing layer can be 1-15 nm, for example, 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 12 nm, or 15 nm, and the thickness of the n-type doped silicon layer can be less than 15 nm, for example, 5 nm, 8 nm, 10 nm, 12 nm, or 15 nm. The material of the anti-reflection layer 700 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, indium tin oxide, and zinc oxide. The thickness of the anti-reflection layer 700 can be 40-200 nm, for example, 40 nm, 100 nm, 120 nm, 150 nm, 180 nm, or 200 nm. The passivation layer 600 and the anti-reflection layer 700 are provided to enhance the passivation and anti-reflection effects of the back-contact solar cell, thereby improving its photoelectric conversion efficiency.

[0064] See also Figure 1 In an embodiment of the present invention, the back surface of the silicon substrate 100 is divided into a first region A, a second region B, and a cross region C. This is not a strict division, but rather a distinction based on the different types of functional layers provided. The first region A can be provided with an n-type conductive film layer, and the second region B can be provided with a p-type conductive film layer. Alternatively, the first region A can be provided with a p-type conductive film layer, and the second region B can be provided with an n-type conductive film layer.

[0065] It should be understood that multiple groups of first regions A and second regions B are alternately distributed on the entire back surface of the silicon substrate 100, and each group of first regions A and second regions B is separated by an intersection region C. The structure of only one group of first regions A, second regions B, and intersection region C is described below as an example.

[0066] The first region A is sequentially stacked from the back surface of the silicon substrate 100 outward, with a first carrier collection layer 200 and a first conductive layer 310, as well as a first electrode 320 electrically connected to the first conductive layer 310. The first conductive layer 310 and the first electrode 320 are used to conduct carriers collected by the first carrier collection layer 200. In other words, the first conductive layer 310 and the first electrode 320 are electrically connected to the first carrier collection layer 200.

[0067] In some embodiments, see Figure 1In a direction away from the silicon substrate 100, the first carrier collection layer 200 includes a stacked tunneling passivation layer 210 and a first doped silicon layer 220, wherein the first doped silicon layer 220 is connected to the first conductive layer 310. The specific materials and thicknesses of the tunneling passivation layer 210 and the first doped silicon layer 220, as well as the specific doping type and doping concentration of the doping elements in the first doped silicon layer 220, can be set according to actual needs, as long as they can be applied to the back-contact solar cell provided by the embodiments of the present invention. For example, in some embodiments, the material of the tunneling passivation layer 210 can be silicon oxide. The thickness of the tunneling passivation layer 210 is 0.5 nm to 3 nm, such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. The first doped silicon layer 220 can be a doped polysilicon layer, and the thickness of the first doped silicon layer 220 can be 20 to 100 nm, such as 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm. Setting the materials and thicknesses of the tunneling passivation layer 210 and the first doped silicon layer 220 in this manner is beneficial to improving the passivation effect and carrier collection capability of the structure.

[0068] In some embodiments, the material of the first conductive layer 310 may include at least one of a metal oxide containing a doping element and a metal nitride containing a doping element, wherein the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, cadmium oxide, and titanium nitride. The metal nitride includes titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, and fluorine. The first conductive layer 310 may be a single layer or a multilayer stack. This configuration can improve the carrier collection efficiency and conductivity of the first conductive layer 310.

[0069] The first electrode 320 is a metal electrode, and specifically can be a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, a nickel / copper / silver multilayer electrode, etc.

[0070] Continue to see Figure 1 The second region B is sequentially stacked from the back surface of the silicon substrate 100 outward and comprises a second carrier collection layer 400, a second conductive layer 510, and a second electrode 520 electrically connected to the second conductive layer 510. The second conductive layer 510 and the second electrode 520 are used to conduct carriers collected by the second carrier collection layer 400. In other words, the second conductive layer 510 and the second electrode 520 are electrically connected to the second carrier collection layer 400.

[0071] In some embodiments, see Figure 1, along the direction away from the silicon substrate 100, the second carrier collection layer 400 includes a stacked first intrinsic hydrogenated silicon-containing layer 410 and a second doped silicon layer 420, and the second doped silicon layer 420 is connected to the second conductive layer 510. Similarly, the materials, thicknesses, and doping types and concentrations of the first intrinsic hydrogenated silicon-containing layer 410 and the second doped silicon layer 420, and the doping types and concentrations of the doping elements in the second doped silicon layer 420 can be set according to actual needs, as long as they can be applied to the back-contact solar cell provided in the embodiment of the present invention. For example, the thickness of the first intrinsic hydrogenated silicon-containing layer 410 is 1-10 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, etc. The material of the second doped silicon layer 420 includes at least one of amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide, and silicon carbide, and the second doped silicon layer 420 includes one or a stack of at least two of the amorphous silicon layer, microcrystalline silicon layer, nanocrystalline silicon layer, silicon oxide layer, and silicon carbide layer. The thickness of the second doped silicon layer 420 can be 1-50 nm, for example, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. The material and thickness of the first intrinsic hydrogenated silicon-containing layer 410 and the second doped silicon layer 420 are configured in this manner to improve the passivation performance of the first intrinsic hydrogenated silicon-containing layer 410 and the carrier collection capability of the second doped silicon layer 420.

[0072] In addition, it should be noted that, in this embodiment, the second doped silicon layer 420 and the first doped silicon layer 220 have different doping types. For example, the second doped silicon layer 420 may be a p-type doped silicon layer doped with boron or other elements, and the first doped silicon layer 220 may be an n-type doped silicon layer doped with phosphorus or other elements. Alternatively, the first doped silicon layer 220 may be a p-type doped silicon layer doped with boron or other elements, and the second doped silicon layer 420 may be an n-type doped silicon layer doped with phosphorus or other elements.

[0073] The second conductive layer 510 may adopt the same structure or material as the first conductive layer 310 , and the second electrode 520 may adopt the same structure as the first electrode 320 , which will not be described in detail here.

[0074] In this embodiment, the electrically conductive film layer between the first region A and the second region B is isolated by the cross region C. Figure 1 In the vertical direction, that is, in the thickness direction of the silicon substrate 100, there is a height difference between the first conductive layer 310 and the second conductive layer 510, so that the two are staggered in the vertical direction, forming a spatial isolation, thereby avoiding the problem of leakage of the back contact solar cell caused by the conduction of the first conductive layer 310 and the second conductive layer 510.

[0075] For example, see Figure 1 A raised portion 120 is formed on the silicon substrate 100. The first region A is located on the surface of the raised portion 120, while the second region B is located on the surface of the non-raised portion of the silicon substrate 100. This creates a step 110 at the junction between the first region A and the second region B. The intersection C also includes the step 110. Furthermore, because the first conductive layer 310 is disposed on the first region A and the second conductive layer 510 is disposed on the second region B, a height difference exists between the first conductive layer 310 and the second conductive layer 510, creating vertical isolation. This prevents electrical conduction between the first conductive layer 310 and the second conductive layer 510, which could lead to leakage in the back-contact solar cell.

[0076] In some embodiments, there is a height difference between the first region A and the second region B, and the height difference is less than or equal to 20 μm. For example, the height difference can be 20 μm, 18 μm, 16 μm, 14 μm, 12 μm, 10 μm, 8 μm, or 6 μm. In addition, the height can also be other values ​​as long as the first conductive layer 310 and the second conductive layer 510 are staggered in the vertical direction and meet actual production requirements.

[0077] See also Figure 1 In the horizontal direction, that is, the horizontal extension direction of the back surface of the silicon substrate 100, there is a horizontal gap between the first conductive layer 310 and the second conductive layer 510, which separates the two in the horizontal direction and forms a spatial isolation, thereby avoiding the problem of leakage of the back contact solar cell caused by the conduction between the first conductive layer 310 and the second conductive layer 510.

[0078] For details, see Figure 1 , the third intersection region C3 is located on the step surface and extends to the edge of the step surface, that is, the third intersection region C3 does not extend to the side of the step surface. Since the surface of the third intersection region C3 is only provided with the second carrier collection layer 400, and the first carrier collection layer 200 is not provided, this reduces the area of ​​the stacked first carrier collection layer 200 and the second carrier collection layer 400 relative to the entire intersection region where the first carrier collection layer 200 and the second carrier collection layer 400 are stacked, thereby reducing the risk of leakage caused by the conduction between the two. In addition, the first conductive layer 310 is only provided on the first area A, and the second conductive layer 510 does not extend to the step surface of the step 110. In this way, there is a horizontal spacing between the first conductive layer 310 and the second conductive layer 510, forming a horizontal isolation, thereby avoiding the problem of leakage of the back contact solar cell caused by the conduction of the first conductive layer 310 and the second conductive layer 510.

[0079] The width of the third intersection region C3 is 0.01-10 μm, for example, 0.01 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. This configuration ensures a gap between the first carrier collection layer 200 and the side of the step 110, reducing the stacking area between the first carrier collection layer 200 and the second carrier collection layer 400, while not occupying the larger areas of the first region A and the second region B, thereby ensuring the carrier collection efficiency of the first carrier collection layer 200 and the second carrier collection layer 400.

[0080] It should be noted that the "width" involved in the present invention can be combined with Figure 1 It is understood that the size of a certain area along a direction parallel to the surface of the silicon substrate 100 .

[0081] Continue to see Figure 1 The intersection C also includes a fourth intersection C4 located between the third intersection C3 and the second region B. The fourth intersection C4 includes the side of the step surface. The second carrier collection layer 400 covers the side of the step surface. An isolation trench 800 is formed between the second conductive layer 510 and the second carrier collection layer 400 located on the side of the step surface. In this way, a horizontal spacing is provided between the second conductive layer 510 and the side of the step 110, thereby ensuring a larger isolation spacing between the first conductive layer 310 and the second conductive layer 510, and achieving a better isolation effect. Similarly, in this embodiment, there is no specific limitation on the horizontal spacing between the first conductive layer 310 and the second conductive layer 510, as long as the two can be separated in the horizontal direction.

[0082] The width of the fourth intersection region C4 is 30-90 μm, for example, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, or 90 μm. This configuration ensures a sufficient distance between the second carrier collection layer 400 and the side of the step 110 while not occupying the larger area of ​​the second region B, thereby ensuring the carrier collection efficiency of the second carrier collection layer 400.

[0083] Continue to see Figure 1 The intersection region C also includes a second intersection region C2 connected to the third intersection region C3 and extending toward the first region A. The second intersection region C2 is sequentially provided with a first carrier collection layer 200 and a second carrier collection layer 400 extending outward from the surface of the silicon substrate 100. In other words, the area of ​​the first conductive layer 310 is smaller than that of the first carrier collection layer 200, thereby avoiding the risk of electrical conduction between the large-area first conductive layer 310 and the second carrier collection layer 400.

[0084] The width of the second intersection region C2 is 30-90 μm, such as 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm or 90 μm, etc. This configuration does not occupy a large area of ​​the first region A, ensuring the carrier collection efficiency of the first carrier collection layer 200 .

[0085] Continue to see Figure 1 The intersection region C also includes a first intersection region C1 located between the first region A and the second intersection region C2. The first intersection region C1 includes a first carrier collection layer 200, a second carrier collection layer 400, and a first conductive layer 310 stacked in sequence from the surface of the silicon substrate 100 outward. This arrangement extends the first conductive layer 310 and overlaps the second carrier collection layer 400, appropriately increasing the area of ​​the first conductive layer 310. This facilitates carrier collection by the first conductive layer 310, reduces the contact resistance of the film layer in the first region A, and improves the conductive performance.

[0086] The width of the first intersection region C1 can be 50-150 μm, for example, 50 μm, 80 μm, 100 μm, 110 μm, 130 μm, or 150 μm. This configuration reduces the area between the first carrier collection layer 200 and the second carrier collection layer 400 compared to the prior art, and helps balance the areas of the first carrier collection layer 200 and the second carrier collection layer 400, thereby improving the carrier collection rate.

[0087] In some embodiments, when the second carrier collection layer 400 includes a stacked first intrinsic hydrogenated silicon-containing layer 410 and a second doped silicon layer 420, the first intrinsic hydrogenated silicon-containing layer 410 directly covers the surface of the silicon substrate 100 in the fourth intersection region C4 and the third intersection region C3. This has a better passivation effect than the tunneling passivation layer 210 of the first carrier collection layer 200 covering the silicon substrate 100, thereby enabling the back-contact solar cell to have better passivation performance, thereby improving the photoelectric conversion efficiency.

[0088] It should be noted that the first intrinsic hydrogenated silicon-containing layer 410 reduces carrier recombination through the dual effects of chemical passivation and field-effect passivation. Chemical passivation utilizes free hydrogen atoms to saturate dangling bonds on the silicon surface, while field passivation utilizes the interfacial electric field to achieve selective carrier transport. The tunneling passivation layer 210 reduces carrier transport resistance through the tunneling effect while suppressing recombination caused by surface states. Research has shown that the passivation effect of the first intrinsic hydrogenated silicon-containing layer 410 is superior to that of the tunneling passivation layer 210.

[0089] Continue to see Figure 1Because the first carrier collection layer 200 is not laid in the third intersection region C3, there is a gap between the first carrier collection layer 200 and the side of the step 110. This forms an enhanced passivation region A1 in the third intersection region C3. Simultaneously, the first intrinsic hydrogenated silicon-containing layer 410 and the second doped silicon layer 420 extend from the second region B to the first region A, with the extended portions completely covering the side of the step 110 and the enhanced passivation region A1, i.e., the third intersection region C3. In this manner, the side surfaces of the step 110 and the edges of the surface of the step 110 are covered and wrapped by the extended portions of the first intrinsic hydrogenated silicon-containing layer 410 and the second doped silicon layer 420, and since the passivation effect of the second carrier collection layer 400 composed of the first intrinsic hydrogenated silicon-containing layer 410 and the second doped silicon layer 420 is better than the passivation effect of the first carrier collection layer 200 composed of the tunneling passivation layer 210 and the first doped silicon layer 220, the second carrier collection layer 400 can be used to enhance the passivation effect of the boundary area, thereby improving the performance of the back-contact solar cell.

[0090] In the above-mentioned intersection areas, the second intersection area C2, the third intersection area C3, and the fourth intersection area C4 are not provided with the first conductive layer 310 and the second conductive layer 510, which is beneficial to the insulation isolation between the first area A and the second area B, and is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

[0091] On the other hand, an embodiment of the present invention further provides a photovoltaic module, which includes the back-contact solar cell according to any one of the above embodiments.

[0092] Specifically, a photovoltaic module may further include a cover sheet, a back sheet, and an adhesive film. Multiple back-contact solar cells are connected in series and / or in parallel to form a cell string, and one or more series or parallel cell strings are encapsulated between the cover sheet and the back sheet by an adhesive film.

[0093] The photovoltaic module provided by the present invention, based on a back-contact solar cell, only has the second carrier collection layer 400 disposed on the third intersection region C3, also known as the step surface. Compared to prior art methods in which the first and second carrier collection layers 200 and 400 are fully stacked in the intersection region, this reduces the stacking area of ​​the first and second carrier collection layers 200 and 400, thereby reducing the risk of electrical leakage caused by electrical conduction between the first and second carrier collection layers 200 and 400. Because the second conductive layer 510 does not extend onto the step surface, this increases the horizontal spacing between the first and second conductive layers 310 and 510, creating horizontal isolation and preventing electrical leakage caused by electrical conduction between the first and second conductive layers 310 and 510. Furthermore, the height difference between the first and second carrier collection layers 200 and 310 disposed in the first region A and the second and second carrier collection layers 400 and 510 disposed in the second region B, due to the step 110, creates vertical isolation between the two, preventing leakage. It can be seen that by reducing the stacking area between the first carrier collection layer 200 and the second carrier collection layer 400, and by horizontally isolating and vertically isolating the first conductive layer 310 and the second conductive layer 510, the back-contact solar cell provided by the embodiment of the present invention has an excellent anti-leakage effect, which is beneficial to improving the photoelectric conversion efficiency and further improving the photoelectric conversion efficiency and power of the photovoltaic module.

[0094] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A back contact solar cell, characterized in that: include: A silicon substrate (100), the back surface of which comprises a first region (A), a second region (B), and an intersection region (C) located between the first region (A) and the second region (B), the first region (A) being higher than the second region (B), and the intersection region (C) comprising a step (110); The first region (A) is provided with a first carrier collection layer (200) and a first conductive layer (310) stacked in sequence from the surface of the silicon substrate (100) outwards; The second region (B) is provided with a second carrier collection layer (400) and a second conductive layer (510) stacked sequentially from the surface of the silicon substrate (100) outward, the second conductive layer (510) does not extend to the step surface of the step (110), a horizontal distance exists between the second conductive layer (510) and the side surface of the step (110), and the first conductive layer (310) and the second conductive layer (510) are vertically isolated by a height difference; The intersection region (C) includes a third intersection region (C3) located on the step surface and extending to the edge of the step surface, the second carrier collection layer (400) extends from the second region (B) to the third intersection region (C3), and the second carrier collection layer (400) is provided on the surface of the third intersection region (C3), and the first carrier collection layer (200) is not provided in the third intersection region (C3); The intersection region (C) further includes a second intersection region (C2) connected to the third intersection region (C3) and extending toward the first region (A), and a first intersection region (C1) provided between the first region (A) and the second intersection region (C2), wherein both the second intersection region (C2) and the first intersection region (C1) are provided with the first carrier collection layer (200) and the second carrier collection layer (400) stacked in sequence from the surface of the silicon substrate (100) outwards. The width of the first intersection region (C1) is 50-150 μm, and the width of the second intersection region (C2) is 30-90 μm.

2. The back contact solar cell according to claim 1, wherein: The width of the third intersection region (C3) is 0.01-10 μm.

3. The back contact solar cell according to claim 1, wherein: The intersection region (C) further includes a fourth intersection region (C4) located between the third intersection region (C3) and the second region (B), the fourth intersection region (C4) includes a side surface of the step surface, the second carrier collection layer (400) covers the side surface of the step surface, and an isolation groove (800) is formed between the second conductive layer (510) and the second carrier collection layer (400) located on the side surface of the step surface.

4. The back contact solar cell according to claim 3, characterized in that The width of the fourth intersection region (C4) is 30-90 μm.

5. The back contact solar cell according to claim 1, wherein: The first conductive layer (310) is provided outside the second carrier collection layer (400) located in the first intersection region (C1).

6. The back contact solar cell according to claim 1, wherein: The second carrier collection layer (400) comprises a stacked first intrinsic hydrogenated silicon-containing layer (410) and a second doped silicon layer (420) in a direction away from the silicon substrate (100), and the second doped silicon layer (420) is connected to the second conductive layer (510); The first carrier collection layer (200) comprises a stacked tunneling passivation layer (210) and a first doped silicon layer (220) in a direction away from the silicon substrate (100), and the first doped silicon layer (220) is connected to the first conductive layer (310).

7. The back contact solar cell according to claim 6, characterized in that The thickness of the first intrinsic hydrogenated silicon-containing layer (410) is 1-10 nm; And / or, the material of the second doped silicon layer (420) includes at least one of amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide and silicon carbide; And / or, the second doped silicon layer (420) includes one layer or a stack of at least two of an amorphous silicon layer, a microcrystalline silicon layer, a nanocrystalline silicon layer, a silicon oxide layer, and a silicon carbide layer; And / or, the thickness of the second doped silicon layer (420) is 1-50 nm; And / or, the tunnel passivation layer (210) has a thickness of 0.5 nm to 3 nm; And / or, the thickness of the first doped silicon layer (220) is 20-100 nm; And / or, the materials of the first conductive layer (310) and the second conductive layer (510) include at least one of a metal oxide containing a doping element and a metal nitride containing a doping element, wherein the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, cadmium oxide and titanium nitride, the metal nitride includes titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, cadmium, zinc, cerium and fluorine; The first conductive layer (310) and the second conductive layer (510) are single-layer film layers or multi-layer stacked film layers; And / or, the silicon substrate (100) is an n-type silicon substrate, the first doped silicon layer is an n-type doped silicon layer, and the second doped silicon layer is a p-type doped silicon layer.

8. The back contact solar cell according to claim 1, wherein: There is a height difference between the first region (A) and the second region (B), and the height difference is less than or equal to 20 μm.

9. The back contact solar cell according to claim 1, wherein: The back-contact solar cell further comprises: a first electrode (320) electrically connected to the first conductive layer (310), and a second electrode (520) electrically connected to the second conductive layer (510); And / or, the back-contact solar cell further comprises: a passivation layer (600) and an anti-reflection layer (700) stacked sequentially from the front surface of the silicon substrate (100) outward.

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