Light emitting diode for improving over-etching and preparation method thereof

Abstract

The invention provides a light emitting diode for improving over-etching and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light emitting diode comprises an epitaxial layer and an insulation barrier layer, the insulation barrier layer is located on the surface of the epitaxial layer, the insulation barrier layer comprises at least two barrier layers which are stacked in sequence, each barrier layer comprises an etching barrier layer and an ion barrier layer, and the etching barrier layer is located on the surface of the epitaxial layer. The compactness of the etching barrier layer is lower than that of the ion barrier layer, and the thickness of the etching barrier layer is larger than that of the ion barrier layer. According to the embodiment of the invention, the problem of over-etching of the epitaxial layer can be improved, and etching gas can be prevented from penetrating through the insulating barrier layer to corrode the metal film layer.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technologies, and particularly to a light-emitting diode for improving over-etching and a preparation method thereof. Background Art

[0002] A light-emitting diode (abbreviation: LED) is a common product. An LED is usually formed by fabricating various film layers on a substrate, performing patterning, and then cutting.

[0003] In related technologies, during the preparation of a light-emitting diode, an epitaxial layer is usually epitaxially grown on a patterned substrate. The surface of the patterned substrate usually has nanoscale patterns (such as protrusions or grooves), and these patterns can effectively reduce the dislocation density of the epitaxial material grown on the patterned substrate to improve the preparation quality of the epitaxial layer.

[0004] However, after epitaxial growth, the epitaxial layer is peeled off from the patterned substrate by a laser lift-off method, and multiple spaced-apart holes are formed on the surface of the epitaxial layer in contact with the patterned substrate, resulting in an uneven surface of the epitaxial layer. Therefore, when etching grooves in the epitaxial layer, the etching rate in the area where the holes are located is faster than that in the area without holes, making the area where the holes are located prone to over-etching problems. In addition, some etching gases can pass through the exposed insulating layer in the over-etched area and corrode the metal film layer under the insulating layer, resulting in abnormalities in the light-emitting diode. Summary of the Invention

[0005] Embodiments of the present disclosure provide a light-emitting diode for improving over-etching and a preparation method thereof, which can improve the problem of over-etching of the epitaxial layer and avoid etching gases from penetrating the insulating layer to corrode the metal film layer. The technical solutions are as follows:

[0006] On the one hand, embodiments of the present disclosure provide a light-emitting diode, which includes an epitaxial layer and an insulating barrier layer. The insulating barrier layer is located on the surface of the epitaxial layer. The insulating barrier layer includes at least two stacked barrier layers, and each barrier layer includes an etching barrier layer and an ion barrier layer. The compactness of the etching barrier layer is lower than that of the ion barrier layer, and the thickness of the etching barrier layer is greater than that of the ion barrier layer.

[0007] In an implementation manner of the present disclosure, the barrier layer is a current blocking layer. The etching barrier layer of the current blocking layer is located on the surface of the epitaxial layer, and the etching barrier layer of the current blocking layer is located between the epitaxial layer and the ion barrier layer of the current blocking layer.

[0008] In one implementation of the present disclosure, the thickness of the etch stop layer of the current blocking layer is from 3000 angstroms to 6000 angstroms, and the thickness of the ion blocking layer of the current blocking layer is from 500 angstroms to 2000 angstroms.

[0009] In another implementation of the present disclosure, the blocking layer further includes an insulating layer. The etch stop layer of the insulating layer is located on the surface of the epitaxial layer and covers the current blocking layer. The etch stop layer of the insulating layer is located between the current blocking layer and the ion blocking layer of the insulating layer.

[0010] In another implementation of the present disclosure, the thickness of the etch stop layer of the insulating layer is from 6000 angstroms to 12000 angstroms, and the thickness of the ion blocking layer of the insulating layer is from 500 angstroms to 2000 angstroms.

[0011] In another implementation of the present disclosure, each of the etch stop layer and the ion blocking layer includes at least one of a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an aluminum nitride layer.

[0012] In another implementation of the present disclosure, the light-emitting diode further includes a metal blocking layer. The metal blocking layer is located within the insulating layer and between opposite two surfaces of the insulating layer.

[0013] In another implementation of the present disclosure, the surface of the epitaxial layer has isolation grooves. The isolation grooves are located at the peripheral edge of the epitaxial layer. The orthographic projection of the metal blocking layer on the surface of the epitaxial layer covers the isolation grooves.

[0014] In another implementation of the present disclosure, the thickness of the metal blocking layer is greater than or equal to 1000 angstroms.

[0015] On the other hand, embodiments of the present disclosure provide a method for manufacturing a light-emitting diode. The manufacturing method includes: preparing an epitaxial layer on a substrate; forming an insulating blocking layer on the surface of the epitaxial layer. The insulating blocking layer is located on the surface of the epitaxial layer. The insulating blocking layer includes at least two stacked blocking layers. Each blocking layer includes an etch stop layer and an ion blocking layer. The density of the etch stop layer is lower than that of the ion blocking layer, and the thickness of the etch stop layer is greater than that of the ion blocking layer.

[0016] The beneficial effects brought by the technical solutions provided by the embodiments of the present disclosure at least include:

[0017] The surface of the epitaxial layer of the light-emitting diode provided by the embodiment of the present disclosure is provided with an insulating barrier layer, and the insulating barrier layer includes at least two barrier layers stacked in sequence. Each barrier layer includes an etching barrier layer and an ion barrier layer. The density of the etching barrier layer is lower than that of the ion barrier layer, that is, the density of the ion barrier layer is higher, so that the pores inside the ion barrier layer are smaller. Since the structure of the ion barrier layer is denser and the pores inside the ion barrier layer are finer, even if the etching gas penetrates the etching barrier layer, it can effectively resist the penetration of the etching gas through the ion barrier layer under the barrier of the denser ion barrier layer, thus avoiding the corrosion of the metal film layer under the insulating barrier layer. At the same time, the thickness of the etching barrier layer is larger, that is, the etching barrier layer is used to resist etching to avoid over-etching and causing the insulating barrier layer to be etched through, and to improve the problem of over-etching. Brief Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 is a schematic structural diagram of a light-emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 is a schematic structural diagram of another light-emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 3 is a schematic structural diagram of another light-emitting diode provided by an embodiment of the present disclosure;

[0022] Figure 4 is a process flow chart for preparing a light-emitting diode provided by an embodiment of the present disclosure.

[0023] The descriptions of the marks in the drawings are as follows:

[0024] 20. Epitaxial layer; 201. Electrode groove; 202. Isolation groove;

[0025] 21. First semiconductor layer; 22. Multi-quantum well layer; 23. Second semiconductor layer;

[0026] 301. Etching barrier layer; 302. Ion barrier layer;

[0027] 31. Current blocking layer;

[0028] 32. Insulating layer;

[0029] 33. Metal blocking layer;

[0030] 41. Transparent conductive layer; 42. Metal reflective layer; 43. Metal protection layer;

[0031] 51. Bonding metal layer; 52. Conductive substrate. Detailed implementation manners

[0032] To make the objectives, technical solutions and advantages of the present disclosure clearer, the following will further describe the implementation manners of the present disclosure in detail with reference to the accompanying drawings.

[0033] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", "third" and similar terms used in the specification and claims of the present patent application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "one" do not denote a quantity limitation, but mean that there is at least one. The terms "comprising" or "including" and similar terms mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.

[0034] An embodiment of the present disclosure provides a light-emitting diode. The light-emitting diode includes an epitaxial layer and an insulating barrier layer. The insulating barrier layer is located on the surface of the epitaxial layer. The insulating barrier layer includes at least two barrier layers stacked in sequence, and each barrier layer includes an etching barrier layer and an ion barrier layer.

[0035] For example, the etching barrier layer and the ion barrier layer in each barrier layer may be alternately stacked.

[0036] For another example, the etching barrier layer in each barrier layer may be located on one side of the barrier layer, and the ion barrier layer is located on the other side of the barrier layer. That is, the etching barrier layers in the barrier layers are stacked together, and the ion barrier layers in the barrier layers are also stacked together.

[0037] Among them, the density of the etching barrier layer is lower than that of the ion barrier layer, and the thickness of the etching barrier layer is greater than that of the ion barrier layer.

[0038] The surface of the epitaxial layer of the light-emitting diode provided by the embodiment of the present disclosure is provided with an insulating barrier layer, and the insulating barrier layer includes at least two barrier layers stacked in sequence. Each barrier layer includes an etching barrier layer and an ion barrier layer. The compactness of the etching barrier layer is lower than that of the ion barrier layer, that is, the ion barrier layer has higher compactness, so that the pores inside the ion barrier layer are smaller. Since the structure of the ion barrier layer is denser and the pores inside the ion barrier layer are finer, even if the etching gas penetrates the etching barrier layer, it can effectively resist the penetration of the etching gas through the ion barrier layer under the barrier of the denser ion barrier layer, thus avoiding the corrosion of the metal film layer under the insulating barrier layer. At the same time, the etching barrier layer has a larger thickness, that is, the etching barrier layer is used to resist etching to avoid over-etching and causing the insulating barrier layer to be etched through, and to improve the problem of over-etching.

[0039] In one implementation manner of the present disclosure, Figure 1 is a schematic structural diagram of a light-emitting diode provided by the embodiment of the present disclosure. As Figure 1 shown, the light-emitting diode includes an epitaxial layer 20 and a current blocking layer 31. The etching barrier layer of the current blocking layer 31 is located on the surface of the epitaxial layer 20, and the etching barrier layer of the current blocking layer 31 is located between the epitaxial layer 20 and the ion barrier layer of the current blocking layer 31.

[0040] The surface of the epitaxial layer 20 of the light-emitting diode provided by the embodiment of the present disclosure is provided with a current blocking layer 31, and the current blocking layer 31 includes an etching barrier layer 301 and an ion barrier layer 302 stacked in sequence. Among them, the compactness of the etching barrier layer 301 is lower than that of the ion barrier layer 302, that is, the ion barrier layer 302 has higher compactness, so that the pores inside the ion barrier layer 302 are smaller. Since the structure of the ion barrier layer 302 is denser and the pores inside the ion barrier layer 302 are finer, even if the etching gas penetrates the etching barrier layer 301, it can effectively resist the penetration of the etching gas through the ion barrier layer 302 under the barrier of the denser ion barrier layer 302, thus avoiding the corrosion of the metal film layer under the current blocking layer 31. At the same time, the etching barrier layer 301 above the ion barrier layer 302 has a larger thickness, that is, the etching barrier layer 301 is used to resist etching to avoid over-etching and causing the current blocking layer 31 to be etched through, and to improve the problem of over-etching.

[0041] Exemplarily, the thickness of the etching barrier layer 301 is 3000 Å to 6000 Å. For example, the thickness of the etching barrier layer 301 is 5000 Å. In this way, the relatively thick etching barrier layer 301 can be used to resist etching to avoid over-etching and causing the current blocking layer 31 to be etched through, and to improve the problem of over-etching.

[0042] Exemplarily, the thickness of the ion blocking layer 302 is from 500 angstroms to 2000 angstroms. For example, the thickness of the ion blocking layer 302 is 1000 angstroms. In this way, the denser ion blocking layer 302 is utilized to resist the penetration of the etching gas, thereby avoiding the corrosion of the metal film layer below the current blocking layer 31. At the same time, setting the thickness of the ion blocking layer 302 within the above range can avoid the excessive thickness of the ion blocking layer 302. Since the ion blocking layer 302 has higher density, the preparation difficulty of the ion blocking layer 302 is also greater. Therefore, making the thickness of the ion blocking layer 302 smaller can effectively reduce the preparation difficulty of the current blocking layer 31.

[0043] Optionally, as Figure 1 shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 that are stacked in sequence.

[0044] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0045] Exemplarily, the first semiconductor layer 21 is a p-type layer, and the second semiconductor layer 23 is an n-type layer.

[0046] Optionally, the n-type layer is an n-type GaN layer doped with silicon. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0047] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Among them, the multi-quantum well layer 22 can include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0048] As an example, in the embodiments of the present disclosure, the multi-quantum well layer 22 includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0049] Optionally, the thickness of the multi-quantum well layer 22 can be from 150 nm to 200 nm.

[0050] Optionally, the p-type layer is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0051] Optionally, as Figure 1 shown, the light-emitting diode further includes: a transparent conductive layer 41, a metal reflective layer 42, and a metal protective layer 43.

[0052] As Figure 1As shown, the transparent conductive layer 41 is located on the surface of the first semiconductor layer 21. The current blocking layer 31 further covers the transparent conductive layer 41. The current blocking layer 31 has a through hole exposing the transparent conductive layer 41. The metal reflective layer 42 is located on the surface of the current blocking layer 31 and is connected to the transparent conductive layer 41 through the through hole. The metal protective layer 43 is located on the surface of the insulating layer 32, and the metal protective layer 43 covers the metal reflective layer 42.

[0053] Exemplarily, the transparent conductive layer 41 can be an Indium Tin Oxide (ITO) layer. The ITO layer has good transmittance and low resistivity.

[0054] Exemplarily, the transparent conductive layer 41 can be an Indium Zinc Oxide (IZO) layer. The IZO layer has good transmittance and low resistivity.

[0055] Among them, using the ITO layer or the IZO layer as the transparent conductive layer 41 can allow more light to transmit through the transparent conductive layer 41, thus ensuring the light output effect. At the same time, due to the low resistivity, the metal reflective layer 42 is stacked on the transparent conductive layer 41, so that carriers can be more efficiently conducted from the metal reflective layer 42 to the epitaxial layer 20, improving the injection efficiency.

[0056] Exemplarily, the thickness of the transparent conductive layer 41 can be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 41 is 1500 angstroms.

[0057] In the embodiments of the present disclosure, by providing the metal reflective layer 42, it can be used to reflect the light emitted from the epitaxial layer 20, allowing more light to be emitted from the light output surface of the epitaxial layer 20, and enhancing the light emission intensity of the light-emitting diode.

[0058] At the same time, a layer of metal protective layer 43 is also covered on the reflective layer, which can prevent the metal in the metal reflective layer 42 from migrating upward.

[0059] Optionally, the metal reflective layer 42 includes a stacked Ag layer in sequence.

[0060] Since Ag has a good reflection effect, setting an Ag layer in the metal reflective layer 42 can enhance the reflection of light by the metal reflective layer 42 and improve the light emission brightness of the light output surface of the light-emitting diode.

[0061] Optionally, the metal protective layer 43 includes a Ni layer or a TiW layer.

[0062] Among them, the Ni layer has good corrosion resistance and wear resistance. The TiW layer can be successfully deposited on other thin films as an adhesion layer without peeling or cracking. The alternately stacked Ni layer and TiW layer can be used as a barrier layer to protect the silver mirror.

[0063] Exemplarily, the thickness of the Ag layer is from 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0064] Exemplarily, the thickness of the Ni layer is from 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0065] Exemplarily, the thickness of the TiW layer is from 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0066] In another implementation of the present disclosure, Figure 2 is a schematic structural diagram of another light-emitting diode provided by an embodiment of the present disclosure. As Figure 2 shown, the light-emitting diode further includes an insulating layer 32. The etching stop layer of the insulating layer 32 is located on the surface of the epitaxial layer 20, and the insulating layer 32 covers the current blocking layer 31. The etching stop layer of the insulating layer 32 is located between the current blocking layer 31 and the ion blocking layer of the insulating layer 32.

[0067] In the embodiment of the present disclosure, the density of the etching stop layer 301 is lower than that of the ion blocking layer 302, that is, the density of the ion blocking layer 302 is higher, so that the pores inside the ion blocking layer 302 are smaller. Since the structure of the ion blocking layer 302 is tighter and the holes inside the ion blocking layer 302 are finer, even if the etching gas penetrates the etching stop layer 301, under the blocking of the denser ion blocking layer 302, the etching gas can be effectively resisted from penetrating the ion blocking layer 302, thereby avoiding the corrosion of the metal film layer below the current blocking layer 31. At the same time, the thickness of the etching stop layer 301 above the ion blocking layer 302 is larger, that is, the etching stop layer 301 is used to resist etching, avoiding over-etching and causing the current blocking layer 31 to be etched through, and improving the problem of over-etching.

[0068] Optionally, as Figure 2 shown, the light-emitting diode further includes an electrode groove 201 and a bonding metal layer 51. The electrode groove 201 is located on the surface of the current blocking layer 31 and exposes the second semiconductor layer 23. The bonding metal layer 51 is located on the side where the first semiconductor layer 21 is located and is connected to the second semiconductor layer 23 through the electrode groove 201.

[0069] Exemplarily, the bonding metal layer 51 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0070] Among them, the thickness of the first Al layer is from 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is from 100 angstroms to 500 angstroms, the thickness of the second Al layer is from 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is from 500 angstroms to 1500 angstroms, and the thickness of the Au layer is from 2000 angstroms to 5000 angstroms.

[0071] For example, the thickness of the first Al layer is 10,000 Å, the thickness of the first Ti layer is 200 Å, the thickness of the second Al layer is 10,000 Å, the thickness of the second Ti layer is 1,000 Å, and the thickness of the Au layer is 3,000 Å.

[0072] Optionally, as Figure 2 shown, a conductive substrate 52 is provided on the surface of the bonding metal layer 51 away from the epitaxial layer 20.

[0073] Exemplarily, the conductive substrate 52 can be a silicon substrate.

[0074] Optionally, the thickness of the etching barrier layer 301 is 6,000 Å to 12,000 Å. Exemplarily, the thickness of the etching barrier layer 301 is 10,000 Å. In this way, the relatively thick etching barrier layer 301 can be used for anti-etching to avoid over-etching and causing the insulating layer 32 to be etched through, thus improving the problem of over-etching.

[0075] Optionally, the thickness of the ion barrier layer 302 is 500 Å to 2,000 Å. Exemplarily, the thickness of the ion barrier layer 302 is 1,000 Å. In this way, the denser ion barrier layer 302 can resist the penetration of the etching gas, thereby avoiding the corrosion of the bonding metal layer 51 under the insulating layer 32. At the same time, setting the thickness of the ion barrier layer 302 within the above range can avoid the excessive thickness of the ion barrier layer 302. Since the ion barrier layer 302 has higher density, the preparation difficulty of the ion barrier layer 302 is also greater. Therefore, making the thickness of the ion barrier layer 302 smaller can effectively reduce the preparation difficulty of the insulating layer 32.

[0076] Optionally, both the etching barrier layer 301 and the ion barrier layer 302 include at least one of a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an aluminum nitride layer.

[0077] Exemplarily, both the etching barrier layer 301 and the ion barrier layer 302 in the current blocking layer 31 can be silicon oxide layers. The silicon oxide layer has a relatively high density and a low porosity, which can effectively block the etching gas and avoid the corrosion of the metal film layer.

[0078] Exemplarily, both the etching barrier layer 301 and the ion barrier layer 302 in the insulating layer 32 can be aluminum oxide layers. The aluminum oxide layer has high insulation and can effectively block current conduction, avoiding the problem of short circuit in the light-emitting diode.

[0079] Figure 3 is a schematic structural diagram of another light-emitting diode provided by an embodiment of the present disclosure. As Figure 3As shown, the light emitting diode further includes a metal barrier layer 33 . The metal barrier layer 33 is located inside the insulating layer 32 , and the metal barrier layer 33 is located between two opposite surfaces of the insulating layer 32 .

[0080] For example, Figure 3 As shown, the metal barrier layer 33 is located on the surface of the insulating layer 32 away from the epitaxial layer 20. By providing the metal barrier layer 33 on the surface of the insulating layer 32, it is possible to effectively prevent the etching ions from penetrating the insulating layer 32 and prevent the etching ions from corroding the bonding metal layer 51.

[0081] Optionally, the thickness of the metal barrier layer 33 is greater than or equal to 1000 angstroms. Exemplarily, the thickness of the metal barrier layer 33 is 1500 angstroms. In this way, the thickness of the metal barrier layer 33 is large enough to prevent the etching ions from penetrating the insulating layer 32 as much as possible.

[0082] Optionally, the metal barrier layer 33 includes at least one of a Cr layer and a Pt layer. Exemplarily, the metal barrier layer 33 includes a Cr layer and a Pt layer stacked in sequence.

[0083] The thickness of the Cr layer is 500 angstroms, and the thickness of the Pt layer is 1000 angstroms.

[0084] In the above implementation, the Cr layer is in contact with the bonding metal layer 51. The Cr layer has good adhesion, which allows the metal barrier layer 33 to be tightly bonded to the bonding metal to prevent the metal barrier layer 33 from easily falling off. The Pt layer can block the diffusion path of metal ions and effectively prevent the etching ions from penetrating, thereby preventing the bonding metal layer 51 from being corroded.

[0085] Alternatively, if Figure 3 As shown, the surface of the epitaxial layer 20 has an isolation groove 202 , and the isolation groove 202 is located at the peripheral edge of the epitaxial layer 20 ; the orthographic projection of the metal barrier layer 33 on the surface of the epitaxial layer 20 covers the isolation groove 202 .

[0086] Since the thickness of the epitaxial layer 20 where the isolation groove 202 is located is relatively thin, the film layer in this area is more easily etched through. Therefore, the metal barrier layer 33 is arranged opposite to the isolation groove 202 to enhance the ability of the isolation groove 202 to resist the erosion of the etching gas.

[0087] It should be noted that in the embodiments of the present disclosure, the insulating barrier layer may include at least one of a current blocking layer and an insulating layer. That is, the insulating barrier layer may include only a current blocking layer, or only an insulating layer, or both a current blocking layer and an insulating layer. The insulating barrier layer may be selected based on actual conditions, and the embodiments of the present disclosure do not limit this.

[0088] Figure 4 FIG. 1 is a flow chart of manufacturing a light emitting diode according to an embodiment of the present disclosure.Figure 4 As shown, the preparation method includes:

[0089] Step S11: Prepare an epitaxial layer on a substrate.

[0090] Exemplarily, the substrate can be a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. And the sapphire material is relatively hard and has relatively stable chemical properties, enabling the LED to have good light-emitting effects and stability.

[0091] The process of preparing the epitaxial layer can include the following steps:

[0092] First, the epitaxial layer grown on the sapphire substrate includes a second semiconductor layer, a multi-quantum well layer, and a first semiconductor layer stacked in sequence.

[0093] Among them, the sapphire substrate can be pretreated by placing the sapphire substrate in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. As an example, in the embodiments of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0094] Specifically, the baking temperature can be 1000°C to 1200°C, and the pressure in the MOCVD reaction chamber during baking can be 100 mbar to 200 mbar.

[0095] Exemplarily, the first semiconductor layer can be a p-type layer, and the second semiconductor layer can be an n-type layer.

[0096] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be 0.5 μm to 3 μm.

[0097] The growth temperature of the n-type GaN layer can be 1000°C to 1100°C, and the growth pressure of the n-type GaN layer can be 100 torr to 300 torr.

[0098] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Among them, the multi-quantum well layer can include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0099] When growing the multi-quantum well layer, the pressure in the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the reaction chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the reaction chamber temperature is 860°C to 890°C.

[0100] As an example, in the embodiments of the present disclosure, the multi-quantum well layer includes 5 cycles of InGaN quantum well layers and GaN quantum barrier layers stacked alternately.

[0101] Optionally, the thickness of the multi-quantum well layer can be 150 nm to 200 nm.

[0102] Optionally, the p-type layer is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer can be 0.5 μm to 3 μm.

[0103] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer can be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer can be 800 °C to 1000 °C.

[0104] Then, etch the epitaxial layer to form an electrode groove and an isolation groove exposing the second semiconductor layer on the surface of the first semiconductor layer.

[0105] Among them, the isolation groove is located at the peripheral edge of the epitaxial layer, and the isolation groove surrounds the electrode groove.

[0106] After step S11, it may further include: forming a transparent conductive layer on the surface of the first semiconductor layer.

[0107] Among them, the transparent conductive layer is located outside the electrode groove.

[0108] Exemplarily, the transparent conductive layer is an indium tin oxide layer or an indium zinc oxide layer.

[0109] Exemplarily, the thickness of the transparent conductive layer is 100 Å to 300 Å. For example, the thickness of the transparent conductive layer is 200 Å.

[0110] Step S12: Form an insulating barrier layer on the surface of the epitaxial layer.

[0111] Optionally, the insulating barrier layer is located on the surface of the epitaxial layer. The insulating barrier layer includes at least two barrier layers stacked in sequence, and each barrier layer includes an etching barrier layer and an ion barrier layer.

[0112] Among them, the density of the etching barrier layer is lower than that of the ion barrier layer, and the thickness of the etching barrier layer is greater than that of the ion barrier layer.

[0113] Exemplarily, the barrier layer is a current blocking layer. The current blocking layer includes an etching barrier layer and an ion barrier layer stacked in sequence on the surface of the epitaxial layer. The density of the etching barrier layer is lower than that of the ion barrier layer, and the thickness of the etching barrier layer is greater than that of the ion barrier layer

[0114] Exemplarily, as Figures 1 to 3 shown, the current blocking layer covers the transparent conductive layer, and the current blocking layer has a through hole exposing the transparent conductive layer.

[0115] Exemplarily, both the etch stop layer and the ion barrier layer include at least one of a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an aluminum nitride layer.

[0116] For example, both the etch stop layer and the ion barrier layer can be a silicon oxide layer.

[0117] Optionally, the etch stop layer can be prepared by Chemical Vapor Deposition (CVD), so that the etch stop layer can be grown rapidly. Since the thickness of the etch stop layer is thicker than that of the ion barrier layer, the etch stop layer can be prepared more rapidly by chemical vapor deposition.

[0118] Exemplarily, the growth rate of the etch stop layer is 4 Å / s.

[0119] Optionally, the ion barrier layer can be prepared by Atomic Layer Deposition (ALD), so that the ion barrier layer can be grown slowly to obtain an ion barrier layer with higher density.

[0120] Exemplarily, the growth rate of the ion barrier layer is 2 Å / s.

[0121] After step S12, the following steps can further be included:

[0122] First step, form a metal reflective layer on the surface of the current blocking layer, and connect the metal reflective layer to the transparent conductive layer through a via hole.

[0123] Second step, form a metal protection layer on the surface of the current blocking layer, and cover the metal reflective layer with the metal protection layer.

[0124] Third step, form an insulating layer on the current blocking layer, in the electrode groove, and in the isolation groove.

[0125] Optionally, the barrier layer further includes an insulating layer, and the insulating layer includes an etch stop layer and an ion barrier layer that are sequentially stacked on the surface of the epitaxial layer.

[0126] Among them, the density of the etch stop layer is lower than that of the ion barrier layer, and the thickness of the etch stop layer is greater than that of the ion barrier layer.

[0127] The specific process of preparing the insulating layer can include: first, rapidly grow the etch stop layer by CVD process, and then slowly grow the ion barrier layer by ALD process.

[0128] Exemplarily, both the etch stop layer and the ion barrier layer can be a silicon oxide layer.

[0129] Optionally, the thickness of the etching stop layer is from 6000 angstroms to 12000 angstroms. Exemplarily, the thickness of the etching stop layer is 10000 angstroms.

[0130] Optionally, the thickness of the ion barrier layer is from 500 angstroms to 2000 angstroms. Exemplarily, the thickness of the ion barrier layer is 10000 angstroms.

[0131] In the fourth step, the insulating layer is etched to form a through hole exposing the bottom of the electrode groove, and a bonding metal layer is formed in the through hole so that the bonding metal layer is electrically connected to the second semiconductor layer.

[0132] Exemplarily, the bonding metal layer can be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0133] Wherein, the thickness of the first Al layer is from 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is from 100 angstroms to 500 angstroms, the thickness of the second Al layer is from 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is from 500 angstroms to 1500 angstroms, and the thickness of the Au layer is from 2000 angstroms to 5000 angstroms.

[0134] For example, the thickness of the first Al layer is 10000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10000 angstroms, the thickness of the second Ti layer is 1000 angstroms, and the thickness of the Au layer is 3000 angstroms.

[0135] In the fifth step, the side of the light-emitting diode having the insulating layer is bonded to the conductive substrate, and the substrate is removed.

[0136] Specifically, it may include: forming a bonding metal layer on the conductive substrate, bonding the bonding metal layer of the conductive substrate with the bonding metal layer on the epitaxial layer, and removing the sapphire substrate by laser lift-off to expose the second semiconductor layer.

[0137] Exemplarily, the conductive substrate can be a silicon substrate.

[0138] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes an epitaxial layer (20) and an insulating barrier layer. The insulating barrier layer is located on the surface of the epitaxial layer (20). The insulating barrier layer includes at least two stacked barrier layers. Each barrier layer includes an etching barrier layer and an ion barrier layer. The density of the etching barrier layer is lower than that of the ion barrier layer, and the thickness of the etching barrier layer is greater than that of the ion barrier layer.

2. The light-emitting diode according to claim 1, wherein The barrier layer is a current blocking layer (31). The etching barrier layer of the current blocking layer (31) is located on the surface of the epitaxial layer (20), and the etching barrier layer of the current blocking layer (31) is located between the epitaxial layer (20) and the ion barrier layer of the current blocking layer (31).

3. The light-emitting diode according to claim 2, wherein The thickness of the etching barrier layer of the current blocking layer (31) is 3000 Å to 6000 Å, and the thickness of the ion barrier layer of the current blocking layer (31) is 500 Å to 2000 Å.

4. The light-emitting diode according to claim 2 or 3, characterized in that, The barrier layer further includes an insulating layer (32). The etching barrier layer of the insulating layer (32) is located on the surface of the epitaxial layer (20) and covers the current blocking layer (31). The etching barrier layer of the insulating layer (32) is located between the current blocking layer (31) and the ion barrier layer of the insulating layer (32).

5. The light-emitting diode according to claim 4, wherein The thickness of the etching barrier layer of the insulating layer (32) is 6000 Å to 12000 Å, and the thickness of the ion barrier layer of the insulating layer (32) is 500 Å to 2000 Å.

6. The light-emitting diode according to claim 4, wherein Both the etching barrier layer and the ion barrier layer include at least one of a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an aluminum nitride layer.

7. The light-emitting diode according to claim 4, wherein, The light-emitting diode further includes a metal blocking layer (33). The metal blocking layer (33) is located within the insulating layer (32) and between two opposite surfaces of the insulating layer (32).

8. The light-emitting diode according to claim 7, wherein, The surface of the epitaxial layer (20) has isolation grooves (202). The isolation grooves (202) are located at the peripheral edge of the epitaxial layer (20). The orthographic projection of the metal blocking layer (33) on the surface of the epitaxial layer (20) covers the isolation grooves (202).

9. The light-emitting diode according to claim 8, wherein, The thickness of the metal blocking layer (33) is greater than or equal to 1000 Å.

10. A method for preparing a light-emitting diode, characterized in that, The preparation method includes: Preparing an epitaxial layer on a substrate; Forming an insulating barrier layer on the surface of the epitaxial layer. The insulating barrier layer is located on the surface of the epitaxial layer. The insulating barrier layer includes at least two stacked barrier layers. Each barrier layer includes an etching barrier layer and an ion barrier layer. The density of the etching barrier layer is lower than that of the ion barrier layer, and the thickness of the etching barrier layer is greater than that of the ion barrier layer.

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