Regulator-follower dynamic voltage and frequency scaling scheme for integrated circuit components

Abstract

Various dynamic voltage and frequency scaling (DVFS) techniques may optimize high voltage dwell of a device that includes multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce high voltage dwell (duration) of a voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to pending U.S. Non - Provisional Application No. 18 / 082,518, filed on December 15, 2022, which is assigned to the assignee of this application and is hereby incorporated by reference in its entirety as if set forth in full herein and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure generally relate to clocking frequencies for integrated circuit components and, more particularly, to dynamic voltage and frequency scaling (DVFS) techniques suitable for use with integrated circuits. Background Art

[0004] Some integrated circuits such as system - on - a - chip (SoC) may include multiple processors or cores integrated on the same chip. For example, an SoC may include two or more of the following: a central processing unit (CPU), a display processor, a video encoder / decoder, an audio processor, a graphics processing unit (GPU), etc. Generally, an SoC includes resources shared among multiple processors or cores. For example, the shared resources may include a shared memory interface configured to interface the processors with an external memory (e.g., dynamic random access memory (DRAM)). The shared resources may also include shared power rails, a shared system bus, etc.

[0005] The performance of an SoC can be increased by increasing the clocking frequency applied to the SoC. The increased clocking frequency may require a corresponding increase in the operating voltage to ensure that the SoC operates correctly. For some integrated circuit (IC) components, different

[0006] clock frequencies are mapped to different voltage inflection points such that the voltage changes with the clocking frequency. The increased speed and voltage increase the heat generated by the circuit and the temperature of the SoC.

[0007] An SoC typically operates at far below the maximum steady - state clocking frequency and voltage in order to reduce power consumption and heat generation. Dynamic voltage and frequency scaling (DVFS) is a technique that can be used to adjust the frequency and voltage applied to an SoC to deliver the required performance at an optimal power level. An SoC enabled with DVFS can dynamically scale the clock frequency and / or the power voltage of a corresponding one of the processors / cores in the processor / core. Summary of the Invention

[0008] The following presents a generalization of one or more specific implementations to provide a basic understanding of such specific implementations. This generalization is not an exhaustive overview of all expected specific implementations, and is not intended to identify key or important elements of all specific implementations, nor to delineate the scope of any or all specific implementations. Its sole purpose is to present some concepts of one or more specific implementations in a simplified form as a prelude to the more detailed description that follows.

[0009] In one example, a device for dynamic voltage and frequency scaling is provided. The device includes a plurality of processing cores and a dynamic voltage and frequency scaling (DVFS) resource manager coupled to the plurality of processing cores. The DVFS resource manager is configured to: adjust a first clocked frequency of a first processing core of the device based on a request from the first processing core; adjust a second clocked frequency based on a first mapping rule between the first clocked frequency and a second clocked frequency of a second processing core of the device that shares a voltage rail with the first processing core; and adjust the voltage of the voltage rail such that the first processing core can operate at the first clocked frequency and the second processing core can operate at the second clocked frequency.

[0010] Another example provides a method for dynamic voltage and frequency scaling (DVFS) at a device. The method includes: adjusting a first clocked frequency of a first processing core of the device based on a request from the first processing core; adjusting a second clocked frequency based on a first mapping rule between the first clocked frequency and a second clocked frequency of a second processing core of the device that shares a voltage rail with the first processing core; and adjusting the voltage of the voltage rail such that the first processing core can operate at the first clocked frequency and the second processing core can operate at the second clocked frequency.

[0011] Another example provides a device for dynamic voltage and frequency scaling. The device includes: means for adjusting a first clocked frequency of a first processing core of the device based on a request from the first processing core; means for adjusting a second clocked frequency based on a first mapping rule between the first clocked frequency and a second clocked frequency of a second processing core of the device that shares a voltage rail with the first processing core; and means for adjusting the voltage of the voltage rail such that the first processing core can operate at the first clocked frequency and the second processing core can operate at the second clocked frequency.

[0012] To achieve the foregoing and related purposes, one or more specific implementations include the features described in detail below and particularly pointed out in the claims. The following description and the accompanying drawings elaborate certain illustrative aspects of one or more specific implementations. However, these aspects are merely indicative of several of the various ways in which the principles of the respective specific implementations may be employed, and the described specific implementations are intended to cover all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A block diagram of a system-on-chip (SoC) illustrating some aspects of the present disclosure.

[0014] Figure 2 A block diagram of a processor with dynamic voltage and frequency scaling (DVFS) illustrating some aspects of the present disclosure.

[0015] Figure 3 An exemplary DVFS frequency and voltage pattern illustrating some aspects of the present disclosure.

[0016] Figure 4 Another exemplary DVFS frequency and voltage pattern illustrating some aspects of the present disclosure.

[0017] Figure 5 A flowchart of a governor-follower DVFS process illustrating some aspects of the present disclosure.

[0018] Figure 6 A mapping table for implementing a governor-follower DVFS scheme illustrating some aspects of the present disclosure.

[0019] Figure 7 Yet another exemplary DVFS frequency and voltage pattern illustrating some aspects of the present disclosure.

[0020] Figure 8 A flowchart of another governor-follower DVFS process illustrating some aspects of the present disclosure.

[0021] Figure 9 A flowchart of a governor-follower DVFS process for controlling a voltage rail illustrating some aspects of the present disclosure.

[0022] Figure 10 A block diagram of an example of a hardware implementation for a device illustrating some aspects of the present disclosure.

[0023] Figure 11 A flowchart of a DVFS method illustrating some aspects of the present disclosure. DETAILED DESCRIPTION

[0024] The following detailed description, presented in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. For a thorough understanding of the various concepts, the detailed description includes specific details. It will be apparent, however, to one of ordinary skill in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0025] Aspects disclosed herein provide various dynamic voltage and frequency scaling (DVFS) techniques to optimize high-voltage dwell for a device that includes multiple processing cores sharing a voltage rail (supply voltage). Each processing core is a separate processing unit within a processor of the device. The device may include one or more processors. The DVFS techniques described herein may reduce the high-voltage dwell (duration) of the voltage rail by aligning the high-frequency durations of multiple cores sharing the same voltage rail. In some aspects, the disclosed DVFS techniques use a governor-follower mechanism that allows processing cores to register as governor cores, follower cores, or non-participating (neutral) cores. A governor core may influence the frequency or voting of follower cores sharing the same voltage rail. A governor core may have one or more follower cores, and a follower core may follow one or more governor cores.

[0026] In some aspects, when a governor core votes in favor of a higher clocking frequency, a follower core may follow the governor core to operate at the higher clocking frequency. In some examples, a follower core may be restricted to following a governor core, but subject to certain limitations (e.g., frequency limitations, bandwidth constraints, and / or power or current limitations). The disclosed governor-follower DVFS mechanism may improve the alignment of high-frequency dwell between cores to minimize high-voltage dwell on the shared voltage rail. High-frequency dwell refers to the time that a core operates at a clocking frequency higher than its default or nominal clocking frequency. High-voltage dwell refers to the time that a core operates at a rail voltage higher than its default or nominal rail voltage. In some examples, the governor-follower mechanism may be restricted to specific frequency and voltage inflection levels to limit rail peak current and also avoid data bandwidth shortages for one or more processing cores (e.g., real-time cores). In some aspects, the disclosed DVFS techniques may be used for a single IC, a packaged processor, or clocking components of a system-on-chip (SoC), including a central processing unit (CPU) and one or more cores of the CPU.

[0027] While aspects and examples are described herein by way of illustration of some examples, those skilled in the art will appreciate that additional implementations and use cases can be generated in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects or uses can be generated via integrated circuit chip examples and other non-module component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / shopping devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically target use cases or applications, a wide variety of applicability of the described innovations can occur. The scope of implementations can range from chip-level or modular components to non-modular non-chip-level implementations and further to aggregative, distributed, or OEM (original equipment manufacturer) devices or systems incorporating one or more aspects of the described innovations. In some practical environments, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, temperature and power sensors can use multiple components for analog and digital purposes (e.g., hardware components including power supplies, transducers, detectors, accumulators, digital-to-analog converters, etc.). It is intended that the innovations described herein can be practiced in a wide variety of devices, chip-level components, systems, distributed arrangements, end-user devices, etc. having various sizes, shapes, and configurations.

[0028] Figure 1 is a block diagram of a system-on-chip (SoC) suitable for use with a portable device or a computer. The SoC 102 has a multi-core processor such as a CPU 104, a multi-core graphics processor such as a graphics processing unit (GPU) 106, a multi-core digital signal processor such as a DSP (digital signal processor) 108, and a security module 110 that provides secret keys, device security, encryption, and decryption. Each of the CPU 104, GPU 106, and DSP 108 may include one or more processing cores. Each processing core is a separate processing unit within the processor of the SoC. In some aspects, the cores can be controlled to use the same or different clock frequencies. The SoC 102 may also include a user interface 112 coupled to external components such as a touch screen, a keyboard, buttons, etc. Figure 1 The illustrated SoC may also include a mass storage device 114, an inertial reference unit 116, a camera 118, a display driver 120, and a position sensor 122 such as a satellite positioning system. Additionally, the SoC may include a wireless interface 124 that is coupled to analog radio frequency components and an antenna (not shown) to support wireless data and control interfaces.

[0029] Each component in the assembly can be coupled via a bus (not shown) or via the CPU 104, and more or fewer components can be used to accommodate a particular application. As an alternative to the SoC 102, as shown, any one or more components can be fabricated on separate chips and packaged together or separately.

[0030] The SoC 102 is coupled to a power source 130 (such as a battery or power converter) via a power manager 132 that can be located on the SoC or on discrete components. The power manager 132 regulates the power of the components of the SoC 102. The power manager 132 can control the clocking frequency and voltage applied to the components of the SoC 102. The power manager 132 can also control the voltage applied to the SoC and is also capable of measuring the battery charge level of the power source.

[0031] The cores of the CPU 104, GPU 106, and other components such as the mass storage device 114 and wireless interface 124 etc. can include or be equipped with thermal sensors and power sensors in the form of voltage sensors, current sensors, or both. The sensors provide sensor data to the power manager 132, which can be used by the power manager 132 to regulate the frequency and / or voltage provided to the components. For example, the power manager 132 can include clocking circuitry and voltage regulators and other components, as described in more detail below. In some examples, the CPU 104, GPU 106, and other clocked components can also include power manager circuitry or software for determining appropriate clocking frequencies and voltages. The determined clocking frequencies and voltages can be communicated to the power manager 132 for application, or the clocked components can adjust the clocking frequencies and voltages independently of the power manager 132.

[0032] Figure 2 A block diagram of a processor 200 is illustrated having multiple processing cores and a dynamic voltage and frequency scaling (DVFS) resource manager 202 configured to control the clocking frequency of the processing cores. In some aspects, the processor 200 can be implemented within the Figure 1 SoC 102. The processor 200 can include Figure 1More components that are not shown for simplicity of description. The DVFS resource manager 202 may optimize the power consumption of processing cores (e.g., core A 204, core B 206, core C 208, and core D 210) while maintaining an acceptable performance level. Cores 204, 206, 208, and 210 may be used to implement clocked components (e.g., CPU 104, GPU 106, and DSP 108) in the SoC 102. The DVFS resource manager 202 may receive votes from each of the processing cores 204, 206, 208, and 210. In some aspects, each core may transmit a DVFS request or vote to the DVFS resource manager 202 to indicate a clocking frequency and / or voltage request. For example, a core may transmit a vote to increase or decrease its clocking frequency. In some aspects, the vote may indicate a desired frequency (F_req) and an optimal frequency (F_opt). F_req may indicate the minimum clocking frequency required for the current workload of the core processing core, and F_opt may indicate the optimal clocking frequency (e.g., most energy-efficient) for the core to handle the current workload. In some aspects, it is contemplated that the DVFS request or vote may indicate voltage and / or clocking frequency.

[0033] In some aspects, each core may determine its vote based on expected application processing or workload requirements. The DVFS resource manager 202 aggregates the votes and determines the corresponding clocking frequency of the core based on the votes. In addition to the votes, the DVFS resource manager 202 may also consider additional parameters (e.g., data bandwidth constraints and power rail current constraints) to determine the clocking frequency. Based on the votes and / or additional parameters, the DVFS resource manager 202 may select a higher or lower clocking frequency for each processor core.

[0034] In some aspects, the processor 200 includes a clocking and rail voltage controller 212 that may work with the DVFS resource manager to supply and control the rail voltage and frequency of each processing core (e.g., cores 204, 206, 208, and 210). The DVFS resource manager 202 may use the clocking and rail voltage controller 212 to change the clocking frequency and / or rail voltage of each core based on a regulator-follower DVFS scheme according to the votes received from one or more cores. An example of the regulator-follower DVFS scheme is described in more detail below. The cores may be controlled to use the same or different clocking frequencies. In some aspects, the DVFS techniques described herein may be performed by an application-specific integrated circuit (ASIC) and / or software executed in a programmable processor (e.g., CPU 104). A single DVFS ASIC or program may be shared among more than one core.

[0035] Figure 3Illustrates an example of the DVFS frequency and voltage pattern 300 of an SoC according to some aspects. The DVFS resource manager (e.g., Figure 2 the DVFS resource manager 202 shown) may use the first clocking frequency pattern 302 of the first core (Core A) and the second clocking frequency pattern 304 of the second core (Core B). In one example, the first core and the second core may be any of the cores included in the CPU 104, GPU 106, and DSP 108 described above in Figure 1 . In these clocking frequency patterns, the x-axis (horizontal direction) indicates time, and the y-axis (vertical direction) indicates the clocking frequency for the corresponding core. The higher frequency portion indicates a higher frequency vote requested by the core; the lower frequency portion indicates a lower frequency vote requested by the core. In this example, the first core and the second core share the same voltage rail but use independent DVFS schemes. This means that the first core and the second core independently vote for the desired clocking frequency to meet their respective use cases.

[0036] In Figure 3 the example shown, the first clocking frequency pattern 302 of the first core corresponds to approximately 50% of the high-frequency dwell (high-frequency duration), and the second clocking frequency pattern 304 of the second core also corresponds to approximately 50% of the high-frequency dwell. To enable the cores to operate at a higher clocking frequency, the SoC may increase the voltage rail supplying power to the first core and the second core. In some aspects, the voltage rail may be configured to support multiple voltages (e.g., V1, V2, V3,... Vmax). When the cores use independent DVFS schemes, the resulting voltage dwell of the shared voltage rail may not be optimal. Figure 3 Illustrates the voltage rail activity 306 corresponding to the first clocking frequency pattern 302 and the second clocking frequency pattern 304. In this case, the voltage rail activity has a dwell (duration) of approximately 75% at the higher voltage level 308 rather than at the lower voltage level 310. The above independent DVFS scheme does not attempt to overlap or align the high-frequency durations of the clocking frequency patterns in response to votes from multiple cores, resulting in spending a longer duration than necessary at the higher voltage 308.

[0037] Figure 4 Illustrates another example of the DVFS frequency and voltage pattern 400 of an SoC according to some aspects. For example, the SoC may be the Figure 1 SoC 102 or any processing device with multiple cores. Figure 4Illustrates a first clocked frequency pattern 402 of a first core (Core A) and a second clocked frequency pattern 404 of a second core (Core B). In one example, the first core and the second core can be any of the cores of the SoC 102 (e.g., the CPU 104, the GPU 106, and the DSP 108). In these clocked frequency patterns, the x-axis (horizontal direction) indicates time, and the y-axis (vertical direction) indicates the clocked frequency for the corresponding core. In this example, the first core and the second core share the same voltage rail and implement a regulator-follower DVFS scheme that can optimize (e.g., minimize) the high-voltage dwell (duration) of the voltage rail.

[0038] In Figure 4 the example shown, the first core (Core A) is the regulator, and the second core (Core B) is the follower. In one aspect, a core can be pre-configured by default as a regulator or a follower. In one aspect, a core can register with the DVFS resource manager 202 ( Figure 2 ) as a regulator core or a follower core. In terms of transmitting DVFS requests or votes to change the clocked frequency and / or rail voltage timing, the follower core is associated with the regulator core and (opportunistically) follows the regulator core. The regulator core may affect the timing of the DVFS requests or votes of the follower core. In some aspects, the DVFS requests or votes can indicate the rail voltage and / or clocked frequency required by the core. For example, when the regulator core votes in favor of a higher clocked frequency / voltage, the follower core can follow to increase its

[0039] clock frequency / voltage (if needed). When the regulator core votes in favor of a lower clocked frequency / voltage, the follower core can follow the regulator to use a lower clocked frequency / voltage. It is also conceivable that when the follower core needs to adjust its clocked frequency / voltage to meet specific performance and / or power consumption requirements, the follower core can transmit a DVFS request or vote in the absence of a regulator core DVFS request or vote. In some cases, the DVFS resource manager (e.g., Figure 2 the DVFS resource manager 202 shown) can increase or decrease the clocked frequency of the follower core to follow the clocked frequency of the regulator core. The regulator-follower DVFS scheme enables the follower core to opportunistically use a higher clock frequency in time alignment with the regulator core.

[0040] In Figure 4In the illustrated example, the first clocked frequency pattern 402 of the governor core corresponds to approximately 50% of the high-frequency dwell (duration), and the second clocked frequency pattern 404 of the follower core also corresponds to approximately 50% of the high-frequency dwell. In this case, the two clocked frequency patterns are aligned in time. The high-frequency portion 408 of the first clocked frequency pattern 402 is aligned in time with the high-frequency portion 410 of the second clocked frequency pattern 404. Similarly, the low-frequency portion 412 of the first clocked frequency pattern 402 is aligned in time with the low-frequency portion 414 of the second clocked frequency pattern 404. To enable the cores to operate at a higher clocked frequency, the SoC can increase the voltage rail that supplies power to the governor core and the follower core. Increasing the voltage rail means increasing the voltage level of the power supply voltage of the core. In some aspects, the voltage rail can be configured to support multiple voltages (e.g., V1, V2, V3, …… Vmax). Since the governor core and the follower core implement the governor-follower DVFS scheme, the resulting high-voltage dwell 416 (high-voltage portion) of the voltage rail can be better (e.g., minimized) than the high-voltage dwell achievable in the independent DVFS scheme described above in Figure 3 is better (e.g., minimized) than the high-voltage dwell achievable in the independent DVFS scheme described above in Figure 4 Illustrates the voltage rail activity 418 corresponding to the first clocked frequency pattern 402 and the second clocked frequency pattern 404. Using the governor-follower DVFS scheme, the voltage rail activity has approximately 50% of the high-voltage dwell (less than Figure 3 the 75% dwell in

[0041] Figure 5 is a flowchart illustrating a governor-follower DVFS process 500 according to some aspects of the present disclosure. In one example, the DVFS process 500 can be performed by an SoC 102 equipped with Figure 2 the DVFS resource manager 202 shown in Figure 1 or any processor. The SoC 102 can have multiple processing cores (e.g., cores in the CPU 104, GPU 106, and / or DSP 108). One or more of the processing cores can be a governor core, and one or more of the processing cores can be a follower core, as described above with respect to Figure 3 and Figure 4 It is contemplated that the governor core can have one or more follower cores, and the follower core can follow one or more governor cores in terms of the clocked frequency.

[0042] At 502, the governor core may request an increase in the clocked frequency. For example, the governor core may need to increase its clocked frequency to handle a higher workload. For example, the workload can be a task, program, or process running on the governor core. When the workload is above a certain threshold, the governor core may send a request (e.g., a DVFS vote) to the DVFS resource manager to request an increase in the clocked frequency. The governor core may be configured to operate at multiple clocked frequencies. In one example, Figure 6 Table 600 of Figure 6 illustrates multiple clocked frequencies Fa-1, Fa-2, Fa-3, ……, Fa-max that may be used by the governor core. Fa-1 is the lowest clocked frequency, Fa-2 is a higher clocked frequency than Fa-1, Fa-3 is a higher clocked frequency than Fa-2, and Fa-max is the highest clocked frequency. When the governor core operates at a higher clocked frequency (e.g., at Fa-2 instead of Fa-1), the governor core may handle a higher workload. The multiple available clock frequencies enable the governor core to use different clocked frequencies to meet different target performance levels.

[0043] In some aspects, it is conceivable that the governor core may request an increase in the rail voltage, which implicitly indicates a corresponding increase in the clocked frequency (e.g., based on Figure 6 Table 600 of Figure 6 ). A high rail voltage also enables the governor core to operate at a high clocked frequency. Similarly, the governor core may request a decrease in the rail voltage, which implicitly indicates a corresponding decrease in the clocked frequency.

[0044] At 504, the DVFS resource manager may determine the clocked frequencies of one or more follower cores that may follow the governor core. In some aspects, the DVFS resource manager may determine the clocked frequency of each follower core based on a frequency mapping rule between the governor core and the follower cores. Figure 6Table 602 illustrates exemplary mapping rules between a governor core (e.g., core A) and two follower cores (e.g., core B and core C). In some examples, SoC 102 may have one or more neutral cores (e.g., core D) that do not follow the governor core in terms of clocking frequency. In Table 602, the clocking frequencies Fa-1, Fa-2, Fa-3, ……, Fa-max of core A (governor core) are respectively mapped to the clocking frequencies Fb-1, Fb-2, Fb-3, ……, Fb-max of core B (follower core). In this example, the clocking frequencies have a 1-to-1 mapping. Each increase in the clocking frequency of core A is followed by a corresponding increase in the clocking frequency of core B. In other respects, the clocking frequencies between cores may not have a 1-to-1 mapping. For example, when the clocking frequency of core A (governor core) increases, the clocking frequency of core C (follower core) may increase to a predetermined limit or threshold (e.g., Fc-2) and stop increasing even when the governor core further increases its clocking frequency. Setting a limit on the increase in the clocking frequency of the follower core can provide a safety mechanism to prevent the supply current from exceeding the current limit of the shared power rail.

[0045] In one example, when the frequency Fa-1 of core A (governor) is mapped to the frequency Fc-1 of core C, multiple clocking frequencies of core A (e.g., Fa-2 to Fa-max) are mapped to the same clocking frequency (e.g., Fc-2) of core C (follower). In one example, when the governor core (core A) changes its clocking frequency to Fa-2, the DVFS resource manager may change the clocking frequencies of core B and core C (follower cores) to Fb-2 and Fc-2 respectively.

[0046] At 506, the DVFS resource manager may determine the voltage rail level to support the requested clocking frequency of the governor core and the clocking frequency of each follower core. In some respects, the DVFS resource manager may configure the voltage rail to provide various voltage levels (e.g., Figure 6 V1, V2, ……, and Vmax as shown in Table 600). For example, when the voltage rail is at V1, the governor core (e.g., Figure 6The core A) in can operate at Fa-1. When the voltage rail is at V2, the regulator core can operate at Fa-2. When the voltage rail is at Vmax, the regulator core can operate at Fa-max, and so on. Generally, a higher voltage rail allows the regulator core to operate at a higher clocking frequency. However, a higher voltage and / or clocking frequency may increase the power consumption of the core. In some aspects, the DVFS resource manager can adjust the voltage rail level to the minimum voltage level required to enable the clocking frequencies of the regulator core and each follower core. In some aspects, it is conceivable that the regulator core and the follower core can use different voltage rail levels.

[0047] At 508, the DVFS resource manager can change the clocking frequency of the regulator core to the requested clocking frequency (e.g., Fa-2) according to a mapping rule (e.g., a mapping table) and change the clocking frequency of each follower core. For example, the DVFS resource manager can change the clocking frequency of the regulator core from Fa-1 to Fa-2. In some aspects, the request (e.g., vote) of the regulator core can indicate the required clocking frequency (F_req) and the optimal clocking frequency (F_opt), and the DVFS resource manager can set the clocking frequency to a frequency between F_req and F_opt (including F_req and F_opt).

[0048] Figure 7 Illustrates another example of the DVFS frequency and voltage pattern 700 of an SoC according to some aspects. For example, the SoC can be Figure 1 the SoC 102 or any processing device with multiple cores. Figure 7 Illustrates the first clocking frequency pattern 702 of the first core (regulator core) and the second clocking frequency pattern 704 of the second core (follower core). In one example, the first core and the second core can be any of the cores of the SoC 102 (e.g., CPU 104, GPU 106, and DSP 108). In these clocking frequency patterns, the x-axis (horizontal direction) indicates time, and the y-axis (vertical direction) indicates the clocking frequency for the corresponding core. In this example, the first core and the second core can share the same voltage rail and implement a regulator-follower DVFS scheme that can optimize (e.g., minimize) the high-voltage dwell (duration) of the voltage rail. Only the Figure 7 relevant differences between the Figure 4 illustrated examples are described to reduce unnecessary repetition of the present disclosure.

[0049] In some aspects, the regulator core has the first clocking frequency pattern 702, and the follower core has the second clocking frequency pattern 704. Compared with Figure 4Similar to the example of, the follower core may opportunistically follow the governor core to align their high-frequency dwells and / or high-voltage dwells. For example, the high-frequency portion 708 of the first clocked frequency pattern 702 may be substantially aligned in time with the high-frequency portion 710 of the second clocked frequency pattern 704. Similarly, the low-frequency portion 712 of the first clocked frequency pattern 702 may be substantially aligned in time with the low-frequency portion 714 of the second clocked frequency pattern 704. The resulting high-voltage dwell 716 (high-voltage portion) of the voltage rail may be superior (e.g., minimized) to the high-voltage dwell that can be achieved in the independent DVFS example described above in Figure 3 The voltage rail activity 718 corresponds to the first clocked frequency pattern 702 and the second clocked frequency pattern 704.

[0050] In some aspects, when the follower core opportunistically follows the governor core in timing to transmit a DVFS request or vote, the follower core may request or vote in favor of a clocked frequency and / or rail voltage that is higher than the default DVFS mapping rule (e.g., Figure 6 Table 602 of) indicated by the follower core. In some aspects, it is conceivable that the follower core may request or vote in favor of an increase in the clocked frequency or rail voltage in the absence of a governor core request or vote. For example, the follower core (e.g., a software entity running at the follower core) may determine that the current workload (e.g., image processing, signal processing, etc.) may use a clocked frequency higher than the clocked frequency indicated by the mapping rule when the follower core follows the governor core to increase the clocked frequency. In this case, the follower core may request (vote or special message) to implement a clocked frequency 720 higher than the high-frequency portion 710 to override the mapping rule. This will result in a higher and / or longer high-voltage dwell 722 than the high-voltage dwell 716. In one example, the DVFS resource manager 202 may receive a request or vote from the follower core that requests a clocked frequency higher than the clocked frequency provided according to the default mapping rule. In one example, when the device has sufficient resources (e.g., power, bandwidth, etc.) to operate the follower core at the requested higher clocked frequency and corresponding higher voltage (if required), the DVFS resource manager 202 may grant the follower's request to override the mapping rule.

[0051] Figure 8 FIG. is a flowchart illustrating a governor-follower DVFS process 800 according to some aspects of the present disclosure. In one example, the DVFS process 800 may be performed by a device equipped with Figure 2 The DVFS resource manager 202 shown in Figure 1be performed by the illustrated SoC 102, as described above. The SoC 102 may have multiple processing cores, the multiple processing cores including one or more governor cores and one or more follower cores, as described above with respect to Figure 3 and Figure 4 described. It is contemplated that a governor core may have one or more follower cores, and a follower core may follow one or more governor cores.

[0052] At 802, the governor core may request a reduction in the clock control frequency. For example, the governor core may request a reduction in its clock control frequency to reduce power consumption and / or when the governor core has a low workload. For example, the governor core may send a request (e.g., a vote) to the DVFS resource manager to request a reduction in the clock control frequency. The governor core may be configured to operate at multiple clock control frequencies (e.g., Fa-1, Fa-2, Fa-3, ……, and Fa-max for core A in Table 600). When the governor core operates at a lower clock control frequency, the core may reduce power consumption. The multiple available clock control frequencies enable the governor core to operate at different power consumption levels, for example, based on the current workload.

[0053] At 804, the DVFS resource manager may change the clock control frequency of the governor core (e.g., core A) to the requested clock control frequency based on the received request (e.g., vote) and / or other parameters (e.g., power limit, bandwidth constraint, core temperature, etc.). In one example, the DVFS resource manager may change the clock control frequency of the governor core from a higher frequency to a lower frequency (e.g., Fa-2 to Fa-1).

[0054] At 806, the DVFS resource manager may change the clock control frequency of the follower core based on the frequency mapping rule between the governor core and the follower core. Figure 6 Table 602 of illustrates an exemplary mapping rule between a governor core (e.g., core A) and two follower cores (e.g., core B and core C), as described above. In one example, when the governor core (core A) reduces its clock control frequency from Fa-2 to Fa-1, the DVFS resource manager may change the clock control frequency of core B from Fb-2 to Fb1 and change the frequency of core C (the follower core) from Fc-2 to Fc-1.

[0055] At 808, the DVFS resource manager may adjust the voltage rail level (if needed) to support the clock control frequencies of the governor core and the follower core. In some aspects, the DVFS resource manager may configure the voltage rail to provide various voltage levels (e.g., Figure 6V1, V2, …… Vmax) shown in Table 600. For example, when the voltage rail is at V1, the governor core (e.g., Core A) can operate at Fa-1, when the voltage rail is at V2, the governor core can operate at Fa-2, when the voltage rail is at Vmax, the governor core can operate at Fa-max, and so on. In some aspects, the DVFS resource manager can set the voltage rail to the lowest level that can still support the clocking frequencies of all cores.

[0056] The above governor-follower DVFS mechanism can minimize the high voltage residency of the shared voltage rail by aligning the high-frequency residencies of the governor cores and follower cores sharing the same voltage rail. In some aspects, SoC 102 can have multiple governor cores, and the DVFS resource manager can maintain mapping rules (e.g., mapping tables) for each governor core.

[0057] Figure 9 is a flowchart illustrating a DVFS process 900 for controlling a voltage rail according to some aspects of the present disclosure. In one example, the DVFS process 900 can be performed by Figure 1 the SoC 102 shown, which can include, for example, a DVFS resource manager 202 and a clocking and rail voltage controller 212, as described above in connection with Figure 2 SoC 102 can have multiple processing cores, which include one or more governor cores, one or more follower cores, and one or more neutral cores, as described above with respect to Figure 3 and Figure 4 It is contemplated that a governor core can have one or more follower cores, and a follower core can follow one or more governor cores.

[0058] At block 902, the DVFS resource manager can receive a clocking frequency vote from a processing core (e.g., a core in CPU 104). The processing core can transmit a vote (request) to increase its clocking frequency to handle a higher workload or provide higher bandwidth (e.g., play a video stream). At 904, the DVFS resource manager determines whether a vote is received from a governor core. A change (e.g., increase or decrease) in the clocking frequency of a governor core can also cause a change in the clocking frequency of a follower core.

[0059] At 906, if the vote is not from a governor core (i.e., a core without a follower core), the DVFS resource manager can change the clocking frequency of the processing core that requested the frequency change and adjust the rail voltage (if needed) to enable the new clocking frequency.

[0060] At 908, if the vote is from the governor core, the DVFS manager determines the frequency mapping between the governor core and the follower cores. For example, the DVFS manager may maintain a mapping table (e.g., Table 602) for each governor core. Each mapping table maps the clocking frequency of the governor core to the clocking frequencies of the follower cores. When the DVFS manager changes the clocking frequency of the governor core based on a request (vote) received from the governor core, the DVFS manager may determine the clocking frequencies of the follower cores based on the mapping table. In one example, the DVFS manager may adjust (e.g., increase or decrease) the clocking frequencies of the follower cores to follow the governor core.

[0061] At 910, the DVFS manager may change the rail voltage (if needed) after determining the clocking frequencies of the governor core and the follower cores. The DVFS manager may determine the appropriate rail voltage (e.g., the minimum level sufficient to enable the clocking frequency) that allows the governor core and the follower cores to operate at their respective clocking frequencies. In one example, the DVFS manager increases the rail voltage when the governor core frequency increases and decreases the rail voltage when the governor core frequency decreases.

[0062] Figure 10 A block diagram illustrating an example of a hardware implementation for apparatus 1000, such as a user equipment, a portable device, a laptop computer, a tablet computer, a computer, a server, a router, a memory array, or any other suitable device having one or more integrated circuits with clocked components (e.g., processing cores). In accordance with various aspects of the present disclosure, elements or any portion of an element or any combination of elements may be implemented using processing system 1002. Processing system 1002 may include one or more processors 1020. Processors 1020 may include one or more processing cores as described above. Examples of processors 1020 include a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuits, and other suitable hardware configured to control in terms of clocking frequencies and power rail voltages as described throughout the present disclosure. In various examples, apparatus 1000 may be configured to perform any one or more of the functions and processes described herein.

[0063] In this example, a bus architecture, generally represented by bus 1022, may be utilized to implement processing system 1002. Bus 1022 may include any number of interconnected buses and bridges, depending on the specific application of processing system 1002 and overall design constraints. Bus 1022 communicatively couples together various circuits including one or more processors, generally represented by processor 1020, DVFS circuit 1004, memory 1008, and a computer-readable medium storing instructions thereon, generally represented by computer-readable medium 1006. Bus 1022 may also link various other circuits and components, such as a timing source, peripherals, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. Bus interface 1010 provides an interface between bus 1022 and a primary radio component shown as first transmitter / receiver 1012 or transceiver and at least one first antenna 1014, and between bus 1022 and interface 1030 (optional). First transmitter / receiver 1012 provides a communication interface or component for communicating with various other devices over a wireless transmission medium via at least one first antenna 1014. Bus interface 1010 also provides an interface between bus 1022 and a secondary radio component shown as second transmitter / receiver 1016 and at least one second antenna 1018. In some examples, a wireless device may include two or more transceivers, each configured to communicate with a respective network type (e.g., terrestrial or non-terrestrial) via the same or different antennas. Interface 1030 provides a communication interface or component for communicating with various other devices and equipment (e.g., other devices housed within the same device or other external devices) via an internal bus or an external transmission medium such as an Ethernet cable or a Universal Serial Bus (USB). Depending on the nature of the device, interface 1030 may include a user interface (e.g., keypad, display, speaker, microphone, joystick). Of course, such a user interface is optional and may be omitted in some examples, such as IoT devices.

[0064] Processor 1020 is responsible for managing bus 1022 and general processing, including executing software stored on computer-readable medium 1006. The software, when executed by processor 1020, causes processing system 1002 to perform the various functions described herein for any particular device. Computer-readable medium 1006 and memory 1008 may also be used to store data or information manipulated by processor 1020 when executing the software.

[0065] In some aspects, the DVFS circuit 1004 can be part of one or more processor cores of the processor 1020 and perform operations by means of a processor core executing software stored in the computer-readable medium 1006. In some aspects, the DVFS circuit 1004 can operate independently of the processor 1020 within the processing system 1002 to execute software stored on the computer-readable medium 1006 using its own processing resources. Software should be interpreted broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software can reside on the computer-readable medium 1006. In some aspects, the DVFS circuit 1004 can perform operations executed by the Figure 2 DVFS resource manager 202 and the clocking and rail voltage controller 212. In some aspects, the DVFS circuit 1004 can be configured to perform the operations described above with respect to Figures 3 to 9 as described.

[0066] The computer-readable medium 1006 can be a non-transitory computer-readable medium. By way of example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic tape), optical disks (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards, flash memory devices (e.g., cards, sticks, or key drives), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, removable disks, and any other suitable medium for storing software or instructions that can be accessed and read by a computer. The computer-readable medium 1006 can reside within the processing system 1002, be located external to the processing system 1002, or be distributed across multiple entities including the processing system 1002. The computer-readable medium 1006 can be embodied as a computer program product. By way of example, a computer program product can include the computer-readable medium in a package material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure, depending on the particular application and overall design constraints imposed on the overall system.

[0067] The apparatus 1000 can be configured to perform any one or more of the operations and processes described herein. In some aspects of the present disclosure, the DVFS circuit 1004, as utilized in the apparatus 1000, can include circuitry configured to implement various functions and processes of the DVFS techniques described herein.

[0068] The DVFS circuit 1004 is coupled to the memory 1008 via the bus 1022. The memory 1008 may include one or more governor-follower frequency mapping tables (governors) 1048. Each governor-follower frequency table (e.g., Figure 6 Table 600) provides rules for mapping the clock frequency of the governor core to the clock frequency of the follower core, as described herein. In some aspects, the DVFS circuit 1004 may include a frequency adjustment circuit 1040, a voltage rail adjustment circuit 1042, and a governor-follower frequency mapping circuit 1044.

[0069] The frequency adjustment circuit 1040 may include one or more hardware components that provide the physical structure for performing various processes related to adjusting (e.g., increasing or decreasing) the clock frequency of the processor 1020 including one or more processing cores. The frequency adjustment circuit 1040 may also be configured to execute the frequency adjustment software 1060 included on the computer-readable medium 1006 to implement the DVFS frequency adjustment techniques described herein. The voltage rail adjustment circuit 1042 may include one or more hardware components that provide the physical structure for performing various processes related to adjusting (e.g., increasing or decreasing the voltage) the voltage rail of the processor 1020 including one or more processing cores. The voltage rail adjustment circuit 1042 may also be configured to execute the voltage rail adjustment software 1062 included on the computer-readable medium 1006 to implement the DVFS voltage rail adjustment techniques described herein.

[0070] The governor-follower frequency mapping circuit 1044 may include one or more hardware components that provide the physical structure for performing various processes related to frequency mapping between the governor core and one or more follower cores of the processor 1020, e.g., based on the governor-follower frequency mapping table 1048. The governor-follower frequency mapping circuit 1044 may also be configured to execute the governor-follower frequency mapping software 1064 included on the computer-readable medium 1006 to implement the DVFS frequency mapping techniques described herein.

[0071] The circuit architectures described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architectures described herein may also be fabricated using various process technologies such as complementary metal oxide semiconductor (CMOS), NMOS, PMOS, bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistor (HBT), high electron mobility transistor (HEMT), silicon-on-insulator (SOI), etc.

[0072] The apparatus for implementing a circuit described herein can be a stand-alone device or can be part of a larger device. The device can be (i) a stand-alone IC, (ii) a collection of one or more ICs that can include a memory IC for storing data and / or instructions, (iii) a radio frequency integrated circuit (RFIC), such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC, such as a mobile station modem (MSM), (v) a module embeddable within other devices, (vi) a receiver, a cellular phone, a wireless device, a handset, or a mobile unit, (vii) and so on.

[0073] Figure 11 is an example process flow diagram of performing the DVFS method 1100 at a device (such as Figure 1 device 102, Figure 2 processor 200, or Figure 10 device 1000) that includes a plurality of processing cores. The method can also be performed by other circuits or components or processing resources other than those shown and described herein. In one example, the method can use Figure 10 DVFS circuit 1004 or other circuits and software described in the context of Figure 10 to perform. The method can start with a first processing core of the device operating at a first clocking frequency. In one example, the first processing core can operate at a default frequency in the case of a default voltage rail.

[0074] At block 1102, the device can adjust a first DVFS parameter of the first processing core of the device to execute a workload. The first DVFS parameter can include a first clocking frequency and / or a first rail voltage requested by the first processing core. For example, the frequency adjustment circuit 1040 shown and described above in conjunction with Figure 10 can provide components for adjusting the first clocking frequency of the first processing core. The voltage rail adjustment circuit 1042 shown and described above in conjunction with Figure 10 can provide components for adjusting the first rail voltage of the first processing core. In one example, the first processing core can be a core in the CPU 104, DSP 108, or GPU 106 of the SoC 102; or one of the cores 204, 206, 208, and 210 of the processor 200.

[0075] At block 1104, the device can adjust the second DVFS parameter based on a first mapping rule between the first DVFS parameter and a second DVFS parameter of a second processing core of the device that shares a voltage rail with the first processing core. The second DVFS parameter can include a second clocking frequency and / or a second rail voltage requested by the second processing core. In one example, the above in conjunction with Figure 10The illustrated and described frequency adjustment circuit 1040 may provide components for adjusting the second clocked frequency of the second processing core. The voltage rail adjustment circuit 1042( Figure 10 ) may provide components for adjusting the second rail voltage of the second processing core. In one example, the second processing core may be a core in the CPU 104, DSP 108, or GPU 106 of the SoC 102; or one of the cores 204, 206, 208, and 210 of the processor 200. In some aspects, the first processing core may be a regulator core and the second processing core may be a follower core. The regulator-follower frequency mapping circuit 1044 may provide components for mapping the first clocked frequency to the second clocked frequency based on a regulator-follower frequency mapping table 1048 that may be stored in the memory 1008. The apparatus may adjust the clocked frequency of the follower core to follow the clocked frequency of the regulator core as described herein.

[0076] At block 1106, the apparatus may adjust the voltage of the voltage rail such that the first processing core can operate at the first clocked frequency and the second processing core can operate at the second clocked frequency. In one example, the voltage rail adjustment circuit 1042 may provide components for adjusting the voltage of the voltage rail. Since the follower core may opportunistically follow the regulator core in terms of the clocked frequency, the apparatus may reduce the residence or use of a higher voltage at the shared voltage rail because the follower core and the regulator core will have better time alignment when they use a higher clocked frequency.

[0077] As used herein, "or" is intended to be interpreted in an inclusive sense unless otherwise explicitly stated. For example, "a or b" may include only a, only b, or a combination of a and b. As used herein, a phrase referring to "at least one of" or "one or more of" a list of items refers to any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to cover examples such as only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a, b, and c.

[0078] The various illustrative components, logic components, logic blocks, modules, circuits, operations, and algorithmic processes described in connection with the specific implementations disclosed herein may be implemented as electronic hardware, firmware, software, or any combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been described generally in terms of their functionality and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends upon the particular application and the design constraints imposed on the overall system.

[0079] The various illustrative logical blocks, modules, and circuits described in connection with the various exemplary aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0080] In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0081] For those of ordinary skill in the art, various modifications to the specific implementations described herein will be readily apparent, and the general principles defined herein may be applied to other specific implementations without departing from the spirit or scope of the disclosure. Thus, the claims are not intended to be limited to the specific implementations shown herein but are to be accorded the widest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0082] Additionally, various features described in the context of separate embodiments in this specification can also be implemented in combination in a single embodiment. Conversely, each feature described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. Thus, although features may be described above as acting in a particular combination and even initially claimed as such, one or more features from the claimed combination can in some cases be deleted from the combination, and the claimed combination can be directed to a sub-combination or a variant of the sub-combination.

[0083] Similarly, although operations are depicted in the figures in a particular order, this should not be construed as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired result. Additionally, the figures may schematically depict one or more example processes in the form of a flowchart or a flow diagram. However, other operations not depicted may be incorporated into the example processes schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously with, or in between any of the illustrated operations. In some environments, multitasking and parallel processing may be advantageous. Further, the separation of various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, but rather it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated into multiple software products.

[0084] An overview of the embodiments of the present disclosure is provided below.

[0085] A first aspect of the present disclosure provides an apparatus for dynamic voltage and frequency scaling. The apparatus includes: a plurality of processing cores; and a dynamic voltage and frequency scaling (DVFS) resource manager coupled to the plurality of processing cores, wherein the DVFS resource manager is configured to: adjust a first clock control frequency of a first processing core of the apparatus based on a request of the first processing core; adjust a second clock control frequency based on a first mapping rule between the first clock control frequency and a second clock control frequency of a second processing core of the apparatus that shares a voltage rail with the first processing core; and adjust a voltage of the voltage rail such that the first processing core can operate at the first clock control frequency and the second processing core can operate at the second clock control frequency.

[0086] In a second aspect of the present disclosure, either alone or in combination with the first aspect, in order to adjust the voltage of the voltage rail, the DVFS resource manager is further configured to set the voltage rail to a minimum level sufficient to enable the first processing core to operate at the first clocking frequency and to enable the second processing core to operate at the second clocking frequency.

[0087] In a third aspect of the present disclosure, either alone or in combination with the first aspect, the DVFS resource manager is further configured to: adjust the third clocking frequency based on a second mapping rule between the first clocking frequency and a third clocking frequency of a third processing core of the device, the third processing core being configured to share the voltage rail with the first processing core and the second processing core; and adjust the voltage of the voltage rail such that the first processing core can operate at the first clocking frequency, the second processing core can operate at the second clocking frequency, and the third processing core can operate at the third clocking frequency.

[0088] In a fourth aspect of the present disclosure, either alone or in combination with any one of the first aspect to the third aspect, in order to adjust the second clocking frequency, the DVFS resource manager is further configured to increase the second clocking frequency based on the first mapping rule to follow an increase in the first clocking frequency.

[0089] In a fifth aspect of the present disclosure, either alone or in combination with any one of the first aspect to the third aspect, in order to adjust the second clocking frequency, the DVFS resource manager is further configured to increase the second clocking frequency to a frequency higher than the frequency indicated by the first mapping rule.

[0090] In a sixth aspect of the present disclosure, either alone or in combination with any one of the first aspect to the third aspect, in order to adjust the second clocking frequency, the DVFS resource manager is further configured to: increase the second clocking frequency to follow an increase in the first clocking frequency until a frequency threshold; and maintain the second clocking frequency at the frequency threshold regardless of a further increase in the first clocking frequency.

[0091] In a seventh aspect of the present disclosure, either alone or in combination with any one of the first aspect to the third aspect, the DVFS resource manager is further configured to decrease the second clocking frequency based on the first mapping rule to follow a decrease in the first clocking frequency.

[0092] In an eighth aspect of the present disclosure, either alone or in combination with any one of the first to third aspects, the first mapping rule includes a plurality of first values of the first clock control frequency, and each of the first values is mapped to a corresponding second value of the second clock control frequency.

[0093] In a ninth aspect of the present disclosure, either alone or in combination with any one of the first to third aspects, wherein the first mapping rule includes a plurality of first values of the first clock control frequency, and two or more of the first values are mapped to the same second value of the second clock control frequency.

[0094] In a tenth aspect of the present disclosure, either alone or in combination with any one of the first to third aspects, in order to adjust the second clock control frequency, the DVFS resource manager is further configured to adjust the second clock control frequency according to at least one of a power rail current constraint or a bandwidth constraint of the device.

[0095] An eleventh aspect of the present disclosure provides a method for performing dynamic voltage and frequency scaling (DVFS) at a device. The method includes: adjusting a first clock control frequency of a first processing core based on a request of the first processing core of the device; adjusting a second clock control frequency based on a first mapping rule between the first clock control frequency and a second clock control frequency of a second processing core of the device that shares a voltage rail with the first processing core; and adjusting a voltage of the voltage rail such that the first processing core can operate at the first clock control frequency and the second processing core can operate at the second clock control frequency.

[0096] In a twelfth aspect of the present disclosure, either alone or in combination with the eleventh aspect, wherein adjusting the voltage of the voltage rail includes: setting the voltage rail to a minimum level sufficient to enable the first processing core to operate at the first clock control frequency and the second processing core to operate at the second clock control frequency.

[0097] In a thirteenth aspect of the present disclosure, either alone or in combination with the eleventh aspect, the method further includes: adjusting a third clock control frequency based on a second mapping rule between the first clock control frequency and a third clock control frequency of a third processing core of the device, the third processing core being configured to share the voltage rail with the first processing core and the second processing core; and

[0098] adjusting the voltage of the voltage rail such that the first processing core can operate at the first clock control frequency, the second processing core can operate at the second clock control frequency, and the third processing core can operate at the third clock control frequency.

[0099] In a fourteenth aspect of the present disclosure, either alone or in combination with any one of the eleventh to thirteenth aspects, wherein adjusting the second clocked frequency includes: increasing the second clocked frequency based on the first mapping rule to follow an increase in the first clocked frequency.

[0100] In a fifteenth aspect of the present disclosure, either alone or in combination with any one of the eleventh to thirteenth aspects, wherein adjusting the second clocked frequency includes increasing the second clocked frequency to a frequency higher than the frequency indicated by the first mapping rule.

[0101] In a sixteenth aspect of the present disclosure, either alone or in combination with any one of the eleventh to thirteenth aspects, wherein adjusting the second clocked frequency includes: increasing the second clocked frequency to follow an increase in the first clocked frequency until a frequency threshold; and maintaining the second clocked frequency at the frequency threshold regardless of a further increase in the first clocked frequency.

[0102] In a seventeenth aspect of the present disclosure, either alone or in combination with any one of the eleventh to thirteenth aspects, the method further includes reducing the second clocked frequency based on the first mapping rule to follow a decrease in the first clocked frequency.

[0103] In an eighteenth aspect of the present disclosure, either alone or in combination with any one of the eleventh to thirteenth aspects, wherein the first mapping rule includes a plurality of first values of the first clocked frequency, and each of the first values is mapped to a corresponding second value of the second clocked frequency.

[0104] In a nineteenth aspect of the present disclosure, either alone or in combination with any one of the eleventh to thirteenth aspects, wherein the first mapping rule includes a plurality of first values of the first clocked frequency, and two or more of the first values are mapped to the same second value of the second clocked frequency.

[0105] In a twentieth aspect of the present disclosure, either alone or in combination with any one of the eleventh to thirteenth aspects, wherein adjusting the second clocked frequency includes adjusting the second clocked frequency according to at least one of a power rail current constraint or a bandwidth constraint of the device.

[0106] A twenty - first aspect of the present disclosure provides an apparatus for dynamic voltage and frequency scaling (DVFS). The apparatus includes: components for adjusting a first clocked frequency of a first processing core based on a request of the first processing core of the apparatus; components for adjusting a second clocked frequency based on a first mapping rule between the first clocked frequency and a second clocked frequency of a second processing core of the apparatus that shares a voltage rail with the first processing core; and components for adjusting a voltage of the voltage rail such that the first processing core can operate at the first clocked frequency and the second processing core can operate at the second clocked frequency.

[0107] In a twenty - second aspect of the present disclosure, either alone or in combination with the twenty - first aspect, the apparatus further includes components for setting the voltage rail to a minimum level sufficient to enable the first processing core to operate at the first clocked frequency and the second processing core to operate at the second clocked frequency.

[0108] In a twenty - third aspect of the present disclosure, either alone or in combination with any one of the twenty - first aspect to the twenty - second aspect, the apparatus further includes components for increasing the second clocked frequency to follow an increase in the first clocked frequency based on the first mapping rule.

[0109] In a twenty - fourth aspect of the present disclosure, either alone or in combination with any one of the twenty - first aspect to the twenty - second aspect, the apparatus further includes components for increasing the second clocked frequency to a frequency higher than the frequency indicated by the first mapping rule.

Claims

1. A device for dynamic voltage and frequency scaling, the device comprising: a plurality of processing cores; and a dynamic voltage and frequency scaling (DVFS) resource manager coupled to the plurality of processing cores, wherein the DVFS resource manager is configured to: adjust the DVFS parameters of a first processing core of the device based on a request of the first processing core; adjust the second DVFS parameters based on a first mapping rule between the first DVFS parameters and second DVFS parameters of a second processing core of the device sharing a voltage rail with the first processing core; and and adjust the voltage of the voltage rail such that the first processing core can operate using the first DVFS parameters and the second processing core can operate using the second DVFS parameters.

2. The device according to claim 1, wherein in order to adjust the voltage of the voltage rail, the DVFS resource manager is further configured to: set the voltage rail to a minimum level sufficient to enable the first processing core to operate using the first DVFS parameters and the second processing core to operate using the second DVFS parameters.

3. The device according to claim 1, wherein the DVFS resource manager is further configured to: adjust the third DVFS parameters based on a second mapping rule between the first DVFS parameters and third DVFS parameters of a third processing core of the device, the third processing core being configured to share the voltage rail with the first processing core and the second processing core; and adjust the voltage of the voltage rail such that the first processing core can operate using the first DVFS parameters, the second processing core can operate using the second DVFS parameters, and the third processing core can operate using the third DVFS parameters.

4. The device according to claim 1, wherein the first DVFS parameters include a first clocked frequency, and the second DVFS parameters include a second clocked frequency, and the DVFS resource manager is further configured to: increase the second clocked frequency to follow an increase in the first clocked frequency based on the first mapping rule.

5. The device according to claim 1, wherein the first DVFS parameters include a first clocked frequency, and the second DVFS parameters include a second clocked frequency, and the DVFS resource manager is further configured to: increase the second clocked frequency to a frequency higher than the frequency indicated by the first mapping rule.

6. The device according to claim 1, wherein the first DVFS parameters include a first clocked frequency, and the second DVFS parameters include a second clocked frequency, and the DVFS resource manager is further configured to: increase the second clocked frequency to follow an increase in the first clocked frequency until a frequency threshold; and Maintain the second clock control frequency at the frequency threshold regardless of a further increase in the first clock control frequency.

7. The apparatus according to claim 1, wherein the first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency, and the DVFS resource manager is further configured to: Reduce the second clock control frequency based on the first mapping rule to follow a decrease in the first clock control frequency.

8. The apparatus according to claim 1, wherein: The first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency; and The first mapping rule includes a plurality of first values of the first clock control frequency, and each of the first values is mapped to a corresponding second value of the second clock control frequency.

9. The apparatus according to claim 1, wherein: The first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency; and The first mapping rule includes a plurality of first values of the first clock control frequency, and two or more of the first values are mapped to the same second value of the second clock control frequency.

10. The apparatus according to claim 1, wherein the first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency, and the DVFS resource manager is further configured to: Adjust the second clock control frequency according to at least one of a power rail current constraint or a bandwidth constraint of the apparatus.

11. The apparatus according to claim 1, wherein each of the first DVFS parameter and the second DVFS parameter includes at least one of a clock control frequency and a rail voltage.

12. A method for performing dynamic voltage and frequency scaling (DVFS) at an apparatus, the method comprising: Adjust a first DVFS parameter of a first processing core of the apparatus based on a request of the first processing core; Adjust a second DVFS parameter based on a first mapping rule between the first DVFS parameter and a second DVFS parameter of a second processing core of the apparatus that shares a voltage rail with the first processing core; And Adjust a voltage of the voltage rail such that the first processing core can operate using the first DVFS parameter and the second processing core can operate using the second DVFS parameter.

13. The method according to claim 11, wherein adjusting the voltage of the voltage rail includes: Setting the voltage rail to a minimum level sufficient to enable the first processing core to operate using the first DVFS parameter and the second processing core to operate using the second DVFS parameter.

14. The method according to claim 11, the method further comprising: Adjust the third DVFS parameter based on a second mapping rule between the first DVFS parameter and the third DVFS parameter of a third processing core of the device, the third processing core being configured to share the voltage rail with the first processing core and the second processing core; and Adjust the voltage of the voltage rail such that the first processing core can operate using the first DVFS parameter, the second processing core can operate with the second DVFS parameter, and the third processing core can operate with the third DVFS parameter.

15. The method according to claim 11, wherein the first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency, and the method further comprises: Increasing the second clock control frequency based on the first mapping rule to follow an increase in the first clock control frequency.

16. The method according to claim 11, wherein the first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency, and the method further comprises: Increasing the second clock control frequency to a frequency higher than the frequency indicated by the first mapping rule.

17. The method according to claim 11, wherein the first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency, and the method further comprises: Increasing the second clock control frequency to follow an increase in the first clock control frequency until a frequency threshold; and Maintaining the second clock control frequency at the frequency threshold regardless of a further increase in the first clock control frequency.

18. The method according to claim 11, wherein the first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency, and the method further comprises: Reducing the second clock control frequency based on the first mapping rule to follow a decrease in the first clock control frequency.

19. The method according to claim 11, wherein: The first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency; and The first mapping rule includes a plurality of first values of the first clock control frequency, each of the first values being mapped to a corresponding second value of the second clock control frequency.

20. The method according to claim 11, wherein: The first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency; and The first mapping rule includes a plurality of first values of the first clock control frequency, two or more of the first values being mapped to the same second value of the second clock control frequency.

21. The method according to claim 11, wherein the first DVFS parameter includes a first clock control frequency, and the second DVFS parameter includes a second clock control frequency, and the method further comprises: Adjusting the second clock control frequency according to at least one of a power rail current constraint or a bandwidth constraint of the device.

22. A device for dynamic voltage and frequency scaling (DVFS), the device comprising: means for adjusting a first DVFS parameter of the first processing core based on a request of the first processing core of the device; means for adjusting the second DVFS parameter based on a first mapping rule between the first DVFS parameter and a second DVFS parameter of a second processing core of the device that shares a voltage rail with the first processing core; and means for adjusting the voltage of the voltage rail such that the first processing core can operate using the first DVFS parameter and the second processing core can operate using the second DVFS parameter.

23. The device according to claim 21, the device further comprising: means for setting the voltage rail to a minimum level sufficient to enable the first processing core to operate using the first DVFS parameter and the second processing core to operate using the second DVFS parameter.

24. The device according to claim 21, wherein the first DVFS parameter includes a first clocked frequency, and the second DVFS parameter includes a second clocked frequency, and the device further comprises: means for increasing the second clocked frequency to follow an increase in the first clocked frequency based on the first mapping rule.

25. The device according to claim 21, wherein the first DVFS parameter includes a first clocked frequency, and the second DVFS parameter includes a second clocked frequency, and the device further comprises: means for increasing the second clocked frequency to a frequency higher than the frequency indicated by the first mapping rule.

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