Integrated substrate, preparation method thereof and electronic equipment
Patent Information
- Application Number
- CN202380011738.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-16
- Publication Date
- 2025-07-18
AI Technical Summary
There are a large number of discrete devices on existing RF PCB boards, which are large in size, high in power consumption, many solder joints, and large changes in parasitic parameters, making it difficult to meet future needs. Integrated passive devices on the market are mainly based on Si and GaAs substrates. Si-based devices are cheap but have high microwave losses. GaAs-based devices have excellent performance but are expensive.
An integrated substrate is provided, including a dielectric substrate, a buffer layer and a conductive structure. A buffer layer and a conductive structure are formed on the upper and lower surfaces of the dielectric substrate, and electrically connected through a connecting via hole through the substrate to form an inductive coil structure.
It realizes integrated passive devices with small area, high performance and good consistency, reduces the interconnection and matching needs between RF chips, and improves the efficiency and reliability of electronic devices.
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Figure CN120345068A_ABST
Abstract
Description
Integrated substrate and preparation method thereof, and electronic equipment Technical Field
[0001] The present disclosure belongs to the technical field of passive devices, and particularly relates to an integrated substrate and a preparation method thereof, and an electronic device. Background Art
[0002] The contemporary consumer electronics industry is rapidly evolving, with mobile communication terminals, particularly 5G phones, experiencing rapid growth. Mobile phones are required to process an increasing number of signal frequency bands, and the number of RF chips required is also increasing. Consumer-favored mobile phone designs are increasingly trending towards miniaturization, thinness, and longer battery life. Traditional mobile phones often feature a large number of discrete components on RF PCBs, such as resistors, capacitors, inductors, and filters. These components suffer from large size, high power consumption, numerous solder joints, and significant parasitic parameter variation, making them difficult to meet future demands. The interconnection and matching between RF chips require integrated passive components that are compact, high-performance, and highly consistent. Currently, the integrated passive components on the market are primarily based on Si (silicon) and GaAs (gallium arsenide) substrates. Si-based integrated passive components offer the advantage of low cost, but inherent trace impurities (poor insulation) in Si lead to high microwave loss and mediocre performance. GaAs-based integrated passive components offer excellent performance but are expensive.
[0003] Summary of the Invention
[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides an integrated substrate and a preparation method thereof, and an electronic device.
[0005] An embodiment of the present disclosure provides an integrated substrate, comprising:
[0006] A dielectric substrate having a first surface and a second surface disposed opposite to each other along a thickness direction thereof; the dielectric substrate including a first connecting via extending through the dielectric substrate along the thickness direction thereof;
[0007] a first buffer layer, disposed on the first surface side, the first buffer layer having a first hollow pattern;
[0008] a second buffer layer, disposed on the second surface side, the second buffer layer having a second hollow pattern;
[0009] a first conductive structure, located in the first hollow pattern;
[0010] a second conductive structure, located in the second hollow pattern;
[0011] The first connecting electrode is located in the first connecting via hole. The first conductive structure and the second conductive structure are connected via the first connecting electrode, and the three form an integrated structure.
[0012] Wherein, the integrated substrate further includes a first protective layer provided on a side of the first conductive structure away from the dielectric substrate.
[0013] Wherein, the first connecting electrode fills the first connecting via hole.
[0014] The first conductive structure and the second conductive structure are electrically connected via the first connecting electrode to form an inductor coil structure.
[0015] The present disclosure provides a method for preparing an integrated substrate, which includes:
[0016] A dielectric substrate is provided, which has a first surface and a second surface arranged opposite to each other along the thickness direction of the dielectric substrate; the dielectric substrate includes a first connecting via hole penetrating along the thickness direction of the dielectric substrate;
[0017] On the first surface, a pattern including a first buffer layer is formed by a patterning process, wherein a first hollow pattern of the first buffer layer is the same as a pattern of a first conductive structure to be formed;
[0018] On the second surface, forming a pattern including a second buffer layer by a patterning process, wherein a second hollow pattern of the second buffer layer is the same as a pattern of a second conductive structure to be formed;
[0019] forming a seed layer on both the side of the first buffer layer facing away from the first surface and the side of the second buffer layer facing away from the second surface, and electroplating the seed layer to form a first conductive layer located on the first surface side, a second conductive layer located on the second surface side, and a first connecting electrode located in the first connecting via hole;
[0020] performing patterning on the first conductive layer to form a pattern including the first conductive structure;
[0021] The second conductive layer is patterned to form a pattern including the second conductive structure, and the second conductive structure is connected to the first conductive structure through the first connecting electrode to form an integrated structure.
[0022] The step of patterning the first conductive layer to form a pattern including the first conductive structure includes:
[0023] The first conductive structure is formed by removing a portion of the first conductive layer located on a surface of the first buffer layer facing away from the dielectric substrate through chemical mechanical polishing, and planarizing a portion of the first conductive layer located in the first hollow pattern facing away from the dielectric substrate.
[0024] The step of patterning the second conductive layer to form a pattern including the second conductive structure includes:
[0025] The second conductive structure is formed by removing a portion of the second conductive layer located on a surface of the second buffer layer facing away from the dielectric substrate by chemical mechanical polishing, and planarizing a portion of the second conductive layer located in the second hollow pattern facing away from the dielectric substrate.
[0026] The thickness of the first conductive layer is 1 to 5 μm thicker than that of the first buffer layer; and / or the thickness of the second conductive layer is 1 to 5 μm thicker than that of the second buffer layer.
[0027] In which, the seed layer includes an auxiliary film layer and a conductive film layer arranged in a stacked manner, and the auxiliary film layer is configured to increase the adhesion between the conductive film layer and the dielectric substrate; the auxiliary film layer in the first conductive structure contacts the side wall of the first hollow pattern, and the auxiliary film layer in the second conductive structure contacts the side wall of the second hollow pattern.
[0028] Wherein, the first buffer layer is away from the surface of the dielectric substrate and is flush with the surface of the first conductive structure away from the surface of the dielectric substrate;
[0029] The second buffer layer is away from the surface of the dielectric substrate and is flush with the surface of the second conductive structure away from the dielectric substrate.
[0030] Wherein, the preparation method further comprises:
[0031] A first protective layer is formed on a side of the first conductive structure facing away from the dielectric substrate.
[0032] Wherein, the first connecting electrode fills the first connecting via hole.
[0033] Wherein, the first buffer layer is made of an organic dielectric material; and / or the second buffer layer is made of an organic dielectric material.
[0034] The first conductive structure and the second conductive structure are electrically connected via the first connecting electrode to form an inductor coil structure.
[0035] An embodiment of the present disclosure provides an electronic device, which includes any of the above-mentioned integrated substrates. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] FIG1 is a flow chart of a first exemplary method for preparing an integrated substrate.
[0037] FIG2 is a flow chart of a second exemplary method for preparing an integrated substrate.
[0038] FIG3 is a flow chart of a third exemplary method for preparing an integrated substrate.
[0039] FIG4 is a schematic structural diagram of a seed layer according to an embodiment of the present disclosure.
[0040] FIG5 is a schematic structural diagram of an integrated substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0041] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0043] The integrated substrate in the embodiments of the present disclosure mainly refers to the integration of passive devices on a glass substrate. That is, the dielectric substrate of the integrated substrate in the embodiments of the present disclosure is a glass substrate, but it should be understood that the dielectric substrate of the integrated substrate can also be a silicon substrate, an LTCC substrate, etc. Passive devices on the integrated substrate include but are not limited to capacitors, inductors, resistors, etc. As the main energy-consuming component in electronic products, the integrated substrate requires a significant reduction in the electromagnetic loss of the device at the RF front end. The advantages of the glass substrate in terms of dielectric loss and cost have made the integration of passive devices on the glass substrate gradually become a mainstream circuit.
[0044] For passive devices integrated on a glass substrate, there are 2D passive devices and 3D passive devices, depending on whether the glass substrate has connection vias. 2D passive devices refer to a conductive layer on one surface of the glass substrate, and a dielectric layer located between the conductive layers, forming devices such as inductors and capacitors. 3D passive devices refer to conductive layers made on the upper and lower surfaces of the glass substrate, respectively, and then the conductive layers on the upper and lower surfaces of the glass substrate are electrically connected through connection vias that penetrate the glass substrate, forming devices such as inductors and capacitors. In the embodiments disclosed herein, only 3D passive devices formed on an integrated substrate are used as an example for explanation.
[0045] In the first example, FIG1 is a flow chart of a method for preparing an integrated substrate of the first example. As shown in FIG1 , a method for preparing an integrated substrate is provided, and the method specifically comprises the following steps:
[0046] S11 , providing a dielectric substrate 10 ; the dielectric substrate 10 includes a first surface and a second surface oppositely disposed along a thickness direction thereof, and the dielectric substrate 10 has a first connecting via 101 penetrating along the thickness direction thereof.
[0047] In some examples, the dielectric substrate 10 includes but is not limited to a glass substrate, and in the embodiment of the present disclosure, a glass substrate is used as an example, and the thickness of the glass substrate is about 0.1 to 1 mm.
[0048] Various methods can be used to fabricate the first connecting vias 101 on the dielectric substrate 10. These methods include sandblasting, photosensitive glass etching, focused discharge etching, plasma etching, laser ablation, electrochemical etching, and laser-induced etching. Different methods have different advantages and disadvantages, as well as applicable scopes. For example, the sandblasting method offers advantages in terms of simplicity. This method produces first connecting vias 101 with larger diameters, but is only suitable for first connecting vias 101 with diameters greater than 200 μm. The photosensitive glass etching method offers advantages in terms of simplicity and the ability to produce high-density, high-aspect-ratio first connecting vias 101. The focused discharge etching method offers advantages in terms of high hole-forming speed. Plasma etching produces low sidewall roughness for first connecting vias. Laser ablation allows for the production of high-density, high-aspect-ratio first connecting vias 101 with high roughness. The electrochemical method offers advantages in terms of low cost, simple equipment, high hole-forming speed, and large diameters for first connecting vias 101. The advantages of the laser induced etching method are that the hole-forming rate is fast, and high-density, high-aspect-ratio first connection vias can be produced without damage to the inside of the through-hole. The disadvantage is that the laser equipment is expensive. Here, laser induced etching is taken as an example, and the laser induced etching method is used to make a rear through-hole on its back. First, a laser is used to perform laser-induced modification on the position where the first connection via 101 is to be made, and then hydrofluoric acid or hot alkali is used to wet-etch the modified position to make the through-hole. Since the rear through-hole can only be made by a single-sided etching method, the obtained hole can only be an inverted tapered hole. For the laser induced etching drilling method, this single-sided etched inverted tapered hole is a typical feature of the rear through-hole on the back of the first connection via 101.
[0049] The first connection via hole 101 formed in step S11 has a diameter of about 20 to 120 μm.
[0050] S12 , forming a first connection electrode 11 in the first connection via hole 101 .
[0051] In some examples, step S12, a first auxiliary film layer is formed by a method including but not limited to magnetron sputtering, and then a first conductive film layer is continuously sputtered as a first seed layer, and the first seed layer is electroplated. After the electroplating is completed, the excess electroplated copper on the first surface and the second surface is removed by chemical mechanical polishing (CMP) to form a first connection electrode 11 that fills the first connection via 101.
[0052] The first auxiliary film layer serves to enhance the adhesion of the first conductive film layer. Materials for the first auxiliary film layer include, but are not limited to, titanium (Ti), and materials for the first conductive film layer include, but are not limited to, copper (Cu). The thickness of the first auxiliary film layer is approximately 20 to 200 nm, and the thickness of the first conductive film layer is approximately 100 to 1000 nm.
[0053] S13 , forming a first conductive structure 21 on the first surface of the dielectric substrate 10 .
[0054] In some examples, step S13 may include: forming a second auxiliary film layer and a second conductive film layer on the first surface of a dielectric substrate 10 using a method including but not limited to magnetron sputtering, as a second seed layer, and then electroplating the second seed layer. The thickness of the second seed layer after electroplating is generally greater than 2 to 10 μm, and then patterning is performed to form the first conductive structure 21.
[0055] The second auxiliary film layer can be a molybdenum (Mo) or nickel (Ni) alloy layer with a thickness of approximately 20 to 200 nm, and the second conductive film layer can be a copper (Cu) layer with a thickness of approximately 100 to 1000 nm. The second auxiliary film layer is provided to enhance the adhesion of the second conductive film layer.
[0056] S14 , forming a first protective layer 41 on a side of the first conductive structure 21 facing away from the dielectric substrate 10 .
[0057] In some examples, step S14 can specifically utilize a standard process such as PECVD to deposit and form a first protective layer 41, which is then cured. The first protective layer 41 is used to prevent water and oxygen from corroding the devices formed on the first surface of the dielectric substrate 10. The thickness of the first protective layer 41 is between 2 and 8 μm. The material of the first protective layer 41 can be polyimide (PI), for example.
[0058] S15 , turning over the dielectric substrate 10 , and forming a buffer layer 50 on the second surface of the dielectric substrate 10 . The hollow pattern of the buffer layer 50 is the same as the pattern of the second conductive structure 31 to be formed.
[0059] In some examples, the buffer layer 50 is an organic dielectric layer, such as polyimide (PI), with a thickness of 2 to 10 μm. In step S15 , a layer of PI glue may be applied, followed by exposure, development, and curing to form the buffer layer 50 having a hollow pattern.
[0060] S16 , forming a second conductive structure 31 on the second surface.
[0061] In some examples, step S16 may include sequentially forming a third auxiliary film layer and a third conductive film layer as a third seed layer using a method including but not limited to magnetron sputtering, and then electroplating the third seed layer. The thickness of the electroplated third seed layer is approximately 2 to 12 μm. Next, chemical mechanical polishing (CMP) is performed using the buffer layer 50 as a cutoff layer to remove the electroplated second seed layer on the surface of the buffer layer 50 facing away from the dielectric substrate 10. The surface of the electroplated second seed layer in the hollow pattern facing away from the dielectric substrate 10 is planarized to form the second conductive structure 31.
[0062] The third auxiliary film layer can be a molybdenum (Mo) or nickel (Ni) alloy layer with a thickness of approximately 20 to 200 nm; the third conductive film layer can be a copper (Cu) layer with a thickness of approximately 100 to 1000 nm. The second auxiliary film layer is provided to enhance the adhesion of the second conductive film layer.
[0063] In some examples, the first conductive structure 21 and the second conductive structure 31 on the integrated substrate are electrically connected via the first connecting electrode 11 to form an inductor coil structure. In some examples, a portion of the first conductive structure 21 can also function as the first plate of a capacitor. The integrated substrate fabrication method may further include forming an interlayer dielectric layer, a second plate of a capacitor, and other structures on the side of the layer containing the second conductive structure 31 facing away from the dielectric substrate 10, which are not further described here.
[0064] Second Example: FIG2 is a flow chart of a method for preparing an integrated substrate of the second example. As shown in FIG2 , this example also provides a method for preparing an integrated substrate, which includes the following steps:
[0065] S21 , providing a dielectric substrate 10 ; the dielectric substrate 10 comprises a first surface and a second surface opposite to each other along its thickness direction, and the dielectric substrate 10 has a first connecting via 101 penetrating along its thickness direction.
[0066] The same process steps as those in S11 can be used for step S21 , so they will not be repeated here.
[0067] S22 , forming a seed layer on both the first surface and the second surface of the dielectric substrate 10 , and electroplating the seed layer to form a first conductive layer 20 located on the first surface side, a second conductive layer 30 located on the second surface side, and a first connection electrode 11 located in the first connection via 101 .
[0068] In some examples, an auxiliary film layer and a conductive film layer are sequentially formed on the first surface and the second surface of the dielectric substrate 10 using methods including but not limited to magnetron sputtering to serve as a seed layer. The seed layer is then electroplated to form a first conductive layer 20 on the first surface, and a second conductive layer 30 on the first surface. The first connection via 101 is filled with a conductive material to form a first connection electrode 11.
[0069] It should be noted that the thickness of the first conductive layer 20 on the first surface is equivalent to the thickness of the first conductive structure 21 to be formed, while the thickness of the second conductive layer 30 on the second surface is 1-5 μm thicker than the thickness of the second conductive structure 31 to be formed.
[0070] The auxiliary film layer can be a molybdenum (Mo) or nickel (Ni) alloy layer with a thickness of about 20 to 200 nm, and the conductive film layer can be a copper (Cu) layer with a thickness of about 100 to 1000 nm. The auxiliary film layer is provided to enhance the adhesion of the conductive film layer.
[0071] S23 , patterning the first conductive layer 20 to form a pattern including a first conductive structure 21 .
[0072] In some examples, step S23 may include forming a first photoresist layer on a side of the first conductive layer 20 facing away from the dielectric substrate 10, then exposing and developing to produce a mask pattern of the first conductive structure 21, removing the exposed portion of the first conductive layer 20, and then removing the remaining portion of the first photoresist layer to form a first conductive pattern.
[0073] S24 , forming a first protective layer 41 on a side of the first conductive structure 21 facing away from the dielectric substrate 10 .
[0074] In some examples, step S24 can specifically utilize a standard process such as PECVD to deposit and form the first protective layer 41, which is then cured. The first protective layer 41 is used to prevent water and oxygen from corroding the devices formed on the first surface of the dielectric substrate 10. The thickness of the first protective layer 41 is between 2 and 8 μm. The material of the first protective layer 41 can be polyimide (PI), for example.
[0075] S25 , processing the second conductive layer 30 to form a pattern including a second conductive structure 31 .
[0076] In some examples, step S25 may include using a chemical mechanical polishing (CMP) method to grind the second conductive layer 30 to a desired thickness, then forming a second photoresist layer on the side of the second conductive layer 30 facing away from the dielectric substrate 10, then exposing and developing to produce a mask pattern of the second conductive structure 31, removing the exposed second conductive layer 30 portion, and then removing the remaining second photoresist layer portion to form a second conductive pattern.
[0077] S26 , forming a second protective layer 42 on a side of the second conductive structure 31 facing away from the dielectric substrate 10 .
[0078] In some examples, the preparation of the second protective layer 42 in step S26 may be the same as the preparation of the first protective layer 41 described above, and the same materials may be used, so the details will not be repeated here.
[0079] In some examples, the first conductive structure 21 and the second conductive structure 31 on the integrated substrate are electrically connected via the first connecting electrode 11 to form an inductor coil structure. In some examples, a portion of the first conductive structure 21 can also function as the first plate of a capacitor. The integrated substrate fabrication method may further include forming an interlayer dielectric layer, a second plate of a capacitor, and other structures on the side of the layer containing the second conductive structure 31 facing away from the dielectric substrate 10, which are not further described here.
[0080] Comparing the first example with the second example, the process flow of the first example is obviously more complicated than that of the second example.
[0081] In the first example, a) the first connection electrode 11 and the first conductive structure 21 / the second conductive structure 31 are prepared separately. After the first connection electrode 11 is formed in the first connection via 101, the first connection electrode 11 expands due to heat during the subsequent two curing processes. After the temperature drops, it contracts again, squeezing the first connection via 101. Since there is no glass at both ends of the first connection via 101, the thermal stress from the expansion and contraction of the first connection electrode 11 accumulates at both ends of the first connection via 101, making cracks more likely to form. b) the first connection electrode 11 and the first conductive structure 21 / the second conductive structure 31 are prepared separately. Before the first conductive structure 21 and the second conductive structure 31 are formed, the first connection electrode 11 is exposed at both ends, making it susceptible to oxidation and contamination by foreign matter. Subsequently, the first conductive structure 21 and the second conductive structure 31 have high contact resistance with the first connection electrode 11, and delamination is more likely to occur.
[0082] In the second example, although the first connection electrode 11, the first conductive structure 21, and the second conductive structure 31 are formed by a single electroplating process, when the first conductive structure 21 and the second conductive structure 31 are patterned, since the first surface and the second surface of the dielectric substrate 10 are both made of metal light-shielding materials, the alignment marks of the first photoresist layer and the second photoresist layer cannot be identified, making it difficult to complete the photolithography.
[0083] FIG3 is a flow chart of a method for preparing an integrated substrate according to a third example. As shown in FIG3 , in order to address some of the problems existing in the first and second examples, the present disclosure further provides a method for preparing an integrated substrate according to the third example, which specifically includes the following steps:
[0084] S31 , providing a dielectric substrate 10 ; the dielectric substrate 10 comprises a first surface and a second surface opposite to each other along its thickness direction, and the dielectric substrate 10 has a first connecting via 101 penetrating along its thickness direction.
[0085] The same process steps as those in S11 can be used for step S31 , so they will not be repeated here.
[0086] S32 , forming a first buffer layer 51 on the first surface of the dielectric substrate 10 by a patterning process; the first hollow pattern 511 of the first buffer layer 51 is the same as the pattern of the first conductive structure 21 to be formed.
[0087] In some examples, the first buffer layer 51 is an organic dielectric layer, such as polyimide (PI), with a thickness of 2 to 10 μm. Step S32 can be specifically performed using a standard process such as PECVD to deposit a layer of PI adhesive, followed by exposure, development, and curing to form the first buffer layer 51 having the first hollow pattern 511 .
[0088] S33 , forming a second buffer layer 52 on the second surface of the dielectric substrate 10 by a patterning process; the second hollow pattern 521 of the second buffer layer 52 is the same as the pattern of the second conductive structure 31 to be formed.
[0089] In some examples, the second buffer layer 52 is an organic dielectric layer, such as polyimide (PI), with a thickness of 2 to 10 μm. Step S32 can be specifically performed using a standard process such as PECVD to deposit a layer of PI adhesive, followed by exposure, development, and curing to form the second buffer layer 52 having the second hollow pattern 521 .
[0090] It should be noted that the order of step S32 and step S33 can be interchanged.
[0091] S34. A seed layer is formed on the side of the first buffer layer 51 facing away from the first surface and on the side of the second buffer layer 52 facing away from the second surface, and the seed layer is electroplated to form a first conductive layer 20 located on the first surface side, a second conductive layer 30 located on the second surface side, and a first connecting electrode 11 located on the first connecting via 101.
[0092] In some examples, step S34 may include forming an auxiliary film layer and a conductive film layer on a side of the first buffer layer 51 facing away from the first surface and a side of the second buffer layer 52 facing away from the second surface. Methods including but not limited to magnetron sputtering are used to sequentially form a first conductive layer 20 and a second conductive layer 30 on the first surface. The first connecting via 101 is filled with a conductive material to form a first connecting electrode 11. The thickness of the first conductive layer 20 is 1 to 5 μm thicker than that of the first buffer layer 51. Similarly, the thickness of the second conductive layer 30 is 1 to 5 μm thicker than that of the second buffer layer 52.
[0093] The auxiliary film layer can be a molybdenum (Mo) or nickel (Ni) alloy layer with a thickness of about 20 to 200 nm, and the conductive film layer can be a copper (Cu) layer with a thickness of about 100 to 1000 nm. The auxiliary film layer is provided to enhance the adhesion of the conductive film layer.
[0094] S35 , processing the first conductive layer 20 and the second conductive layer 30 respectively to form a pattern including the first conductive structure 21 .
[0095] In some examples, step S35 specifically includes removing, by chemical mechanical polishing (CMP), a portion of the first conductive layer 20 located on a surface of the first buffer layer 51 facing away from the dielectric substrate 10, and planarizing a portion of the first conductive layer 20 located in the first hollow pattern 511 facing away from the dielectric substrate 10, thereby forming the first conductive structure 21. Similarly, by chemical mechanical polishing (CMP), a portion of the second conductive layer 30 located on a surface of the second buffer layer 52 facing away from the dielectric substrate 10 is removed, and planarizing a portion of the second conductive layer 30 located in the second hollow pattern 521 facing away from the dielectric substrate 10, thereby forming the second conductive structure 31.
[0096] In some examples, the first conductive structure 21 formed in step S35 faces away from the surface of the dielectric substrate 10 and is flush with the surface of the first buffer layer 51 facing away from the dielectric substrate 10 , and the second conductive structure 31 faces away from the surface of the dielectric substrate 10 and is flush with the surface of the second buffer layer 52 facing away from the dielectric substrate 10 .
[0097] In some examples, the auxiliary film layer in the first conductive structure 21 contacts the sidewalls of the first hollow pattern 511, and the auxiliary film layer in the second conductive structure 31 contacts the sidewalls of the second hollow pattern 521. In this case, the first conductive structure 21 and the second conductive structure 31 are more firmly bonded to the dielectric substrate 10.
[0098] S36 , forming a first protective layer 41 on a side of the first conductive structure 21 facing away from the dielectric substrate 10 .
[0099] In some examples, step S14 can specifically utilize a standard process such as PECVD to deposit and form a first protective layer 41, which is then cured. The first protective layer 41 is used to prevent water and oxygen from corroding the devices formed on the first surface of the dielectric substrate 10. The thickness of the first protective layer 41 is between 2 and 8 μm. The material of the first protective layer 41 can be polyimide (PI), for example.
[0100] In some examples, the first conductive structure 21 and the second conductive structure 31 on the integrated substrate are electrically connected via the first connecting electrode 11 to form an inductor coil structure. In some examples, a portion of the first conductive structure 21 can also function as the first plate of a capacitor. The integrated substrate fabrication method may further include forming an interlayer dielectric layer, a second plate of a capacitor, and other structures on the side of the layer containing the second conductive structure 31 facing away from the dielectric substrate 10, which are not further described here.
[0101] It should be noted that, as shown in FIG4 , FIG4 is a schematic diagram of the structure of the seed layer of an embodiment of the present disclosure. The first seed layer, the second seed layer, and the third seed layer mentioned in the first and second examples can all have the same structure as the seed layer in the third example, that is, they are all composed of an auxiliary film layer 102 and a conductive film layer 101. During the electroplating process, the thickness of the auxiliary film layer 102 generally does not change, and the thickness of the conductive film layer 101 will mainly increase.
[0102] Compared to the second example, in the integrated substrate formed by the third example method for preparing an integrated substrate, the auxiliary film layer in the first conductive structure 21 contacts the sidewalls of the first hollow pattern 511, and the auxiliary film layer in the second conductive structure 31 contacts the sidewalls of the second hollow pattern 521. This ensures a more secure bond between the first and second conductive structures 21, 31 and the dielectric substrate 10. In the third example method, the first and second buffer layers 51, 52 define the subsequently formed first and second conductive structures 21, 31, eliminating the need for photoresist layer alignment, making this method easier to implement.
[0103] Compared to the first example, in the integrated substrate formed by the integrated substrate manufacturing method of the third example, the auxiliary film layer in the first conductive structure 21 contacts the sidewalls of the first hollow pattern 511, and the auxiliary film layer in the second conductive structure 31 contacts the sidewalls of the second hollow pattern 521. In this case, the first conductive structure 21 and the second conductive structure 31 are more firmly bonded to the dielectric substrate 10. The manufacturing method of the third example has a relatively simple process flow.
[0104] Figure 5 is a schematic structural diagram of an integrated substrate according to an embodiment of the present disclosure. As shown in Figure 5 , the present disclosure also provides an integrated substrate, which can be prepared using any of the aforementioned methods. Preferably, the integrated substrate is prepared using the third exemplary preparation method described above. Specifically, the integrated substrate includes a dielectric substrate 10, a first buffer layer 51, a second buffer layer 52, a first conductive structure 21, a second conductive structure 31, and a first connection electrode 11.
[0105] The dielectric substrate 10 has a first surface and a second surface oppositely disposed along its thickness direction; the dielectric substrate 10 includes a first connection via 101 extending through its thickness direction; a first buffer layer 51 is disposed on the first surface side, the first buffer layer 51 having a first hollow pattern 511; a second buffer layer 52 is disposed on the second surface side, the second buffer layer 52 having a second hollow pattern 521; a first conductive structure 21 is located in the first hollow pattern 511; a second conductive structure 31 is located in the second hollow pattern 521; a first connection electrode 11 is located within the first connection via 101, and the first conductive structure 21 and the second conductive structure 31 are connected via the first connection electrode 11, forming an integrated structure.
[0106] In some examples, a first protective layer 41 is provided on the side of the first conductive structure 21 facing away from the dielectric substrate 10. The first protective layer 41 is used to prevent water and oxygen from corroding devices formed on the first surface of the dielectric substrate 10. The thickness of the first protective layer 41 ranges from 2 to 8 μm. The material of the first protective layer 41 can be polyimide (PI), for example.
[0107] In some examples, the first conductive structure 21 and the second conductive structure 31 on the integrated substrate are electrically connected via the first connecting electrode 11 to form an inductor coil structure. In some examples, a portion of the first conductive structure 21 can also function as the first plate of a capacitor. The integrated substrate may also include an interlayer dielectric layer and a second plate of a capacitor formed on the side of the layer containing the second conductive structure 31 facing away from the dielectric substrate 10, and other structures, which are not described here.
[0108] An embodiment of the present disclosure further provides an electronic device, which may include the above-mentioned integrated substrate.
[0109] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. An integrated substrate, include: A dielectric substrate having a first surface and a second surface arranged opposite to each other along a thickness direction thereof; the dielectric substrate comprising a first connecting via hole penetrating along the thickness direction thereof; A first buffer layer, disposed on the first surface side, the first buffer layer having a first hollow pattern; A second buffer layer, disposed on the second surface side, the second buffer layer having a second hollow pattern; A first conductive structure, located in the first hollow pattern; A second conductive structure, located in the second hollow pattern; The first connecting electrode is located in the first connecting via hole. The first conductive structure and the second conductive structure are connected via the first connecting electrode, and the three are an integrated structure.
2. The integrated substrate according to claim 1, in, The invention also includes a first protective layer arranged on a side of the first conductive structure away from the dielectric substrate.
3. The integrated substrate according to claim 1, in, The first connection electrode fills the first connection via hole.
4. The integrated substrate according to claim 1, in, The first conductive structure and the second conductive structure are electrically connected via the first connecting electrode to form an inductor coil structure.
5. A method for preparing an integrated substrate, include: A dielectric substrate is provided, which has a first surface and a second surface arranged opposite to each other along the thickness direction thereof; the dielectric substrate includes a first connecting via hole penetrating along the thickness direction thereof; On the first surface, a pattern including a first buffer layer is formed by a patterning process, wherein a first hollow pattern of the first buffer layer is the same as a pattern of a first conductive structure to be formed; On the second surface, forming a pattern including a second buffer layer by a patterning process, wherein a second hollow pattern of the second buffer layer is the same as a pattern of a second conductive structure to be formed; The first buffer layer is disposed on a side away from the first surface and the second buffer layer is disposed on a side away from the first surface. A seed layer is formed on one side of the second surface, and the seed layer is electroplated to form a first conductive layer located on the first surface side, a second conductive layer located on the second surface side, and a first connecting electrode located on the first connecting via hole; performing patterning on the first conductive layer to form a pattern including the first conductive structure; The second conductive layer is patterned to form a pattern including the second conductive structure, and the second conductive structure is connected to the first conductive structure through the first connecting electrode to form an integrated structure.
6. The method for preparing the integrated substrate according to claim 5, in, The step of patterning the first conductive layer to form a pattern including the first conductive structure includes: The first conductive structure is formed by removing a portion of the first conductive layer located on a surface of the first buffer layer away from the dielectric substrate by chemical mechanical polishing, and planarizing a surface of a portion of the first conductive layer located in the first hollow pattern away from the dielectric substrate.
7. The method for preparing an integrated substrate according to claim 5, in, The step of patterning the second conductive layer to form a pattern including the second conductive structure includes: The second conductive structure is formed by removing a portion of the second conductive layer located on a surface of the second buffer layer away from the dielectric substrate by chemical mechanical polishing, and planarizing a surface of a portion of the second conductive layer located in the second hollow pattern away from the dielectric substrate.
8. The method for preparing an integrated substrate according to claim 5, in, The thickness of the first conductive layer is 1 to 5 μm thicker than that of the first buffer layer; and / or the thickness of the second conductive layer is 1 to 5 μm thicker than that of the second buffer layer.
9. The method for preparing an integrated substrate according to claim 5, in, The seed layer includes an auxiliary film layer and a conductive film layer which are stacked, and the auxiliary film layer is configured to increase the adhesion between the conductive film layer and the dielectric substrate; The auxiliary film layer in the first conductive structure contacts the side wall of the first hollow pattern, and the auxiliary film layer in the second conductive structure contacts the side wall of the second hollow pattern.
10. The method for preparing an integrated substrate according to claim 5, in, The surface of the first buffer layer facing away from the dielectric substrate is flush with the surface of the first conductive structure facing away from the dielectric substrate; The second buffer layer is away from a surface of the dielectric substrate and is flush with a surface of the second conductive structure away from the dielectric substrate.
11. The method for preparing an integrated substrate according to claim 5, in, Also includes: A first protective layer is formed on a side of the first conductive structure facing away from the dielectric substrate.
12. The method for preparing an integrated substrate according to claim 5, in, The first connection electrode fills the first connection via hole.
13. The method for preparing an integrated substrate according to claim 5, in, The first buffer layer is made of an organic dielectric material; and / or the second buffer layer is made of an organic dielectric material.
14. The method for preparing an integrated substrate according to claim 5, in, The first conductive structure and the second conductive structure are electrically connected via the first connecting electrode to form an inductor coil structure.
15. An electronic device comprising the integrated substrate according to any one of claims 1 to 4.