Three-dimensional memory device including memory openings arranged in non-equilateral triangle layout and method of manufacturing same

Abstract

A memory device includes: an alternating stack of insulating layers and conductive layers; memory openings extending vertically through the alternating stack, the smallest cell shape of three nearest neighbor memory openings being a non-equilateral triangle; and memory opening filling structures in the memory opening, where each of the memory opening filling structures includes a vertical semiconductor channel and a vertical stack of memory elements.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Non - Provisional Application No. 18 / 362,706, filed on July 31, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE CONTAINING MEMORY OPENINGS ARRANGED IN NON - EQUILATERAL TRIANGULAR LAYOUT AND METHOD OF MAKING THEREOF", which claims priority to U.S. Provisional Application No. 63 / 493,149, filed on March 20, 2023, and the entire contents of which are hereby incorporated by reference in their entirety for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices containing memory openings arranged in a non - equilateral triangular layout and methods of manufacturing the same. Background Art

[0004] A three - dimensional vertical NAND string with one bit per cell is disclosed in the article by T. Endoh et al., entitled "Novel Ultra High - Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell" (Proceedings of the International Electron Devices Meeting (IEDM) (2001) 33 - 36). Summary of the Invention

[0005] According to one aspect of the present disclosure, a memory device includes: an alternating stack of insulating layers and conductive layers; memory openings that vertically extend through the alternating stack, wherein a minimum unit shape of three nearest - neighbor memory openings is a non - equilateral triangle; and memory - opening fill structures located in the memory openings, wherein each memory - opening fill structure in the memory - opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.

[0006] According to another aspect of the present disclosure, a memory device includes: an alternating stack of insulating layers and conductive layers; memory openings that vertically extend through the alternating stack, wherein each of the memory openings has a corresponding elongated horizontal cross-sectional shape having a corresponding major axis and a corresponding minor axis, and the major axis of the memory opening extends in a direction of a nearest neighbor memory opening; and memory opening fill structures located within the memory openings, wherein each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.

[0007] According to yet another aspect of the present disclosure, a method of forming a memory device includes: forming an alternating stack of insulating layers and a sacrificial material layer on a substrate; forming memory openings that vertically extend through the alternating stack, wherein a minimum unit shape of three nearest neighbor memory openings is a non-equilateral triangle; forming memory opening fill structures located within the memory openings, wherein each of the memory opening fill structures includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; removing the sacrificial material layer between the memory opening fill structures to form a laterally extending cavity; and forming a conductive layer within the laterally extending cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure after forming an optional semiconductor device, an optional lower-level metal interconnect structure, a semiconductor material layer, and an alternating stack of insulating layers and a sacrificial material layer, according to an embodiment of the present disclosure.

[0009] Figure 2 is a schematic vertical cross-sectional view of an exemplary structure after forming a stepped mesa and an inverse stepped dielectric material portion, according to an embodiment of the present disclosure.

[0010] Figure 3A is a schematic vertical cross-sectional view of an exemplary structure after forming memory openings and support openings, according to an embodiment of the present disclosure.

[0011] Figure 3B is Figure 3A a top-down view of an exemplary structure. The vertical plane A-A' is Figure 3A the plane of the cross-section of

[0012] Figures 4A to 4I is Figure 3A and Figure 3B an enlarged top-down view of various configurations of a portion of a memory array region after processing steps of

[0013] Figure 5 A vertical cross-sectional view of an exemplary structure after forming a support pillar structure, according to an embodiment of the present disclosure.

[0014] Figures 6A to 6D A sequential schematic vertical cross-sectional view of a memory opening within an exemplary structure during formation of a memory opening fill structure, according to an embodiment of the present disclosure.

[0015] Figure 7 A schematic vertical cross-sectional view of an exemplary structure after forming a memory opening fill structure and a support pillar structure, according to an embodiment of the present disclosure.

[0016] Figure 8A A schematic vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric layer, a lateral isolation trench, and a source region, according to an embodiment of the present disclosure.

[0017] Figure 8B is Figure 8A A partial perspective top-down view of the exemplary structure. The vertical plane A-A' is the Figure 8A plane of the schematic vertical cross-sectional view.

[0018] Figure 9 A vertical cross-sectional view of an exemplary structure after forming a source-level cavity, according to an embodiment of the present disclosure.

[0019] Figure 10 A vertical cross-sectional view of an exemplary structure after forming a source contact layer, according to an embodiment of the present disclosure.

[0020] Figure 11 A vertical cross-sectional view of an exemplary structure after forming a laterally extending cavity, according to an embodiment of the present disclosure.

[0021] Figure 12 A vertical cross-sectional view of an exemplary structure after forming a conductive layer, according to an embodiment of the present disclosure.

[0022] Figure 13A A vertical cross-sectional view of an exemplary structure after forming a lateral isolation trench fill structure and a contact via structure, according to an embodiment of the present disclosure.

[0023] Figure 13B is Figure 13A A top-down view of the exemplary structure. The vertical plane A-A' is the Figure 13A cutting plane of the vertical cross-sectional view.

[0024] Figure 14A A vertical cross-sectional view of an exemplary structure after forming a connection via structure and a bit-line level metal wire, according to an embodiment of the present disclosure.

[0025] Figure 14B is Figure 14A a top - down view of an exemplary structure. The vertical plane A - A' is Figure 14A the cutting plane of a vertical cross - sectional view of

[0026] Figure 15 a vertical cross - sectional view of an exemplary structure after forming a memory die including a memory - side dielectric material layer and a memory - side metal interconnect structure according to an embodiment of the present disclosure.

[0027] Figure 16 a vertical cross - sectional view of a logic die according to an embodiment of the present disclosure.

[0028] Figure 17 a vertical cross - sectional view of an exemplary structure after attaching a logic die to a memory die according to an embodiment of the present disclosure.

[0029] Figure 18 a vertical cross - sectional view of an exemplary structure after removing a carrier substrate according to an embodiment of the present disclosure. Detailed Description

[0030] As discussed above, embodiments of the present disclosure relate to a three - dimensional memory device and a method of manufacturing the same. The three - dimensional memory device includes memory openings arranged in a non - equilateral triangular layout to facilitate lateral diffusion of reactants during the formation of replacement word lines. Various aspects of the three - dimensional memory device and the method of manufacturing the same are described below. In one embodiment, the memory openings may be elongated along the nearest - neighbor distance.

[0031] The figures are not drawn to scale. In cases where a single instance of an element is illustrated, multiple instances of the element may be repeated unless otherwise explicitly described or clearly indicated as not existing. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0032] Like reference numerals denote like or similar elements. Unless otherwise specified, elements with the same reference numeral are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or do not contact each other directly among themselves, the two elements are "separated" from each other or "separated" from each other among themselves. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element "is directly located on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element "is electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a temporary structure in which the shape or composition of at least one component is subsequently changed.

[0033] As used herein, a "layer" refers to a portion of a material including a region having a certain thickness. The layer may extend over the entire underlying structure or overlying structure, or may have a scope smaller than the scope of the underlying structure or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers on, above, and / or below it.

[0034] Generally speaking, a semiconductor die or a semiconductor package may include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two planes). The same, concurrent operations may occur on each plane, although there are some limitations. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a plurality of pages, which are the smallest units that can be programmed, i.e., the smallest units on which a read operation can be performed.

[0035] Reference Figure 1 , illustrates an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 9, which may be a semiconductor substrate or a conductive substrate. For example, the substrate 9 may include a commercially available silicon wafer. Alternatively, the substrate 9 may include a carrier substrate 9 formed of any material that can selectively remove the insulating layer 32 and a portion of the dielectric material to be formed subsequently.

[0036] An optional insulating material layer may be formed on the top surface of the carrier substrate 9. The insulating material layer may then be used as an etch stop material layer in the process of removing the carrier substrate 9, and is referred to herein as the etch stop insulating layer 106, or the backside liner dielectric layer. If a polishing process such as a chemical mechanical polishing process is used to subsequently remove the carrier substrate 9, the etch stop material layer 106 may then be used as a polishing stop material layer. If an etching process such as a wet etching process is used to subsequently remove the carrier substrate 9, the etch stop material layer 106 may then be used as an etch stop material layer. In one embodiment, the etch stop insulating layer 106 includes a dielectric material such as undoped silicate glass, doped silicate glass, or silicon nitride. The thickness of the etch stop insulating layer 106 may range from 50 nm to 600 nm, such as from 100 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0037] An optional in-process source level material layer 110' may be formed on the etch stop insulating layer 106. The in-process source level material layer 110' may include various layers that are subsequently modified to form the source level material layer. When formed, the source level material layer includes a source contact layer that serves as a common source region for the vertical field effect transistors of the three-dimensional memory device. In one embodiment, the in-process source level material layer 110' may include, from bottom to top, a lower source level semiconductor layer 112, an optional lower sacrificial liner 103, a source level sacrificial layer 104, an optional upper sacrificial liner 105, and an upper source level semiconductor layer 116.

[0038] The lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon. The conduction type of the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conduction type, the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 have a doping of a second conduction type opposite to the first conduction type. The thickness of each of the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may range from 10 nm to 300 nm, such as from 20 nm to 150 nm, but smaller and larger thicknesses may also be used.

[0039] The source - side sacrificial layer 104 includes a sacrificial material that can be selectively removed relative to the lower sacrificial liner 103 (or relative to the lower source - side semiconductor layer 112) and the upper sacrificial liner 105 (or relative to the upper source - side semiconductor layer 116). In one embodiment, the source - side sacrificial layer 104 may include a semiconductor material, such as undoped amorphous silicon or a silicon - germanium alloy with a germanium atom concentration greater than 20%. The thickness of the source - side sacrificial layer 104 may range from 30 nm to 400 nm, such as from 60 nm to 200 nm, although smaller and larger thicknesses may also be used. The lower sacrificial liner 103 (if present) and the upper sacrificial liner 105 (if present) include materials that can be used as etch - stop materials during the removal of the source - side sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 may include silicon oxide, silicon nitride, and / or dielectric metal oxides. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 may contain a silicon oxide layer having a thickness in the range from 2 nm to 30 nm, although smaller and larger thicknesses may also be used.

[0040] An alternating stack of a first material layer and a second material layer may be formed on the in - process source - side material layer 110'. The first material layer may be an insulating layer, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42 may be formed on the in - process source - side material layer 110'. The insulating layer 32 includes an insulating material such as undoped silicate glass or doped silicate glass, and the sacrificial material layer 42 includes a sacrificial material such as silicon nitride or a silicon - germanium alloy. In one embodiment, the insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer, and the sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer. The alternating stack (32, 42) may include multiple repetitions of a unit - layer stack including the insulating layer 32 and the sacrificial material layer 42. The total number of repetitions of the unit - layer stack within the alternating stack (32, 42) may be, for example, in the range from 8 to 1,024, such as from 32 to 256, although smaller and larger numbers of repetitions may also be employed. Hereinafter, the top - most insulating layer among the insulating layers 32 is referred to as the top - most insulating layer 32T. The bottom - most insulating layer among the insulating layers 32 is the insulating layer 32 closest to the carrier substrate 9, which is referred to herein as the bottom - most insulating layer 32B.

[0041] Each of the insulating layers 32 other than the topmost insulating layer 32 may have a thickness in the range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although smaller and larger thicknesses may also be employed. Each of the sacrificial material layers 42 in the sacrificial material layer may have a thickness in the range from 20 nm to 100 nm, such as from 30 nm to 60 nm, but smaller and larger thicknesses may also be employed. In one embodiment, the topmost insulating layer 32 may have a thickness that is about half the thickness of the other insulating layers 32.

[0042] Exemplary structures include a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will be subsequently formed in the memory array region, and a layer contact via structure for contacting a contact word line will be subsequently formed in the contact region.

[0043] Although embodiments are described in which the spacer material layer is formed as the sacrificial material layer 42, in an alternative embodiment, the spacer material layer may be formed as a conductive layer. Generally speaking, the spacer material layer of the present disclosure may be formed as a conductive layer or may subsequently be at least partially replaced with a conductive layer.

[0044] In an alternative embodiment, a drive circuit semiconductor device (e.g., a transistor) may be formed above or below the substrate 9 adjacent to the alternating stack (32, 42). In yet another alternative embodiment, in the case where the substrate 9 is a carrier substrate to be removed later and a top source contact layer is formed on the exposed surface of the memory device, the in-process source level material layer 110' may be omitted.

[0045] Reference Figure 2 , an optional stepped surface is formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and a portion of the alternating stack (32, 42) is removed from the stepped cavity by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0046] The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the source electrode layer 110' in the process. In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process. The first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally expands the area vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including a plurality of alternating ones is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0047] Each sacrificial material layer 42 within the alternating stack (32, 42) except the topmost sacrificial material layer 42 extends further laterally than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the mesa region. The stepped surface of the alternating stack (32, 42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stack (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stack (32, 42).

[0048] An inverse-stepped dielectric material portion 65 (i.e., an insulating fill material portion) may be formed in the stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. The excess portion of the deposited dielectric material may be removed, for example, by chemical mechanical planarization (CMP) above the top surface of the topmost insulating layer 32T. The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the inverse-stepped dielectric material portion 65. As used herein, an "inverse-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the inverse-stepped dielectric material portion 65, the silicon oxide of the inverse-stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0049] Optionally, a drain select level isolation structure (not shown) may be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 at the drain select level. For example, the drain select level isolation structure may be formed by forming a drain select level lateral isolation trench and filling the drain select level lateral isolation trench with a dielectric material such as silicon oxide. The excess portion of the dielectric material may be removed above the top surface of the topmost insulating layer 32T.

[0050] Reference Figure 3A and Figure 3B, An etch mask layer (not shown) may be formed on the alternating stack (32, 42) and may be lithographically patterned to form various openings therein. An anisotropic etch process may be performed to transfer the pattern of the openings in the etch mask layer through the alternating stack (32, 42). Various openings may be formed through the alternating stack (32, 42). The various openings may include a memory opening 49 formed in the memory array region 100 and a support opening 19 formed in the contact region 300. Each of the memory opening 49 and the support opening 19 may vertically extend through the alternating stack (32, 42) and into the in-process source level material layer 110'. In one embodiment, the bottom surfaces of the memory opening 49 and the support opening 19 may be formed within the lower source level semiconductor layer 112 or at the interface between the lower source level semiconductor layer and the blocking insulating layer 106.

[0051] The support opening 19 may have a diameter in the range from 60 nm to 400 nm, such as from 120 nm to 300 nm, but smaller and larger thicknesses may be employed. The memory opening 49 may have a diameter in the range from 60 nm to 400 nm, such as from 120 nm to 300 nm, but smaller and larger thicknesses may be employed.

[0052] In one embodiment, the memory array region 100 may be laterally spaced from the contact region 300 along a first horizontal direction hd1. The memory opening 49 may include rows of memory openings 49 arranged along the first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2. A plurality of clusters of memory openings 49 may be formed in the memory array region 100, each cluster of memory openings including a corresponding two-dimensional periodic array of the memory openings 49. The clusters of memory openings 49 may be laterally spaced apart along the second horizontal direction hd2.

[0053] Figures 4A to 4I is a magnified top-down view of various configurations of a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B

[0054] Referring to Figure 4A , there is shown a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B according to a first embodiment. In the first embodiment, each memory opening 49 within the plurality of rows of memory openings 49 has a corresponding circular horizontal cross-sectional shape. As used herein, "circular" includes an exact circular shape or a shape slightly deviated from a circular shape due to lithography and etch biases.

[0055] The minimum cell shape of the three nearest neighbor memory openings 49 is a non-equilateral triangle. In one embodiment, the non-equilateral triangle includes a scalene triangle having three sides A, B, and C that are not equal to each other (i.e., A ≠ B ≠ C) and three angles θ1, θ2, and θ3 that are not equal to each other (i.e., θ1 ≠ θ2 ≠ θ3). The vertices of the scalene triangle are located at the geometric centers of the three memory openings 49 in the horizontal plane. In this configuration of the memory openings, there is a direction that provides a greater average lateral distance between adjacent pairs of memory openings 49. This horizontal direction is labeled the "direction of easy lateral diffusion" and provides a wider diffusion path during subsequent processing steps for isotropically etching the sacrificial material layer 42 to form a laterally extending cavity and conformally depositing at least one conductive material to form a conductive layer. Thus, the direction of easy lateral diffusion includes a first diffusion path disposed in the laterally extending cavity between a first set of memory openings 49 that is wider than a second diffusion path disposed in the laterally extending cavity between a second set of memory openings. Accordingly, improved conductive layer filling can be achieved. If fluorine is used to deposit the conductive layer (e.g., if WF6 is used to deposit a tungsten conductive layer), such paths also provide enhanced outward diffusion paths for fluorine. Thus, less fluorine is trapped in the device, which improves device reliability because trapped fluorine can damage various device layers due to solid-state diffusion between device layers.

[0056] Reference Figure 4B , shows a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B according to a second embodiment. In the second embodiment, the memory openings 49 are arranged in a zigzag configuration. The minimum cell shape of the three nearest neighbor memory openings 49 remains a non-equilateral triangle, such as a scalene triangle. However, in this configuration, the direction of easy lateral diffusion (DELD) is the zigzag horizontal direction.

[0057] Reference Figure 4C , shows a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B according to a third embodiment. In the third embodiment, the memory openings 49 have a non-circular horizontal cross-sectional shape. For example, the memory openings can have an elliptical horizontal cross-sectional shape having a major axis and a minor axis. The major axis extends along the direction of the nearest neighbor memory openings (such as the DELD direction). The minimum cell shape of the three nearest neighbor memory openings 49 remains a non-equilateral triangle, such as a scalene triangle.

[0058] Reference Figure 4D , shows a portion of the memory array region 100 after the processing steps of Figure 3A andFigure 3B A portion of the memory array region 100 after the processing steps. In a fourth embodiment, the memory opening 49 has a non-circular horizontal cross-sectional shape such as an ellipse. The minimum unit shape of three nearest neighbor memory openings 49 is an equilateral triangle, with all three sides "A" equal to each other and all three angles equal to 60 degrees. Thus, in this configuration, the memory openings 49 are arranged in a hexagonal close-packed grid.

[0059] Figures 4E to 4I Illustrates additional geometric features of the layout of the memory openings 49 in various embodiments of the present disclosure.

[0060] Reference Figure 4E , shows a first configuration of a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B In the first configuration, each memory opening 49 within the plurality of rows of memory openings 49 has a corresponding circular horizontal cross-sectional shape.

[0061] According to one aspect of the present disclosure, the alternating stacks (32, 42) of memory openings 49 that can pass through each cluster form a plurality of rows of memory openings 49. Each row in the plurality of rows includes a corresponding one-dimensional periodic array of memory openings 49 having a uniform pitch p along a first horizontal direction hd1. The plurality of rows are laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0062] When numbering the memory openings 49 in the plurality of rows of memory openings 49 in any cluster in integer order starting from 1 along the second horizontal direction hd2, the memory openings 49 in the plurality of rows include odd rows and even rows. For each memory opening 49, a corresponding geometric center can be defined as the centroid of a hypothetical object having the same volume as the memory opening 49 (i.e., occupying the same space) and having a uniform density everywhere. In addition, for each memory opening 49, a corresponding vertical axis passing through the geometric center can be defined. Each vertical axis passing through the geometric center of the corresponding memory opening 49 is perpendicular to the top surface of the carrier substrate 9 and / or the bottommost surface of the alternating stack (32, 42).

[0063] In the illustrated example, five rows of memory openings 49 are illustrated, which include the (i - 2)th row (labeled "R_i-2"), the (i - 1)th row (labeled "R_i-1"), the ith row (labeled "R_i"), the (i + 1)th row (labeled "R_i+1"), and the (i + 2)th row (labeled "R_i+2"). If R is odd, the (i - 2)th row, the ith row, and the (i + 2)th row are odd rows, and the (i - 1)th row and the (i + 1)th row are even rows. In one embodiment, the center-to-center distance between the memory openings 49 of adjacent rows can be √3 / 2 times the uniform pitch p. In another embodiment, the center-to-center distance between the memory openings 49 of adjacent rows can be different from √3 / 2 times the uniform pitch p, and can be in the range from 0.85 times √3 / 2 times the uniform pitch p to 1.15 times √3 / 2 times the uniform pitch p, and / or in the range from 0.90 times √3 / 2 times the uniform pitch p to 1.10 times √3 / 2 times the uniform pitch p, and / or in the range from 0.95 times √3 / 2 times the uniform pitch p to 1.05 times √3 / 2 times the uniform pitch p.

[0064] Generally, the pattern of the memory openings 49 can have three periodic repetition directions. The first periodic repetition direction DPR_1 can be the first horizontal direction hd1, and the pattern of the memory openings 49 can repeat along the first periodic repetition direction DPR_1 with a uniform pitch p, which is the center-to-center distance between the geometric centers of an adjacent pair of memory openings 49 within any row of the memory openings 49. The second periodic repetition direction DPR_2 can be rotated by an angle π / 3–α from the first periodic repetition direction DPR_1 along the first rotation direction (which can be counterclockwise or clockwise), and this angle is less than π / 3. The pattern of the memory openings 49 can repeat every other row along the second periodic repetition direction DPR_2. The third periodic repetition direction DPR_3 can be rotated by an angle π / 3+β from the opposite direction of the first periodic repetition direction DPR_1 along the second rotation direction (which is the opposite direction of the first rotation direction), and this angle is greater than π / 3. The pattern of the memory openings 49 can repeat every other row along the third periodic repetition direction DPR_3.

[0065] According to one aspect of the present disclosure, for each first vertical axis VA1 passing through the geometric center of the corresponding memory opening 49 in any odd row, a second vertical axis VA2 passing through the geometric center of the nearest memory opening 49 within the nearest odd row is laterally offset from the first vertical axis VA1 by a first lateral offset distance Δ in a first horizontal direction hd1, and the first lateral offset distance is greater than 0 and less than half of the uniform pitch p. In one embodiment, the first lateral offset distance Δ may be greater than 0.01 times the uniform pitch p, and / or may be in the range of 0.02 times the uniform pitch p, and / or may be in the range of 0.03 times the uniform pitch p, and / or may be in the range of 0.05 times the uniform pitch p, and / or may be in the range of 0.10 times the uniform pitch p, and / or may be in the range of 0.15 times the uniform pitch p, and / or may be in the range of 0.20 times the uniform pitch p, and / or may be in the range of 0.25 times the uniform pitch p, and / or may be in the range of 0.30 times the uniform pitch p, and / or may be in the range of 0.35 times the uniform pitch p, and / or may be in the range of 0.40 times the uniform pitch p. Additionally, the first lateral offset distance Δ may be less than 0.49 times the uniform pitch p, and / or may be in the range of 0.48 times the uniform pitch p, and / or may be in the range of 0.47 times the uniform pitch p, and / or may be in the range of 0.45 times the uniform pitch p, and / or may be in the range of 0.40 times the uniform pitch p, and / or may be in the range of 0.35 times the uniform pitch p, and / or may be in the range of 0.30 times the uniform pitch p, and / or may be in the range of 0.25 times the uniform pitch p, and / or may be in the range of 0.20 times the uniform pitch p, and / or may be in the range of 0.15 times the uniform pitch p, and / or may be in the range of 0.10 times the uniform pitch p.

[0066] In one embodiment, for each first vertical axis VA1 passing through the geometric center of the corresponding memory opening 49 in any odd row, a third vertical axis VA3 passing through the geometric center of the nearest memory opening 49 within the nearest even row is laterally offset from the first vertical axis VA1 by a second lateral offset distance (p - Δ) / 2 - η in a first horizontal direction hd1, and the second lateral offset distance is greater than 0 and less than (p - Δ) / 2. In this case, the periodicity of the pattern of the memory openings 49 along a second horizontal direction hd2 is greater than the center-to-center distance between adjacent row pairs, and may be twice the center-to-center distance between adjacent row pairs.

[0067] In one embodiment, the difference between (p - Δ) / 2 and the second lateral offset distance (p - Δ) / 2 - η is the lateral shift distance η, which is greater than 0 and less than Δ / 2. In one embodiment, the lateral shift distance η can be greater than 0.05 times Δ / 2, and / or can be greater than 0.1 times Δ / 2, and / or can be greater than 0.2 times Δ / 2, and / or can be greater than 0.3 times Δ / 2, can be greater than 0.4 times Δ / 2, and / or can be greater than 0.5 times Δ / 2, can be greater than 0.6 times Δ / 2, and / or can be greater than 0.7 times Δ / 2, can be greater than 0.8 times Δ / 2, and / or can be greater than 0.9 times Δ / 2. Additionally, the lateral shift distance η can be less than 0.95 times Δ / 2, and / or can be less than 0.9 times Δ / 2, and / or can be less than 0.8 times Δ / 2, and / or can be less than 0.7 times Δ / 2, can be less than 0.6 times Δ / 2, and / or can be less than 0.5 times Δ / 2, can be less than 0.4 times Δ / 2, and / or can be less than 0.3 times Δ / 2, can be less than 0.2 times Δ / 2, and / or can be less than 0.1 times Δ / 2.

[0068] In one embodiment, for each first vertical axis VA1 passing through the geometric center of the corresponding memory opening 49 in any odd row, the flat vertical plane passing through the first vertical axis VA1 and parallel to the second horizontal direction hd2 does not pass through the geometric center of any memory opening 49 within the memory openings 49 of any nearest neighbor row or within the memory openings 49 of any second nearest neighbor row.

[0069] In one embodiment, the first vertical plane VP1 passing through the geometric center of the memory opening 49 within the memory opening 49 of an odd row and passing through the geometric center of the memory opening 49 within the memory opening 49 of the nearest neighbor odd row is at a first angle (π / 3 - α) with respect to the first horizontal direction hd1. The first vertical plane VP1 can be parallel to the second periodic repetition direction DPR_2. The first angle (π / 3 - α) is less than π / 3 and greater than In the case where the center - to - center distance between the memory openings 49 of adjacent rows is √3 / 2 times the uniform pitch p, the lateral offset distance along the first horizontal direction between the geometric center of the memory opening 49 within the memory opening 49 of an odd row and the geometric center of the memory opening 49 within the memory opening 49 of the nearest neighbor odd row is greater than p and less than 1.5 times p. In the present disclosure, all angles are measured in radians.

[0070] In one embodiment, a second vertical plane VP2 passing through the geometric center of a memory opening 49 within an odd row of memory openings 49 and through the geometric center of another memory opening 49 within a memory opening 49 of the nearest neighbor odd row is at a second angle (π / 3 + β) relative to a first horizontal direction hd1. The second angle (π / 3 + β) is greater than π / 3 and less than The second vertical plane VP2 may be parallel to a third periodic repeat direction DPR_3.

[0071] In one embodiment, a third vertical plane VP3 passing through the geometric center of a memory opening 49 within an odd row of memory openings 49 and through the geometric center of a memory opening 49 of the nearest neighbor even row of memory openings 49 is at a third angle (π / 3 + γ) relative to the first horizontal direction hd1. The third angle (π / 3 + γ) is greater than the second angle (π / 3 + β).

[0072] A first configuration of the array of memory openings 49 provides a horizontal direction that provides a greater average lateral distance between adjacent pairs of memory openings 49. This horizontal direction is labeled the "direction of easy lateral diffusion" and provides a high diffusivity diffusion path during subsequent processing steps for isotropically etching a sacrificial material layer 42 to form laterally extending cavities and conformally depositing at least one conductive material to form a conductive layer. In the illustrated example, the "direction of easy lateral diffusion" may be parallel to the third periodic repeat direction DPR_3.

[0073] Reference Figure 4F , shows a second configuration of a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B . In the second configuration, each memory opening 49 within a plurality of rows of memory openings 49 has a corresponding circular horizontal cross-sectional shape. The second configuration of the memory openings 49 may be derived from the first configuration of the memory openings 49 illustrated in Figure 4A by setting the value of a parameter η equal to zero. Additionally, the value of the parameter γ may be the same as the value of β in the second configuration. In the second configuration, for each first vertical axis VA1 passing through the geometric center of a corresponding memory opening 49 within any odd row, a third vertical axis VA3 passing through the geometric center of the nearest memory opening 49 within the nearest even row is laterally offset from the first vertical axis VA1 along the first horizontal direction hd1 by a second lateral offset distance equal to p / 2.

[0074] In the second configuration, the pattern of the memory openings 49 may have three periodic repetition directions. The first periodic repetition direction DPR_1 may be a first horizontal direction hd1, and the pattern of the memory openings 49 may repeat along the first periodic repetition direction DPR_1 with a uniform pitch p, which is the center-to-center distance between a neighboring pair of memory openings 49 within any row of the memory openings 49. The second periodic repetition direction DPR_2 may be rotated from the first periodic repetition direction DPR_1 by an angle π / 3–α, which may be counterclockwise or clockwise, along a first rotation direction, the angle being less than π / 3. The pattern of the memory openings 49 may repeat along the second periodic repetition direction DPR_2 within each row. Thus, compared to the repetition distance in the first configuration, the repetition distance along the second periodic repetition direction DPR_2 is halved in the second configuration. The third periodic repetition direction DPR_3 may be rotated from the opposite direction of the first periodic repetition direction DPR_1 by an angle π / 3+β, which is the opposite direction of the first rotation direction, along a second rotation direction, the angle being greater than π / 3. The pattern of the memory openings 49 may repeat along the third periodic repetition direction DPR_3 within each row. Thus, compared to the repetition distance in the first configuration, the repetition distance along the third periodic repetition direction DPR_3 is halved in the second configuration.

[0075] The second configuration of the array of memory openings 49 provides a horizontal direction that provides a greater average lateral distance between neighboring pairs of memory openings 49. This horizontal direction is labeled the “direction of easy lateral diffusion” and provides a high-diffusion-rate diffusion path during subsequent processing steps for isotropically etching the sacrificial material layer 42 to form laterally extending cavities and conformally depositing at least one conductive material to form a conductive layer. In the illustrated example, the “direction of easy lateral diffusion” may be parallel to the third periodic repetition direction DPR_3.

[0076] Reference Figure 4G , shows a third configuration of a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B . In the third configuration, each memory opening 49 within the memory openings 49 of multiple rows has a corresponding non-circular horizontal cross-sectional shape, which may be an elliptical shape. In other words, the third configuration of the memory openings 49 may be derived from the first configuration of the memory openings 49 illustrated in Figure 4A by elongating each of the memory openings 49 along a horizontal direction in such a way as to produce a horizontal direction that provides a greater average lateral distance between neighboring pairs of memory openings 49.

[0077] In the illustrated example, the elongation direction of the memory opening 49 may be parallel to the reference Figure 4A “direction of easy lateral diffusion” being discussed. By selecting the elongation direction of the memory opening 49 to be parallel to the “direction of easy lateral diffusion”, a diffusion path parallel to the “direction of easy lateral diffusion” can provide a high diffusion rate diffusion path during subsequent processing steps for isotropically etching the sacrificial material layer 42 to form a laterally extending cavity and conformally depositing at least one conductive material to form a conductive layer. In the illustrated example, the “direction of easy lateral diffusion” may be parallel to the third periodic repeat direction DPR_3.

[0078] In a third configuration of the array of memory openings 49, multiple rows of memory openings 49 extend vertically through the alternating stacks (32, 42). Each row of the multiple rows includes a respective one-dimensional periodic array of memory openings 49 having a uniform pitch p along a first horizontal direction hd1. The multiple rows are laterally spaced from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each memory opening 49 within the multiple rows of memory openings 49 has a respective elongate horizontal cross-sectional shape having a major axis in a respective horizontal direction and a minor axis in a respective horizontal direction. As used herein, the major axis of a two-dimensional shape is the maximum lateral dimension of the two-dimensional shape, and the minor axis of a two-dimensional shape is the minimum lateral dimension of the two-dimensional shape. In the case where the two-dimensional shape is an ellipse, the major axis may be the same as the mathematical definition of the major axis of the ellipse, and the minor axis may be the same as the mathematical definition of the minor axis of the ellipse.

[0079] Each horizontal direction of the major axis of the memory openings 49 in the multiple rows of memory openings 49 may be parallel to each other and may be at a non-zero and non-orthogonal angle with respect to the first horizontal direction hd1. In one embodiment, the non-zero and non-orthogonal angle is greater than π / 3 and less than arctan(2√3). In one embodiment, the horizontal direction of the major axis of the memory opening 49 may be parallel to the third periodic repeat direction DPR3, or may be along an azimuthal direction deviated from the third periodic repeat direction DPR3 by an angle less than π / 6, and / or less than π / 12, and / or less than π / 24. The ellipticity e of the horizontal shape of each memory opening 49 is given by e = (1 – (b / a) 2 ) 1 / 2Definition, where a is the major axis and b is the minor axis, the ellipticity e can be greater than 0 and less than 0.6 (which corresponds to b / a of 0.8). In one embodiment, the ellipticity e can be greater than 0.001, and / or greater than 0.01, and / or greater than 0.03, and / or greater than 0.1, and / or greater than 0.2, and / or greater than 0.3, and / or greater than 0.4, and / or greater than 0.5. In addition, the ellipticity e can be less than 0.59, and / or less than 0.5, and / or less than 0.4, and / or less than 0.3, and / or less than 0.2, and / or less than 0.1, and / or less than 0.05, and / or less than 0.03.

[0080] In one embodiment, when numbering in integer order starting from 1 along the second horizontal direction hd2, the multiple rows include odd rows and even rows, and each pattern of the memory openings 49 in any odd row repeats periodically in every other odd row along the second horizontal direction hd2, where the periodicity is equal to the center-to-center distance between adjacent pairs of odd rows within the multiple rows. In one embodiment, for each first vertical axis VA1 passing through the geometric center of the corresponding memory opening 49 in any odd row, a second vertical axis VA2 passing through the geometric center of the nearest memory opening 49 in the nearest odd row is laterally offset from the first vertical axis VA1 by a first lateral offset distance Δ along the first horizontal direction hd1, and the first lateral offset distance is greater than 0 and less than half of the uniform pitch p.

[0081] Generally, the values of various parameters α, β, γ, Δ and η in the third configuration can be within the same range as the corresponding values of the various parameters in the first configuration.

[0082] Reference Figure 4H shows a fourth configuration of a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B . In the fourth configuration, each memory opening 49 within the memory openings 49 of the multiple rows has a corresponding elongated horizontal cross-sectional shape. The fourth configuration of the memory opening 49 can be derived from the third configuration of the memory opening 49 illustrated in Figure 4C by setting the value of the parameter η equal to zero. In addition, the value of the parameter γ can be the same as the value of β in the fourth configuration. In the fourth configuration, for each first vertical axis VA1 passing through the geometric center of the corresponding memory opening 49 in any odd row, a third vertical axis VA3 passing through the geometric center of the nearest memory opening 49 in the nearest even row is laterally offset from the first vertical axis VA1 by a second lateral offset distance along the first horizontal direction hd1, and the second lateral offset distance is equal to (p - Δ) / 2.

[0083] In the fourth configuration, the pattern of the memory openings 49 can have three periodic repetition directions. The first periodic repetition direction DPR_1 can be a first horizontal direction hd1, and the pattern of the memory openings 49 can repeat along the first periodic repetition direction DPR_1 with a uniform pitch p, which is the center-to-center distance between a neighboring pair of memory openings 49 within any row of the memory openings 49. The second periodic repetition direction DPR_2 can be rotated by an angle π / 3–α from the first periodic repetition direction DPR_1 along a first rotation direction (which can be counterclockwise or clockwise), and this angle is less than π / 3. The pattern of the memory openings 49 can repeat along the second periodic repetition direction DPR_2 in each row. Thus, compared with the repetition distance in the third configuration, the repetition distance along the second periodic repetition direction DPR_2 in the fourth configuration is halved. The third periodic repetition direction DPR_3 can be rotated by an angle π / 3+β from the opposite direction of the first periodic repetition direction DPR_1 along a second rotation direction (which is the opposite of the first rotation direction), and this angle is greater than π / 3. The pattern of the memory openings 49 can repeat along the third periodic repetition direction DPR_3 in each row. Thus, compared with the repetition distance in the third configuration, the repetition distance along the third periodic repetition direction DPR_3 in the fourth configuration is halved.

[0084] The fourth configuration of the array of memory openings 49 provides a horizontal direction that provides a greater average lateral distance between neighboring pairs of memory openings 49. This horizontal direction is labeled the “direction of easy lateral diffusion” and provides a high-diffusion-rate diffusion path during subsequent processing steps for isotropically etching the sacrificial material layer 42 to form laterally extending cavities and conformally depositing at least one conductive material to form a conductive layer. In the illustrated example, the “direction of easy lateral diffusion” can be parallel to the third periodic repetition direction DPR_3.

[0085] Reference Figure 4I , shows a fifth configuration of a portion of the memory array region 100 after the processing steps of Figure 3A and Figure 3B . In the fifth configuration, each memory opening 49 within the memory openings 49 of multiple rows has a corresponding elongated horizontal cross-sectional shape. The fifth configuration of the memory openings 49 can be obtained from Figure 4CDerivation of the fourth configuration of the memory opening 49 illustrated therein. Furthermore, the value of the parameter γ can be the same as the value of β in the fifth configuration. In the fifth configuration, for each first vertical axis VA1 passing through the geometric center of the corresponding memory opening 49 in any odd row, a fourth vertical axis VA3 passing through the geometric center of the nearest memory opening 49 within the nearest even row is laterally offset from the first vertical axis VA1 by a second lateral offset distance along the first horizontal direction hd1, and the second lateral offset distance is equal to p / 2.

[0086] In the fifth configuration, the pattern of the memory openings 49 can have three periodic repetition directions. The first periodic repetition direction DPR_1 can be the first horizontal direction hd1, and the pattern of the memory openings 49 can repeat along the first periodic repetition direction DPR_1 with a uniform pitch p, where the uniform pitch p is the center-to-center distance between the geometric centers of an adjacent pair of memory openings 49 within any row of the memory openings 49. The second periodic repetition direction DPR_2 can be rotated by an angle π / 3–α from the first periodic repetition direction DPR_1 along the first rotation direction (which can be counterclockwise or clockwise), and this angle is less than π / 3. The pattern of the memory openings 49 can repeat along the second periodic repetition direction DPR_2 in each row. Thus, compared with the repetition distance in the fourth configuration, the repetition distance along the second periodic repetition direction DPR_2 in the fifth configuration is halved. The fourth periodic repetition direction DPR_3 can be rotated by an angle π / 3+β from the opposite direction of the first periodic repetition direction DPR_1 along the second rotation direction (which is the opposite direction of the first rotation direction), and this angle is greater than π / 3. The pattern of the memory openings 49 can repeat along the fourth periodic repetition direction DPR_3 in each row. Thus, compared with the repetition distance in the fourth configuration, the repetition distance along the fourth periodic repetition direction DPR_3 in the fifth configuration is halved.

[0087] The fifth configuration of the array of memory openings 49 provides a horizontal direction that provides a greater average lateral distance between adjacent pairs of memory openings 49. This horizontal direction is labeled the "direction of easy lateral diffusion" and provides a high-diffusion-rate diffusion path during subsequent processing steps for isotropically etching the sacrificial material layer 42 to form a laterally extending cavity and conformally depositing at least one conductive material to form a conductive layer. In the illustrated example, the "direction of easy lateral diffusion" can be parallel to the fourth periodic repetition direction DPR_3.

[0088] In one embodiment, the geometric centers of the memory openings 49 in the fifth configuration of the memory array 49 can be located at the grid positions of a periodically closely packed hexagonal array.

[0089] Reference Figure 5, Optional etch stop liners (not shown) and sacrificial fill materials (not shown) may be deposited in the memory openings 49 and the support openings. Optional etch stop liners (if present) include a thin dielectric material layer that includes silicon oxide, silicon nitride, or dielectric metal oxide and has a thickness in the range from 1 nm to 6 nm. The sacrificial fill material may include a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or polycrystalline silicon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymer material. The excess portions of the sacrificial fill material may be removed from above the horizontal plane of the topmost layer of the alternating stack (32, 42) by a planarization process (such as an etch-back process). The remaining portions of the sacrificial fill material that fill the memory openings 49 and the support openings 19 constitute a sacrificial memory opening fill structure (not shown) and a sacrificial support opening fill structure (not shown).

[0090] A photoresist layer (not shown) may be applied over the alternating stack (32, 42) and the inverse stepped dielectric material portion 65 and may be lithographically patterned to cover the memory array region 100 without covering the contact region 300. The sacrificial support opening fill structures in the contact region 300 and the portions of the optional etch stop liner may be selectively removed for the materials of the inverse stepped dielectric material portion 65 and the alternating stack (32, 42). For example, an etch process or an ashing process may be employed to remove the sacrificial support opening fill structures in the contact region 300 and the portions of the optional etch stop liner. Subsequently, the photoresist layer may be removed.

[0091] A dielectric fill material (such as silicon oxide) may be deposited in the support openings 19 by a conformal deposition process. The excess portions of the dielectric fill material may be removed from above the top surface of the topmost insulating layer 32T, for example, by a recess etch process. Each portion of the dielectric fill material that fills the corresponding support opening 19 constitutes a support pillar structure 20, which may be used to provide structural support to the insulating layer 32 and the inverse stepped dielectric material portion 65 during replacement of the sacrificial material layer 42 with a conductive layer.

[0092] Subsequently, the sacrificial memory opening fill structures in the memory array region 100 and the portions of the optional etch stop liner may be selectively removed for the materials of the inverse stepped dielectric material portion 65 and the alternating stack (32, 42). For example, an etch process or an ashing process may be employed to remove the sacrificial memory opening fill structures in the memory array region 100 and the portions of the optional etch stop liner. A void is formed in the volume of the memory opening 49.

[0093] Figures 6A to 6DFIG. 0 is a series of consecutive schematic vertical cross-sectional views of a memory opening 49 within an exemplary structure during formation of a memory opening fill structure 58 in accordance with an embodiment of the present disclosure.

[0094] Reference Figure 6A , illustrates the memory opening 49 after the processing steps of Figure 5 .

[0095] Reference Figure 6B , a layer stack including a memory material layer 54 may be conformally deposited. In an illustrative example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in resistivity, ferroelectric polarization, or any other measurable physical property. In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 may include a tunneling dielectric layer.

[0096] A semiconductor channel material layer 60L may be deposited on the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, the semiconductor channel material layer 60L may have a doping of a first conductivity type, which may be p-type or n-type. In one embodiment, the first semiconductor material includes a first doped silicon material having a doping of a first conductivity type. In an illustrative example, the atomic concentration of the dopant of the first conductivity type in the semiconductor channel material layer 60L may be in the range from 1.0×10 13 / cm 3 to 3.0×10 17 / cm 3 , such as 1.0×10 14 / cm 3 to 3.0×10 16 / cm 3 , but smaller and larger atomic concentrations may also be employed. A dielectric core layer 62L including a dielectric fill material may be deposited in the remaining volume of the memory opening 49 and over the alternating stack (32, 42).

[0097] Reference Figure 6C , the dielectric core layer 62L may be vertically recessed such that each remaining portion of the dielectric core layer 62L has a top surface at or near a horizontal plane of the bottom surface including the topmost insulating layer 32T. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.

[0098] Reference Figure 6D, a doped semiconductor material of a second conductivity type may be deposited within each of the recessed regions above the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material may be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon.

[0099] The excess portions of the deposited doped semiconductor material of the second conductivity type and the horizontal portions of the semiconductor channel layer 60L may be removed, for example, by chemical mechanical planarization (CMP) or recess etching processes above the horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel 60.

[0100] Each portion of the layer stack including the memory material layer 54 retained within the respective memory opening 49 constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, which may include portions of the memory material layer 54 located at respective levels of the sacrificial material layer 42 (or generally, at respective levels of a spacer material layer that may be formed as a conductive layer or may be subsequently at least partially replaced by a conductive layer).

[0101] Reference Figure 7 , illustrates an exemplary structure after forming the memory opening fill structure 58 within the memory opening 49. Each memory opening fill structure within the memory opening fill structure 58 may include a respective vertical semiconductor channel 60 (which may be embodied as portions of the memory film 50 located at respective levels of the sacrificial material layer 42 and subsequently replaced with a conductive layer) laterally surrounded by a respective vertical stack of memory elements.

[0102] Reference Figure 8A and Figure 8B, A dielectric material, such as undoped silicate glass or doped silicate glass, can be deposited on the alternating stack (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range from 100 nm to 600 nm, such as from 200 nm to 400 nm, but smaller and larger thicknesses can also be employed.

[0103] A photoresist layer (not shown) can be applied on the contact-level dielectric layer 80 and can be lithographically patterned to form elongated openings that extend laterally along a first horizontal direction hd1 between adjacent clusters of the memory opening filling structure 58. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42), the stepped dielectric material portion 65, and the in-process source-level material layer 110'. Lateral isolation trenches 79 that extend laterally along the first horizontal direction hd1 can be formed to pass through the alternating stack (32, 42), the stepped dielectric material portion 65, the contact-level dielectric layer 80, and the in-process source-level material layer 110'. Each of the lateral isolation trenches 79 can include a corresponding pair of longitudinal sidewalls that are parallel to the first horizontal direction hd1 and extend vertically from the blocking insulating layer 106 to the top surface of the contact-level dielectric layer 80. The top surface of the blocking insulating layer 106 can be physically exposed under each lateral isolation trench 79. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0104] Reference Figure 9 , An etchant can be introduced into the lateral isolation trenches 79 by performing an isotropic etching process, and the etchant selectively etches the material of the source-level sacrificial layer 104 with respect to the materials of the alternating stack (32, 42), the contact-level dielectric layer 80, the stepped dielectric material portion 65, the lower source-level semiconductor layer 112, the upper source-level semiconductor layer 116, the upper sacrificial liner 105 (if present), and the lower sacrificial liner 103 (if present). For example, if the source-level sacrificial layer 104 includes undoped amorphous silicon or a silicon-germanium alloy, a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be used to selectively remove the source-level sacrificial layer 104 with respect to the alternating stack (32, 42), the contact-level dielectric layer 80, the stepped dielectric material portion 65, the lower source-level semiconductor layer 112, and the upper source-level semiconductor layer 116. Source cavities 109 are formed in the volumes from which the source-level sacrificial layer 104 is removed.

[0105] Wet etching chemicals such as hot TMY and TMAH are selective to doped semiconductor materials such as p-doped semiconductor materials and / or n-doped semiconductor materials of the upper source-level semiconductor layer 116 and the lower source-level semiconductor layer 112. Therefore, the use of selective wet etching chemicals (such as hot TMY and TMAH) for the wet etching process of forming the source cavity 109 provides a large process window for resisting etching depth variations during the formation of the lateral isolation trench 79. Specifically, even if the sidewalls of the upper source-level semiconductor layer 116 are physically exposed or even if the surface of the lower source-level semiconductor layer 112 is physically exposed when forming the source cavity 109, the collateral etching of the upper source-level semiconductor layer 116 and / or the lower source-level semiconductor layer 112 is minimal, and the structural changes to the exemplary structure caused by the accidental physical exposure of the surface of the upper source-level semiconductor layer 116 and / or the lower source-level semiconductor layer 112 during the manufacturing steps do not result in device failure. Each memory opening filling structure in the memory opening filling structure 58 is physically exposed to the source cavity 109. Specifically, each memory opening filling structure in the memory opening filling structure 58 includes sidewalls and is physically exposed to the source cavity 109.

[0106] A series of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 to sequentially etch various groups of layers of the memory film 50 from the outside in, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper sacrificial liner 105 (if present) and the lower sacrificial liner 103 (if present) can be collaterally etched during the removal of the portion of the memory film 50 located at the level of the source cavity 109. The volume of the source cavity 109 can be enlarged by removing the portions of the memory film 50 at the levels of the source cavity 109 and the upper and lower sacrificial liners. The top surface of the lower source-level semiconductor layer 112 and the bottom surface of the upper source-level semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 is formed by selectively isotropically etching the source-level sacrificial layer 104 and the bottom portion of each memory film in the memory film 50 for at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116) and the vertical semiconductor channel 60.

[0107] Reference Figure 10, a doped semiconductor material of a second conductivity type can be deposited on the physically exposed semiconductor surface surrounding the source cavity 109. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and the horizontal surfaces of at least one source-level semiconductor layer (such as the bottom surface of the upper source-level semiconductor layer 116 and / or the top surface of the lower source-level semiconductor layer 112). For example, the physically exposed semiconductor surface can include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the upper source-level semiconductor layer 116.

[0108] In one embodiment, a doped semiconductor material of a second conductivity type can be deposited on the physically exposed semiconductor surface surrounding the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and a dopant gas can be simultaneously introduced into the process chamber including the exemplary structure. For example, the semiconductor precursor gas can include silane, disilane, or dichlorosilane, the etchant gas can include gaseous hydrogen chloride, and the dopant gas can include hydrides of dopant atoms such as phosphine, arsine, stibine, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material of a second conductivity type from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped semiconductor material forms the source contact layer 114, which can contact the sidewall of the vertical semiconductor channel 60. The atomic concentration of the dopant of the second conductivity type in the deposited semiconductor material can be in the range from 1.0×10 20 / cm 3 to 2.0×10 21 / cm 3 , such as from 2.0×10 20 / cm 3 to 8.0×10 20 / cm 3 . The initially formed source contact layer 114 can consist essentially of semiconductor atoms and dopant atoms of a second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process can be used to form the source contact layer 114. Optionally, one or more etch-back processes can be used in combination with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0109] The duration of the selective semiconductor deposition process can be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material of a second conductivity type on the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material can include doped polysilicon. Thus, the source level sacrificial layer 104 can be replaced with the source contact layer 114. A layer stack including the lower source level semiconductor layer 112, the source contact layer 114, and the upper source level semiconductor layer 116 constitutes the source layer 110, which replaces the source level material layer 110' in the process. The source layer 110 contacts the end portions of each of the vertical semiconductor channels 60 in the vertical semiconductor channel 60.

[0110] Reference Figure 11 , an isotropic etching process can be performed to selectively remove the sacrificial material layer 42 for the insulating layer 32, the stop insulating layer 106, the memory opening filling structure 58, the sacrificial etch stop liner 71, and the source layer 110. According to an embodiment of the present disclosure, the presence of a direction in which lateral diffusion is facilitated (illustrated in Figures 4A to 4I ) contributes to the lateral diffusion of the isotropic etchant during the isotropic etching process. Generally speaking, the direction in which lateral diffusion is facilitated provides a larger lateral spacing between adjacent pairs of the memory opening filling structures 58 than other lateral directions in the exemplary structure (such as the first periodic repeat direction DPR_1 or the third periodic repeat direction DPR_3). Compared with a comparative exemplary structure employing a hexagonal periodic array of the memory opening filling structures 58 having a corresponding circular horizontal cross-sectional shape (thereby not providing any direction in which lateral diffusion is facilitated), in various embodiments of the present disclosure, the larger lateral spacing in the horizontal direction perpendicular to the direction in which lateral diffusion is facilitated between adjacent pairs of the memory opening filling structures 58 allows for more effective lateral diffusion of the isotropic etchant during the isotropic etching process. Therefore, various configurations of the present disclosure provide more effective etching of the sacrificial material layer 42.

[0111] A laterally extending cavity 43 can be formed in the volume from which the sacrificial material layer 42 has been removed. The sidewall surface segments of the memory opening filling structure 58 can be physically exposed to the laterally extending cavity 43. In an illustrative example, if the sacrificial material layer 42 includes silicon oxide, the isotropic etching process can include a wet etching process using hot phosphoric acid, which is a process in which the exemplary structure is immersed in phosphoric acid at or near the boiling point of phosphoric acid. A suitable cleaning process can be performed as needed.

[0112] Reference Figure 12, a backside blocking dielectric layer (not shown) can optionally be formed in the laterally extending cavity 43 by a conformal deposition process. At least one conductive material (such as at least one metallic material) can be conformally deposited in the laterally extending cavity 43. At least one chemical vapor deposition process and / or at least one atomic layer deposition process can be employed to deposit the at least one conductive material. According to an embodiment of the present disclosure, the presence of a direction of easy lateral diffusion (illustrated in Figures 4A to 4I ) facilitates the lateral diffusion of reactant gases during the conformal deposition process. Generally speaking, the direction of easy lateral diffusion provides a larger lateral pitch between adjacent pairs of memory opening filling structures 58 than other lateral directions (such as the first periodic repeat direction DPR_1 or the third periodic repeat direction DPR_3) in the exemplary structure. Compared with a comparative exemplary structure employing a hexagonal periodic array of memory opening filling structures 58 having a corresponding circular horizontal cross-sectional shape (thereby not providing any direction of easy lateral diffusion), in various embodiments of the present disclosure, the larger lateral pitch along the horizontal direction perpendicular to the direction of easy lateral diffusion between adjacent pairs of memory opening filling structures 58 allows for more efficient lateral diffusion of reactant gases during each conformal deposition process. Thus, various configurations of the present disclosure provide more efficient conformal deposition of the at least one conductive material while minimizing the formation of any unfilled voids.

[0113] The at least one conductive material can include, for example, a combination of a metal barrier material and a metal fill material. The metal barrier material can include, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof. The metal fill material can include, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and / or their alloys or layer stacks. The excess portion of the at least one conductive material deposited in the laterally isolated trench 79 or above the contact-level dielectric layer 80 can be removed by performing an etch-back process, which can include an isotropic etching process and / or an anisotropic etching process. Each remaining portion of the at least one conductive material filling a corresponding one of the laterally extending cavities in the laterally extending cavity 43 constitutes a conductive layer 46. An alternating stack of the insulating layer 32 and the conductive layer 46 can be formed between each pair of adjacent laterally isolated trenches 79 above the carrier substrate 9. A plurality of alternating stacks of the insulating layer 32 and the conductive layer 46 can be laterally spaced apart from each other by the laterally isolated trenches 79.

[0114] Referring to Figure 13A and Figure 13B, an insulating filler material can be conformally deposited in the lateral isolation trench 79. The excess of the insulating filler material can be removed, for example, by a recess etching process, from above the contact-level dielectric layer 80. Each remaining portion of the insulating filler material that fills the corresponding lateral isolation trench 79 constitutes an isolation trench fill structure 76. Alternatively, each isolation trench fill structure 76 can include a combination of a tubular insulating spacer (not explicitly shown) and a conductive connection via structure (not explicitly shown) that is laterally surrounded by the tubular insulating spacer.

[0115] A photoresist layer (not shown) can be applied above the contact-level dielectric layer 80, and the photoresist layer can be lithographically patterned to form openings above each memory opening fill structure in the memory opening fill structure 58 above the horizontal extension surface of the stepped surface in the contact area. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80 and the inverse stepped dielectric material portion 65. A drain contact via cavity can be formed through the contact-level dielectric layer 80 above the memory opening fill structure 58. The layer contact via structure can be formed through the contact-level dielectric layer 80 and the inverse stepped dielectric material portion 65 on the top surface of a corresponding one of the conductive layers in the conductive layer 46. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0116] At least one conductive material (such as a combination of a metal barrier material and a metal fill material) can be deposited in the drain contact via cavity and the layer contact via cavity. The excess of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process, which can employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the at least one conductive material that fills the drain contact via cavity constitutes a drain contact via structure 88 on the top surface of a corresponding one of the drain regions in the contact drain region 63. The remaining portion of the at least one conductive material that fills the layer contact via cavity constitutes a layer contact via structure 86 on the top surface of a corresponding one of the conductive layers that contact the conductive layer 46.

[0117] Reference Figure 14A and Figure 14B , a connection-level dielectric layer 90 can be formed above the contact-level dielectric layer 80. A connection via cavity can be formed through the connection-level dielectric layer 90 and can be filled with at least one conductive material (which can include at least one metal material) to form a connection-level via structure (98, 96). The connection-level via structure (98, 96) includes a drain connection via structure 98 of a corresponding one of the drain contact via structures in the contact drain contact via structure 88, and a layer connection via structure 96 of a corresponding one of the layer contact via structures in the layer contact via structure 86.

[0118] The bit - line level dielectric layer 120 may be formed over the contact - level dielectric layer 90. A bit - line level wire cavity may be formed through the bit - line level dielectric layer 120 and may be filled with at least one conductive material (which may include at least one metal material) to form bit - line level metal wires (128, 126). The bit - line level metal wires may include bit lines 128 that generally extend laterally along a second horizontal direction hd2 and have a periodic change in the lateral extension direction such that the periodicity of the periodic change in the lateral extension direction is the same as the periodicity of the isolation trench fill structure 76. This feature may occur when a first lateral offset distance Δ is not equal to zero, as in the case of the first through fourth configurations of the array of memory openings 49 (and thus the array of memory opening fill structures 58) described above. In this case, the inclination angle of the longer segment of the bit line 128 with respect to the second horizontal direction hd2 may be the arctangent of the ratio of the first lateral offset distance Δ to the center - to - center distance between adjacent pairs of memory openings 49 in even rows (which is the same as the center - to - center distance between adjacent pairs of memory opening fill structures 58 in even rows).

[0119] Reference Figure 15 , an additional dielectric material layer and additional metal interconnect structures may be formed over the bit - line level dielectric layer 120. The additional dielectric material layer may include at least one via - level dielectric layer, at least one additional wire - level dielectric layer, and / or at least one additional wire and via - level dielectric layer. The additional metal interconnect structures may include metal via structures, metal wire structures, and / or integrated metal wire and via structures. The additional dielectric material layer formed over the bit - line level dielectric layer 120 is referred to herein as the memory - side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory - side metal interconnect structures 980.

[0120] A metal bonding pad (which is referred to herein as the upper bonding pad 988) may be formed at the top - most level of the memory - side dielectric material layer 960. The upper bonding pad 988 may be electrically connected to the memory - side metal interconnect structures 980 and various nodes of the three - dimensional memory array, which includes an alternating stack of insulating layers 32 and conductive layers 46 and memory opening fill structures 58. A memory die 900 may be provided thereby.

[0121] The memory - side dielectric material layer 960 is formed over the alternating stack (32, 46). The memory - side metal interconnect structures 980 are embedded in the memory - side dielectric material layer 960. The memory - side bonding pad 988 may be embedded within the memory - side dielectric material layer 960, and specifically, within the top - most layer among the memory - side dielectric material layers 960. The memory - side bonding pad 988 may be electrically connected to the memory - side metal interconnect structures 980.

[0122] In one embodiment, memory die 900 may include: a three-dimensional memory array located below a first dielectric material layer 110 and including an alternating stack (32, 46) of insulating layers 32 and conductive layers 46; a two-dimensional array of memory openings 49 extending vertically through the alternating stack (32, 46); and a two-dimensional array of memory opening fill structures 58 located in the two-dimensional array of memory openings 49 and including corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; a two-dimensional array of drain contact via structures 88 electrically connected to a respective one of the vertical semiconductor channels 60 in the vertical semiconductor channels; and a two-dimensional array of layer contact via structures 86 electrically connected to a respective one of the conductive layers 46 in the conductive layers, with a subset of the conductive layers serving as word lines of the three-dimensional memory array.

[0123] Generally speaking, memory die 900 includes a memory array, a memory-side metal interconnect structure 980, and memory-side bond pads 988 embedded within a memory-side dielectric material layer 960. Memory die 900 includes a memory device, which may include a three-dimensional memory array comprising an alternating stack of insulating layers 32 and conductive layers 46, and further includes a two-dimensional array of NAND strings (e.g., memory opening fill structures 58) extending vertically through the alternating stack (32, 46). In one embodiment, conductive layer 46 includes the word lines of the two-dimensional array of NAND strings.

[0124] Reference Figure 16 , logic die 700 is provided. Logic die 700 includes peripheral circuitry 720 formed on a logic-side substrate 709. According to one aspect of the present disclosure, peripheral circuitry 720 may be configured to control the operation of the memory array within memory die 900. For example, peripheral circuitry 720 may include a word line driver region, a bit line driver region, a sense amplifier region, an input / output buffer region, and the like. A logic-side metal interconnect structure 780 embedded within a logic-side dielectric material layer 760 may be formed above peripheral circuitry 720. Logic die 700 includes logic-side bond pads 788 embedded within the logic-side dielectric material layer 760.

[0125] Reference Figure 17, a bonded component can be formed by bonding a logic die 700 to a memory die 900. The logic die 700 can be attached to the memory die 900, for example, by bonding a logic-side bonding pad 788 to a memory-side bonding pad 988. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process, in which a two-dimensional array of the memory die 900 is bonded to a two-dimensional array of the logic die 700 through a die-to-bonding process or through a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0126] The logic die 700 can be attached to the memory die 900, for example, by bonding a logic-side bonding pad 788 to a memory-side bonding pad 988. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process, in which a two-dimensional array of the memory die 900 is bonded to a two-dimensional array of the logic die 700 through a die-to-bonding process or through a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0127] Reference Figure 18 , the carrier substrate 9 can be optionally removed, for example, by grinding, polishing, cleaving, isotropic etching processes, and / or anisotropic etching processes. If a polishing process such as a chemical mechanical polishing process is used to remove the carrier substrate 9, then the stop insulating layer 106 can be subsequently used as a polishing stop material layer. If an etching process such as a wet etching process is used to remove the carrier substrate 9, then the stop insulating layer 106 can be subsequently used as an etching stop material layer.

[0128] Referring to all the figures and in accordance with the first, second, and third embodiments of the present disclosure, a memory device includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46; a memory opening 49 that vertically extends through the alternating stack, wherein a minimum unit shape of three nearest-neighbor memory openings is a non-equilateral triangle; and a memory opening filling structure 58 that is located in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a vertical semiconductor channel 60 and a vertical stack of memory elements (e.g., portions of a memory film 50).

[0129] In one embodiment, the non-equilateral triangle includes a scalene triangle.

[0130] In one embodiment, the memory openings 49 are arranged as a plurality of rows of memory openings. Each row of the plurality of rows includes a respective one-dimensional periodic array of memory openings 49 having a uniform pitch p along a first horizontal direction hd1, and the plurality of rows are laterally spaced from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, wherein the plurality of rows include odd rows and even rows when numbered in integer order starting from 1 along the second horizontal direction hd2, and wherein for each first vertical axis VA1 passing through the geometric center of a respective memory opening 49 in any odd row, a second vertical axis VA2 passing through the geometric center of the nearest memory opening 49 in the nearest odd row is laterally offset from the first vertical axis VA1 along the first horizontal direction hd1 by a first lateral offset distance Δ, the first lateral offset distance being greater than 0 and less than half of the uniform pitch p.

[0131] In one embodiment, for each first vertical axis VA1 passing through the geometric center of a respective memory opening 49 in any odd row, a third vertical axis VA3 passing through the geometric center of the nearest memory opening 49 within the nearest even row is laterally offset from the first vertical axis VA1 along the first horizontal direction hd1 by a second lateral offset distance (p - Δ) / 2 - η, the second lateral offset distance being greater than 0 and less than (p - Δ) / 2. In one embodiment, the difference between the (p - Δ) / 2 and the second lateral offset distance (p - Δ) / 2 - η is a lateral shift distance η, the lateral shift distance being greater than 0 and less than Δ / 2.

[0132] In one embodiment, for each first vertical axis VA1 passing through the geometric center of a respective memory opening 49 in any odd row, a third vertical axis VA3 passing through the geometric center of the nearest memory opening 49 within the nearest even row is laterally offset from the first vertical axis VA1 along the first horizontal direction hd1 by a second lateral offset distance equal to (p - Δ) / 2.

[0133] In one embodiment, for each first vertical axis VA1 passing through the geometric center of a respective memory opening 49 in any odd row, a flat vertical plane passing through the first vertical axis VA1 and parallel to the second horizontal direction hd2 does not pass through the geometric center of any memory opening 49 within any nearest neighbor row of memory openings 49 or within any second nearest neighbor row of memory openings 49.

[0134] In one embodiment, a first vertical plane VP1 passing through the geometric center of a memory opening 49 within a memory opening 49 in an odd row and passing through the geometric center of a memory opening 49 within a memory opening 49 in the nearest neighbor odd row is at a first angle (π / 3 - α) relative to the first horizontal direction hd1, wherein the first angle (π / 3 - α) is less than π / 3 and greater than In one embodiment, a second vertical plane VP2 passing through the geometric center of a memory opening 49 within the memory openings 49 of odd rows and through the geometric center of another memory opening 49 within the memory openings 49 of the nearest neighbor odd rows is at a second angle (π / 3 + β) relative to a first horizontal direction hd1, where the second angle (π / 3 + β) is greater than π / 3 and less than In one embodiment, a third vertical plane VP3 passing through the geometric center of a memory opening 49 within the memory openings 49 of odd rows and through the geometric center of the memory opening 49 within the nearest neighbor even rows of the memory openings 49 is at a third angle (π / 3 + γ) relative to the first horizontal direction hd1, where the third angle (π / 3 + γ) is greater than the second angle (π / 3 + β).

[0135] In the first and second embodiments, each of the memory openings 49 has a corresponding circular horizontal cross-sectional shape. In the third embodiment, each of the memory openings 49 has a corresponding elongated horizontal cross-sectional shape having a corresponding major axis and a corresponding minor axis. The major axis of the memory opening extends along the nearest neighbor memory opening direction.

[0136] According to the third and fourth embodiments of the present disclosure, a memory device includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46; a memory opening 49 extending vertically through the alternating stack, where each of the memory openings 49 has a corresponding elongated horizontal cross-sectional shape having a corresponding major axis and a corresponding minor axis, and the major axis of the memory opening extends along the nearest neighbor memory opening direction; and a memory opening filling structure 58 located within the memory opening, where each of the memory opening filling structures includes a vertical semiconductor channel 60 and a vertical stack of memory elements (e.g., portions of a memory film 50).

[0137] In one embodiment, the memory openings 49 are arranged in multiple rows of memory openings. Each row of the multiple rows includes a corresponding one-dimensional periodic array of memory openings 49 having a uniform pitch p along a first horizontal direction hd1, and the multiple rows are laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and the major axes of the memory openings 49 are parallel to each other and at a non-zero and non-orthogonal angle relative to the first horizontal direction hd1.

[0138] In one embodiment, when numbering the plurality of rows in integer order starting from 1 along the second horizontal direction hd2, the plurality of rows include odd rows and even rows; and each pattern of the memory openings 49 in any odd row is periodically repeated in every other odd row along the second horizontal direction hd2, wherein the periodicity is equal to the center-to-center distance between adjacent pairs of odd rows within the plurality of rows.

[0139] In one embodiment, when numbering the plurality of rows in integer order starting from 1 along the second horizontal direction hd2, the plurality of rows include odd rows and even rows; and for each first vertical axis VA1 passing through the geometric center of the corresponding memory opening 49 in any odd row, a second vertical axis VA2 passing through the geometric center of the nearest memory opening 49 in the nearest odd row is laterally offset from the first vertical axis VA1 by a first lateral offset distance Δ along the first horizontal direction hd1, the first lateral offset distance being greater than 0 and less than half of the uniform pitch p. In one embodiment, the non-zero and non-orthogonal angle is greater than p / 3 and less than arctan(2√3).

[0140] In a third embodiment, the minimum cell shape of three nearest neighbor memory openings is a scalene triangle. In a fourth embodiment, the minimum cell shape of three nearest neighbor memory openings is an equilateral triangle.

[0141] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or "consisting of..." replace the words "comprising" or "including". Where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A memory device, the memory device comprising: An alternating stack of insulating layers and conductive layers; Memory openings that vertically extend through the alternating stack, wherein a minimum unit shape of three nearest neighbor memory openings is a non-equilateral triangle; And A memory opening filling structure located in the memory openings, wherein each memory opening filling structure in the memory opening filling structure comprises a vertical semiconductor channel and a vertical stack of memory elements.

2. The memory device according to claim 1, wherein the non-equilateral triangle comprises a scalene triangle.

3. The memory device according to claim 2, wherein: The memory openings are arranged as multiple rows of memory openings; Each row in the multiple rows comprises a respective one-dimensional periodic array of memory openings having a uniform pitch p along a first horizontal direction, and the multiple rows are laterally spaced apart from each other along a second horizontal direction perpendicular to the first horizontal direction; The multiple rows include odd rows and even rows when numbered in integer order starting from 1 along the second horizontal direction, and wherein, for each first vertical axis passing through the geometric center of a corresponding memory opening in any odd row, a second vertical axis passing through the geometric center of the nearest memory opening in the nearest odd row is laterally offset from the first vertical axis along the first horizontal direction by a first lateral offset distance Δ, the first lateral offset distance being greater than 0 and less than half of the uniform pitch p.

4. The memory device according to claim 3, wherein, For each first vertical axis passing through the geometric center of the corresponding memory opening in any odd row, a third vertical axis passing through the geometric center of the nearest memory opening in the nearest even row is laterally offset from the first vertical axis along the first horizontal direction by a second lateral offset distance (p - Δ) / 2 - η, the second lateral offset distance being greater than 0 and less than (p - Δ) / 2.

5. The memory device according to claim 4, wherein a difference between (p - Δ) / 2 and the second lateral offset distance (p - Δ) / 2 - η is a lateral shift distance η, the lateral shift distance being greater than 0 and less than Δ / 2.

6. The memory device according to claim 3, wherein, For each first vertical axis passing through the geometric center of the corresponding memory opening in any odd row, a third vertical axis passing through the geometric center of the nearest memory opening in the nearest even row is laterally offset from the first vertical axis along the first horizontal direction by a second lateral offset distance, the second lateral offset distance being equal to (p - Δ) / 2.

7. The memory device according to claim 3, wherein, For each first vertical axis passing through the geometric center of the corresponding memory opening in any odd row, a flat vertical plane passing through the first vertical axis and parallel to the second horizontal direction does not pass through the geometric center of any memory opening within any nearest neighbor row of memory openings or within any second nearest neighbor row of memory openings.

8. The memory device according to claim 3, wherein a first vertical plane passing through the geometric centers of the memory openings within the memory openings of the odd rows and through the geometric centers of the memory openings within the memory openings of the nearest neighbor odd rows is at a first angle (π / 3 - α) with respect to the first horizontal direction, where the first angle (π / 3 - α) is less than π / 3 and greater than arctan(√3 / (1.5)).

9. The memory device according to claim 8, wherein a second vertical plane passing through the geometric centers of the memory openings within the memory openings of the odd rows and through the geometric centers of another memory opening within the memory openings of the nearest neighbor odd rows is at a second angle (π / 3 + β) with respect to the first horizontal direction, where the second angle (π / 3 + β) is greater than π / 3 and less than arctan(√3 / (1.5)).

10. The memory device according to claim 8, wherein a third vertical plane passing through the geometric centers of the memory openings within the memory openings of the odd rows and through the geometric centers of the memory openings within the memory openings of the nearest neighbor even rows is at a third angle (π / 3 + γ) with respect to the first horizontal direction, where the third angle (π / 3 + γ) is greater than the second angle (π / 3 + β).

11. The memory device according to claim 1, wherein each of the memory openings has a corresponding circular horizontal cross-sectional shape.

12. The memory device according to claim 1, wherein: each of the memory openings has a corresponding elongated horizontal cross-sectional shape, the elongated horizontal cross-sectional shape having a corresponding major axis and a corresponding minor axis; and the major axis of the memory opening extends along the direction of the nearest neighbor memory opening.

13. A memory device, the memory device comprising: an alternating stack of insulating layers and conductive layers; memory openings extending vertically through the alternating stack, wherein each of the memory openings has a corresponding elongated horizontal cross-sectional shape, the elongated horizontal cross-sectional shape having a corresponding major axis and a corresponding minor axis, and the major axis of the memory opening extends along the direction of the nearest neighbor memory opening; and a memory opening filling structure located within the memory openings, wherein each of the memory opening filling structures includes a vertical semiconductor channel and a vertical stack of memory elements.

14. The memory device according to claim 13, wherein: the memory openings are arranged in multiple rows of memory openings; each row of the multiple rows includes a corresponding one-dimensional periodic array of memory openings having a uniform pitch p along a first horizontal direction, and the multiple rows are laterally spaced from each other along a second horizontal direction perpendicular to the first horizontal direction; and the major axes of the memory openings are parallel to each other and at a non-zero and non-orthogonal angle with respect to the first horizontal direction.

15. The memory device according to claim 14, wherein: When numbered in integer order starting from 1 along the second horizontal direction, the plurality of rows include odd rows and even rows; and Each pattern of the memory openings in any odd row is periodically repeated in every other odd row along the second horizontal direction, wherein the periodicity is equal to the center-to-center distance between adjacent pairs of odd rows within the plurality of rows.

16. The memory device according to claim 14, wherein: When numbered in integer order starting from 1 along the second horizontal direction, the plurality of rows include odd rows and even rows; and For each first vertical axis passing through the geometric center of the corresponding memory opening in any odd row, a second vertical axis passing through the geometric center of the nearest memory opening in the nearest odd row is laterally offset from the first vertical axis by a first lateral offset distance Δ along the first horizontal direction, the first lateral offset distance being greater than 0 and less than half of the uniform pitch p.

17. The memory device according to claim 13, wherein the minimum cell shape of three nearest neighbor memory openings is a scalene triangle.

18. The memory device according to claim 13, wherein the minimum cell shape of three nearest neighbor memory openings is an equilateral triangle.

19. A method of forming a memory device, the method comprising: Forming an alternating stack of an insulating layer and a sacrificial material layer on a substrate; Forming memory openings that vertically extend through the alternating stack, wherein the minimum cell shape of three nearest neighbor memory openings is a non-equilateral triangle; Forming a memory opening filling structure that is located in the memory openings, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; Removing the sacrificial material layer between the memory opening filling structures to form a laterally extending cavity; And Forming a conductive layer in the laterally extending cavity.

20. The method according to claim 19, wherein: The non-equilateral triangle includes a scalene triangle; and A first diffusion path is provided in the laterally extending cavity between a first group of memory openings, the first diffusion path being wider than a second diffusion path provided in the laterally extending cavity between a second group of memory openings.

Images