High voltage field effect transistor with different sidewall spacer configurations and method of manufacturing same

Abstract

A semiconductor structure includes a first field effect transistor including a first gate spacer having a first laterally straight bottom edge coincident with a top edge of a first laterally straight sidewall of a first gate dielectric. The semiconductor structure further includes a second field effect transistor including: a second gate dielectric including at least one discrete gate dielectric opening overlying a respective second active region; and a second gate spacer including a contour portion overlying and laterally surrounding a second gate electrode, and at least one horizontal extension portion overlying the second active region and including at least one discrete gate spacer opening. The second field effect transistor may have a symmetric or asymmetric configuration.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority of the following applications: U.S. Non - Provisional Application No. 18 / 358,633, filed on July 25, 2023; and U.S. Non - Provisional Application No. 18 / 358,653, filed on July 25, 2023; the entire contents of the above - mentioned applications are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to high - voltage field - effect transistors having different sidewall spacer configurations and methods of manufacturing the same. Background Art

[0004] High - voltage field - effect transistors of the prior art are often affected by the surface breakdown voltage. Such transistors typically have a complex extended lightly doped drain (LDD) to improve the surface breakdown characteristics, but at the cost of complex processes and increased costs. Summary of the Invention

[0005] According to one aspect of the present disclosure, a semiconductor structure includes: a first field - effect transistor located in a first device region above a substrate and including: first active regions that are laterally spaced apart from each other by a first semiconductor channel; a first gate dielectric overlying the first semiconductor channel; a first gate electrode overlying the first gate dielectric; and a first gate spacer having a first laterally straight outer sidewall having a first laterally straight bottom edge that coincides with a top edge of a first laterally straight sidewall of the first gate dielectric. The semiconductor structure further includes: a second field - effect transistor located in a second device region of the substrate and including: second active regions that are laterally spaced apart from each other by a second semiconductor channel; a second gate dielectric overlying the second semiconductor channel and the second active regions and including a pair of discrete gate dielectric openings that pass through the second gate dielectric and overlie a respective one of the second active regions; a second gate electrode overlying the second gate dielectric; and a second gate spacer including: a contour portion overlying a portion of a top surface of the second gate electrode and laterally surrounding the second gate electrode; and horizontal extension portions overlying the second active regions and including a pair of discrete gate spacer openings that pass through the horizontal extension portions and overlie the pair of discrete gate dielectric openings.

[0006] A method of forming a semiconductor structure is provided. The method includes: forming a shallow trench isolation structure in an upper portion of a semiconductor substrate; forming a first gate dielectric, a second gate dielectric, a first active region extension, and a second active region extension in the upper portion of the semiconductor substrate; forming a first gate electrode and a second gate electrode over the first gate dielectric and the second gate dielectric, respectively; conformally forming at least one gate spacer layer over the first gate electrode and the second gate electrode; and patterning the at least one gate spacer layer, the first gate dielectric, and the second gate dielectric to form a first gate spacer and a second gate spacer. The remaining portion of the first gate dielectric includes two first laterally straight sidewalls that laterally extend over and cover the first active region extensions and are vertically aligned with two first laterally straight outer sidewalls of the first gate spacer, and wherein the remaining portion of the second gate dielectric includes two discrete gate dielectric openings that are underlying discrete gate spacer openings in the second gate spacer, overlie the second active region extensions, and are entirely within the area of the openings in the shallow trench isolation structures.

[0007] According to another aspect of the present disclosure, another semiconductor structure includes: a first field-effect transistor located in a first device region above a substrate and including: first active regions that are laterally spaced apart from each other by a first semiconductor channel; a first gate dielectric overlying the first semiconductor channel; a first gate electrode overlying the first gate dielectric; and a first gate spacer having a first laterally straight outer sidewall having a first laterally straight bottom edge that coincides with a top edge of a first laterally straight sidewall of the first gate dielectric. The semiconductor structure further includes: a second field-effect transistor located in a second device region of the substrate and including: second active regions that are laterally spaced apart from each other by a second semiconductor channel; a second gate dielectric overlying the second semiconductor channel and the second active regions; a second gate electrode overlying the second gate dielectric; and a second gate spacer including: a first portion located on a first side of the second gate electrode and having a second laterally straight outer sidewall having a first laterally straight bottom edge that coincides with a top edge of a second laterally straight sidewall of the second gate dielectric; and a second portion located on a second side of the second gate electrode and having: a contoured portion overlying a portion of a top surface of the second side of the second gate electrode and laterally surrounding the second gate electrode; and a horizontally extending portion overlying one of the second active regions in the second active regions and including a discrete gate spacer opening that passes through the horizontally extending portion and overlies a discrete gate dielectric opening that passes through the second gate dielectric.

[0008] According to yet another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes: forming a shallow trench isolation structure in an upper portion of a semiconductor substrate; forming a first gate dielectric, a second gate dielectric, a first active region extension, and a second active region extension in the upper portion of the semiconductor substrate; forming a first gate electrode and a second gate electrode over the first gate dielectric and the second gate dielectric, respectively; conformally forming at least one gate spacer layer over the first gate electrode and the second gate electrode; and patterning the at least one gate spacer layer, the first gate dielectric, and the second gate dielectric to form a first gate spacer and a second gate spacer. A remaining portion of the first gate dielectric includes two first laterally straight sidewalls that laterally extend over and cover the first active region extensions and are vertically coincident with two first laterally straight outer sidewalls of the first gate spacer. A remaining portion of the second gate dielectric includes: a second laterally straight sidewall that laterally extends over and covers one of the second active region extensions and is vertically coincident with a second laterally straight outer sidewall of the second gate spacer; and a discrete gate dielectric opening that underlies a discrete gate spacer opening in the second gate spacer and covers the other of the second active region extensions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a vertical cross-sectional view of a first subset of a device region in an exemplary structure after forming a shallow trench isolation structure according to an embodiment of the present disclosure.

[0010] Figure 1B is Figure 1A a vertical cross-sectional view of a second subset of a device region in the exemplary structure.

[0011] Figure 2A is a vertical cross-sectional view of a first subset of a device region in an exemplary structure after forming an active region extension according to an embodiment of the present disclosure.

[0012] Figure 2B is Figure 2A a vertical cross-sectional view of a second subset of a device region in the exemplary structure.

[0013] Figure 3A is a vertical cross-sectional view of a first subset of a device region in an exemplary structure after forming an additional active region extension according to an embodiment of the present disclosure.

[0014] Figure 3B is Figure 3AA vertical cross-sectional view of a second subset of device regions in an exemplary structure.

[0015] Figure 4A Is a vertical cross-sectional view of a first subset of device regions in an exemplary structure after forming a gate dielectric, according to an embodiment of the present disclosure.

[0016] Figure 4B Is Figure 4A A vertical cross-sectional view of a second subset of device regions in an exemplary structure.

[0017] Figure 5A Is a vertical cross-sectional view of a first subset of device regions in an exemplary structure after forming a gate electrode, according to an embodiment of the present disclosure.

[0018] Figure 5B Is Figure 5A A vertical cross-sectional view of a second subset of device regions in an exemplary structure.

[0019] Figure 6A Is a vertical cross-sectional view of a first subset of device regions in an exemplary structure after forming at least one gate spacer layer, according to an embodiment of the present disclosure.

[0020] Figure 6B Is Figure 6A A vertical cross-sectional view of a second subset of device regions in an exemplary structure.

[0021] Figure 7A Is a vertical cross-sectional view of a first subset of device regions in an exemplary structure after patterning the at least one gate spacer layer into gate spacers, according to an embodiment of the present disclosure.

[0022] Figure 7B Is Figure 7A A vertical cross-sectional view of a second subset of device regions in an exemplary structure.

[0023] Figure 8A Is a vertical cross-sectional view of a first subset of device regions in an exemplary structure after a first masked ion implantation process, according to an embodiment of the present disclosure.

[0024] Figure 8B Is Figure 8A A vertical cross-sectional view of a second subset of device regions in an exemplary structure.

[0025] Figure 9A Is a vertical cross-sectional view of a first subset of device regions in an exemplary structure after a second masked ion implantation process, according to an embodiment of the present disclosure.

[0026] Figure 9B IsFigure 9A A vertical cross-sectional view of a second subset of a device region in an exemplary structure.

[0027] Figure 10A Is a vertical cross-sectional view of a first subset of a device region in an exemplary structure after removing a second ion implantation mask layer, according to an embodiment of the present disclosure.

[0028] Figure 10B Is Figure 10A A vertical cross-sectional view of a second subset of a device region in an exemplary structure.

[0029] Figure 10C Is Figure 10A A top view of a first subset of a device region of an exemplary structure.

[0030] Figure 10D Is Figure 10B A top view of a second subset of a device region of an exemplary structure.

[0031] Figure 11A Is a vertical cross-sectional view of a first subset of a device region in an exemplary structure after forming a metal-semiconductor alloy region, according to an embodiment of the present disclosure.

[0032] Figure 11B Is Figure 11A A vertical cross-sectional view of a second subset of a device region in an exemplary structure.

[0033] Figure 12A Is a vertical cross-sectional view of a first subset of a device region in an exemplary structure after forming a planarized dielectric layer, according to an embodiment of the present disclosure.

[0034] Figure 12B Is Figure 12A A vertical cross-sectional view of a second subset of a device region in an exemplary structure.

[0035] Figure 13A Is a vertical cross-sectional view of a first subset of a device region in an alternative configuration of an exemplary structure, according to an embodiment of the present disclosure.

[0036] Figure 13B Is a vertical cross-sectional view of a second subset of a device region in an alternative configuration of an exemplary structure. Detailed Description

[0037] Embodiments of the present disclosure provide high-voltage field effect transistors having different sidewall spacer configurations and methods of manufacturing the same, aspects of which are described below.

[0038] The accompanying drawings are not drawn to scale. Multiple instances of an element may be replicated in the case of a single instance of an illustrated element, unless otherwise explicitly described or clearly indicated that no replication of the element exists. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The same reference numerals denote the same or similar elements. Unless otherwise stated, it is assumed that elements with the same reference numerals have the same composition. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" located on the second element.

[0039] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. For example, the layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure or at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it, and / or below it.

[0040] As used herein, a "layer stack" refers to a stack of layers. As used herein, a "line" or "line structure" refers to a layer having a principal direction of extension (i.e., the direction in which the layer extends the most).

[0041] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm in the absence of an electrical dopant, and capable of producing a doped material having a conductivity in the range of 1.0 S / cm to 1.0×10 5 S / cm when appropriately doped with an electrical dopant. As used herein, an "electrical dopant" is a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / cm. As used herein, an "insulator material", "insulating material", or "dielectric material" refers to a material having a conductivity less than 1.0×10 -6a material having a conductivity of S / cm. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) providing a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm. An "intrinsic semiconductor material" refers to a semiconductor material not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material containing at least one metallic element. All conductivity measurements are made under standard conditions.

[0042] As used herein, a "field effect transistor" refers to any semiconductor device having a semiconductor channel through which current flows with a current density modulated by an external electric field. As used herein, a "channel region" refers to a semiconductor region in which the mobility of charge carriers is affected by an applied electric field. A "gate electrode" refers to a portion of a conductive material that controls the electron mobility in the channel region by applying an electric field. A "source region" refers to a doped semiconductor region that supplies charge carriers flowing through the channel region. A "drain region" refers to a doped semiconductor region that receives the charge carriers supplied by the source region and flowing through the channel region. An "active region" refers to the source region of a field effect transistor or the drain region of a field effect transistor. A "source extension region" refers to a doped semiconductor region having a smaller dopant concentration than the source region, having the same doping type as the source region, and including a portion disposed between the source region and the channel region. A "drain extension region" refers to a doped semiconductor region having a smaller dopant concentration than the drain region, having the same doping type as the drain region, and including a portion disposed between the drain region and the channel region. An "active region extension" refers to a source extension region or a drain extension region.

[0043] Many high voltage transistors have reliability issues, i.e., the performance of the transistor degrades over time due to electrons being trapped in the silicon nitride gate sidewall spacer. In addition, when an additional silicide blocking silicon nitride layer is used during metal silicide formation on the source and drain regions, this additional dielectric layer tends to exacerbate the reliability issues.

[0044] Embodiments of the present disclosure provide a semiconductor device that includes a p-type high-voltage transistor and an n-type high-voltage transistor having gate sidewall spacer structures that are different from each other to improve device reliability. The semiconductor gate electrode can be selectively metallized and then annealed to form a metal silicide low contact resistance and low leakage current gate contact structure. In some embodiments, an elongated silicon nitride sidewall spacer can be used as both a partial silicide blocking structure and an ion implantation mask in the n-type high-voltage transistor, while a narrower silicon nitride sidewall spacer can be used as an ion implantation mask structure in the p-type high-voltage transistor without blocking silicide formation to improve device reliability.

[0045] Reference Figure 1A and Figure 1B , illustrates an exemplary structure according to an embodiment of the present disclosure, the exemplary structure including a semiconductor substrate 8, a shallow trench isolation structure 20 formed in an upper portion of the semiconductor substrate 8, and doped wells that can be formed in a subset of the device regions. The semiconductor substrate 8 can be any semiconductor substrate known in the art. For example, the semiconductor substrate 8 can be a commercially available single-crystal semiconductor substrate, such as a single-crystalline silicon wafer. The semiconductor substrate 8 can include a semiconductor material layer, such as a doped first conductive type semiconductor layer 11 having a first conductive type at a first atomic concentration. The first conductive type can be p-type or n-type, and the first atomic concentration can be in the range of 1.0×10 13 / cm 3 to 1.0×10 17 / cm 3 , but smaller or larger atomic concentrations can also be employed.

[0046] The exemplary structure includes at least one device region, which can include any combination of, for example, a first device region 100, a second device region 200, a third device region 300, a fourth device region 400, and a fifth device region 500. As described above, the ordinal numbers in the device names are for counting purposes only and do not form part of the element names. Similarly, the ordinal numbers attached to the structural components of the present disclosure do not form part of the element names. Thus, the ordinal numbers assigned to elements in the claims of this application may or may not match the ordinal numbers assigned to the same elements in the specification, and the specification and claims must be interpreted in accordance with the possible variations in the ordinal numbers assigned to the elements.

[0047] Figure 1A and Figure 1BShows different subsets of device regions (100, 200, 300, 400, 500) of embodiments of the present disclosure. Device region 100 is for forming a high-voltage p-type field-effect transistor. Device region 200 is for forming a high-voltage n-type field-effect transistor. Device region 300 is for forming a low-voltage n-type field-effect transistor. Device region 400 is for forming an asymmetric low-voltage to high-voltage n-type field-effect transistor, which can be used as a bit-line hook-up transistor in a driver circuit of a memory device. Device region 500 is for forming another high-voltage p-type field-effect transistor.

[0048] Figure 1A Shows device regions 100, 200, and 300. Figure 1B Shows device regions 200, 400, and 500. In one embodiment, all five device regions (100, 200, 300, 400, 500) are located on the same substrate 8 and are fabricated using the steps described hereinafter with respect to all the figures in Figures 1A to 13B below.

[0049] In another embodiment, Figure 1A device regions 100, 200, and 300 are located on one substrate 8, and device regions 200, 400, and 500 are located on different substrates 8. Thus, in this embodiment, the high-voltage n-type field-effect transistor in device region 200 can be used in the same device with the high-voltage p-type field-effect transistor in device region 100 and the low-voltage n-type transistor in device region 300, or the high-voltage n-type field-effect transistor in device region 200 can be used in the same device with the high-voltage p-type field-effect transistor in device region 500 and the asymmetric low-voltage to high-voltage n-type field-effect transistor in device region 400. Thus, the transistors in device regions 100, 200, and 300 can be fabricated on one substrate 8 using the steps described hereinafter with respect to those numbered with "A" in Figures 1A to 13A below, while the transistors in device regions 200, 400, and 500 can be fabricated on different substrates 8 using the steps described hereinafter with respect to those numbered with "B" in Figures 1B to 13B below.

[0050] Each device region can be formed adjacent to any other device region. Thus, Figure 1A and Figure 1B the lateral order of the illustrated set of device regions can be arranged in any order. In addition, any number of instances of the illustrated device regions can be repeated with or without modification in the lateral direction. In one embodiment, Figure 1A and Figure 1B one or more instances of each illustrated device region in below can be disposed above the same semiconductor substrate 8. Each device region can include a corresponding opening in a shallow trench isolation structure, where a top surface section of the semiconductor material in the semiconductor substrate 8 is physically exposed.

[0051] In one embodiment, a doped well (such as a doped second conductivity type well 12 of a second conductivity type) may be formed in a subset of the device regions. In the illustrated example, the second conductivity type well 12 may be formed in each of the first device region 100 and the fifth device region 500. The second conductivity type is opposite to the first conductivity type. Each second conductivity type well 12 includes dopants of the second conductivity type at a corresponding second atomic concentration, which may be in the range of 1.0×10 13 / cm 3 to 1.0×10 17 / cm 3 , but smaller or larger atomic concentrations may also be employed. The first conductivity type may include p-type, and the second conductivity type may include n-type.

[0052] Referring to Figure 2A and Figure 2B , at least one photoresist layer (not shown) may be applied and patterned over the top surface of the semiconductor substrate 8, and may be lithographically patterned to cover corresponding subsets of the top surface segments of the semiconductor substrate 8. The corresponding patterned photoresist layer may be used as an implantation mask to implant dopants of the first conductivity type to form a first conductivity type doped semiconductor region, which may include first conductivity type active region extensions (131, 141) and first conductivity type wells (231, 241, 431, 441). Alternatively, the first conductivity type well 441 may be omitted.

[0053] The first conductivity type active region extensions (131, 141) include first conductivity type doped regions, which may be used as source extensions or drain extensions if the source and drain regions will also have the first conductivity type. For example, the first conductivity type active region extensions (131, 141) may include a first conductivity type source extension region 131 and a first conductivity type drain extension region 141.

[0054] The first conductivity type wells (231, 241, 431, and optionally 441) include various doped wells, which may be used to enhance the performance of subsequently formed second conductivity type field effect transistors (e.g., n-type transistors) (i.e., field effect transistors including source / drain regions (collectively referred to herein as active regions) doped with a second conductivity type (e.g., n-type)). For example, if the source and drain regions will have the second conductivity type, these wells may be used as halo regions. The first conductivity type wells (231, 241, 431, 441) may include source side first conductivity type wells (231, 431) and drain side first conductivity type wells (241, 441). As described above, the first conductivity type well 441 may be omitted.

[0055] In one embodiment, a subset of the first conductivity type wells (231, 241, 441) may have the same depth and the same dopant concentration as the first conductivity type active region extensions (131, 141), and may be formed by the same ion implantation process. In the illustrated example, the source side first conductivity type well 231, the drain side first conductivity type wells (241, 441), and the first conductivity type active region extensions (131, 141) may be formed by the same ion implantation process, and may have the same depth and the same dopant concentration of the dopant of the first conductivity type.

[0056] In one embodiment, the first conductivity type well 431 may be formed separately using a patterned photoresist layer different from the remaining first conductivity type active region extensions (131, 141) and first conductivity type wells (231, 241, and optionally 441). Higher ion energy implantation may be used to form the first conductivity type well 431 compared to the remaining first conductivity type active region extensions (131, 141) and first conductivity type wells (231, 241, and optionally 441). In this embodiment, the first conductivity type well 431 extends deeper into the substrate 8 compared to the remaining first conductivity type active region extensions (131, 141) and first conductivity type wells (231, 241, and optionally 441).

[0057] Generally, the first conductivity type active region extensions (131, 141) and the first conductivity type wells (231, 241, 431, 441) include a dopant of the first conductivity type at a corresponding third atomic concentration, which may be in the range of 1.0×10 14 / cm 3 to 3.0×10 18 / cm 3 range, but smaller and larger atomic concentrations may also be employed. The depth of each of the first conductivity type active region extensions (131, 141) and the first conductivity type wells (231, 241, 431, 441) may be in the range of 50 nm to 400 nm, but smaller and larger depths may also be employed.

[0058] Reference Figure 3A and Figure 3B, at least one photoresist layer (not shown) may be applied and patterned over the top surface of the semiconductor substrate 8, and may be lithographically patterned to cover corresponding subsets of the top surface segments of the semiconductor substrate 8 in the device regions 100 and 300. The corresponding patterned photoresist layer may be used as an implantation mask to implant dopants of a second conductivity type to form second conductivity type doped semiconductor regions, which may include second conductivity type active region extensions (232, 242, 432, 442) in the device regions 200 and 400.

[0059] The second conductivity type active region extensions (232, 242, 432, 442) include second conductivity type doped regions that can be used as source extension regions or drain extension regions. For example, the second conductivity type active region extensions (232, 242, 432, 442) may include second conductivity type source extension regions (232, 432) and second conductivity type drain extension regions (242, 442). In one embodiment, the second conductivity type source extension regions (232, 432) may be entirely formed within the volume of a respective one of the source side first conductivity type wells (231, 431), and the second conductivity type drain extension regions (242, 442) may be entirely formed within the volume of a respective one of the drain side first conductivity type wells (241, 441). In such a case, the depth of each of the second conductivity type source extension regions (232, 432) and the second conductivity type drain extension regions (242, 442) may be less than the depth of a respective one of the source side first conductivity type wells (231, 431), or less than the depth of a respective one of the drain side first conductivity type wells (241, 441).

[0060] Generally, the second conductivity type active region extensions (232, 242, 432, 442) include dopants of a second conductivity type at a respective fourth atomic concentration, which may be in the range of 1.0×10 14 / cm 3 to 3.0×10 18 / cm 3 but smaller and larger atomic concentrations may also be employed. The depth of each of the second conductivity type active region extensions (232, 242, 432, 442) may be in the range of 30 nm to 200 nm, but smaller and larger depths may also be employed.

[0061] Reference Figure 4A and Figure 4B, a gate dielectric (150, 250, 350, 450) may be formed in each device region. The gate dielectric (150, 250, 350, 450) may include a first gate dielectric 150 formed in the first device region 100, a second gate dielectric 250 formed in the second device region 200, a third gate dielectric 350 formed in the third device region 300, a fourth gate dielectric 450 formed in the fourth device region 400, and a fifth gate dielectric 150 formed in the fifth device region 500 (which may have the same material composition and the same thickness as the first gate dielectric 150). Thus, the fifth gate dielectric 150 in the fifth device region 500 may also be referred to as the first gate dielectric.

[0062] In an illustrative example, the gate dielectric (150, 250, 350, 450) may include thicker gate dielectrics (such as the first gate dielectric 150, the second gate dielectric 250, and the fourth gate dielectric 450) for forming high-voltage field-effect transistors, and thinner gate dielectrics (such as the third gate dielectric 350) for forming low-voltage field-effect transistors. The gate dielectric (150, 250, 350, 450) may include any gate dielectric material known in the art, such as silicon oxide. The thickness of each thicker gate dielectric may be in the range of 20 nm to 100 nm (such as 50 nm to 50 nm), but smaller and larger thicknesses may also be employed. The thickness of each thinner gate dielectric may be in the range of 1 nm to 10 nm (such as 2 nm to 8 nm), but smaller and larger thicknesses may also be employed.

[0063] Reference Figure 5A and Figure 5B, a semiconductor material such as polysilicon may be deposited over a semiconductor substrate 8 and a gate dielectric (150, 250, 350, 450), and may be patterned into semiconductor gate electrodes (151, 251, 351, 451). The semiconductor gate electrodes (151, 251, 351, 451) may be suitably doped with a dopant of a first conductivity type or a second conductivity type by in-situ doping or ex-situ doping (such as ion implantation after depositing the semiconductor material). In one embodiment, the semiconductor gate electrodes (151, 251, 351, 451) may have the same conductivity type (e.g., may include in-situ doped n-type polysilicon). In another embodiment, an ion implantation mask may be employed to provide different doping of the semiconductor gate electrodes (151, 251, 351, 451) between p-type field effect transistors and n-type field effect transistors. The semiconductor gate electrodes (151, 251, 351, 451) may include a first semiconductor gate electrode 151, a second semiconductor gate electrode 251, a third semiconductor gate electrode 351, a fourth semiconductor gate electrode 451, and a fifth semiconductor gate electrode 151 (which may have the same material composition as the first semiconductor gate electrode 151). The first semiconductor gate electrode 151 may be formed over the first gate dielectric 150, the second semiconductor gate electrode 251 may be formed over the second gate dielectric 250, the third semiconductor gate electrode 351 may be formed over the third gate dielectric 350, the fourth semiconductor gate electrode 451 may be formed over the fourth gate dielectric 450, and the fifth semiconductor gate electrode 151 may be formed over the fifth gate dielectric 150.

[0064] Reference Figure 6A and Figure 6B, at least one gate spacer layer (62L, 64L) may be conformally deposited over each semiconductor gate electrode (151, 251, 351, 451). In one embodiment, the at least one gate spacer layer (62L, 64L) may include a dielectric layer stack that includes a silicon oxide layer 62L having a first thickness and a silicon nitride layer 64L having a second thickness. Each of the silicon oxide layer 62L and the silicon nitride layer 64L may be deposited by a respective conformal deposition process (such as a low-pressure chemical vapor deposition (LPCVD) process). The first thickness may be in the range of 5 nm to 50 nm (such as 10 nm to 20 nm), and the second thickness may be in the range of 50 nm to 300 nm (such as 100 nm to 200 nm), although smaller and larger thicknesses may also be employed. Each vertical extension portion of the at least one gate spacer layer (62L, 64L) may have a lateral thickness LT. The lateral thickness LT may be the same as the sum of the first thickness and the second thickness. The lateral thickness LT may be in the range of 100 nm to 400 nm, although smaller and larger thicknesses may also be employed. Each horizontal extension portion of the at least one gate spacer layer (62L, 64L) may always have the same uniform thickness, which may be the same as or less than the lateral thickness LT.

[0065] Reference Figure 7A and Figure 7B , a photoresist layer 177 may be applied over the at least one gate spacer layer (62L, 64L) and may be lithographically patterned to cover a first region of the exemplary structure without covering a second region (which is complementary to the first region) of the exemplary structure. The portion of the photoresist layer 177 that is located in the second device region 200 may cover the entire region of the second device region except for: discrete regions that overlie the second-conductivity-type source extension region 232, discrete regions that overlie the second-conductivity-type drain extension region 242, and discrete regions that overlie the second semiconductor gate electrode 251.

[0066] In Figure 7A one embodiment shown, during patterning of the photoresist layer 177, the portion of the photoresist layer 177 that is located in the first device region 100 or the third device region 300 may be completely removed. In other words, the photoresist layer 177 may be completely removed from the first device region 100 and the third device region 300.

[0067] In Figure 7BIn one embodiment shown, the portion of the photoresist layer 177 located in the fifth device region 500 may be patterned such that: the patterned photoresist layer 177 does not cover any horizontally extending portion of at least one gate spacer layer (62L, 64L) that is outside the region surrounded by the outer sidewalls of the at least one gate spacer layer (such as the outer sidewall of the silicon nitride layer 64L), and the at least one gate spacer layer laterally surrounds the fifth semiconductor gate electrode 551 in the fifth device region. In this case, in a plan view such as a top view, the portion of the photoresist layer 177 located in the fifth device region 500 may cover the entire region of the fifth semiconductor gate electrode 551. Thus, in a plan view such as a top view, all sidewalls of the patterned portion of the photoresist layer 177 may be located within a frame-shaped region that is outside the inner sidewalls of the vertical extending portions of the at least one gate spacer layer (62L, 64L) and inside the outer sidewalls of the vertical extending portions of the at least one gate spacer layer (62L, 64L). The overlay tolerance of the position of the sidewalls of the patterned portion of the photoresist layer 177 in the fifth device region 500 may be the same as the lateral thickness LT.

[0068] In Figure 7B In one embodiment shown, the portion of the photoresist layer 177 located in the fourth device region 400 may be patterned to cover the entire second-conductivity-type drain extension region 442, except for discrete smaller regions therein, and to cover the portion of the fourth semiconductor gate electrode 451 that is close to the second-conductivity-type drain extension region 442, without covering the portion of the fourth semiconductor gate electrode 451 that is close to the second-conductivity-type source extension region 432. In this case, a laterally straight edge of the photoresist layer 177 that is perpendicular to the channel direction (i.e., the lateral separation direction between the second-conductivity-type drain extension region 442 and the second-conductivity-type source extension region 432) may be formed above the fourth semiconductor gate electrode 451.

[0069] The unmasked portion of at least one gate spacer layer (62L, 64L) can be anisotropically etched by performing at least one anisotropic etching process. For example, if at least one gate spacer layer (62L, 64L) includes a dielectric layer stack of a silicon oxide layer 62L and a silicon nitride layer 64L, a first anisotropic etching process can be performed to etch through the unmasked portion of the silicon nitride layer 64L, and a second anisotropic etching process can be performed to etch through the unmasked portion of the silicon oxide layer 62L. At least one gate spacer layer (62L, 64L) can be patterned into various gate sidewall spacers, including a first gate spacer 160 formed in a first device region 100, a second gate spacer 260 formed in a second device region 200, a third gate spacer 360 formed in a third device region 300, a fourth gate spacer 460 formed in a fourth device region 400, and a fifth gate spacer 560 formed in a fifth device region 500.

[0070] The second anisotropic etching process can also remove each portion of the gate dielectric (150, 250, 350, 450) that is not masked by the photoresist layer 177. Thus, the area of the gate dielectric (150, 250, 350, 450) can be the same as the combination of the area of the semiconductor gate electrode (151, 252, 351, 451) and the area of the gate spacers (160, 260, 360, 460, 560).

[0071] The first gate spacer 160 can include a dielectric layer stack of a first silicon oxide layer 162 and a first silicon nitride layer 164. The second gate spacer 260 can include a dielectric layer stack of a second silicon oxide layer 262 and a second silicon nitride layer 264. The third gate spacer 360 can include a dielectric layer stack of a third silicon oxide layer 362 and a third silicon nitride layer 364. The fourth gate spacer 460 can include a dielectric layer stack of a fourth silicon oxide layer 462 and a fourth silicon nitride layer 464. The fifth gate spacer 560 can include a dielectric layer stack of a fifth silicon oxide layer 562 and a fifth silicon nitride layer 564.

[0072] In one embodiment, the remainder of the first gate dielectric 150 (which may be located in the first device region 100 or the fifth device region 500) includes two first laterally straight sidewalls 150S that laterally extend over and cover the first active region extensions (131, 141) and are vertically coincident with the two first laterally straight outer sidewalls (160S, 560S) of the first gate spacers (160, 560). As used herein, a laterally straight surface refers to a surface that is straight in a planar view such as a top view. In one embodiment, the laterally straight bottom edge of the first laterally straight outer sidewall (160S, 560S) of the first gate spacers (160, 560) coincides with the top edge of the laterally straight sidewall of the first gate spacers (160, 560).

[0073] In one embodiment, the remainder of the second gate dielectric 250 includes two discrete gate dielectric openings 250O that are under the discrete gate spacer openings 260O in the second gate spacers 260 (which are the second patterned portions of the at least one gate spacer layer), cover the second active region extensions (232, 242), and are entirely within the region of the openings in the shallow trench isolation structure 20. The remainder of the second gate dielectric 250 laterally extends over and covers the shallow trench isolation structures 20. In one embodiment, the top edge of the pair of discrete gate dielectric openings 250O in the second gate dielectric 250 coincides with the bottom edge of the discrete gate spacer openings 260O in the second gate spacers 260.

[0074] In one embodiment, the remainder of the third gate dielectric 350 includes two laterally straight sidewalls that laterally extend over and cover the underlying portion of the first conductivity type semiconductor layer 11 and are vertically coincident with the two laterally straight outer sidewalls of the third gate spacers 360.

[0075] The remaining portion of the fourth gate dielectric 450 includes a laterally straight sidewall 450S that laterally extends over and covers a low-voltage active region extension in the fourth active region extension, such as the fourth source extension region 432, and is vertically coincident with a laterally straight outer sidewall 460S of the fourth gate spacer 460. This side of the field effect transistor may be the low-voltage side. The remaining portion of the fourth gate dielectric 450 further includes discrete gate dielectric openings 450O that are underlying a discrete gate spacer opening in the fourth gate spacer 460, which is referred to as the second gate spacer opening 460O, and cover a high-voltage active region extension in the fourth active region extension, such as the fourth drain extension region 442, and the shallow trench isolation structure 20. This side of the field effect transistor may be the high-voltage side.

[0076] Each of the first device region 100 and the fifth device region 500 may include: a first active region extension (such as the first active region extensions (131, 141) or the fifth active region extensions (531, 541)) that are laterally spaced apart from each other by a first semiconductor channel 152, such as a surface portion of a second conductivity type well 12; a first gate dielectric 150 that covers the first semiconductor channel 152; a first semiconductor gate electrode 151 that covers the first gate dielectric 150; and a first gate spacer (160, 560) having first laterally straight outer sidewalls (160S, 560S) that are spaced apart from the first semiconductor gate electrode 151 by a lateral thickness LT of the first gate spacer (160, 560), wherein the first laterally straight outer sidewalls (160S, 560S) have a first laterally straight bottom edge that coincides with a top edge of a first laterally straight sidewall 150S of the first gate dielectric 150. In one embodiment, the first active region extensions (such as the first active region extensions (131, 141) or the fifth active region extensions (531, 541)) are laterally spaced apart from each other along a first channel direction by the first semiconductor channel 152; and the first laterally straight outer sidewalls (160S, 560S) laterally and straightly extend along a horizontal direction perpendicular to the first channel direction.

[0077] The second device region 200 may include: second active region extensions (232, 242) that are laterally spaced apart from each other by a second semiconductor channel 252 (such as a surface portion of the first conductivity type semiconductor layer 11); a second gate dielectric 250 that overlies the second semiconductor channel 252 and the second active region extensions (232, 242) and includes a pair of discrete gate dielectric openings 250O that pass through the second gate dielectric and overlie a respective one of the second active region extensions (232, 242). The second gate spacer 260 includes a profile portion that overlies the second semiconductor gate electrode 251 and laterally surrounds the second semiconductor gate electrode, and the second gate spacer further includes horizontally extending portions that overlie the second active region extensions (232, 242) and include a pair of discrete gate spacer openings 260O that pass through the horizontally extending portions and overlie the second active region extensions (232, 242).

[0078] In one embodiment, the semiconductor structure further includes shallow trench isolation structures 20 that are located in an upper portion of the semiconductor substrate 8, include a first opening in a first device region (such as the first device region 100 or the fifth device region 500), and include a second opening in a second device region (such as the second device region 200), wherein the first opening laterally surrounds a first active region extension (such as the first active region extensions (131, 141) or the fifth active region extensions (531, 541)), and the second opening laterally surrounds the second active region extensions (232, 242). In one embodiment, each of the pair of discrete gate dielectric openings 250O is laterally offset from the shallow trench isolation structures 20 and has no area overlap with the shallow trench isolation structures in a top view.

[0079] In one embodiment, each of the pair of discrete gate dielectric openings 250O has a respective top perimeter that coincides with a bottom perimeter of a respective one of the pair of discrete gate spacer openings 260O of the second gate spacer 260. In one embodiment, each of the second active region extensions (232, 242) is laterally spaced from the second gate spacer 260 by a lateral spacing that is greater than a lateral thickness LT of the first gate spacers (160, 560).

[0080] The fourth device region 400 may include: fourth active region extensions (432, 442) that are laterally spaced apart from each other by a fourth semiconductor channel 452 (such as a surface portion of the first conductivity type semiconductor layer 11); a fourth gate dielectric 450 overlying the second semiconductor channel 452 and the fourth active region extensions (432, 442); and a fourth semiconductor gate electrode 451 overlying the fourth gate dielectric 450. The fourth gate dielectric 450 includes a second laterally straight sidewall 450S that is laterally spaced from the fourth semiconductor gate electrode 451 by a lateral thickness LT, and also includes a discrete gate dielectric opening 450O overlying one of the fourth active region extensions in the fourth active region extensions (such as the fourth drain extension region 442). In one embodiment, the fourth active region extensions (432, 442) are laterally spaced apart from each other by the second semiconductor channel 452 along a second channel direction; and the second laterally straight sidewall 450S extends laterally straight along a horizontal direction perpendicular to the second channel region.

[0081] In one embodiment, the semiconductor structure includes shallow trench isolation structures 20 that include additional openings (such as fourth openings) that laterally surround the fourth active region extensions (432, 442) in the fourth device region 400. In one embodiment, the discrete gate dielectric opening 450O is laterally offset from the shallow trench isolation structures 20 and does not overlap any regions with the shallow trench isolation structures in a top view.

[0082] In one embodiment, the semiconductor structure includes a fourth gate spacer 460. The fourth gate spacer 460 includes: a profile portion that overlies the fourth semiconductor gate electrode 451 and laterally surrounds the fourth semiconductor gate electrode; and a horizontally extending portion that overlies one of the second active region extensions in the second active region extensions 442 and includes a discrete gate spacer opening 460O. In one embodiment, the fourth gate spacer 460 includes a second laterally straight outer sidewall 460S that has a second laterally straight bottom edge that coincides with the top edge of the second laterally straight sidewall 450S of the fourth gate dielectric 450. In one embodiment, the discrete gate dielectric opening 450O has a top perimeter that coincides with the bottom perimeter of the discrete gate spacer opening 460O of the fourth gate spacer 460.

[0083] Subsequently, the photoresist layer 177 may be removed, for example, by ashing.

[0084] Reference Figure 8A and Figure 8B, a first patterned photoresist layer 171 may be formed over an exemplary structure to cover device regions where a second-conductivity-type (e.g., n-type) field-effect transistor is to be formed, without covering device regions where a first-conductivity-type (e.g., p-type) field-effect transistor is to be formed. The first-conductivity-type field-effect transistor is a transistor including an active region (i.e., source region and drain region) doped with a first conductivity type. The second-conductivity-type field-effect transistor is a transistor including an active region doped with a second conductivity type. In an illustrative example, the first patterned photoresist layer 171 covers the second device region 200, the third device region 300, and the fourth device region 400, and does not cover the first device region 100 or the fifth device region 500.

[0085] A first masking ion implantation process may be performed to implant a dopant of the first conductivity type into portions of the semiconductor substrate 8 that are not masked by the first patterned photoresist layer 171 or not masked by a combination of gate spacers (such as the first gate spacer 160 and the fifth gate spacer 560), semiconductor gate electrodes (such as the first semiconductor gate electrode 151 and the fifth semiconductor gate electrode 551), and gate dielectrics (150, 250, 350, 450).

[0086] A heavily doped first active region (133, 143) may be formed in the first active region extensions (131, 141) by using the first patterned photoresist layer 171 as a component of a first ion implantation mask structure to implant a dopant of the first conductivity type. By using the first semiconductor gate electrode 151 and the first gate spacers (160, 560) as components of the first ion implantation mask structure, a dopant of the first conductivity type may be implanted into the first active region extensions (131, 141) around the first gate spacers (160, 560).

[0087] In one embodiment, the first ion implantation mask structure includes the first patterned photoresist layer 171 that covers all regions of the second active region extensions (232, 242), the fourth active region extensions (432, 442), the second gate dielectric 250, the fourth gate dielectric 450, the second semiconductor gate electrode 251, and the fourth semiconductor gate electrode 451, and does not cover any regions of the first active region extension or the first semiconductor gate electrode 151.

[0088] The first active region (133, 143) may include a first source region 133 and a first drain region 143. An upper portion of the first semiconductor gate electrode 151 may be converted into a first conductivity type doped semiconductor gate electrode 153. A combination of the remaining portion of the first semiconductor gate electrode 151 including a second conductivity type doped semiconductor material and the first conductivity type doped semiconductor gate electrode 153 constitutes the first gate electrode 155.

[0089] According to one aspect of the present disclosure, an implantation depth of the first masking ion implantation process may be less than a thickness of the fifth gate spacer 560, which is a lateral thickness LT of each of the gate spacers (160, 260, 360, 460, 560). In this case, the fifth semiconductor gate electrode 551 may not be implanted with a dopant of the first conductivity type, which may be advantageously used to control a work function of the fifth semiconductor gate electrode 551. The implantation depth of the first masking ion implantation process may be the same as a vertical thickness of the first active region (133, 143) and may be in a range of 40 nm to 200 nm (such as 60 nm to 150 nm), but smaller and larger implantation depths may also be employed. Subsequently, the first patterned photoresist layer 171 may be removed, for example, by ashing.

[0090] Reference Figure 9A and Figure 9B , a second patterned photoresist layer 172 may be formed over the exemplary structure to cover a device region including a first conductivity type field effect transistor and not to cover a device region in which a second conductivity type field effect transistor is to be formed. In an illustrative example, the second patterned photoresist layer 172 covers the first device region 100 and the fifth device region 500 and does not cover the second device region 200, the third device region 300, or the fourth device region 400.

[0091] In one embodiment, the second patterned photoresist layer 172 covers the entirety of the first active region extensions (132, 141), the first gate electrode 151, and the fifth gate electrode 551 and does not cover the second active region extensions (232, 242, 432, 442).

[0092] A second masking ion implantation process may be performed to implant dopants of a second conductivity type into portions of the semiconductor substrate 8 that are not masked by the second patterned photoresist layer 172 or not masked by a combination of gate spacers (such as the second gate spacer 260, the third gate spacer 360, and the fourth gate spacer 460), semiconductor gate electrodes (such as the second semiconductor gate electrode 251, the third semiconductor gate electrode 351, and the fourth semiconductor gate electrode 451), and gate dielectrics (150, 250, 350, 450). Accordingly, the combination of the second patterned photoresist layer 172, the gate semiconductor gate electrodes (151, 251, 351, 451), the gate dielectrics (150, 250, 350, 450), and the gate spacers (160, 260, 360, 460, 560) may act as a second ion implantation mask structure for the second masking ion implantation process.

[0093] The heavily doped active regions (234, 244, 334, 344, 434, 444) may be formed by implanting dopants of a second conductivity type using the second patterned photoresist layer 172 as a component of a second ion implantation mask structure that is a composite ion implantation mask structure including a plurality of components. The dopants of the second conductivity type may be implanted into the second active region extensions (232, 242) through the pair of discrete gate dielectric openings 250O to form the second source region 234 and the second drain region 244. The dopants of the second conductivity type may be implanted into a portion of the semiconductor substrate 8 within the third device region 300 to form the third source region 334 and the third drain region 344. The dopants of the second conductivity type may be implanted into the region between the second lateral straight sidewall 450S and the edge of the shallow trench isolation structure 20 within the fourth device region 400 to form the fourth source region 434. The dopants of the second conductivity type may be implanted into the fourth drain extension region 442 through the discrete gate dielectric opening 450O to form the fourth drain region 444.

[0094] The upper portion of the second semiconductor gate electrode 251 may be additionally doped with dopants of the second conductivity type to form a second conductivity type heavily doped semiconductor gate electrode 253. The combination of the remaining portion of the second semiconductor gate electrode 251 including the second conductivity type doped semiconductor material and the second conductivity type heavily doped semiconductor gate electrode 253 constitutes the second gate electrode 255.

[0095] The upper portion of the third semiconductor gate electrode 351 may be additionally doped with dopants of the second conductivity type to form a second conductivity type heavily doped semiconductor gate electrode 353. The combination of the remaining portion of the third semiconductor gate electrode 351 including the second conductivity type doped semiconductor material and the second conductivity type doped semiconductor gate electrode 353 constitutes the third gate electrode 355.

[0096] The upper portion of the fourth semiconductor gate electrode 451 may be additionally doped with a dopant of a second conductivity type to form a second conductivity type heavily doped semiconductor gate electrode 453. The combination of the remaining portion of the fourth semiconductor gate electrode 451 including the second conductivity type doped semiconductor material and the second conductivity type doped semiconductor gate electrode 453 constitutes the fourth gate electrode 455.

[0097] The implantation depth of the second masked ion implantation process may be less than the sum of the thickness of each gate spacer (i.e., the lateral thickness LT of each gate spacer in the gate spacers (160, 260, 360, 460, 560)) and the thickness of the thick gate dielectric (such as the thicknesses of the first gate dielectric 150, the second gate dielectric 250, and the fourth gate dielectric 450). In this case, the lateral extent of each second active region (234, 244) may be the sum of the lateral dimension of the discrete gate dielectric opening 250O and twice the lateral straggle distance of the second masked ion implantation process. Similarly, the lateral extent of the fourth drain region 444 may be the sum of the lateral dimension of the discrete gate dielectric opening 450O and twice the lateral straggle distance of the second masked ion implantation process. The implantation depth of the first masked ion implantation process may be the same as the vertical thickness of the second active region (234, 244) and may be in the range of 40 nm to 300 nm (such as 60 nm to 200 nm), but smaller and larger implantation depths may also be employed. Subsequently, the second patterned photoresist layer 172 may be removed, for example, by ashing.

[0098] Reference Figures 10A to 10D , an exemplary structure after removing the second patterned photoresist layer 172 is illustrated. Although the channel direction of each field effect transistor in the field effect transistors is the first horizontal direction hd1, and all the lateral straight sidewalls of the gate spacers (160, 360, 460) spanning and contacting the corresponding underlying active regions (133, 143, 334, 344, 434) extend laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, embodiments in which the channel directions of the field effect transistors are independent of each other are explicitly contemplated herein.

[0099] Reference Figure 11A and Figure 11B, various metal-semiconductor alloy regions (136, 146, 236, 246, 336, 346, 436, 446, 156, 256, 356, 456) can be formed, for example, by depositing a metal layer or a metal alloy layer including at least one metal that forms a metal-semiconductor alloy (such as a metal silicide) over an exemplary structure. The metal layer or the metal alloy layer can include Ni, Pt, NiPt, Co, Ti, etc. An annealing process can be performed at an elevated temperature to induce the formation of the metal-semiconductor alloy regions (136, 146, 236, 246, 336, 346, 436, 446, 156, 256, 356, 456). The various metal-semiconductor alloy regions (136, 146, 236, 246, 336, 346, 436, 446, 156, 256, 356, 456) can include source-side metal-semiconductor alloy regions (136, 236, 336, 436), drain-side metal-semiconductor alloy regions (146, 246, 346, 446), and gate metal-semiconductor alloy regions (156, 256, 356, 456). Formation of the gate metal-semiconductor alloy region over the fifth gate electrode 551 covered by the spacer 560 can be omitted. The unreacted portion of the metal layer can be removed by performing a selective etching process that selectively etches the metal in the remaining portion of the metal layer with respect to the metal-semiconductor alloy material in the metal-semiconductor alloy regions (136, 146, 236, 246, 336, 346, 436, 446, 156, 256, 356, 456). In one embodiment, the metal-semiconductor alloy regions (136, 146, 236, 246, 336, 346, 436, 446, 156, 256, 356, 456) include and / or consist essentially of a metal silicide material (such as nickel silicide, platinum silicide, nickel platinum silicide, cobalt silicide, titanium silicide, etc.).

[0100] A first subset of the source-side metal-semiconductor alloy regions (136, 236, 336, 436) and the drain-side metal-semiconductor alloy regions (146, 246, 346, 446) may be in direct contact with the shallow trench isolation structure 20, and a second subset of the source-side metal-semiconductor alloy regions (136, 236, 336, 436) and the drain-side metal-semiconductor alloy regions (146, 246, 346, 446) may be laterally spaced apart from the shallow trench isolation structure 20. For example, the first source-side metal-semiconductor alloy region 136, the first drain-side metal-semiconductor alloy region 146, the third source-side metal-semiconductor alloy region 336, the third drain-side metal-semiconductor alloy region 346, and the fourth source-side metal-semiconductor alloy region 436 may be in direct contact with the shallow trench isolation structure 20. The second source-side metal-semiconductor alloy region 236, the second drain-side metal-semiconductor alloy region 246, and the fourth drain-side metal-semiconductor alloy region 446 may be laterally spaced apart from the shallow trench isolation structure 20.

[0101] Reference Figure 12A and Figure 12B , a planarized dielectric layer 70 may be deposited over the gate spacers (160, 260, 360, 460, 560) and may optionally be planarized to form a horizontal top surface. Contact via cavities may be formed through the planarized dielectric layer 70 to the top surface of a respective one of the metal-semiconductor alloy regions (136, 146, 236, 246, 336, 346, 436, 446, 156, 256, 356, 456). Additionally, additional contact via cavities may be formed through the planarized dielectric layer 70 and through a horizontal extension of the fifth gate spacer 560 to expose the top surface of the fifth gate electrode 551. At least one conductive material (such as a combination of a metal nitride liner material and a metal fill material) may be deposited in these contact via cavities. The excess portion of the at least one conductive material may be removed from above a horizontal plane including the top surface of the planarized dielectric layer 70. Each remaining portion of the at least one conductive material filling a respective one of the contact via cavities constitutes a contact via structure. These contact via structures include active region contact via structures (82, 88) and a gate contact via structure 85. The active region contact via structures (82, 88) include source-side contact via structures 82 contacting a respective one of the source-side metal-semiconductor alloy regions (136, 236, 336, 436), and drain-side contact via structures 88 contacting a respective one of the drain-side metal-semiconductor alloy regions (146, 246, 346, 446). The gate contact via structure 85 may contact a gate metal-semiconductor alloy region (156, 256, 356, 456), or may directly contact a semiconductor gate electrode, such as the fifth semiconductor gate electrode 551.

[0102] A high-voltage p-type field-effect transistor 100T is formed in the first device region 100. Another high-voltage p-type field-effect transistor 500T is formed in the fifth device region 500. A high-voltage n-type field-effect transistor 200T is formed in the second device region 200. The transistors 100T, 200T, and 500T can be used as word line switch transistors of a driver circuit of a memory device. A low-voltage n-type field-effect transistor 300T is formed in the third device region. An asymmetric low-voltage to high-voltage n-type field-effect transistor 400T is formed in the fourth device region 400. The transistor 400T can be used as a bit line hook-up transistor in a driver circuit of a memory device.

[0103] In one embodiment, each of the second active region contact via structures (82, 88) in the second device region 200 can vertically extend through a corresponding one of the pair of discrete gate dielectric openings 250O and can vertically extend through a corresponding one of the pair of discrete gate spacer openings 260O. In one embodiment, each of the second active region contact via structures (82, 88) can be laterally spaced from the corresponding discrete gate dielectric opening 250O and can be laterally spaced from the corresponding discrete gate spacer opening 260O.

[0104] In one embodiment, the fourth drain-side contact via structure 88 in the fourth device region 400 can vertically extend through the discrete gate dielectric opening 450O and can vertically extend through the discrete gate spacer opening 460O. In one embodiment, the fourth drain-side contact via structure 88 in the fourth device region 400 can be laterally spaced from the discrete gate dielectric opening 450O and can be laterally spaced from the discrete gate spacer opening 460O.

[0105] Reference Figure 13A and Figure 13B and, an alternative configuration of the exemplary structure can be obtained from the exemplary structure of Figure 12A and Figure 12B by omitting the formation of the source-side first-conductivity-type well 231 and the drain-side first-conductivity-type well 241 (e.g., halo regions) in the second device region 200.

[0106] Referring to all embodiments of the present disclosure, a semiconductor structure includes: a first field-effect transistor (100T, 500T) in a first device region (such as the first device region 100 or the fifth device region 500) above a substrate 8 and including: a first active region (133, 143) laterally spaced apart from each other by a first semiconductor channel 152; a first gate dielectric 150 overlying the first semiconductor channel 152; a first gate electrode (155 or 151) overlying the first gate dielectric 150; and a first gate spacer (160, 560) having a first laterally straight outer sidewall (160S, 560S) with a first laterally straight bottom edge coinciding with a top edge of a first laterally straight sidewall 150S of the first gate dielectric 150. The semiconductor structure further includes: a second field-effect transistor 200T in a second device region (such as the second device region 200) of the substrate 8 and including: a second active region (such as the second active region (234, 244)) laterally spaced apart from each other by a second semiconductor channel 252; a second gate dielectric 250 overlying the second semiconductor channel 252 and the second active region (such as the second active region (234, 244)) and including a pair of discrete gate dielectric openings 250O extending through the second gate dielectric and overlying a respective one of the second active regions (such as the second active region (234, 244)); and a second gate spacer 260 including: a profile portion overlying a portion of a top surface of the second gate electrode 255 and laterally surrounding the second gate electrode 255; and horizontally extending portions overlying the second active region (such as the second active region (234, 244)) and including a pair of discrete gate spacer openings 260O extending through the horizontally extending portions and overlying the pair of discrete gate dielectric openings 250O.

[0107] In one embodiment, the first active regions (133, 143) are laterally spaced apart from each other by the first semiconductor channel 152 along a first channel direction (such as a first horizontal direction hd1); and the first laterally straight outer sidewalls (160S, 560S) extend laterally straight along a horizontal direction (such as a second horizontal direction hd2) perpendicular to the first channel direction (such as the first horizontal direction hd1).

[0108] In one embodiment, the semiconductor structure further includes shallow trench isolation structures 20 that are located in an upper portion of the substrate 8, include a first opening in a first device region (such as the first device region 100 or the fifth device region 500), and include a second opening in a second device region (such as the second device region 200), where the first opening laterally surrounds a first active region (133, 143), and the second opening laterally surrounds a second active region (such as the second active region (234, 244)). In one embodiment, a horizontal extension portion of the second gate spacer 260 extends over and contacts a top surface section of the shallow trench isolation structure 20. In one embodiment, each of the pair of discrete gate dielectric openings 250O is laterally offset from the shallow trench isolation structure 20 and has no area overlap with the shallow trench isolation structures in a top view.

[0109] In one embodiment, each of the pair of discrete gate dielectric openings 250O of the semiconductor structure has a respective top perimeter that coincides with a bottom perimeter of a respective one of the pair of discrete gate spacer openings 260O of the second gate spacer 260.

[0110] In one embodiment, the semiconductor structure includes: a planarized dielectric layer 70 that overlies and contacts each of the first gate spacers (160, 560) and the second gate spacer 260; a first active region contact via structure (82, 88) that contacts the planarized dielectric layer 70 and is electrically connected to a respective one of the first active regions (133, 143); and a second active region contact via structure (82, 88) that contacts the planarized dielectric layer 70 and is electrically connected to a respective one of the second active regions (such as the second active regions (234, 244)). In one embodiment, each of the second active region contact via structures (82, 88) vertically extends through a respective one of the pair of discrete gate dielectric openings 250O and vertically extends through a respective one of the pair of discrete gate spacer openings 260O.

[0111] In one embodiment, the semiconductor structure includes: first metal-semiconductor alloy regions (136, 146) that contact respective ones of the first active regions (133, 143), respective ones of first laterally straight outer sidewalls (160S, 560S) of the first gate spacers (160, 560), and bottom surfaces of respective ones of the first active region contact via structures (82, 88); and second metal-semiconductor alloy regions (236, 246) that contact respective ones of second active regions (such as the second active regions (234, 244)), bottom perimeters of respective ones of the pair of discrete gate dielectric openings 250O, and bottom surfaces of respective ones of the second active region contact via structures (82, 88). In one embodiment, a third metal-semiconductor alloy region 254 is located in a top portion of the second gate electrode 255; and a gate contact via structure 85 extends through an opening in a profile portion of the second gate spacer 260 and contacts the third metal-semiconductor alloy region 254.

[0112] In one embodiment, the semiconductor structure includes shallow trench isolation structures 20 that are located in an upper portion of the substrate 8, wherein: the first metal-semiconductor alloy regions (136, 146) contact the shallow trench isolation structures 20; and the second metal-semiconductor alloy regions do not contact the shallow trench isolation structures 20. In one embodiment, each of the first gate spacers (160, 560) and the second gate spacer 260 includes a respective dielectric layer stack of a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layers in the first gate spacers (160, 560) and the second gate spacer 260 have the same first thickness, and the silicon nitride layers in the first gate spacers (160, 560) and the second gate spacer 260 have the same second thickness.

[0113] In one embodiment, the semiconductor structure includes a low-voltage third field-effect transistor 300T that is located in a third device region 300 of the substrate 8 and includes: third active regions (334, 344) that are laterally spaced apart from each other by a third semiconductor channel 352; and a third gate dielectric 350 that overlies the third semiconductor channel and the third active regions (334, 344) and has a thickness that is less than the thicknesses of the first gate dielectric 150 and the second gate dielectric 250.

[0114] Reference Figures 1B to 13BAnd additional embodiments of the present disclosure, a semiconductor structure includes: a first field effect transistor (100T, 500T) located in a first device region (such as, the first device region 100 or the fifth device region 500) above a substrate 8 and including: a first active region (133, 143) laterally spaced apart from each other by a first semiconductor channel 152; a first gate dielectric 150 overlying the first semiconductor channel 152; a first gate electrode (155 or 151) overlying the first gate dielectric 150; and a first gate spacer (160, 560) having a first laterally straight outer sidewall (160S, 560S) with a first laterally straight bottom edge coinciding with a top edge of a first laterally straight sidewall 150S of the first gate dielectric 150; and a second field effect transistor 400T located in a second device region (such as, the fourth device region 400) of the substrate 8 and including: a second active region (such as, the fourth active region (434, 444)) laterally spaced apart from each other by a second semiconductor channel 452; a second gate dielectric (such as, the fourth gate dielectric 450) overlying the second semiconductor channel 452 and the second active region (such as, the fourth active region (434, 444)); a second gate electrode (such as, the fourth gate electrode 455) overlying the second gate dielectric (such as, the fourth gate dielectric 450); and a second gate spacer 460. Refer to Figure 11B , the second gate spacer 460 includes a first portion 460A located on a first side (e.g., Figure 11B the left side in) of the second gate electrode 455 and having a second laterally straight outer sidewall with a first laterally straight bottom edge coinciding with a top edge of a second laterally straight sidewall of the second gate dielectric 450. The second gate spacer 460 further includes a second portion 460B located on a second side (e.g., Figure 11B the right side in) of the second gate electrode 455 and having: a profile portion overlying a part of a top surface of the second side of the second gate electrode 455 and laterally surrounding the second gate electrode 455; and a horizontally extending portion overlying one of the second active regions in the second active region 444 and including a discrete gate spacer opening 460O passing through the horizontally extending portion and overlying a discrete gate dielectric opening 450O passing through the second gate dielectric 450.

[0115] In one embodiment, the first active regions (133, 143) are laterally spaced apart from each other by a first semiconductor channel 152 along a first channel direction (such as a first horizontal direction hd1); and the first laterally straight outer sidewalls (160S, 560S) extend laterally straight along a horizontal direction (such as a second horizontal direction hd2) perpendicular to the first channel direction (such as the first horizontal direction hd1).

[0116] In one embodiment, the second active regions (such as the fourth active regions (434, 444)) are laterally spaced apart from each other by a second semiconductor channel 452 along a second channel direction (such as a first horizontal direction hd1); and the second laterally straight sidewalls 450S extend laterally straight along a horizontal direction (such as a second horizontal direction hd2) perpendicular to the second channel region.

[0117] In one embodiment, the semiconductor structure includes shallow trench isolation structures 20 located in an upper portion of the substrate 8, including a first opening in a first device region (such as the first device region 100 or the fifth device region 500) and including a second opening in a second device region (such as the fourth device region 400), wherein the first opening laterally surrounds the first active regions (133, 143), and the second opening laterally surrounds the second active regions (such as the fourth active regions (434, 444)). In one embodiment, a horizontal extension portion of the second gate spacer 460 extends above a top surface section of the shallow trench isolation structure 20. In one embodiment, the discrete gate dielectric openings 450O are laterally offset from the shallow trench isolation structures 20 and do not overlap any region with the shallow trench isolation structures in a top view.

[0118] In one embodiment, the discrete gate dielectric openings 450O have a top perimeter that coincides with a bottom perimeter of a discrete gate spacer opening (such as the second gate spacer opening 460O) of a second gate spacer (such as the fourth gate spacer 460).

[0119] In one embodiment, the semiconductor structure further includes: a planarized dielectric layer 70 that overlies and contacts each of the first gate spacers (160, 560) and the second gate spacers (such as the fourth gate spacer 460); first active region contact via structures (82, 88) that contact the planarized dielectric layer 70 and are electrically connected to a corresponding one of the first active regions (133, 143); and second active region contact via structures (82, 88) that contact the planarized dielectric layer 70 and are electrically connected to a corresponding one of the second active regions (such as the fourth active regions (434, 444)).

[0120] In one embodiment, the semiconductor structure includes: first metal-semiconductor alloy regions (136, 146) that contact respective ones of first active regions (133, 143), respective ones of first laterally straight outer sidewalls (160S, 560S) of first gate spacers (160, 560), and bottom surfaces of respective ones of first active region contact via structures (82, 88); and second metal-semiconductor alloy regions (436, 446) that contact respective ones of second active regions (such as fourth active regions (434, 444)) and bottom surfaces of respective ones of second active region contact via structures (82, 88). In one embodiment, the semiconductor structure includes shallow trench isolation structures 20 that are located in an upper portion of substrate 8, wherein: one of the second metal-semiconductor alloy regions in the first metal-semiconductor alloy regions (136, 146) and the second metal-semiconductor alloy region 436 contacts the shallow trench isolation structure 20; and the other second metal-semiconductor alloy region in the second metal-semiconductor alloy region 446 does not contact the shallow trench isolation structure 20.

[0121] In one embodiment, a third metal-semiconductor alloy region 456 is located in a top portion of second gate electrode 455; and a gate contact via structure 85 extends through the second gate spacer and contacts the third metal-semiconductor alloy region 456.

[0122] In one embodiment, each of the first gate spacers (160, 560) and the second gate spacers (such as fourth gate spacer 460) includes a respective dielectric layer stack of a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layers in the first gate spacers (160, 560) and the second gate spacers (such as fourth gate spacer 460) have the same first thickness, and the silicon nitride layers in the first gate spacers (160, 560) and the second gate spacers (such as fourth gate spacer 460) have the same second thickness.

[0123] In one embodiment, the semiconductor structure further includes: a third field effect transistor 200T located in a third device region (such as the second device region 200) of the substrate 8 and including: third active regions (such as the second active regions (234, 244)) that are laterally spaced apart from each other by a third semiconductor channel 252; a third gate dielectric (such as the second gate dielectric 250) that overlies the third semiconductor channel 252 and the third active regions (such as the second active regions (234, 244)) and includes a pair of additional discrete gate dielectric openings 250O that pass through the third gate dielectric and overlie a respective one of the third active regions; a third gate electrode 255 that overlies the third gate dielectric 250; and a third gate spacer (such as the second gate spacer 260) that includes: an additional profile portion that overlies a portion of the top surface of the third gate electrode 255 and laterally surrounds the third gate electrode 255; and additional horizontally extending portions that overlie the third active regions and include a pair of additional discrete gate spacer openings 260O that pass through the additional horizontally extending portions and overlie a pair of additional discrete gate dielectric openings 250O.

[0124] In one embodiment, the first and third field effect transistors (500T, 200T) include word line switch transistors of a peripheral circuit of a memory device; and the second field effect transistor 400T includes a bit line hook-up transistor of a peripheral circuit of the memory device.

[0125] The increased distance between the semiconductor channel and the silicon nitride portion due to the thick gate dielectric (e.g., layer 250) reduces electron trapping and increases the reliability of device characteristics. The embodiment devices can be fabricated with a fewer number of processing steps relative to previously known methods for fabricating high voltage transistors, and thus the manufacturing cost can be reduced. For example, during the fabrication of the devices of some embodiments of the present disclosure, the formation of an intermediate silicon oxide liner and / or an intermediate silicon nitride liner is not necessary.

[0126] The field effect transistors of embodiments of the present disclosure may include a metal silicide region having a larger lateral extent than an overlying contact via structure (e.g., a source or drain electrode). The non-self-aligned configuration between the metal silicide region and the electrode suppresses breakdown and junction leakage current at the non-self-aligned contact region. The metal silicide contact may provide enhanced input / output performance, while the non-self-aligned configuration of the contact structure may suppress transistor breakdown and junction leakage. In one embodiment, a silicon nitride gate spacer may be formed to at least partially cover a top surface of the gate electrode and at least partially block metallization of a semiconductor material in the semiconductor gate electrode. The vertical extension portion of the silicon nitride liner acts as an etch stop structure during patterning of the silicon nitride liner, and thus allows an overlap variation up to the thickness of the silicon nitride liner during patterning of the silicon nitride liner.

[0127] Active region extension (i.e., lightly doped drain) may provide the benefit of reduced voltage during high voltage operation and may reduce or prevent breakdown of the field effect transistor. By preventing the formation of a metal silicide portion directly on the active region extension, junction leakage can be avoided. The vertical extension portion of the silicon nitride liner may act as a buffer structure during patterning of an opening through the silicon nitride liner to inject dopants into the substrate. Thus, the device area loss due to the ion implantation process is minimized. In addition, by using the silicon nitride liner both as a gate spacer and as a silicide blocking layer, the total number of processing steps during fabrication of the field effect transistors of embodiments of the present disclosure can be reduced. A metallized gate electrode (such as a gate electrode for an n-type field effect transistor) can be used as a local interconnect structure. A non-metallized gate electrode for a p-type field effect transistor can be formed without injecting p-type dopants, and gate depletion for the p-type field effect transistor can be avoided.

[0128] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A semiconductor structure, the semiconductor structure comprising: A first field effect transistor located in a first device region of a substrate and comprising: a first active region laterally spaced apart from each other by a first semiconductor channel; a first gate dielectric overlying the first semiconductor channel; a first gate electrode overlying the first gate dielectric; and a first gate spacer having a first laterally straight outer sidewall having a first laterally straight bottom edge coinciding with a top edge of a first laterally straight sidewall of the first gate dielectric; and A second field effect transistor located in a second device region of the substrate and comprising: a second active region laterally spaced apart from each other by a second semiconductor channel; a second gate dielectric overlying the second semiconductor channel and the second active region and comprising a pair of discrete gate dielectric openings passing through the second gate dielectric and overlying a respective one of the second active regions; a second gate electrode overlying the second gate dielectric; and a second gate spacer comprising: A contour portion overlying a portion of a top surface of the second gate electrode and laterally surrounding the second gate electrode; and A horizontally extending portion overlying the second active region and comprising a pair of discrete gate spacer openings passing through the horizontally extending portion and overlying the pair of discrete gate dielectric openings.

2. The semiconductor structure according to claim 1, wherein: The first active regions are laterally spaced apart from each other by the first semiconductor channel along a first channel direction; and The first laterally straight outer sidewall extends laterally straight in a horizontal direction perpendicular to the first channel direction.

3. The semiconductor structure according to claim 1, the semiconductor structure further comprising a shallow trench isolation structure located in an upper portion of the substrate, including a first opening in the first device region and including a second opening in the second device region, wherein the first opening laterally surrounds the first active region, and the second opening laterally surrounds the second active region.

4. The semiconductor structure according to claim 3, wherein the horizontally extending portion of the second gate spacer extends over and contacts a top surface section of the shallow trench isolation structure.

5. The semiconductor structure according to claim 3, wherein each of the pair of discrete gate dielectric openings is laterally offset from the shallow trench isolation structure and has no area overlap with the shallow trench isolation structure in a top view.

6. The semiconductor structure according to claim 1, wherein each of the pair of discrete gate dielectric openings has a corresponding top perimeter that coincides with the bottom perimeter of a corresponding one of the pair of discrete gate spacer openings of the second gate spacer.

7. The semiconductor structure according to claim 1, further comprising a planarized dielectric layer that overlies and contacts each of the first gate spacer and the second gate spacer.

8. The semiconductor structure according to claim 7, further comprising: a first active region contact via structure that contacts the planarized dielectric layer and is electrically connected to a corresponding one of the first active regions; and a second active region contact via structure that contacts the planarized dielectric layer and is electrically connected to a corresponding one of the second active regions.

9. The semiconductor structure according to claim 8, wherein each of the second active region contact via structures vertically extends through a corresponding one of the pair of discrete gate dielectric openings and vertically extends through a corresponding one of the pair of discrete gate spacer openings.

10. The semiconductor structure according to claim 8, further comprising: a first metal-semiconductor alloy region that contacts a corresponding one of the first active regions, a corresponding one of the first laterally straight outer sidewalls of the first gate spacer, and a bottom surface of a corresponding one of the first active region contact via structures; and a second metal-semiconductor alloy region that contacts a corresponding one of the second active regions, a bottom perimeter of a corresponding one of the pair of discrete gate dielectric openings, and a bottom surface of a corresponding one of the second active region contact via structures.

11. The semiconductor structure according to claim 10, further comprising a shallow trench isolation structure located in an upper portion of the substrate, wherein: the first metal-semiconductor alloy region contacts the shallow trench isolation structure; and the second metal-semiconductor alloy region does not contact the shallow trench isolation structure.

12. The semiconductor structure according to claim 1, further comprising: a third metal-semiconductor alloy region located in a top portion of the second gate electrode; and a gate contact via structure that extends through an opening in the profile portion of the second gate spacer and contacts the third metal-semiconductor alloy region.

13. The semiconductor structure according to claim 1, wherein each of the first gate spacer and the second gate spacer includes a corresponding dielectric layer stack of a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer in the first gate spacer and the second gate spacer has the same first thickness, and the silicon nitride layer in the first gate spacer and the second gate spacer has the same second thickness.

14. The semiconductor structure according to claim 1, wherein the semiconductor structure further comprises a low-voltage third field-effect transistor, the low-voltage third field-effect transistor being located in a third device region of the substrate and comprising: A third active region, the third active regions being laterally spaced apart from each other by a third semiconductor channel; A third gate dielectric, the third gate dielectric overlying the third semiconductor channel and the third active region and having a thickness smaller than the thicknesses of the first gate dielectric and the second gate dielectric.

15. A method of forming a semiconductor structure, the method comprising: Forming a shallow trench isolation structure in an upper portion of a semiconductor substrate; Forming a first gate dielectric, a second gate dielectric, a first active region extension, and a second active region extension in the upper portion of the semiconductor substrate; Forming a first gate electrode and a second gate electrode over the first gate dielectric and the second gate dielectric, respectively; Conformally forming at least one gate spacer layer over the first gate electrode and the second gate electrode; And Patterning the at least one gate spacer layer, the first gate dielectric, and the second gate dielectric to form a first gate spacer and a second gate spacer, Wherein: The remaining portion of the first gate dielectric includes two first laterally straight sidewalls that laterally extend over and overlie the first active region extension and are vertically coincident with two first laterally straight outer sidewalls of the first gate spacer; and The remaining portion of the second gate dielectric includes two discrete gate dielectric openings that underlie discrete gate spacer openings in the second gate spacer, overlie the second active region extension, and are entirely within the region of the opening in the shallow trench isolation structure.

16. The method according to claim 15, the method further comprising: Forming a first active region by implanting a dopant of a first conductivity type in the first active region extension around the first gate spacer using the first gate electrode and the first gate spacer as components of a first ion implantation mask structure; And Forming a second active region by implanting a dopant of a second conductivity type in the second active region extension around the second gate spacer using the second gate spacer as a component of a second ion implantation mask structure.

17. The method according to claim 16, wherein the first ion implantation mask structure further comprises a first photoresist layer, the first photoresist layer covering all regions of the second active region extension, the second gate dielectric, and the second gate electrode, and not covering any regions of the first active region extension, the first gate dielectric, or the first gate electrode.

18. The method according to claim 17, wherein the second ion implantation mask structure further comprises a second photoresist layer, the second photoresist layer covering all regions of the first active region extension, the first gate dielectric, and the first gate electrode, and not covering any regions of the second active region extension, the second gate dielectric, or the second gate electrode.

19. The method according to claim 15, the method further comprising: forming a patterned photoresist layer over the at least one gate spacer layer, wherein the patterned photoresist layer comprises a pair of openings overlying the second active region extension; and anisotropically etching unmasked portions of the at least one gate spacer layer, the first gate dielectric, and the second gate dielectric.

20. The method according to claim 15, wherein: a transverse straight bottom edge of the first transverse straight outer sidewall of the first gate spacer coincides with a top edge of the first transverse straight sidewall of the first gate dielectric; and a top edge of the pair of discrete gate dielectric openings in the second gate dielectric coincides with a bottom edge of the discrete gate spacer openings in the second gate spacer.

21. A semiconductor structure, the semiconductor structure comprising: a first field effect transistor located in a first device region above a substrate and comprising: a first active region laterally spaced apart from each other by a first semiconductor channel; a first gate dielectric overlying the first semiconductor channel; a first gate electrode overlying the first gate dielectric; and a first gate spacer having a first transverse straight outer sidewall, the first transverse straight outer sidewall having a first transverse straight bottom edge coinciding with a top edge of the first transverse straight sidewall of the first gate dielectric; and a second field effect transistor located in a second device region of the substrate and comprising: a second active region laterally spaced apart from each other by a second semiconductor channel; a second gate dielectric overlying the second semiconductor channel and the second active region; a second gate electrode overlying the second gate dielectric; and a second gate spacer comprising: A first portion, the first portion being located on a first side of the second gate electrode and having a second laterally straight outer wall, the second laterally straight outer wall having a first laterally straight bottom edge that coincides with a top edge of a second laterally straight side wall of the second gate dielectric; and A second portion, the second portion being located on a second side of the second gate electrode and having: a contoured portion that overlies a portion of a top surface of the second side of the second gate electrode and laterally surrounds the second gate electrode; and a horizontally extending portion that overlies one of the second active regions in the second active region and includes discrete gate spacer openings that pass through the horizontally extending portion and overlie discrete gate dielectric openings that pass through the second gate dielectric.

22. The semiconductor structure according to claim 21, wherein: The first active regions are laterally spaced apart from each other by the first semiconductor channels along a first channel direction; and The first laterally straight outer wall extends laterally straight along a horizontal direction perpendicular to the first channel direction.

23. The semiconductor structure according to claim 21, wherein: The second active regions are laterally spaced apart from each other by the second semiconductor channels along a second channel direction; and The second laterally straight outer wall extends laterally straight along a horizontal direction perpendicular to the second channel region.

24. The semiconductor structure according to claim 21, the semiconductor structure further comprising a shallow trench isolation structure located in an upper portion of the substrate, including a first opening in the first device region and including a second opening in the second device region, wherein the first opening laterally surrounds the first active region, and the second opening laterally surrounds the second active region.

25. The semiconductor structure according to claim 24, wherein the horizontally extending portion of the second gate spacer extends above a top surface section of the shallow trench isolation structure.

26. The semiconductor structure according to claim 24, wherein the discrete gate dielectric openings are laterally offset from the shallow trench isolation structure and do not overlap any region of the shallow trench isolation structure in a top view.

27. The semiconductor structure according to claim 21, wherein the discrete gate dielectric openings have a top perimeter that coincides with a bottom perimeter of the discrete gate spacer openings of the second gate spacer.

28. The semiconductor structure according to claim 21, the semiconductor structure further comprising: A planarized dielectric layer that overlies each of the first gate spacer and the second gate spacer and contacts each of them; A first active region contact via structure that contacts the planarized dielectric layer and is electrically connected to a corresponding one of the first active regions; and A second active region contact via structure that contacts the planarized dielectric layer and is electrically connected to a corresponding one of the second active regions.

29. The semiconductor structure according to claim 28, further comprising: A first metal-semiconductor alloy region that contacts a corresponding one of the first active regions, a corresponding one of the first laterally straight outer sidewalls of the first gate spacer, and a bottom surface of a corresponding one of the first active region contact via structures; and A second metal-semiconductor alloy region that contacts a corresponding one of the second active regions and a bottom surface of a corresponding one of the second active region contact via structures.

30. The semiconductor structure according to claim 29, further comprising a shallow trench isolation structure located in an upper portion of the substrate, wherein: One of the first metal-semiconductor alloy region and the second metal-semiconductor alloy region contacts the shallow trench isolation structure; and The other of the second metal-semiconductor alloy regions does not contact the shallow trench isolation structure.

31. The semiconductor structure according to claim 29, further comprising: A third metal-semiconductor alloy region located in a top portion of the second gate electrode; and A gate contact via structure that extends through the second gate spacer and contacts the third metal-semiconductor alloy region.

32. The semiconductor structure according to claim 21, wherein each of the first gate spacer and the second gate spacer comprises a corresponding dielectric layer stack of a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer in the first gate spacer and the second gate spacer has the same first thickness, and the silicon nitride layer in the first gate spacer and the second gate spacer has the same second thickness.

33. The semiconductor structure according to claim 21, wherein the semiconductor structure further includes a third field effect transistor located in a third device region of the substrate and including: A third active region that is laterally spaced apart from each other by a third semiconductor channel; A third gate dielectric that overlies the third semiconductor channel and the third active region and includes a pair of additional discrete gate dielectric openings that pass through the third gate dielectric and overlie a corresponding one of the third active regions; A third gate electrode that overlies the third gate dielectric; and a third gate spacer.

34. The semiconductor structure according to claim 33, wherein the third gate spacer comprises: An additional profile portion that overlies a portion of a top surface of the third gate electrode and laterally surrounds the third gate electrode; and An additional horizontal extension portion that overlies the third active region and includes a pair of additional discrete gate spacer openings that pass through the additional horizontal extension portion and overlie the pair of additional discrete gate dielectric openings.

35. The semiconductor structure according to claim 33, wherein: The first field effect transistor and the third field effect transistor include word line switch transistors of a peripheral circuit of a memory device; and The second field effect transistor includes a bit line hook-up transistor of the peripheral circuit of the memory device.

36. A method of forming a semiconductor structure, the method comprising: Forming a shallow trench isolation structure in an upper portion of a semiconductor substrate; Forming a first gate dielectric, a second gate dielectric, a first active region extension, and a second active region extension in the upper portion of the semiconductor substrate; Forming a first gate electrode and a second gate electrode over the first gate dielectric and the second gate dielectric, respectively; Conformally forming at least one gate spacer layer over the first gate electrode and the second gate electrode; And Patterning the at least one gate spacer layer, the first gate dielectric, and the second gate dielectric to form a first gate spacer and a second gate spacer, Wherein: The remaining portion of the first gate dielectric includes two first laterally straight sidewalls that laterally extend over and overlie the first active region extension and are vertically aligned with two first laterally straight outer sidewalls of the first gate spacer; and The remaining portion of the second gate dielectric includes: A second laterally straight sidewall that laterally extends over and overlies one of the second active region extensions in the second active region extension and is vertically aligned with a second laterally straight outer sidewall of the second gate spacer; and A discrete gate dielectric opening that underlies a discrete gate spacer opening in the second gate spacer and overlies the other second active region extension in the second active region extension.

37. The method according to claim 36, the method further comprising forming a first patterned photoresist layer over the at least one gate spacer layer, wherein the first patterned photoresist layer covers the entirety of the second active region extension, the second gate dielectric, and the second gate electrode.

38. The method according to claim 37, the method further comprising forming a first active region in the first active region extension by implanting a dopant of a first conductivity type using the first patterned photoresist layer as a component of a first ion implantation mask structure.

39. The method according to claim 38, the method further comprising forming a second patterned photoresist layer over the at least one gate spacer layer, wherein the second patterned photoresist layer covers the entirety of the first active region extension, the first gate dielectric, and the first gate electrode, and does not cover the second active region extension.

40. The method according to claim 39, the method further comprising forming a second active region in the second active region extension by using the second patterned photoresist layer as a component of a second ion implantation mask structure to implant dopants of a second conductivity type.

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