Railway signal interlocking equipment fault detection method and system

Abstract

The invention provides a railway signal interlocking equipment fault detection method and system, and relates to the technical field of railway power grids, and the method comprises the steps: obtaining a wiring drawing at the starting moment of a detection period; acquiring drawing information according to the wiring drawing; determining a terminal wiring fault detection score according to the drawing information; acquiring hardware state parameters at a plurality of moments in the detection period; determining an equipment hardware fault detection score according to the hardware state parameters; acquiring logic communication parameters at a plurality of moments in the detection period; determining a logic communication fault detection score according to the logic communication parameters; and generating an equipment fault detection report according to the terminal wiring fault detection score, the equipment hardware fault detection score and the logic communication fault detection score. According to the signal interlocking equipment fault detection method and device, the terminal wiring fault condition, the hardware fault condition and the logic communication fault condition can be detected, and the comprehensiveness and accuracy of signal interlocking equipment fault detection are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of railway power grids, and particularly to a method and a system for detecting faults in railway signal interlocking equipment. Background Art

[0002] In the related art, the fault detection of railway signal interlocking equipment mainly relies on manual inspection by security inspectors. That is, it mainly depends on human factors. The workload of the security inspection work is extremely large. Therefore, relying too much on human factors may make it difficult to accurately detect potential safety hazards, resulting in low efficiency in the fault detection of railway signal interlocking equipment.

[0003] The information disclosed in the background art part of the present application is only intended to deepen the understanding of the general background art of the present application, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0004] The present invention provides a method and a system for detecting faults in railway signal interlocking equipment, which can solve the technical problem that relying too much on human factors may make it difficult to accurately detect potential safety hazards, resulting in low efficiency in the fault detection of railway signal interlocking equipment.

[0005] According to a first aspect of the present invention, there is provided a method for detecting faults in railway signal interlocking equipment, including:

[0006] At the start moment of the detection period, obtain a wiring diagram;

[0007] According to the wiring diagram, obtain drawing information;

[0008] According to the drawing information, determine a terminal wiring fault detection score;

[0009] At multiple moments during the detection period, obtain hardware status parameters;

[0010] According to the hardware status parameters, determine an equipment hardware fault detection score;

[0011] At multiple moments during the detection period, obtain logical communication parameters;

[0012] According to the logical communication parameters, determine a logical communication fault detection score;

[0013] According to the terminal wiring fault detection score, the equipment hardware fault detection score, and the logical communication fault detection score, generate an equipment fault detection report.

[0014] According to the present invention, obtaining drawing information according to the wiring diagram includes:

[0015] Determine recognizable formatted data according to the wiring diagram;

[0016] Determine the cable ID according to the recognizable formatted data;

[0017] Determine the cable starting terminal number and the cable ending terminal number according to the recognizable formatted data;

[0018] Determine a list of legal terminal numbers according to the recognizable formatted data.

[0019] According to the present invention, determine the terminal wiring fault detection score according to the drawing information, including:

[0020] Determine the missing terminal numbers according to the cable starting terminal number, the cable ending terminal number and the list of legal terminal numbers;

[0021] Determine the quantity of the missing terminal numbers;

[0022] Determine the single - end error fault detection score according to the quantity of the missing terminal numbers;

[0023] Determine the double - end error fault detection score according to the cable ID, the cable starting terminal number and the cable ending terminal number;

[0024] Determine the terminal wiring fault detection score according to the single - end error fault detection score and the double - end error fault detection score.

[0025] According to the present invention, determine the double - end error fault detection score according to the cable ID, the cable starting terminal number and the cable ending terminal number, including:

[0026] Determine the same cables according to the cable ID;

[0027] Determine the cable starting terminal number and the cable ending terminal number of the same cables;

[0028] Determine the double - end error fault detection score according to the cable starting terminal number and the cable ending terminal number of the same cables.

[0029] According to the present invention, determine the equipment hardware fault detection score according to the hardware state parameters, including:

[0030] Determine the track circuit frequency, the track circuit impedance value, the power supply voltage and the equipment current according to the hardware state parameters;

[0031] Obtain maintenance information, wherein the maintenance information includes: the number of maintenance times and the most recent maintenance time;

[0032] Input the track circuit frequency, the track circuit impedance value, the power supply voltage, the device current, the number of repairs, and the most recent repair time into the trained fault occurrence prediction model to determine the predicted fault occurrence time;

[0033] Determine the device hardware fault detection score according to the predicted fault occurrence time.

[0034] According to the present invention, the training steps of the fault occurrence prediction model include:

[0035] Obtain the historical hardware state parameters and historical repair information of other signal interlocking devices in the historical detection period. Among them, the historical hardware state parameters include: historical track circuit frequency, historical track circuit impedance value, historical power supply voltage, and historical device current, and the historical repair information includes: the number of historical repairs and the most recent historical repair time;

[0036] Input the historical hardware state parameters and the historical repair information into the fault occurrence prediction model to determine the sample predicted fault occurrence time;

[0037] Obtain the historical fault occurrence time of other signal interlocking devices in the historical detection period;

[0038] Determine the training loss function of the fault occurrence prediction model according to the sample predicted fault occurrence time, the historical fault occurrence time, the historical hardware state parameters, and the historical repair information;

[0039] Train the fault occurrence prediction model according to the training loss function of the fault occurrence prediction model to obtain the trained fault occurrence prediction model.

[0040] According to the present invention, determining the training loss function of the fault occurrence prediction model according to the sample predicted fault occurrence time, the historical fault occurrence time, the historical hardware state parameters, and the historical repair information includes: According to the formula , Determine the training loss function of the fault occurrence prediction model , where is the sample predicted fault occurrence time of the kth other signal interlocking device in the ith historical detection period, is the historical fault occurrence time of the kth other signal interlocking device in the ith historical detection period, is the historical track circuit frequency of the kth other signal interlocking device in the ith historical detection period, is the preset track circuit frequency threshold, is the historical track circuit impedance value of the kth other signal interlocking device in the ith historical detection period, is the preset track circuit impedance threshold value, is the historical power supply voltage of the k-th other signal interlocking device in the i-th historical detection period, is the preset power supply voltage threshold value, is the historical device current of the k-th other signal interlocking device in the i-th historical detection period, is the preset device current threshold value, is the historical maintenance times of the k-th other signal interlocking device, is the preset maintenance times threshold value, is the historical latest maintenance time of the k-th other signal interlocking device, is the preset maintenance time threshold value, K is the number of other signal interlocking devices, n is the number of historical detection periods, k ≤ K, i ≤ n, and k, K, i, and n are all positive integers.

[0041] According to the present invention, according to the predicted fault occurrence time, determining the device hardware fault detection score includes: According to the formula , determining the device hardware fault detection score , where if is a conditional function, is the predicted fault occurrence time, is the preset fault occurrence time threshold value.

[0042] According to the present invention, according to the logical communication parameters, determining the logical communication fault detection score includes:

[0043] Determining the log information and communication parameters according to the logical communication parameters;

[0044] Determining the locking event trigger record and unlocking event trigger record according to the log information;

[0045] Determining the logical fault detection result according to the locking event trigger record and the unlocking event trigger record;

[0046] Determining the transmission delay and bit error rate according to the communication parameters;

[0047] Determining the communication fault detection result according to the transmission delay and the bit error rate;

[0048] Determining the logical communication fault detection score according to the logical fault detection result and the communication fault detection result.

[0049] According to the second aspect of the present invention, providing a railway signal interlocking device fault detection system, including:

[0050] The wiring diagram module is used to obtain the wiring diagram at the start moment of the detection cycle;

[0051] The drawing information module is used to obtain drawing information according to the wiring diagram;

[0052] The wiring fault module is used to determine the terminal wiring fault detection score according to the drawing information;

[0053] The hardware parameter module is used to obtain the hardware status parameters at multiple moments during the detection cycle;

[0054] The hardware fault module is used to determine the equipment hardware fault detection score according to the hardware status parameters;

[0055] The software parameter module is used to obtain the logical communication parameters at multiple moments during the detection cycle;

[0056] The software fault module is used to determine the logical communication fault detection score according to the logical communication parameters;

[0057] The detection report module is used to generate an equipment fault detection report according to the terminal wiring fault detection score, the equipment hardware fault detection score, and the logical communication fault detection score.

[0058] Technical effects: According to the present invention, the wiring diagram of the railway can be accurately obtained, and the hardware state parameters and logical communication parameters of the signal interlocking device can be monitored. Further, according to the wiring diagram, the terminal wiring fault condition is detected, according to the hardware state parameters, the hardware fault condition is detected, and according to the logical communication parameters, the logical communication fault condition is detected, improving the comprehensiveness and accuracy of the signal interlocking device fault detection. Moreover, during the process of obtaining the wiring diagram, the railway signal interlocking drawing resources are re-integrated, and all relevant drawings are integrated into a unified and standard electronic document or system, realizing the construction of a drawing management system from individual functional nodes to dominant functional nodes and then to full-process functional nodes, forming an integrated management of drawing resources, achieving structural innovation, realizing the transformation from paper resources to digital resources, promoting the transformation from single to big data direction, completing data innovation, improving the accuracy and efficiency of work, and significantly improving the efficiency of drawing integration and verification, reducing errors in manual operations, providing strong technical support for the maintenance and management of railway signal equipment. When determining the training loss function of the fault occurrence prediction model, the training loss function of the fault occurrence prediction model can be determined according to the sample predicted fault occurrence time, historical fault occurrence time, historical hardware state parameters, and historical maintenance information. During the calculation process, according to the possible influence of the track circuit frequency, track circuit impedance value, power supply voltage, device current, maintenance times, and the most recent maintenance time on the occurrence of faults in the signal interlocking device, the influence of the above data on the error of the sample predicted fault occurrence time is determined, and based on this influence and the relative error of the sample predicted fault occurrence time, the training loss function is set, so that during the training process of the fault occurrence prediction model, the training loss function is reduced, and the accuracy of the fault occurrence prediction model is more targeted improved. When determining the equipment hardware fault detection score, the equipment hardware fault detection score can be determined according to the predicted fault occurrence time. During the calculation process, according to the predicted fault occurrence time, the operating condition of the hardware device is evaluated, improving the accuracy of the equipment hardware fault detection score.

[0059] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present invention. According to the following detailed description of the exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present invention will be clearer. Brief Description of the Drawings

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings;

[0061] Figure 1 Exemplarily shown is a schematic flowchart of a method for detecting faults in a railway signal interlocking device according to an embodiment of the present invention;

[0062] Figure 2 Exemplarily shown is a flowchart of obtaining drawing information according to an embodiment of the present invention;

[0063] Figure 3 Exemplarily shown is a flowchart of calculating a fault detection score for terminal wiring according to an embodiment of the present invention;

[0064] Figure 4 Exemplarily shown is a flowchart of calculating a fault detection score for device hardware according to an embodiment of the present invention;

[0065] Figure 5 Exemplarily shown is a flowchart of calculating a fault detection score for logical communication according to an embodiment of the present invention;

[0066] Figure 6 Exemplarily shown is a block diagram of a railway signal interlocking device fault detection system according to an embodiment of the present invention. Detailed implementation manners

[0067] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only some, rather than all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0068] The technical solutions of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0069] Figure 1 Exemplarily shown is a schematic flowchart of a method for detecting faults in a railway signal interlocking device according to an embodiment of the present invention. The method includes:

[0070] Step S1, at the start moment of the detection period, obtain a wiring diagram;

[0071] Step S2, according to the wiring diagram, obtain drawing information;

[0072] Step S3, according to the drawing information, determine a fault detection score for terminal wiring;

[0073] Step S4, at multiple moments in the detection period, obtain hardware state parameters;

[0074] Step S5: Determine the device hardware fault detection score according to the hardware status parameters.

[0075] Step S6: Obtain logical communication parameters at multiple moments during the detection period.

[0076] Step S7: Determine the logical communication fault detection score according to the logical communication parameters.

[0077] Step S8: Generate a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score, and the logical communication fault detection score.

[0078] According to the railway signal interlocking device fault detection method of the embodiment of the present invention, the wiring diagram of the railway can be accurately obtained, and the hardware status parameters and logical communication parameters of the signal interlocking device can be monitored. Further, the terminal wiring fault condition is detected according to the wiring diagram, the hardware fault condition is detected according to the hardware status parameters, and the logical communication fault condition is detected according to the logical communication parameters, improving the comprehensiveness and accuracy of the signal interlocking device fault detection. Moreover, during the process of obtaining the wiring diagram, the railway signal interlocking drawing resources are re-integrated, and all relevant drawings are integrated into a unified and standard electronic document or system, realizing the construction of a drawing management system from individual functional nodes to dominant functional nodes and then to full-course functional nodes, forming an integrated management of drawing resources, realizing structural innovation, realizing the transformation from paper resources to digital resources, promoting the transformation from single to big data, completing data innovation, improving the accuracy and efficiency of work, and greatly improving the efficiency of drawing integration and verification, reducing errors in manual operations, providing strong technical support for the maintenance and management of railway signal equipment.

[0079] According to an embodiment of the present invention, in step S1, obtain the wiring diagram at the start moment of the detection period.

[0080] For example, in order to quickly obtain the corresponding wiring diagrams and ensure the information security of the wiring diagrams, the refined management of the access rights of internal users of railway signals is carried out, and a centralized drawing management platform for railway signal equipment is established. Among them, the specific measures for refined management are to effectively control the access of users to various functions and data of the system by setting different levels of user roles and corresponding permissions. This not only ensures the security of sensitive information and key operations, but also enables users in each railway department to focus on the work within their respective responsibilities, improving work efficiency. The drawing management platform can effectively integrate and store various types of wiring diagrams, including but not limited to zero-layer wiring diagrams, side wiring diagrams, and distribution panel wiring diagrams. Functions such as keyword search and drawing type filtering can be used to enable users to quickly and accurately locate and retrieve the required diagrams. Through this drawing management platform, wiring diagrams in different formats corresponding to the railway signal interlocking equipment can be obtained. At the same time, the drawing management platform provides a convenient function for batch exporting railway signal interlocking diagrams, that is, integrating the diagrams and batch exporting them into a unified and standard electronic document or system. Users can select the types and ranges of diagrams to be exported, and the system will automatically generate the integrated diagram file. The exported diagram format is xls format, which is convenient for subsequent distribution, printing, or further processing in other design software. The workflow for exporting the unified electronic document can be summarized into the following stages: First, different types of diagrams such as zero-layer wiring diagrams, side wiring diagrams, and distribution panel wiring diagrams are input into the system and converted into a unified standardized template; then, the system exports the standardized diagrams as data files in a specific format and imports them into the core database. Next, the system uses intelligent algorithms to integrate the wiring data of different specifications, generating a complete and accurate electronic document for each station yard. On this basis, the diagrams after major repairs and intermediate repairs can also be updated and modified immediately to ensure the accuracy and timeliness of the diagrams. The latest diagrams of each station can be viewed in real time at the dispatching terminal to meet the needs of emergency handling.

[0081] According to an embodiment of the present invention, in step S2, drawing information is obtained according to the wiring diagram.

[0082] Figure 2 Exemplarily, a flowchart of obtaining drawing information according to an embodiment of the present invention is shown.

[0083] According to an embodiment of the present invention, step S2 includes:

[0084] Step S21, determining recognizable formatted data according to the wiring diagram;

[0085] Step S22, determining the cable ID according to the recognizable formatted data;

[0086] Step S23: Determine the cable starting terminal number and the cable ending terminal number according to the recognizable formatted data;

[0087] Step S24: Determine the list of legal terminal numbers according to the recognizable formatted data.

[0088] For example, convert wiring diagrams in different formats (such as DWG, PDF, Excel wiring tables) into structured data recognizable by the system (such as JSON, SQL database) through a parser to ensure unified naming of fields; the cables in the wiring diagram have corresponding IDs, query the cable ID in the recognizable formatted data converted from the wiring diagram; query the cable starting terminal number and the cable ending terminal number in the recognizable formatted data. For example, the starting terminal number of cable A is "X1-3" and the ending terminal number is "X5-8"; query all the existing terminals in the design drawing in the recognizable formatted data, and determine the list of legal terminal numbers according to the numbers of all the existing terminals.

[0089] According to an embodiment of the present invention, in step S3, determine the terminal wiring fault detection score according to the drawing information.

[0090] Figure 3 Exemplarily show the flowchart of the calculation of the terminal wiring fault detection score according to the embodiment of the present invention.

[0091] According to an embodiment of the present invention, step S3 includes:

[0092] Step S31: Determine the missing terminal numbers according to the cable starting terminal number, the cable ending terminal number, and the list of legal terminal numbers;

[0093] Step S32: Determine the number of the missing terminal numbers;

[0094] Step S33: Determine the single-end error fault detection score according to the number of the missing terminal numbers;

[0095] Step S34: Determine the double-end error fault detection score according to the cable ID, the cable starting terminal number, and the cable ending terminal number;

[0096] Step S35: Determine the terminal wiring fault detection score according to the single-end error fault detection score and the double-end error fault detection score.

[0097] For example, check whether the cable starting terminal number and the cable ending terminal number of each cable are in the legal terminal number list. If not, they are regarded as missing terminals, and the numbers of the missing terminals, i.e., the missing terminal numbers, are determined; determine the number of missing terminal numbers; if the number of missing terminal numbers is greater than 0, the single-end error fault detection score is 0; if the number of missing terminal numbers is equal to 0, the single-end error fault detection score is 1. If the starting or ending terminal of a cable is not defined in the drawing, it may be wrongly connected to other terminals, resulting in short circuits, signal logic chaos, or even train operation accidents; according to the cable ID, the cable starting terminal number, and the cable ending terminal number, determine whether there is a double-end error and determine the double-end error fault detection score. If there is a double-end error, the double-end error fault detection score is 0; if there is no double-end error, the double-end error fault detection score is 2; according to the sum of the single-end error fault detection score and the double-end error fault detection score, determine the terminal wiring fault detection score. By calculating the terminal wiring fault detection score, the wiring drawing can be intelligently checked to automatically check whether the connections between terminals are correct. When the terminal wiring fault detection score is less than 3, it indicates that there is a single-end error or double-end inconsistency in the terminals, and a prompt can be automatically generated to highlight the incorrect wiring and prompt the details of the drawing modification. The drawing modification details contain the location information of the integrated drawing and the specific name of the integrated drawing, which is convenient for finding specific errors and modifying the drawing. Moreover, for the wiring design of newly built signal stations on railways, a comprehensive consistency check can be performed, and the wiring diagrams of different systems and parts can be analyzed to identify potential inconsistencies, such as inconsistent terminal numbers and incorrect wiring sequences. Through automated checking, problems in the design can be timely discovered and corrected to ensure the coordination and consistency of the wiring information of each part.

[0098] According to an embodiment of the present invention, step S34 includes:

[0099] Step S341, determine the same cable according to the cable ID;

[0100] Step S342, determine the cable starting terminal number and the cable ending terminal number of the same cable;

[0101] Step S343, determine the double-end error fault detection score according to the cable starting terminal number and the cable ending terminal number of the same cable.

[0102] For example, according to the cable ID, the same cable in different wiring diagrams is determined. For example, cable A appears in both the power supply diagram and the interlocking diagram at the same time; the cable start terminal number and the cable end terminal number of the same cable in different wiring diagrams are determined. For example, the cable start terminal number and the cable end terminal number of cable A in the power supply diagram and the interlocking diagram are determined respectively; it is judged whether the cable start terminal number and the cable end terminal number of the same cable match. If there is a mismatch, it indicates that there is a conflict in the cross-diagram definition of the cable (for example, cable W001 is connected to X1-3→X2-5 in the power supply diagram, but is connected to X1-3→X3-2 in the interlocking diagram), which may cause signal misoperation or equipment damage, and the double-end error fault detection score is 0. If there is no mismatch, the double-end error fault detection score is 2.

[0103] According to an embodiment of the present invention, in step S4, at multiple moments in the detection period, the hardware state parameters are obtained.

[0104] For example, through professional detection equipment (such as a digital multimeter and a track circuit analyzer), railway signal interlocking equipment (such as a track circuit, a system power supply, and a switch motor) is detected to obtain hardware state parameters (such as a track circuit frequency and a track circuit impedance). Among them, the hardware state parameter is the average value of the railway signal interlocking equipment in the detection period. For example, the track circuit frequency in the first detection period is the average value of the track circuit frequencies at multiple moments in the first detection period.

[0105] According to an embodiment of the present invention, in step S5, the equipment hardware fault detection score can be determined. During the process of determining the equipment hardware fault detection score, the time when the signal interlocking equipment fails predicted by the trained fault occurrence prediction model can be used, and according to the predicted time when the signal interlocking equipment fails, the equipment hardware fault detection score is determined.

[0106] According to an embodiment of the present invention, the training steps of the fault occurrence prediction model include:

[0107] Obtain the historical hardware state parameters and historical maintenance information of other signal interlocking equipment in the historical detection period, where the historical hardware state parameters include: historical track circuit frequency, historical track circuit impedance value, historical power supply voltage, and historical equipment current, and the historical maintenance information includes: historical maintenance times and historical most recent maintenance time;

[0108] Input the historical hardware state parameters and the historical maintenance information into the fault occurrence prediction model to determine the sample predicted fault occurrence time;

[0109] Obtain the historical fault occurrence time of other signal interlocking equipment in the historical detection period;

[0110] Determine the training loss function of the fault occurrence prediction model according to the predicted fault occurrence time of the sample, the historical fault occurrence time, the historical hardware state parameters, and the historical maintenance information;

[0111] Train the fault occurrence prediction model according to the training loss function of the fault occurrence prediction model to obtain the trained fault occurrence prediction model.

[0112] For example, determine the signal interlocking equipment in other railway lines outside this railway line as other signal interlocking equipment. In the historical database, obtain the historical hardware state parameters and historical maintenance information of the other signal interlocking equipment in the historical detection period. Among them, the historical track circuit frequency is the average frequency of the track circuit in the signal interlocking equipment in the historical detection period, the historical track circuit impedance value is the average impedance value of the track circuit in the signal interlocking equipment in the historical detection period, the historical power supply voltage is the average voltage of the system power supply in the signal interlocking equipment in the historical detection period, the historical equipment current is the average current of the switch motor in the signal interlocking equipment, the historical maintenance times is the total number of times all individual equipment included in the signal interlocking equipment on this railway line have been repaired, and the historical most recent maintenance time is the duration from the time of the most recent maintenance of the signal interlocking equipment on this railway line to the date of the historical detection period. For example, if the corresponding date of the historical detection period is January 8th and the time of the most recent maintenance of the signal interlocking equipment on this railway line is January 7th, then the historical most recent maintenance time of the other signal interlocking equipment in this historical detection period is 1 day; the fault occurrence prediction model is a type of deep learning model, and the fault occurrence prediction model can process the hardware state parameters and maintenance information to predict the time when the signal interlocking equipment fails; obtain the historical fault occurrence time of the other signal interlocking equipment in the historical detection period. For example, when detecting the first other signal interlocking equipment in the first historical detection period, the corresponding date of the first historical detection period is January 1st, and the other signal interlocking equipment fails on January 3rd later, then the historical fault occurrence time of the first other signal interlocking equipment in the first historical detection period is 2 days; determine the training loss function of the fault occurrence prediction model according to the predicted fault occurrence time of the sample, the historical fault occurrence time, the historical hardware state parameters, and the historical maintenance information; use the training loss function of the fault occurrence prediction model to train the fault occurrence prediction model to obtain the trained fault occurrence prediction model.

[0113] According to an embodiment of the present invention, determining the training loss function of the fault occurrence prediction model according to the predicted fault occurrence time of the sample, the historical fault occurrence time, the historical hardware state parameters, and the historical maintenance information includes: determining the training loss function of the fault occurrence prediction model according to formula (1) , (1), wherein, is the sample predicted fault occurrence time of the k-th other signal interlocking device in the i-th historical detection period, is the historical fault occurrence time of the k-th other signal interlocking device in the i-th historical detection period, is the historical track circuit frequency of the k-th other signal interlocking device in the i-th historical detection period, is the preset track circuit frequency threshold, is the historical track circuit impedance value of the k-th other signal interlocking device in the i-th historical detection period, is the preset track circuit impedance threshold, is the historical power supply voltage of the k-th other signal interlocking device in the i-th historical detection period, is the preset power supply voltage threshold, is the historical device current of the k-th other signal interlocking device in the i-th historical detection period, is the preset device current threshold, is the historical maintenance times of the k-th other signal interlocking device, is the preset maintenance times threshold, is the historical most recent maintenance time of the k-th other signal interlocking device, is the preset maintenance time threshold, K is the number of other signal interlocking devices, n is the number of historical detection periods, k ≤ K, i ≤ n, and k, K, i, and n are all positive integers.

[0114] According to an embodiment of the present invention, is the relative difference between the historical track circuit frequency of the k-th other signal interlocking device in the i-th historical detection period and the preset track circuit frequency threshold. The larger this ratio is, the greater the difference between the historical track circuit frequency of the k-th other signal interlocking device in the i-th historical detection period and the preset track circuit frequency threshold. Among them, the preset track circuit frequency threshold is determined according to the setting scheme of the track circuit, generally 25 Hz, is the relative difference between the historical track circuit impedance value of the k-th other signal interlocking device in the i-th historical detection period and the preset track circuit impedance threshold. The larger this ratio is, the greater the difference between the historical track circuit impedance value of the k-th other signal interlocking device in the i-th historical detection period and the preset track circuit impedance threshold. Input the rail parameters and frequency into professional calculation software (such as, MATLAB / Simulink, ETAP) to calculate the theoretical impedance value, that is, the preset track circuit impedance threshold, is the relative difference between the historical power supply voltage of the k-th other signal interlocking device in the i-th historical detection period and the preset power supply voltage threshold. The larger this ratio is, the greater the difference between the historical power supply voltage of the k-th other signal interlocking device in the i-th historical detection period and the preset power supply voltage threshold. Among them, the preset power supply voltage threshold is determined according to the rated voltage of the power supply. is the relative difference between the historical device current of the k-th other signal interlocking device in the i-th historical detection period and the preset device current threshold. The larger this ratio is, the greater the difference between the historical device current of the k-th other signal interlocking device in the i-th historical detection period and the preset device current threshold. Among them, the preset device current threshold is determined according to the rated current of the device. Indicates that the relative differences between the historical track circuit frequency and the preset track circuit frequency threshold, the relative differences between the historical track circuit impedance value and the preset track circuit impedance threshold, the relative differences between the historical power supply voltage and the preset power supply voltage threshold, and the relative differences between the historical device current and the preset device current threshold are negatively correlated with the magnitude of the sample predicted fault occurrence time. For example, when the track circuit frequency is too high relative to the preset track circuit frequency, it may be misreceived by the filter in the adjacent section, resulting in an incorrect judgment that the section is idle, and the greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. When the track circuit frequency is too low relative to the preset track circuit frequency, the frequency reduction may cause signal energy attenuation (e.g., unstable power supply voltage or circuit resonance failure), and the receiving end cannot identify the valid signal and misjudges it as "occupied". The greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. When the historical track circuit impedance value is too large relative to the preset track circuit impedance threshold, the signal at the sending end may not reach the receiving end, and the receiving voltage is zero, misjudging it as "occupied". The greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. When the historical track circuit impedance value is too small relative to the preset track circuit impedance threshold, the short circuit will shunt the track circuit current, resulting in a sudden drop in the receiving end voltage and misjudging it as "occupied". And long-term short circuit may burn out the sending end equipment (e.g., transformer). The greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. When the historical power supply voltage is too large relative to the preset power supply voltage threshold, it may cause the signal lamp to light incorrectly (e.g., the green lamp is abnormally always on), the relay coil overheats and fuses, the capacitor breaks down, and the electronic components are damaged. The greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. When the historical power supply voltage is too small relative to the preset power supply voltage threshold, it may cause the relay not to pull in (resulting in the failure of the interlocking logic), and the signal lamp is dim. The greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. When the historical device current is too large relative to the preset device current threshold, it may trigger an incorrect alarm (e.g., a false section occupancy signal). The greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. When the historical device current is too small relative to the preset device current threshold, it may cause the signal display to be incomplete (e.g., the yellow lamp does not light, resulting in an incorrect train operation instruction). The greater the possibility of a fault occurring, the smaller the sample predicted fault occurrence time. Therefore, the items related to the historical track circuit frequency, the historical track circuit impedance value, the historical power supply voltage, and the historical device current are placed in the denominator position, indicating , , and The smaller the values of, the larger the value of the sample predicted fault occurrence time.

[0115] According to an embodiment of the present invention, is the ratio of the historical maintenance times of the k-th other signal interlocking device to the preset maintenance times threshold. The larger this ratio is, the more historical maintenance times the k-th other signal interlocking device has. Among them, the preset maintenance times threshold can be determined according to the service life of the signal interlocking device. For example, when the service life of the signal interlocking device is 1 year, the preset maintenance times threshold of the signal interlocking device is 1. When the service life of the signal interlocking device is 2 years, the preset maintenance times threshold of the signal interlocking device is 2, and so on. is the ratio of the historical most recent maintenance time of the k-th other signal interlocking device to the preset maintenance time threshold. The larger this ratio is, the larger the value of the historical most recent maintenance time of the k-th other signal interlocking device is. Among them, the preset maintenance time threshold can be set to 30 days. indicates that the historical maintenance times and the historical most recent maintenance time are negatively correlated with the sample predicted fault occurrence time. For example, when the historical maintenance times are larger, it means that the device is frequently maintained, the device life may be shorter, and the possibility of failure is greater, and the sample predicted fault occurrence time is smaller. When the value of the historical most recent maintenance time is larger, it means that the time since the last maintenance of the device is longer, the operating state of the device may be worse, and the possibility of failure is greater, and the sample predicted fault occurrence time is smaller. Therefore, the items related to the historical maintenance times and the historical most recent maintenance time are placed in the denominator position, indicating and the smaller the numerical value is, the larger the value of the sample predicted fault occurrence time is.

[0116] According to an embodiment of the present invention, is the relative error between the sample predicted fault occurrence time and the historical fault occurrence time of the k other signal interlocking devices in the i-th historical detection period. Using and to perform weighted averaging on the relative error between the sample predicted fault occurrence time and the historical fault occurrence time of the other signal interlocking devices in the historical detection period to obtain a training loss function. During the training process, the above training loss function is reduced, so that the error between the sample predicted fault occurrence time and the historical fault occurrence time is reduced, the prediction accuracy of the fault occurrence prediction model for the fault occurrence time is improved, and thus the accuracy of the fault occurrence prediction model is improved.

[0117] In this way, based on the sample to predict the fault occurrence time, historical fault occurrence times, historical hardware status parameters, and historical maintenance information, the training loss function of the fault occurrence prediction model can be determined. During the calculation process, based on the possible impacts of the track circuit frequency, track circuit impedance value, power supply voltage, device current, number of maintenance times, and the most recent maintenance time on the occurrence of faults in the signal interlocking device, the impact of the above data on the error of the sample to predict the fault occurrence time can be determined. And based on this impact, as well as the relative error of the sample to predict the fault occurrence time, the training loss function is set, so that during the training process of the fault occurrence prediction model, the training loss function is reduced, and the accuracy of the fault occurrence prediction model is more targeted improved.

[0118] According to an embodiment of the present invention, in step S5, based on the hardware status parameters, the device hardware fault detection score is determined.

[0119] Figure 4 Exemplarily shown is a flowchart for calculating the device hardware fault detection score according to an embodiment of the present invention.

[0120] According to an embodiment of the present invention, step S5 includes:

[0121] Step S51, based on the hardware status parameters, determine the track circuit frequency, track circuit impedance value, power supply voltage, and device current;

[0122] Step S52, obtain maintenance information, where the maintenance information includes: the number of maintenance times and the most recent maintenance time;

[0123] Step S53, input the track circuit frequency, the track circuit impedance value, the power supply voltage, the device current, the number of maintenance times, and the most recent maintenance time into the trained fault occurrence prediction model to determine the predicted fault occurrence time;

[0124] Step S54, based on the predicted fault occurrence time, determine the device hardware fault detection score.

[0125] For example, through a digital multimeter and a track circuit analyzer, obtain the track circuit frequency, track circuit impedance value, power supply voltage, and device current of the signal interlocking device; through the trained fault occurrence prediction model, process the track circuit frequency, track circuit impedance value, power supply voltage, device current, number of maintenance times, and the most recent maintenance time to obtain the duration from the current detection cycle to the next occurrence of a fault, that is, the predicted fault occurrence time; based on the predicted fault occurrence time, evaluate whether the device hardware has a fault and the operating condition of the hardware to determine the device hardware fault detection score.

[0126] According to an embodiment of the present invention, step S54 includes: determining the device hardware fault detection score according to formula (2): , (2), Among them, if is a conditional function, To predict the time of failure, It is the preset fault occurrence time threshold.

[0127] According to one embodiment of the present invention, in formula (2), the conditional function The value of includes the following two cases, when satisfying 0, it means that a fault has occurred and the value of the condition function is 0. 0, indicating that no fault has occurred, and the value of the conditional function is , It is the ratio of the predicted fault occurrence time to the preset fault occurrence time threshold. The larger the ratio is, the smaller the possibility of fault in the signal interlocking device is. The preset fault occurrence time threshold can be set to thirty days.

[0128] In this way, the device hardware fault detection score can be determined based on the predicted fault occurrence time. During the calculation process, the operating status of the hardware device can be evaluated based on the predicted fault occurrence time, thereby improving the accuracy of the device hardware fault detection score.

[0129] According to an embodiment of the present invention, in step S6, logical communication parameters are acquired at multiple moments in the detection cycle.

[0130] For example, after being authorized by the operating unit, the signal centralized monitoring system (CSM) automatically collects the interlocking device status, communication messages and fault information, and obtains log information and communication parameters, namely logical communication parameters.

[0131] According to an embodiment of the present invention, in step S7, a logical communication fault detection score is determined according to the logical communication parameters.

[0132] Figure 5 The flowchart of calculating the logical communication fault detection score according to an embodiment of the present invention is exemplarily shown.

[0133] According to one embodiment of the present invention, step S7 includes:

[0134] Step S71, determining log information and communication parameters according to the logical communication parameters;

[0135] Step S72, determining a locking event triggering record and an unlocking event triggering record according to the log information;

[0136] Step S73: Determine the logical fault detection result according to the lock event trigger record and the unlock event trigger record;

[0137] Step S74: Determine the transmission delay and the bit error rate according to the communication parameters;

[0138] Step S75: Determine the communication fault detection result according to the transmission delay and the bit error rate;

[0139] Step S76: Determine the logical communication fault detection score according to the logical fault detection result and the communication fault detection result.

[0140] For example, obtain the log information and communication parameters through the signal centralized monitoring system; in the log information, query the lock event trigger record and the unlock event trigger record; automatically generate test cases based on the scenario-based test framework (such as TestRail) to cover all lock / unlock condition branches, and use an automated tool to check whether the lock event trigger record and the unlock event trigger record conform to the preset logic. If they do not conform to the logic, the logical fault detection result is 0, indicating that there are conflicting records in the interlocking system and there is a logical error. If they conform to the logic, the logical fault detection result is 1; in the communication parameters, obtain the transmission delay and the bit error rate of the signal interlocking device; set the preset transmission delay threshold to 500 ms and the preset bit error rate threshold to , if both the transmission delay and the bit error rate are less than the preset transmission delay threshold and the preset bit error rate threshold, the communication fault detection result is 2. If either the transmission delay or the bit error rate is greater than the corresponding set threshold, the communication fault detection result is 0; sum up the logical fault detection result and the communication fault detection result to determine the logical communication fault detection score.

[0141] According to an embodiment of the present invention, in step S8, generate a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score, and the logical communication fault detection score.

[0142] For example, if the terminal wiring fault detection score is 3, it means the connection between terminals is correct; if the score is 1, it means there is a double - end inconsistency in the terminals; if the score is 2, it means there is a single - end error in the terminals; if the score is 0, it means there are both double - end inconsistency and single - end error in the terminals. If the equipment hardware fault detection score equals 0, it means a fault has occurred and the staff should be notified for repair. If the equipment hardware fault detection score is less than 1, it means there is a possibility of fault in the signal interlocking equipment and the staff should be notified for equipment maintenance. If the equipment hardware fault detection score is greater than 1, it means the working condition of the signal interlocking equipment is good. If the logical communication fault detection score is 3, it means the communication condition and logical condition of the signal interlocking equipment are good. If the score is 1, it means the communication condition of the signal interlocking equipment is poor. If the score is 2, it means there is an error in the operating logic of the signal interlocking equipment. If the score is 0, it means the communication condition of the signal interlocking equipment is poor and there is an error in the operating logic.

[0143] The railway signal interlocking equipment fault detection method according to an embodiment of the present invention can accurately obtain the wiring diagrams of the railway, monitor the hardware state parameters and logical communication parameters of the signal interlocking equipment. Further, it can detect the terminal wiring fault condition according to the wiring diagram, detect the hardware fault condition according to the hardware state parameters, and detect the logical communication fault condition according to the logical communication parameters, improving the comprehensiveness and accuracy of the signal interlocking equipment fault detection. Moreover, during the process of obtaining the wiring diagram, it reorganizes the railway signal interlocking drawing resources, integrates all relevant drawings into a unified and standard electronic document or system, realizes the construction of the drawing management system from individual functional nodes to superior functional nodes and then to full-process functional nodes, forms the integrated management of drawing resources, realizes structural innovation, realizes the transformation from paper resources to digital resources, promotes the transformation from single to big data direction, completes data innovation, improves the accuracy and efficiency of work, and can greatly improve the efficiency of drawing integration and verification, reduce the errors of manual operations, and provide strong technical support for the maintenance and management of railway signal equipment. When determining the training loss function of the fault occurrence prediction model, it can determine the training loss function of the fault occurrence prediction model according to the sample predicted fault occurrence time, historical fault occurrence time, historical hardware state parameters and historical maintenance information. During the calculation process, it can determine the influence of the above data on the error of the sample predicted fault occurrence time according to the possible influence of the track circuit frequency, track circuit impedance value, power supply voltage, equipment current, maintenance times and the most recent maintenance time on the occurrence of faults in the signal interlocking equipment, and set the training loss function based on this influence and the relative error of the sample predicted fault occurrence time, so that during the training process of the fault occurrence prediction model, the training loss function is reduced, and the accuracy of the fault occurrence prediction model is more targeted improved. When determining the equipment hardware fault detection score, it can determine the equipment hardware fault detection score according to the predicted fault occurrence time. During the calculation process, it can evaluate the operating condition of the hardware equipment according to the predicted fault occurrence time, improving the accuracy of the equipment hardware fault detection score.

[0144] Figure 6 Exemplarily shown is a block diagram of a railway signal interlocking equipment fault detection system according to an embodiment of the present invention. The system includes:

[0145] A wiring diagram module, configured to obtain a wiring diagram at the start moment of the detection period;

[0146] A drawing information module, configured to obtain drawing information according to the wiring diagram;

[0147] A wiring fault module, configured to determine a terminal wiring fault detection score according to the drawing information;

[0148] A hardware parameter module, configured to obtain hardware status parameters at multiple moments during a detection period;

[0149] A hardware fault module, configured to determine a device hardware fault detection score according to the hardware status parameters;

[0150] A software parameter module, configured to obtain logical communication parameters at multiple moments during a detection period;

[0151] A software fault module, configured to determine a logical communication fault detection score according to the logical communication parameters;

[0152] A detection report module, configured to generate a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score, and the logical communication fault detection score.

[0153] The present invention may be a method, an apparatus, a system, and / or a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for performing various aspects of the present invention.

[0154] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The object of the present invention has been fully and effectively achieved. The functions and structural principles of the present invention have been shown and described in the embodiments. Without departing from the principle, the embodiments of the present invention may have any deformation or modification.

Claims

1. A method for detecting faults in railway signal interlocking equipment, characterized in that, Including: At the start moment of the detection period, obtain the wiring diagram; According to the wiring diagram, obtain the diagram information; According to the diagram information, determine the terminal wiring fault detection score; At multiple moments in the detection period, obtain the hardware status parameters; According to the hardware status parameters, determine the equipment hardware fault detection score; At multiple moments in the detection period, obtain the logical communication parameters; According to the logical communication parameters, determine the logical communication fault detection score; According to the terminal wiring fault detection score, the equipment hardware fault detection score, and the logical communication fault detection score, generate an equipment fault detection report.

2. The method for detecting faults of railway signal interlocking equipment according to claim 1, wherein According to the wiring diagram, obtaining the diagram information includes: According to the wiring diagram, determine the recognizable formatted data; According to the recognizable formatted data, determine the cable ID; According to the recognizable formatted data, determine the cable starting terminal number and the cable ending terminal number; According to the recognizable formatted data, determine the list of legal terminal numbers.

3. The railway signal interlocking equipment fault detection method according to claim 2, characterized in that, According to the diagram information, determining the terminal wiring fault detection score includes: According to the cable starting terminal number, the cable ending terminal number, and the list of legal terminal numbers, determine the missing terminal numbers; Determine the quantity of the missing terminal numbers; According to the quantity of the missing terminal numbers, determine the single-end error fault detection score; According to the cable ID, the cable starting terminal number, and the cable ending terminal number, determine the double-end error fault detection score; According to the single-end error fault detection score and the double-end error fault detection score, determine the terminal wiring fault detection score.

4. The method for detecting faults of a railway signal interlocking device according to claim 3, wherein According to the cable ID, the cable starting terminal number, and the cable ending terminal number, determining the double-end error fault detection score includes: According to the cable ID, determine the same cable; Determine the cable starting terminal number and the cable ending terminal number of the same cable; According to the cable starting terminal number and the cable ending terminal number of the same cable, determine the double-end error fault detection score.

5. The method for detecting faults of railway signal interlocking equipment according to claim 1, characterized in that According to the hardware status parameters, determining the equipment hardware fault detection score includes: According to the hardware status parameters, determine the track circuit frequency, the track circuit impedance value, the power supply voltage, and the equipment current; Obtain the maintenance information, where the maintenance information includes: the number of maintenance times and the most recent maintenance time; Input the track circuit frequency, the track circuit impedance value, the power supply voltage, the equipment current, the number of maintenance times, and the most recent maintenance time into the trained fault occurrence prediction model to determine the predicted fault occurrence time; According to the predicted fault occurrence time, determine the equipment hardware fault detection score.

6. The method for detecting faults of railway signal interlocking equipment according to claim 5, wherein, The training steps of the fault occurrence prediction model include: Obtain the historical hardware status parameters and historical maintenance information of other signal interlocking devices in the historical detection period, where the historical hardware status parameters include: historical track circuit frequency, historical track circuit impedance value, historical power supply voltage, and historical equipment current, and the historical maintenance information includes: historical number of maintenance times and historical most recent maintenance time; Input the historical hardware status parameters and the historical maintenance information into a fault occurrence prediction model to determine the sample predicted fault occurrence time; Obtain the historical fault occurrence times of other signal interlocking devices in historical detection cycles; Determine the training loss function of the fault occurrence prediction model according to the sample predicted fault occurrence time, the historical fault occurrence times, the historical hardware status parameters, and the historical maintenance information; Train the fault occurrence prediction model according to the training loss function of the fault occurrence prediction model to obtain a trained fault occurrence prediction model.

7. The method for detecting faults of railway signal interlocking equipment according to claim 6, wherein, Determine the training loss function of the fault occurrence prediction model according to the sample predicted fault occurrence time, the historical fault occurrence times, the historical hardware status parameters, and the historical maintenance information, including: According to the formula ， Determine the training loss function of the fault occurrence prediction model , where is the sample predicted fault occurrence time of the k-th other signal interlocking device in the i-th historical detection period, is the historical fault occurrence time of the k-th other signal interlocking device in the i-th historical detection period, is the historical track circuit frequency of the k-th other signal interlocking device in the i-th historical detection period, is the preset track circuit frequency threshold, is the historical track circuit impedance value of the k-th other signal interlocking device in the i-th historical detection period, is the preset track circuit impedance threshold, is the historical power supply voltage of the k-th other signal interlocking device in the i-th historical detection period, is the preset power supply voltage threshold, is the historical device current of the k-th other signal interlocking device in the i-th historical detection period, is the preset device current threshold, is the historical maintenance times of the k-th other signal interlocking device, is the preset maintenance times threshold, is the historical nearest maintenance time of the k-th other signal interlocking device, is the preset maintenance time threshold, K is the number of other signal interlocking devices, n is the number of historical detection periods, k ≤ K, i ≤ n, and k, K, i, and n are all positive integers.

8. The method for detecting faults of railway signal interlocking equipment according to claim 5, characterized in that Determine the device hardware fault detection score according to the predicted fault occurrence time, including: According to the formula ， Determine the device hardware fault detection score , where if is a conditional function, is the predicted fault occurrence time, is the preset fault occurrence time threshold.

9. The method for detecting faults of a railway signal interlocking device according to claim 1, wherein Determine the logical communication fault detection score according to the logical communication parameters, including: Determine the log information and communication parameters according to the logical communication parameters; Determine the lock event trigger record and the unlock event trigger record according to the log information; Determine the logical fault detection result according to the lock event trigger record and the unlock event trigger record; Determine the transmission delay and the bit error rate according to the communication parameters; Determine the communication fault detection result according to the transmission delay and the bit error rate; Determine the logical communication fault detection score according to the logical fault detection result and the communication fault detection result.

10. A railway signal interlocking equipment fault detection system, characterized in that, Including: A wiring diagram module, configured to obtain a wiring diagram at the start moment of a detection cycle; A drawing information module, configured to obtain drawing information according to the wiring diagram; A wiring fault module, configured to determine the terminal wiring fault detection score according to the drawing information; A hardware parameter module, configured to obtain hardware status parameters at multiple moments in a detection cycle; A hardware fault module, configured to determine the device hardware fault detection score according to the hardware status parameters; A software parameter module, configured to obtain logical communication parameters at multiple moments in a detection cycle; A software fault module, configured to determine the logical communication fault detection score according to the logical communication parameters; A detection report module, configured to generate a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score, and the logical communication fault detection score.

Images