Three-wire system passive electronic lock state detection method

Abstract

The invention discloses a three-wire system passive electronic lock state detection method in the technical field of electronic lock detection, which comprises the following steps: sending a locking instruction (P = 1, N = 0) to drive a motor to rotate forwards, delaying, switching to a band-type brake state (P = 1, N = 1), and judging the state of a spring bolt by detecting the level change of a port. And if the low level (less than or equal to 0.8 V) is detected for two continuous times, judging that the locking is successful, otherwise, triggering retry or fault protection. And an unlocking instruction (P = 0, N = 1) is sent to drive the motor to rotate reversely, and the port level is detected after band-type brake. And if the voltage is high level (greater than or equal to 4.2 V) for two consecutive times, judging that unlocking succeeds, otherwise, starting retry or fault response. Therefore, the H bridge drives the T3 / T4 MOS tube to be cooperatively closed to form a band-type brake state, the level of a detection point is forcibly lowered to be below 0.2 V (vs is larger than or equal to 4.2 V in a traditional scheme), and a detection blind area during unlocking failure is thoroughly eliminated. Actual measurement unlocking state determination accuracy reaches 99.97% and is improved by 40 times compared with a traditional scheme.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic lock detection, and particularly relates to a method for detecting the state of a three-wire passive electronic lock. Background Art

[0002] Currently, various types of electronic locks are available. Usually, many original equipment manufacturers use cheaper and simpler three-wire passive electronic locks to reduce costs. Due to the special structure of the three-wire passive electronic lock, its current state cannot be detected when the electronic lock is abnormally jammed.

[0003] Existing three-wire passive electronic locks (such as automotive electronic steering column locks) generally adopt an H-bridge drive with a single-channel feedback contact design. In the scenario of unlocking failure, the feedback contact remains closed due to mechanical jamming. However, since the H-bridge continues to supply power, the detection point level remains high (close to Vcc). The traditional solution cannot distinguish between the two states of "unlocking failure with contact adhesion" and "normal unlocking completed", which is prone to false judgment. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to some extent.

[0005] For this purpose, the object of the present invention is to propose a method for detecting the state of a three-wire passive electronic lock. By driving the T3 / T4 MOS transistors in the H-bridge to cooperate and close to form a braking state, the detection point level is forced to be pulled down below 0.2V (vs traditional solution ≥ 4.2V), completely eliminating the detection blind area during unlocking failure. The measured accuracy rate of unlocking state determination reaches 99.97%, which is 40 times higher than the traditional solution.

[0006] To achieve the above object, the present invention proposes a method for detecting the state of a three-wire passive electronic lock. The method for detecting the state of the electronic lock includes: detecting the locking of the electronic lock and detecting the unlocking of the electronic lock, wherein,

[0007] The steps of detecting the locking of the electronic lock are as follows:

[0008] S1.1. The electronic lock is in the starting state, and the electronic lock drive is P = 0, N = 0. At this time, the electronic lock is in an open state and no state is given.

[0009] S1.2. During the process of strategy detection, the electronic lock is detected through the state detection port.

[0010] S1.3. Send a locking command. At this time, P = 1, N = 0, and it lasts for 200 ms. After the drive is completed, a delay of 50 ms is given, and then P = 1, N = 1 is sent, and then it enters the braking state.

[0011] S1.4. Wait for 100 ms and then detect the port level 3 times, with a detection interval of 20 ms each time. When the last two consecutive detections are low levels, it means the locking is normal and the locking operation is completed.

[0012] S1.5. If the last two consecutive detections are not low levels, repeat the steps of S1.3 and S1.4.

[0013] S1.6. Set the number of times to repeat the steps to two. If the number of repetitions is greater than two and the low level is still not satisfied, it is determined that there is a locking failure. At this time, send P = 0, N = 0, and cut off the power.

[0014] The steps for detecting the unlocking of the electronic lock are as follows:

[0015] S2.1. Send an unlocking instruction. At this time, P = 0, N = 1, and it lasts for 200 ms. After the driving is completed, delay for 50 ms, and then send P = 1, N = 1, and then enter the brake state.

[0016] S2.2. Wait for 100 ms and then detect the port level 3 times, with a detection interval of 20 ms each time. When the last two consecutive detections are high levels, it means the unlocking is normal and the unlocking operation is completed.

[0017] S2.3. If the last two consecutive detections are not high levels, repeat the steps of S2.1 and S2.2.

[0018] S2.4. Set the number of times to repeat the steps to two. If the number of repetitions is greater than two and the high level is still not satisfied, it is determined that there is a locking failure. At this time, send P = 0, N = 0, and cut off the power.

[0019] The three - wire passive electronic lock status detection method of the present invention forms a brake state by driving the T3 / T4 MOS transistors in the H - bridge to close cooperatively, and forcibly pulls down the detection point level to below 0.2 V (vs traditional scheme ≥ 4.2 V), completely eliminating the detection blind area during unlocking failure. The measured accuracy rate of the unlocking state determination reaches 99.97%, which is 40 times higher than the traditional scheme.

[0020] In addition, the three - wire passive electronic lock status detection method proposed according to the above application may also have the following additional technical features:

[0021] Specifically, it further includes a detection circuit. The detection circuit includes an H - bridge drive circuit and a low - level detection circuit, where,

[0022] The H - bridge drive circuit includes two MOS transistors (T3, T4), which are used to close to form a brake state when the unlocking detection fails, and forcibly pull down the detection point level to the ground potential, so as to distinguish the feedback signals of successful and failed unlocking.

[0023] Specifically, the detection port is configured with a pull-up power supply, and its voltage value is 5V; the input impedance of the detection port is 10 kΩ to ensure the stability of level detection and anti-interference ability.

[0024] Specifically, the total duration of the three-level detections is 60 ms (with a 20-ms interval each time), and the sampling windows of the last two detections are located in the stable stage after driving the brake to eliminate the influence of transient interference.

[0025] Specifically, when the number of repeated detections exceeds two and still fails to meet the status conditions, the system automatically triggers the fault diagnosis mode, records the fault code, reports the abnormal status through the communication interface, and simultaneously cuts off the drive power supply (P = 0, N = 0) to achieve hardware-level protection.

[0026] Specifically, the determination condition for successful locking is that the level at the detection point is low level (≤0.8V) in both of the last two samplings, while the determination condition for successful unlocking is that both of the last two samplings are high level (≥4.2V), and the threshold voltage is set according to the logic level definition of the H-bridge drive circuit.

[0027] Specifically, the switching process of the drive instructions (P, N signals) includes dead-time control to prevent the upper and lower bridge arms of the H-bridge from being directly connected and short-circuited. The dead time is set to 10 ms to ensure the safe turn-off of the MOS transistors.

[0028] Specifically, the detection circuit integrates a filter capacitor (0.1 μF), which is connected in parallel between the detection port and the ground to suppress the interference of high-frequency noise on level sampling.

[0029] The additional aspects and advantages of the present invention will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0031] Figure 1 is the flowchart of the locking detection process of the present invention;

[0032] Figure 2 is the flowchart of the unlocking detection process of the present invention;

[0033] Figure 3 is the schematic diagram of the electronic lock drive;

[0034] Figure 4 is the schematic diagram of the H-bridge drive circuit control;

[0035] Figure 5 is the schematic diagram of successful unlocking and locking of the electronic lock;

[0036] Figure 6 Schematic diagram of unlocking failure of an electronic lock;

[0037] Figure 7 Schematic diagram of successful locking of an electronic lock;

[0038] Figure 8 Schematic diagram of locking failure;

[0039] Figure 9 Schematic diagram of unlocking failure state judgment circuit when driving the brake;

[0040] Figure 10 Schematic diagram of unlocking success state judgment circuit when driving the brake. Specific implementation manners

[0041] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention. On the contrary, the embodiments of the present invention include all changes, modifications, and equivalents falling within the spirit and scope of the appended claims.

[0042] The three-wire passive electronic lock state detection method according to the embodiments of the present invention will be described below with reference to the drawings.

[0043] As Figure 1-10 shown, the three-wire passive electronic lock state detection method according to the embodiments of the present invention includes: electronic lock locking detection and electronic lock unlocking detection, where

[0044] The steps of electronic lock locking detection are:

[0045] S1.1. The electronic lock is in the starting state, and the electronic lock drive is P = 0, N = 0. At this time, the electronic lock is in an open state and no state is given.

[0046] S1.2. During the strategy detection process, the electronic lock is detected through the state detection port.

[0047] S1.3. Send a locking command. At this time, P = 1, N = 0, and it lasts for 200 ms. After the drive is completed, a delay of 50 ms is given, and then P = 1, N = 1 is sent, and then the brake state is entered.

[0048] S1.4. After waiting for 100 ms, the detection port detects the level 3 times, and the detection interval for each time is 20 ms. When the last two consecutive detections are low levels, the locking is normal and the locking action is completed.

[0049] S1.5. If the last two consecutive detections are not at a low level, repeat the steps of S1.3 and S1.4;

[0050] S1.6. Set the number of times to repeat the steps to two. If the number of repetitions is greater than two and the low level is still not satisfied, it is determined as a locking failure. At this time, P = 0 and N = 0 are sent, and the power is cut off.

[0051] It should be noted that after the detection electronic lock is powered on in this embodiment, it defaults to output P = 0 and N = 0 signals, and the H-bridge is in the cut-off state (all T1 / T2 / T3 / T4 MOS transistors are turned off). At this time, the detection port is pulled high to Vcc (5V) through the internal pull-up resistor (Rpull-up = 10kΩ) to form a high-impedance input state to avoid false triggering caused by external interference.

[0052] When receiving the locking instruction, the controller first outputs P = 1 and N = 0 signals (lasting for 200 ms), driving T1 / T4 to conduct, and the motor rotates forward to perform the locking action;

[0053] After the driving is completed, immediately switch to P = 1 and N = 1 signals (holding brake state). At this time, T1 / T3 conduct, and both ends of the motor are short-circuited to form energy consumption braking to ensure that the locking tongue mechanical structure is in place stably.

[0054] After the holding brake lasts for 100 ms, start the detection program, and collect the voltage signal of the detection point through opto-isolation;

[0055] Collect the voltage value every 20 ms (for a total of 60 ms), and take the results of the last two consecutive samplings as the judgment basis;

[0056] Success state: The voltage at the detection point ≤ 0.8V (corresponding to TTL low level), indicating that the locking tongue is completely closed and the feedback contact is conducting;

[0057] Failure state: The voltage at the detection point ≥ 4.2V (corresponding to TTL high level), indicating that the feedback contact is not conducting or there is mechanical jamming.

[0058] If the first detection fails (not consecutive low levels), the system automatically triggers the retry mechanism and repeats steps S1.3 - S1.4 at most twice;

[0059] When all three consecutive detections fail, it is determined as a permanent failure. The controller immediately cuts off the P / N drive signal and reports an error code (such as 0x01 indicating "locking timeout"), and at the same time activates the hardware watchdog reset circuit.

[0060] The steps for the electronic lock unlocking detection are as follows:

[0061] S2.1. Send an unlocking command. At this time, P = 0 and N = 1, which lasts for 200 ms. After the driving is completed, a 50-ms delay is applied, and then P = 1 and N = 1 are sent, and then the braking state is entered.

[0062] S2.2. After waiting for 100 ms, the port detection level is detected 3 times, and the detection interval is 20 ms each time. When the last two consecutive detections are high levels, the unlocking is normal and the unlocking action is completed.

[0063] S2.3. If the last two consecutive detections are not high levels, repeat the steps of S2.1 and S2.2.

[0064] S2.4. The number of times to repeat the steps is set to two. If the number of repetitions is greater than two and the high level is still not satisfied, it is determined that there is a locking failure. At this time, P = 0 and N = 0 are sent, and the power is cut off.

[0065] It should be noted that when the unlocking command is triggered in this embodiment, the controller outputs a signal of P = 0 and N = 1 (lasting for 200 ms), drives T2 / T3 to conduct, makes the motor rotate in the reverse direction, and releases the mechanical locking state.

[0066] After the brake is activated (P = 1 and N = 1), the detection point shows a high-impedance state due to the disconnection of the feedback contact.

[0067] The voltage signal is collected through an optocoupler isolation circuit. When the unlocking is successful, the detection point voltage ≥ 4.2 V due to the pull-up resistor, and when it fails, the low level is maintained due to the contact adhesion.

[0068] A 0.1 μF filter capacitor is connected in parallel at the detection port to suppress the transient voltage fluctuation during the start and stop of the motor.

[0069] A differential sampling circuit is used to eliminate the common-mode noise and improve the signal-to-noise ratio to more than 60 dB.

[0070] When the first unlocking fails, the system automatically adjusts the PWM duty cycle to 75% for a second attempt to relieve the mechanical resistance by reducing the driving current.

[0071] If two consecutive retries still fail, trigger protective measures: record the fault log and send an alarm through the UART interface (such as 0x02 indicating "unlocking blocked"), and at the same time enter the sleep mode waiting for manual intervention.

[0072] In summary, after actual measurement, in the environment of -20°C to 85°C:

[0073] The success rate of locking detection ≥ 99.8%, and the average response time ≤ 80 ms;

[0074] The unlocking detection resists 500 mV power frequency interference, and the misjudgment rate < 0.1%;

[0075] There is no hardware failure after 100,000 consecutive cycle tests, and MTBF > 100,000 hours.

[0076] In an embodiment of the present invention, as Figure 3 and Figure 4 shown, it further includes a detection circuit. The detection circuit includes an H-bridge drive circuit and a low-level detection circuit. Among them,

[0077] The H-bridge drive circuit includes two MOS transistors (T3, T4), which are used to close to form a brake state when the unlocking detection fails, and force the detection point level to be pulled down to the ground potential, so as to distinguish the feedback signals of successful and failed unlocking.

[0078] It should be noted that through the coordinated switching of the H-bridge T3 / T4 MOS transistors, the detection point level is actively pulled down during the detection stage, effectively distinguishing between the two scenarios of "unlocking failure contact adhesion" and "normal high-impedance state", and solving the detection blind area problem in the traditional scheme.

[0079] In an embodiment of the present invention, as Figure 5-10 shown, the detection port is configured with a pull-up power supply, the voltage value of which is 5V, and the input impedance of the detection port is 10 kΩ to ensure the stability and anti-interference ability of the level detection.

[0080] In summary, for the three-wire passive electronic lock state detection method in the embodiment of the present invention, by the coordinated closing of the H-bridge drive T3 / T4 MOS transistors to form a brake state, the detection point level is forced to be pulled down below 0.2V (vs the traditional scheme ≥ 4.2V), completely eliminating the detection blind area when unlocking fails. The measured accuracy rate of the unlocking state determination reaches 99.97%, which is 40 times higher than the traditional scheme.

[0081] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and deformations to the above embodiments within the scope of the present invention.

Claims

1. A three-wire passive electronic lock state detection method, characterized in that The electronic lock status detection method includes: electronic lock locking detection and electronic lock unlocking detection. Among them, The steps of the electronic lock locking detection are as follows: S1.

1. The electronic lock is in the starting state, and the electronic lock drive is P = 0, N = 0. At this time, the electronic lock is in an open circuit state and there is no status given. S1.

2. During the strategy detection process, the electronic lock is detected through the status detection port. S1.

3. Send a locking instruction. At this time, P = 1, N = 0, and it lasts for 200 ms. After the drive is completed, delay for 50 ms, and then send P = 1, N = 1, then enter the brake state. S1.

4. After waiting for 100 ms, the detection port detects the level 3 times, and the detection interval for each time is 20 ms. When the last two consecutive detections are low levels, the locking is normal and the locking action is completed. S1.

5. If the last two consecutive detections are not low levels, repeat the steps of S1.3 and S1.

4. S1.

6. The number of times of repeating the steps is set to two. If the number of repetitions is greater than two and still does not meet the low level, it is judged as a locking failure. At this time, send P = 0, N = 0, and power off. The steps of the electronic lock unlocking detection are as follows: S2.

1. Send an unlocking instruction. At this time, P = 0, N = 1, and it lasts for 200 ms. After the drive is completed, delay for 50 ms, and then send P = 1, N = 1, then enter the brake state. S2.

2. After waiting for 100 ms, the detection port detects the level 3 times, and the detection interval for each time is 20 ms. When the last two consecutive detections are high levels, the unlocking is normal and the unlocking action is completed. S2.

3. If the last two consecutive detections are not high levels, repeat the steps of S2.1 and S2.

2. S2.

4. The number of times of repeating the steps is set to two. If the number of repetitions is greater than two and still does not meet the high level, it is judged as a locking failure. At this time, send P = 0, N = 0, and power off.

2. The three-wire passive electronic lock state detection method according to claim 1, characterized in that It also includes a detection circuit. The detection circuit includes an H-bridge drive circuit and a low-level detection circuit. Among them, The H-bridge drive circuit includes two MOS transistors (T3, T4), which are used to close to form a brake state when the unlocking detection fails, and forcibly pull the detection point level down to the ground potential, so as to distinguish the feedback signals of successful and failed unlocking.

3. The three-wire passive electronic lock state detection method according to claim 1, characterized in that The detection port is configured with a pull-up power supply, and its voltage value is 5V; the input impedance of the detection port is 10 kΩ to ensure the stability and anti-interference ability of the level detection.

4. The three-wire passive electronic lock status detection method according to claim 1, wherein The total duration of the three-level detections is 60 ms (with an interval of 20 ms each time), and the sampling windows of the last two detections are located in the stable stage after driving the brake to eliminate the influence of transient interference.

5. The three-wire passive electronic lock state detection method according to claim 1, characterized in that, When the number of repeated detections exceeds two and still cannot meet the status conditions, the system automatically triggers the fault diagnosis mode, records the fault code and reports the abnormal status through the communication interface. At the same time, the drive power supply is cut off (P = 0, N = 0) to achieve hardware-level protection.

6. The three-wire passive electronic lock status detection method according to claim 1, characterized in that, The determination condition for successful locking is that the detection point level is low level (≤0.8V) in the last two samplings, while the determination condition for successful unlocking is that the last two samplings are both high level (≥4.2V). The threshold voltage is set according to the logic level definition of the H-bridge drive circuit.

7. The three-wire passive electronic lock state detection method according to claim 1, characterized in that The switching process of the driving instructions (P, N signals) includes dead-time control to prevent the direct short circuit of the upper and lower arms of the H-bridge. The dead time is set to 10 ms to ensure the safe turn-off of the MOS transistor.

8. The three-wire passive electronic lock state detection method according to claim 1, wherein The detection circuit is integrated with a filter capacitor (0.1 μF), which is connected in parallel between the detection port and the ground to suppress the interference of high-frequency noise on the level sampling.

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