Distance measurement method, device and storage medium based on non-uniform sampling digital phase detector

Abstract

The present invention relates to the field of spatial optical communication and ranging technology, and more specifically to a ranging method, device, and storage medium based on a non-uniformly sampled digital phase detector. The present invention uses a non-uniformly sampled method to sample and phase-detect the data bit clocks in the GTX transmit and receive asynchronous clock domains. The hardware resources required for processing all utilize digital logic blocks within an FPGA. The processing clock rate maintains a non-integer multiple of the GTX transmit and receive clock rates, thereby improving the measurement accuracy of the phase difference between the two, thereby achieving the goal of improving laser ranging accuracy while simplifying the hardware design of the ranging system.

Description

Technical Field

[0001] The present invention relates to the field of space optical communication and distance measurement technology, and in particular to a distance measurement method, device and storage medium based on a non-uniformly sampled digital phase detector. Background Art

[0002] With the continuous development of space technology, traditional microwave communication methods are limited by frequency band resources and are gradually unable to meet future development needs in terms of speed, communication capacity, anti-interference and security. Laser communication has the characteristics of large capacity, strong anti-interference ability, low power consumption and small size. Applying it to inter-satellite and inter-satellite-ground communication can greatly improve the performance of various systems; at the same time, laser communication links can realize distance measurement and time difference measurement between communication systems by measuring the delay between output and received signals.

[0003] Currently, high-precision space laser ranging methods primarily utilize incoherent, bidirectional, single-pass or two-pass ranging systems. Their ranging accuracy is directly affected by the synchronization accuracy of the data symbol bits—that is, the accuracy of the data bit clock phase difference. Therefore, selecting the appropriate phase detection technology is crucial for achieving high ranging accuracy. Existing space laser ranging systems generally employ analog phase detection, using a dedicated phase detector chip to accurately identify the data bit clock phase between the transmitted and received signals. For example, the prototype of a laser unified measurement and control system based on an OOK system proposed by Xing Qianglin et al. utilizes an ultra-large-scale FPGA + high-speed ADC processing architecture. This approach significantly increases the software algorithm complexity and hardware design costs of the entire system. Therefore, further improving space laser ranging methods and overcoming the limitations of existing high-precision space laser ranging methods in terms of the size, weight, power consumption, complexity, and engineering of ranging equipment has become a new challenge.

[0004] Furthermore, with the continuous advancement of modern integrated circuit technology, FPGA devices with integrated GTX high-speed transceiver serializers capable of transmission rates reaching over ten Gbps have emerged. The method of implementing laser OOK direct modulation communication systems using FPGA high-speed serial transceivers in conjunction with optoelectronic conversion modules is widely used in engineering practice. When used for ranging, the GTX OOK system suffers from the problem of different data bit clocks on the GTX transmitter and receiver. Due to the metastable effects caused by asynchronous clock sampling, it is impossible to directly sample and process the clock phase or data on one clock source from another, making it difficult to effectively identify the phase difference between the GTX transmitter and receiver clocks. Summary of the Invention

[0005] The present invention provides a ranging method, device and storage medium based on a non-uniformly sampled digital phase detector. The purpose of the present invention is to solve the problem of measurement accuracy jitter caused by the inability to accurately estimate the change in clock phase under non-coherent direct ranging conditions through the design of a digital phase detector, and to improve the accuracy of space laser ranging under high code rate communication.

[0006] To achieve the above object, the technical solution of the present invention is:

[0007] A ranging method based on a non-uniformly sampled digital phase detector, comprising:

[0008] Step a: Generate a data frame containing a synchronization header under the sending clock (clk_send), and record the double word sequence number counter value when the sender starts sending the synchronization header. ;

[0009] Step b, converting the parallel data into a high-speed serial signal through the GTX transmission module of the FPGA, and sending the laser signal at a line rate Vtr;

[0010] Step c: Receive the returned laser signal through the GTX receiving module, recover the receiving clock (clk_rev) and convert the serial data into a parallel data frame;

[0011] Step d: Synchronize the data frame under the receiving clock and capture the double word sequence number at the end of the synchronization header. and bit number , calculate the number of synchronization header offset bytes and bit offset number ;

[0012] Step e: Use a non-integer multiple phase-locked sampling clock (clk_sample) to sample the transmit and receive clocks in unequal intervals, multiply the complex conjugates of the two clock signals after sampling, and perform arc tangent phase lock through a phase-locked loop to obtain the phase difference. ;

[0013] Step f, perform 2 on the phase difference n After the double low-decimation operation, the signal is input into the second-order phase-locked loop, and the bandwidth of the phase-locked loop is set to the order of 1 Hz and the damping coefficient is 0.6≤ξ≤0.8;

[0014] Step g: Calculate the total time difference according to the formula:

[0015]

[0016] in is the parallel clock frequency, is the serial line rate;

[0017] The value of the phase difference coefficient Cptc is the product of the transmit / receive clock frequency division multiple and the parallel data bit width;

[0018] Step h: Pass Calculate the distance measurement value, where c is the speed of light.

[0019] Furthermore, the ratios of the phase-locked sampling clock frequency to the transmitting clock frequency and the receiving clock frequency in step e are all non-integers, specifically satisfying:

[0020]

[0021] in and are the sending clock and receiving clock frequencies respectively, It is the core sampling clock frequency of the digital phase detector.

[0022] Furthermore, the transfer function of the phase-locked loop in step f is:

[0023]

[0024] The loop bandwidth BL satisfies:

[0025]

[0026] in , , K is the loop gain.

[0027] Furthermore, the frequency division multiple is 4, the parallel data bit width is 32 bits, and Cptc=128.

[0028] Furthermore, the 2 n In the double low-decimation operation, n=14.

[0029] A distance measuring device based on a non-uniformly sampled digital phase detector, comprising:

[0030] Laser transmitting unit, including OOK transmitting electro-optical conversion module and GTX transmitting module;

[0031] Laser receiving unit, including OOK receiving photoelectric conversion module and GTX receiving module;

[0032] A digital processing unit, including a frame synchronization module, a non-uniform sampling phase detector, a second-order phase-locked loop, and a time difference calculation module integrated in the FPGA;

[0033] The frame synchronization module is used to realize double word sequence number counting and offset calculation;

[0034] The non-equal sampling phase detector samples the transmit and receive clocks at non-integer multiples of the clock;

[0035] The bandwidth of the second-order phase-locked loop is ≤1Hz;

[0036] The time difference calculation module performs the calculation of the total time difference;

[0037] When the device is running, a distance measurement method based on a non-uniformly sampled digital phase detector is executed.

[0038] A storage medium stores a computer program, which, when executed by a processor, implements the spatial laser ranging method based on a digital phase detector.

[0039] The beneficial effects achieved by the present invention are:

[0040] The present invention is based on a ranging method, device and storage medium of a non-equally divided sampling digital phase detector. The digital phase detector is used to replace a traditional analog phase detector, which can effectively reduce the design complexity and hardware cost of the system. The non-equally divided sampling method is adopted, and a phase detection sampling clock that is a non-integer multiple of the receiving clock and the transmitting clock is used to sample the receiving clock and the transmitting clock respectively, thereby completing the phase detection of the receiving and transmitting clocks and improving the reliability of the phase detector. In addition, the relevant design of the phase-locked loop is carried out to achieve accurate tracking of the digital phase difference, reduce the jitter of the phase detection result, and improve the stability of the phase detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0042] Figure 1 This is a block diagram of the principle of space laser ranging based on digital phase detector.

[0043] Figure 2 This is a block diagram based on the principle of a digital phase detector.

[0044] Figure 3 This is the simulation result diagram of non-equal sampling phase detection.

[0045] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0046] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0048] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, if the meaning of "and / or" appearing in the full text is to include three parallel schemes, taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme in which A and B are satisfied at the same time. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0049] The spatial laser ranging method based on a digital phase detector proposed in the present invention uses a non-uniform sampling method to sample and phase-detect the data bit clocks on the GTX transmit and receive two asynchronous clock domains. The hardware resources required for processing all use the digital logic blocks within the FPGA. The processing clock rate maintains a non-integer multiple relationship with the GTX transmit and receive clock rates, thereby improving the measurement accuracy of the phase difference between the two, achieving the purpose of improving laser ranging accuracy on the basis of simplifying the hardware design of the ranging system.

[0050] The functional structure of a typical device for spatial laser ranging method based on digital phase detector is as follows: Figure 1 As shown in , the OOK receiving optoelectronic conversion module is used to receive laser signals and convert them into electrical signals, and the OOK transmitting optoelectronic conversion module is used to convert the electrical signals to be sent into laser signals. The optoelectronic conversion module is directly connected to the GTX transceiver module: at the transmitting end, the parallel data stream is converted into a high-speed serial data stream through the GTX transmitting module and sent to the optical module; at the receiving end, the GTX receiving module converts the high-speed serial data stream transmitted by the optical module into a low-speed parallel data stream according to the protocol.

[0051] The spatial laser ranging method based on digital phase detector has the following features: based on non-uniform sampling digital phase detector; setting up a phase-locked loop to achieve accurate tracking of digital phase difference; and comprehensively calculating the time difference.

[0052] Based on non-equal sampling digital phase detector. In the laser ranging system, the emitted laser will be modulated into a signal of a specific frequency, such as a sine wave or a square wave. When the laser hits the target object and reflects back, the received signal will have a phase delay, and this delay is proportional to the distance. Therefore, the key technical difficulty of optical ranging is the need to obtain the precise phase difference between the transmitting clock and the receiving clock, so as to calculate the delay time and obtain an accurate ranging value. Therefore, in order to further improve the reliability of ranging, the present invention adopts a digital phase detector based on non-equal sampling, starting from improving the clock accuracy, and performing non-equal sampling on the GTX receiving clock clk_rev and the GTX sending clock clk_send through the phase sampling clock clk_sample, wherein the phase sampling clock and the GTX transceiver clock maintain a non-integer multiple relationship. The product of the sampled receiving clock and the complex conjugate of the sampled sending clock is sent to the phase-locked loop for inverse tangent phase detection. Through Figure 3 The simulation results show that the phase-detection linearity of non-uniform sampling is good. This design not only effectively reduces the system design complexity and equipment cost, but also effectively improves the reliability of the ranging system by using non-uniform sampling technology.

[0053] A phase-locked loop (PLL) is set up to achieve accurate tracking of digital phase differences. To achieve accurate tracking of digital phase differences and improve system stability, the PLL provided by the present invention primarily employs the following measures: 1. High-multiplier, low-decimation of the phase difference output by the digital phase detector reduces jitter in the phase detection result, lowers the loop update rate, and effectively reduces the system's computational load and power consumption; 2. The PLL bandwidth is set to a minimum value to reduce jitter in the tracking result, effectively suppress high-frequency noise, and reduce errors caused by environmental noise or circuit noise itself, thereby improving ranging accuracy.

[0054] Comprehensively calculate the time difference. Laser ranging achieves distance measurement by measuring and calculating the time between the emission of a laser pulse and the reception of the return laser. Therefore, the core influence of time difference in ranging is directly related to the accuracy of distance calculation. The present invention comprehensively calculates the time difference by utilizing the difference in the number of bits of transmitted and received data and the phase difference of the data clock, converting them into a specific time difference using the method in step 7.

[0055] The hardware architecture of the ranging device consists of a laser transmitting unit, a laser receiving unit, and a digital processing unit. The laser transmitting unit includes an OOK transmit electro-optical conversion module and a GTX transmit module within the FPGA. The GTX transmit module converts parallel data (156.25 MHz) into a 5 Gbps high-speed serial signal, which drives the laser to emit a modulated optical signal.

[0056] The laser receiving unit consists of an OOK optical-to-electrical conversion module and an internal GTX receiving module in the FPGA. The optical-to-electrical conversion module converts the received optical signal into an electrical signal. The GTX receiving module performs serial-to-parallel conversion, outputs a 32-bit parallel data frame (156.25 MHz), and recovers the receiving clock clk_rev.

[0057] The digital processing unit is integrated into the FPGA and includes the following modules:

[0058] The frame synchronization module detects the data frame synchronization header and calculates the offset; the non-uniform sampling phase detector samples the transmit and receive clocks in non-integer multiples based on the 200 MHz sampling clock clk_sample; the second-order phase-locked loop with a bandwidth of 1 Hz and a damping coefficient of 0.7071 is used for phase difference tracking; and the time difference calculation module calculates the ranging value.

[0059] The spatial laser ranging method based on a digital phase detector of the present invention adopts a two-way ranging mode, wherein a transmitting unit sends a laser signal and a receiving unit receives a returned laser signal; a non-uniformly sampled digital phase detector is used to identify the phase difference between the GTX transmitting clock and the GTX receiving clock; the digital phase difference is input into a phase-locked loop for precise tracking; and finally, an accurate time value is obtained based on the obtained clock phase difference and synchronization head offset to complete the ranging.

[0060] Taking the link transmission rate of 5Gbps as an example, the present invention simulates and generates a GTX receiving clock clk_rev and a GTX sending clock clk_send with a frequency value of 156.25MHz, and then uses the local sending clock as the reference clock to generate a 200MHz phase-locked sampling clock clk_sample. The phase-locked sampling clock maintains a non-integer multiple relationship with the receiving and transmitting clock. Then, the phase-locked sampling clock is used to perform arc tangent phase-locked processing on the receiving and transmitting clock signals. As shown, the specific parameters of this embodiment are as follows:

[0061] Step 1: Transmit data frame framing. Under the transmit clock clk_send (156.25 MHz), generate a 1000-byte data frame consisting of a 4-byte sync header, a packet identifier, and a data field. Record the double-word sequence counter value DwT at the moment the sender begins sending the sync header and store it in the sender's DRAM.

[0062] The specific process is: under the clk_send clock, the double word sequence number counter at the time when the sender starts sending the synchronization header is set. The value is stored in the DRAM of the transmitting end. At the same time, for the convenience of measurement, the data frame is usually sent with 0 byte as the beginning. In addition, considering that the GTX data interface is generally (n is a positive integer) bytes. The frame length should be designed so that an integer number of data frames are contained per second. Therefore, the encoding frame length is usually a multiple of 4 bytes.

[0063] Step 2: GTX transmit module processing. The GTX transmit module within the FPGA converts the parallel data to be transmitted into a transmit signal according to the required communication rate and obtains the GTX transmit clock clk_send for the transmitted data. In this invention, taking the GTX serial transceiver's data line rate of 5 Gbps as an example, the transmitting end uses a parallel transmit line rate of 156.25 MHz, and after parallel-to-serial conversion by the GTX core, the data is transmitted at a transmit line rate of 5 Gbps, Vtr.

[0064] Step 3: GTX Receive Module Processing. The GTX receive module within the FPGA receives the laser signal data and performs serial-to-parallel conversion. This means the receiver groups the data into parallel data frames according to a fixed 32-bit width, ensuring that each data group contains exactly 32 bits. Simultaneously, the receive clock, clk_rev, is recovered. On the receiver side, the GTX core's serial-to-parallel conversion reduces the 5 Gbps transmit line rate to a 156.25 MHz parallel receive line rate.

[0065] Step 4: Receive data frame synchronization. Under the clk_rev clock, the receiving data processing part first performs data frame synchronization after receiving the parallel data, and searches for the double word sequence number at the end of the receiving frame header. and bit number within the byte ,according to and Parse the received frame format. The specific process is: under the clk_rev clock, when the receiving end detects that the double-word data output by the current GTX receiving port contains the end mark of the synchronization header, the double-word sequence number counter at this moment is set to Set to 0, and at the same time set the double word internal bit number corresponding to the double word internal synchronization header reception mark position The offset value is stored in the DRAM at the receiving end; each subsequent time the GTX receiving port outputs a double word, Add 1 until When the data frame length is reached, it wraps back to 0. At the same time, the calculation is updated synchronously:

[0066] The number of bytes of synchronization header offset : The number of bits that the synchronization header is offset from in the current byte : At this point, the synchronization header offset is obtained.

[0067] Step 5: Non-equal sampling digital phase detector. The present invention simulates and generates a GTX receive clock clk_rev and a GTX transmit clock clk_send with a frequency value of 156.25MHz, and divides them by 4 respectively. Then, using the local transmit clock as the reference clock, a 200MHz phase detection sampling clock clk_sample is generated, the clk_rev clock and the clk_send clock are non-equally sampled, and the sampled receive clock is multiplied by the complex conjugate of the sampled transmit clock. Finally, the product result is sent to the phase-locked loop, and the arc tangent phase detection of the phase difference between the transmit clock and the receive clock is completed based on the non-equal sampling digital phase detector in the clk_sample clock domain.

[0068] Step 6: Phase-locked loop design. The present invention carries out the relevant design of the phase-locked loop to achieve accurate tracking of the digital phase difference. The specific implementation steps are as follows:

[0069] Step 6.1: Perform a high-multiplication and low-decimation operation on the digital phase difference to reduce the jitter of the phase detection result. The phase difference output of the digital phase detector is subjected to a 16384-fold low-decimation operation at the clk_sample clock. The result is then passed through a low-pass filter (LPF) and fed into the DDS, reducing the loop update rate.

[0070] Step 6.2 Set the phase-locked loop bandwidth to a small value to reduce the jitter of the tracking results.

[0071] The present invention adopts an ideal second-order loop filter, and the transfer function of the filter is:

[0072] (1)

[0073] Where, and are circuit parameters, The corresponding system function for:

[0074] (2)

[0075] Where K is the loop gain. and is called the damping coefficient They are defined as:

[0076] (3)

[0077] (4)

[0078] The above formula shows that and These two loop parameters completely determine the performance of the second-order phase-locked loop.

[0079] From the system function , the loop bandwidth can be obtained for:

[0080] (5)

[0081] The loop bandwidth controls the amount of noise that enters the loop. The narrower the noise bandwidth, the fewer frequency components of noise are allowed to enter the loop, so the better the filtering effect of the loop, and the more accurately the loop tracks the signal. Therefore, in the present invention, Set the value to 0.7071 to reduce the loop bandwidth and set the bandwidth to the 1 Hz level.

[0082] Step 7. Calculate the total time difference. The present invention calculates the total time difference based on the phase difference between the sending clock and the receiving clock and the difference in the number of bits of the sent and received data, combined with the above steps. :

[0083] (6)

[0084] Where, Indicates the number of bytes of synchronization header offset received by the receiving end; Indicates the number of bits of the synchronization header offset in the 32 bits of the current byte; Indicates the phase difference between the receiving clock and the sending clock; ; .

[0085] Step 8. Calculate the distance value. It is known that the distance value is equal to the speed value multiplied by the time value, and the speed of light is constant. Therefore, the final distance value can be obtained by the following formula :

[0086] (7)

[0087] in The speed of light is approximately ; It is the total time difference from sending to receiving the laser signal.

[0088] The above descriptions are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present description and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A ranging method based on a non-uniformly sampled digital phase detector, characterized in that: include: Step a: Generate a data frame containing a synchronization header under the sending clock, and record the double word sequence number counter value when the sender starts sending the synchronization header. ; Step b, converting the parallel data into a high-speed serial signal through the GTX transmission module of the FPGA, and sending the laser signal at a line rate Vtr; Step c: Receive the returned laser signal through the GTX receiving module, recover the receiving clock and convert the serial data into a parallel data frame; Step d: Synchronize the data frame under the receiving clock and capture the double word sequence number at the end of the synchronization header. and bit number , calculate the number of synchronization header offset bytes and bit offset number ; Step e: Use a non-integer multiple phase-locked sampling clock to sample the sending clock and the receiving clock in an unequal manner, multiply the complex conjugates of the two clock signals after sampling, and perform inverse tangent phase lock through a phase-locked loop to obtain the phase difference. ; Step f, perform 2 on the phase difference n After the double low-decimation operation, the signal is input into the second-order phase-locked loop, and the bandwidth of the phase-locked loop is set to the order of 1 Hz and the damping coefficient is 0.6≤ξ≤0.8; Step g: Calculate the total time difference according to the formula: in is the parallel clock frequency, is the serial line rate; The value of the phase difference coefficient Cptc is the product of the transmit / receive clock frequency division multiple and the parallel data bit width; Step h: Pass Calculate the distance measurement value, where c is the speed of light.

2. The ranging method based on a non-uniformly sampled digital phase detector according to claim 1, characterized in that: The ratios of the phase-locked sampling clock frequency to the transmitting clock frequency and the receiving clock frequency in step e are all non-integers, specifically satisfying: in and are the sending clock and receiving clock frequencies respectively, It is the core sampling clock frequency of the digital phase detector.

3. The ranging method based on unequal sampling digital phase detector according to claim 1, characterized in that: The transfer function of the phase-locked loop in step f is: The loop bandwidth BL satisfies: in , , K is the loop gain.

4. The ranging method based on unequal sampling digital phase detector according to claim 1, characterized in that: The frequency division multiple is 4, the parallel data bit width is 32 bits, and Cptc=128.

5. The distance measurement method based on non-uniform sampling digital phase detector according to claim 1, characterized in that: Said 2 n In the double low-decimation operation, n=14.

6. A distance measuring device based on a non-uniformly sampled digital phase detector, characterized in that: include: Laser transmitting unit, including OOK transmitting electro-optical conversion module and GTX transmitting module; Laser receiving unit, including OOK receiving photoelectric conversion module and GTX receiving module; A digital processing unit, including a frame synchronization module, a non-uniform sampling phase detector, a second-order phase-locked loop, and a time difference calculation module integrated in the FPGA; The frame synchronization module is used to realize double word sequence number counting and offset calculation; The non-equal sampling phase detector samples the transmit and receive clocks at non-integer multiples of the clock; The bandwidth of the second-order phase-locked loop is ≤1Hz; The time difference calculation module performs the calculation of the total time difference; When the device is running, the method according to any one of claims 1 to 5 is executed.

7. A storage medium, characterized in that: A computer program is stored, and when the computer program is executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 5.

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