High power supply rejection ratio low dropout linear regulator based on gate capacitance cancellation

Abstract

The invention relates to a high-power-supply-rejection-ratio low-dropout linear voltage regulator based on gate capacitance offset. The high-power-supply-rejection-ratio low-dropout linear voltage regulator comprises an error amplifier, a power tube MP, feedback networks R1 and R2, a load capacitor CL, a frequency compensation capacitor CM and a gate capacitance offset circuit. The output end of the error amplifier, the output end of the grid capacitance offset circuit and the grid of the power tube MP are connected with one end of the frequency compensation capacitor CM; the other end of the frequency compensation capacitor CM, the drain electrode of the power tube MP, one end of the resistor R1 and one end of the load capacitor CL are connected with a VOUT end; the source electrode of the power tube MP is connected with the VIN end; the other end of the load capacitor CL and one end of the resistor R2 are connected with a grounding end GND; the other end of the resistor R1 and the other end of the resistor R2 are connected with the in-phase input end VFB of the error amplifier. The gate capacitance offset circuit is introduced to the output of the error amplifier, so that the equivalent capacitance of the node is changed, the gain from input to output is reduced, and the power supply suppression capability is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management chip design, and particularly relates to a low dropout linear regulator with a high power supply rejection ratio based on gate capacitance cancellation. Background Art

[0002] With the rapid development of technology, the importance of portable electronic devices in daily life and work has become increasingly prominent, driving the diversification of power supply solutions. As a common step-down chip, the low dropout linear regulator (LDO) is widely used in small electronic devices. Especially in a system on chip (SoC), the LDO is favored due to its excellent noise performance and easy integration characteristics.

[0003] A typical LDO structure is as Figure 4 shown, which successively includes a bandgap reference, an error amplifier, a power transistor MP, a feedback network R1, R2, and a load capacitor C L . Among them, C gsp , C gdp , C oea are respectively the gate-source equivalent capacitance, the gate-drain equivalent capacitance of the power transistor, and the output equivalent capacitance of the error amplifier.

[0004] As the frequency increases, the transfer function from the input V IN to the output V OUT can be calculated as:

[0005]

[0006] It can be seen from the above formula that the input signal VIN will be directly coupled to the output through the parasitic capacitance of the power transistor MP, reducing the power supply rejection ability. Summary of the Invention

[0007] To solve the problems existing in the background art, the present invention provides a low dropout linear regulator with a high power supply rejection ratio based on gate capacitance cancellation, including: an error amplifier, a power transistor M P , feedback networks R1 and R2, a load capacitor C L , a frequency compensation capacitor C M , and a gate capacitance cancellation circuit; the output end of the error amplifier, the output end of the gate capacitance cancellation circuit, the gate of the power transistor M P , and one end of the frequency compensation capacitor C M are connected; the other end of the frequency compensation capacitor C M , the drain of the power transistor M P , one end of the resistor R1, one end of the load capacitor C L , and the V OUT terminal are connected; the source of the power transistor M P is connected to VIN Terminal; load capacitance C L The other end of the, one end of resistor R2 and the ground terminal GND are connected; the other end of resistor R1, the other end of resistor R2 and the non-inverting input terminal V of the error amplifier FB are connected.

[0008] The present invention has at least the following beneficial effects

[0009] By introducing a gate capacitance cancellation circuit at the output of the error amplifier, the present invention reduces the gain from input to output and improves the power supply rejection ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of the overall circuit structure of the present invention;

[0011] Figure 2 is a schematic diagram of the circuit structure of the gate capacitance cancellation circuit of the present invention;

[0012] Figure 3 is a schematic diagram of the simulation comparison of the PSR curves of the LDO with and without the gate capacitance cancellation circuit;

[0013] Figure 4 is a schematic diagram of the circuit architecture of a conventional LDO;

[0014] Figure 5 is a schematic diagram of the high PSR architecture of the low dropout linear regulator of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention schematically, and the following embodiments and the features in the embodiments can be combined with each other without conflict.

[0016] Please refer to Figure 1 and Figure 2 , the present invention provides a low dropout linear regulator with a high power supply rejection ratio based on gate capacitance cancellation, including: an error amplifier, a power transistor M P , feedback networks R1 and R2, load capacitance C L , frequency compensation capacitance C M and a gate capacitance cancellation circuit; the output terminal of the error amplifier, the output terminal of the gate capacitance cancellation circuit, the power transistor M PThe gate and the frequency compensation capacitor C M are connected at one end; the other end of the frequency compensation capacitor C M , the drain of the power transistor M P , one end of the resistor R1, one end of the load capacitor C L and the V OUT terminal are connected; the source of the power transistor M P is connected to the V IN terminal; the other end of the load capacitor C L , one end of the resistor R2 and the ground terminal GND are connected; the other end of the resistor R1, the other end of the resistor R2 and the non-inverting input terminal V FB of the error amplifier are connected.

[0017] Preferably, the gate capacitance cancellation circuit includes current sources I b1 and I b2 , transistors M C1 to M C6 , and a capacitor C C ; one end of the current source I b1 , the source of the transistor M C3 , the source of the transistor M C4 and the V IN terminal are connected; the gate of the transistor M C3 , the gate of the transistor M C4 , the drain of the transistor M C3 and the drain of the transistor M C2 are connected; the other end of the current source I b1 , one end of the capacitor C C , the drain of the transistor M C1 , the gate of the transistor M C1 and the gate of the transistor M C2 are connected; one end of the current source I b2 , the drain of the transistor M C5 , the gate of the transistor M C5 and the gate of the transistor M C6 are connected; the drain of the transistor M C4 , the drain of the transistor M C6 , the other end of the capacitor C C and the output terminal of the gate capacitance cancellation circuit are connected; the source of the transistor M C1 , the source of the transistor M C2 , the source of the transistor M C5 , the source of the transistor M C6 and the ground terminal GND are connected; the other end of the current source I b2 is connected to the V IN terminal.

[0018] Preferably, the transistor MC3 and transistor M C4 is a P-channel MOS transistor; the transistor M C1 , transistor M C2 , transistor M C5 and transistor M C6 is an N-channel MOS transistor.

[0019] Preferably, the current source I b1 is equal to the current source I b2 .

[0020] Preferably, the transistor M C1 and transistor M C2 constitute a 1-to-N current mirror; the transistor M C5 and transistor M C6 constitute a 1-to-N current mirror; the transistor M C3 and transistor M C6 constitute a 1-to-1 current mirror; where N = 1 + (C oea + C gdp ) / C C , C oea represents the output equivalent capacitance of the error amplifier; C gdp represents the gate-drain equivalent capacitance of the power transistor M P .

[0021] Preferably, the error amplifier includes: transistors M1 to M 20 ; where the source of transistor M7, the source of transistor M8, the source of transistor M9, the source of transistor M 10 , the source of transistor M 11 , the source of transistor M 12 , the source of transistor M 13 , the source of transistor M 14 , the source of transistor M 15 , the source of transistor M 16 and the V IN terminal are connected; the source of transistor M 17 , the source of transistor M 19 , the source of transistor M5, the source of transistor M6, the source of transistor M 20 , the source of transistor M 18 and the ground terminal GND are connected; the gate of transistor M 19 is connected to the bias voltage V b1 ; the drain of transistor M 15 , the drain of transistor M 17 , the gate of transistor M 17 and the gate of transistor M 18 are connected; the gate of transistor M 15The gate of, transistor M 13 The gate of, transistor M 13 The drain of, transistor M 19 The drain of and transistor M 11 is connected to the drain of; transistor M 11 The gate of, the gate of transistor M9, the drain of transistor M9 and the drain of transistor M1 are connected; the gate of transistor M7 is connected to the bias voltage V b2 ; the drain of transistor M7, the gate of transistor M5 and the drain of transistor M3 are connected; the gate of transistor M3, the gate of transistor M1 and the non-inverting input terminal V of the error amplifier FB are connected; the source of transistor M3, the drain of transistor M5 and the source of transistor M2 are connected; the source of transistor M1, the source of transistor M4 and the drain of transistor M6 are connected; transistor M 10 The drain of, transistor M 10 The gate of, transistor M 12 The gate of and the drain of transistor M2 are connected; the gate of transistor M8 is connected to the bias voltage V b2 ; the drain of transistor M8, the drain of transistor M4 and the gate of transistor M6 are connected; the gate of transistor M2, the gate of transistor M4 and the reference voltage VREF are connected; transistor M 12 The drain of, transistor M 14 The drain of, transistor M 14 The gate of, transistor M 16 The gate of and transistor M 20 The drain of are connected; transistor M 20 The gate of is connected to the bias voltage V b1 ; transistor M 16 The drain of, transistor M 18 The drain of and the output terminal of the error amplifier are connected.

[0022] Preferably, the transistors M7 to M 16 are P-channel MOS transistors; the transistors M1 to M6, M 17 to M 20 are N-channel MOS transistors.

[0023] In this embodiment, a PSR LDO with gate capacitance cancellation includes a bandgap reference, an error amplifier, a power transistor M P , a feedback network R1 and R2, a load capacitor C L and a gate capacitance cancellation circuit. As shown in the appendix Figure 5 . The output of the error amplifier is introduced into a gate capacitance cancellation circuit to reduce the gain from input to output and improve the power supply rejection ability. The equivalent capacitance of the gate capacitance cancellation circuit is denoted as C SC, the input-to-output transfer function can be calculated as:

[0024]

[0025] During design

[0026] C sc = -(C oea + C gdp )

[0027] Then the input-to-output transfer function can be recalculated as:

[0028]

[0029] By reasonably designing the equivalent capacitance C of the gate capacitance cancellation circuit SC , the gain from input to output can be made 0, that is, the output voltage is not affected by the input voltage, improving the power supply rejection ability.

[0030] To make the technical means and creative features implemented by the present invention easy to understand, the present invention will be further described in conjunction with the accompanying drawings. The specific circuit of the overall circuit of the present invention is as shown in the attached Figure 1 figure. The entire LDO circuit mainly includes an error amplifier, a power transistor M P , a feedback network R1 and R2, a load capacitance C L , a frequency compensation capacitance C M and a gate capacitance cancellation circuit. Among them, the error amplifier is composed of transistors M 1-20 . The gate capacitance cancellation circuit is composed of current sources I b1 , I b2 and transistors M C1 ~M C6 and a capacitance C C , as shown in Figure 2 the figure. Figure 2 The equivalent capacitance at point G in

[0031] C sc can be calculated as: C

[0032] C oea = -(N - 1)C gdp C Therefore, by designing N = 1 + (C oea

[0033] To verify the rationality of this scheme, the Figure 1 circuit is simulated and verified under the 0.18um process. The PSR curves of the LDO with and without the gate capacitance cancellation circuit are as shown in the attached Figure 3As shown. The simulation results show that the PSR of the LDO without the gate capacitance cancellation circuit is -32 dB at 1 MHz. The PSR of the LDO with the gate capacitance cancellation circuit can reach -62.4 dB at 1 MHz, an improvement of -30 dB.

[0034] In summary, the high power supply rejection ratio low dropout linear regulator based on gate capacitance cancellation of the present invention reduces the gain from input to output and improves the power supply rejection ability by introducing a gate capacitance cancellation circuit at the output of the error amplifier.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A low dropout linear regulator with high power supply rejection ratio based on gate capacitance cancellation, characterized in that, Including: Error amplifier, power transistor M P , feedback network R1 and R2, load capacitor C L , frequency compensation capacitor C M and gate capacitance cancellation circuit; the output terminal of the error amplifier, the output terminal of the gate capacitance cancellation circuit, the gate of the power transistor M P and one end of the frequency compensation capacitor C M are connected; the other end of the frequency compensation capacitor C M , the drain of the power transistor M P , one end of the resistor R1, one end of the load capacitor C L and the V OUT terminal are connected; the source of the power transistor M P is connected to the V IN terminal; the other end of the load capacitor C L , one end of the resistor R2 and the ground terminal GND are connected; the other end of the resistor R1, the other end of the resistor R2 and the non-inverting input terminal V FB of the error amplifier are connected.

2. The high power supply rejection ratio low dropout linear regulator based on gate capacitance cancellation according to claim 1, wherein The gate capacitance cancellation circuit includes current sources I b1 and I b2 , transistors M C1 ~M C6 , and a capacitor C C ; One end of the current source I b1 , the source of the transistor M C3 , the source of the transistor M C4 , and the V IN terminal are connected; The gates of the transistors M C3 , the gates of the transistors M C4 , the drains of the transistors M C3 , and the drains of the transistors M C2 are connected; The other end of the current source I b1 , one end of the capacitor C C , the drain of the transistor M C1 , the gates of the transistors M C1 , and the gates of the transistors M C2 are connected; One end of the current source I b2 , the drain of the transistor M C5 , the gates of the transistors M C5 , and the gates of the transistors M C6 are connected; The drains of the transistors M C4 , the drains of the transistors M C6 , the other end of the capacitor C C , and the output terminal of the gate capacitance cancellation circuit are connected; The sources of the transistors M C1 , the sources of the transistors M C2 , the sources of the transistors M C5 , the sources of the transistors M C6 , and the ground terminal GND are connected; The other end of the current source I b2 is connected to the V IN terminal.

3. A low dropout linear regulator with a high power supply rejection ratio based on gate capacitance cancellation according to claim 2, characterized in that The transistor M C3 and the transistor M C4 are P-channel MOS transistors; the transistor M C1 , the transistor M C2 , the transistor M C5 and the transistor M C6 are N-channel MOS transistors.

4. A low dropout linear regulator with high power supply rejection ratio based on gate capacitance cancellation according to claim 2, characterized in that, The current source I b1 is equal to the current source I b2 .

5. A low dropout linear regulator with high power supply rejection ratio based on gate capacitance cancellation according to claim 2, characterized in that, The transistor M C1 and the transistor M C2 form a 1-to-N current mirror; the transistor M C5 and the transistor M C6 form a 1-to-N current mirror; the transistor M C3 and the transistor M C6 form a 1-to-1 current mirror; where N = 1 + (C oea + C gdp ) / C C , C oea represents the output equivalent capacitance of the error amplifier; C gdp represents the gate-drain equivalent capacitance of the power transistor M P .

6. A low dropout linear regulator with high power supply rejection ratio based on gate capacitance cancellation according to claim 1, characterized in that, The error amplifier includes transistors M1 to M 20 ; wherein, the source electrodes of transistor M7, transistor M8, transistor M9, transistor M 10 , transistor M 11 , transistor M 12 , transistor M 13 , transistor M 14 , transistor M 15 , transistor M 16 are connected to the source electrode and the V IN terminal; the source electrodes of transistor M 17 , transistor M 19 , the source electrode of transistor M5, the source electrode of transistor M6, transistor M 20 , transistor M 18 are connected to the ground terminal GND; the gate electrode of transistor M 19 is connected to the bias voltage V b1 ; the drain electrodes of transistor M 15 , transistor M 17 , transistor M 17 and the gate electrode of transistor M 18 are connected; the gate electrodes of transistor M 15 , transistor M 13 , transistor M 13 , the drain electrodes of transistor M 19 , transistor M 11 are connected; the gate electrodes of transistor M 11 , the gate electrode of transistor M9, the drain electrode of transistor M9 and the drain electrode of transistor M1 are connected; the gate electrode of transistor M7 is connected to the bias voltage V b2 ; the drain electrode of transistor M7, the gate electrode of transistor M5 and the drain electrode of transistor M3 are connected; the gate electrodes of transistor M3, transistor M1 and the non-inverting input terminal V FB of the error amplifier are connected; the source electrode of transistor M3, the drain electrode of transistor M5 and the source electrode of transistor M2 are connected; the source electrode of transistor M1, the source electrode of transistor M4 and the drain electrode of transistor M6 are connected; the drain electrode of transistor M 10 , the gate electrode of transistor M 10 , the gate electrode of transistor M 12 and the drain electrode of transistor M2 are connected; the gate electrode of transistor M8 is connected to the bias voltage V b2 ; the drain electrode of transistor M8, the drain electrode of transistor M4 and the gate electrode of transistor M6 are connected; the gate electrodes of transistor M2, transistor M4 and the reference voltage VREF are connected; the drain electrode of transistor M 12 , the drain electrode of transistor M 14 , the drain electrode of transistor M 14 gate of, transistor M 16 gate and transistor M 20 drain connection of; transistor M 20 gate of is connected to bias voltage V b1 ; transistor M 16 drain of, transistor M 18 drain of and the output terminal of the error amplifier are connected.

7. A low dropout linear regulator with high power supply rejection ratio based on gate capacitance cancellation according to claim 6, characterized in that, The transistors M7 to M 16 are P-channel MOS transistors; the transistors M1 to M6, M 17 to M 20 are N-channel MOS transistors.

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