Dual interface high speed memory subsystem

Abstract

The invention relates to a dual interface high speed memory subsystem. A memory subsystem includes: a memory device; a first host interface; a serial interface controller to provide host access to a boot partition of the memory device using the first host interface; a second host interface; and a high-speed interface controller that provides host access to a user partition of the memory device using the second host interface.

Description

Technical Field

[0001] The present disclosure generally relates to a memory subsystem, and more particularly, to a dual-interface high-speed memory subsystem. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. For example, the memory device may be a non-volatile memory (NVM) device and a volatile memory device. Generally, a host system may utilize the memory subsystem to store data at the memory device and retrieve data from the memory device. Summary of the Invention

[0003] One aspect of the present disclosure relates to a memory subsystem including: a non-volatile memory device including a boot partition and a user partition; a first host interface; a serial interface controller that provides host access to the boot partition using the first host interface; a second host interface; and a high-speed interface controller that provides host access to the user partition using the second host interface.

[0004] Another aspect of the present disclosure relates to a computing system including: a controller; and a non-volatile memory subsystem coupled to the controller through a first interface that is a serial interface and a second interface that is a high-speed interface, the memory subsystem including: a memory device including a boot partition and a user partition; a serial interface controller that transfers data from the boot partition to the controller using the serial interface; and a high-speed interface controller that transfers data from the memory device to the controller using the high-speed interface. Brief Description of the Drawings

[0005] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be regarded as limiting the present disclosure to a particular embodiment, but are for explanation and understanding only.

[0006] Figure 1 Illustrates an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2 Illustrates a more detailed example of a computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 3 Is a flowchart of an example method for booting an embedded computing system including a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 4A flowchart of another example method for guiding an embedded computing system including a memory subsystem in accordance with some embodiments of the present disclosure.

[0010] Figure 5 A block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to dual-interface memory subsystems. A memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem. Figure 1 The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described below. The dies in the package may be assigned to one or more channels for communication with a memory subsystem controller. Each die may be composed of one or more planes. The planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a set of physical blocks, which are groups of memory cells for storing data. A cell is an electronic circuit that stores information.

[0012] Depending on the cell type, a cell may store one or more bits of binary information and have various logical states related to the number of bits stored. The logical states may be represented by binary values, such as "0" and "1" or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC may store one bit of information and have two logical states. Figure 1

[0013]

[0014]

[0015] NVM memory subsystems are often used in embedded computing systems, such as for systems-on-chip (SOCs), industrial applications, and embedded computing systems in the automotive industry. NVM memory subsystems typically provide read and write access to NVM via a peripheral communication interface, such as a Peripheral Component Interconnect Express (PCIe) interface, a Serial Advanced Technology Attachment (SATA) interface, or another high-speed interface. These communication interfaces are used to transfer data between the NVM and the processor or controller of the embedded computing system and, more generally, between the memory subsystem and the host system.

[0015] A bootstrapping embedded computing system involves executing boot code (also known as a "bootloader") that is persistently stored in non-volatile memory. A multi-stage boot process involves executing at least a primary bootloader (such as the BIOS) and a second-stage bootloader (such as a kernel). In some embedded systems that include an NVM memory subsystem, the second-stage bootloader typically resides in the main storage device of the memory subsystem, while the primary bootloader typically resides in a separate dedicated memory component, such as a small-capacity serial NOR (S-NOR) flash memory, which is part of the embedded computing system but external to the memory subsystem. For example, this is the case in a conventional solid-state drive (SSD) memory subsystem. The embedded system controller uses a serial interface (usually a Serial Peripheral Interface (SPI) or a variant thereof) to access the S-NOR component and execute the BIOS or primary bootloader to perform basic initialization of some hardware and operating system components, including initializing the high-speed interface between the SSD and the embedded system controller. Once the high-speed interface is initialized, the BIOS or primary bootloader transfers the kernel or second-stage bootloader from the main storage device of the SSD to the embedded system controller via the high-speed interface. The embedded system controller then executes the kernel or second-stage bootloader to complete the boot process.

[0016] Note that an embedded computing system with an SSD memory subsystem currently cannot boot directly from the SSD. Booting from the S-NOR is an artifact inherited from the personal computer architecture. This allows the computer to be reconfigured, for example, to permit changing the hardware without modifying the operating system image. However, SOC products typically cannot be upgraded / configured like personal computers. Thus, this flexibility is unnecessary, and these embedded systems take longer to boot than necessary and are more costly for manufacturers due to the additional S-NOR components that must be included in these systems.

[0017] Aspects of the present disclosure address the above and other deficiencies by providing an NVM memory subsystem in which the NVM is logically divided into a boot partition and a user partition. The boot partition contains the primary bootloader. The second-stage bootloader may reside in the boot partition or the user partition. To access the boot partition and thus the primary bootloader, the memory subsystem includes a serial interface in addition to the high-speed interface. Before the high-speed interface is initialized (e.g., after the first stage of the boot process), the serial interface provides fast access to the NVM. The serial interface facilitates transferring the primary bootloader from the NVM to the host, enabling the host system to boot directly from the NVM of the NVM memory subsystem and eliminating the need for a separate S-NOR component, thereby saving manufacturing costs and achieving a faster boot time compared to an embedded computing system with a memory subsystem that includes a separate S-NOR component and NVM.

[0018] Figure 1 Describe an example computing system 100 that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof. One or more memory devices 130 may be logically separated into different partitions, including a logical boot partition 137 and a logical user partition 138.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. In an exemplary embodiment, the storage device is an SSD, a flash drive, a universal serial bus (USB) flash drive, an embedded multimedia controller (eMMC) drive, a universal flash storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation means), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device. In the exemplary embodiments described below, the computing system 100 is an embedded computing system.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 Describe an example of a host system 120 coupled to a memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. The memory subsystem 110 may be, for example, an SSD, an eMMC, a UFS, or another type of NVM memory subsystem. In an exemplary embodiment, the memory subsystem 110 is an SSD memory subsystem.

[0022] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (such as an NVDIMM controller), and a storage protocol controller (such as a PCIe controller, a SATA controller). Examples of processor chipsets include a Platform Controller Hub (PCH) (also known as ICH / PCH). For example, the host system 120 uses the memory subsystem 110 to write data to and read data from the memory subsystem 110.

[0023] The memory subsystem 110 is coupled to the host system 120 via a high-speed interface 112 to transfer data (including control, address, data, and other signals) between the host system 120 and the memory subsystem 110. Examples of high-speed interfaces include (but are not limited to) PCIe, SATA, and UniPro. The memory subsystem controller 115 also includes a high-speed interface controller 116 that provides host system 120 access to the logical user partition 138 through the high-speed host interface 112. In an exemplary embodiment, the serial interface controller 118 is a Quad-SPI (QSPI) controller.

[0024] The memory subsystem 110 is also coupled to the host system 120 via a serial interface 114 to transfer data (including control, address, data, and other signals) between the host system 120 and the memory subsystem 110. Examples of serial interfaces include SPI and its variants, such as QSPI. The memory subsystem 110 includes a serial interface controller 118 that provides host system 120 access to the logical boot partition 137 through the serial host interface 114. In an exemplary embodiment, the serial interface controller 118 is a QSPI controller.

[0025] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (such as the memory device 140) may be (but is not limited to) a random access memory (RAM), such as a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM).

[0026] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memories and in-situ write memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are arrays of cross-points of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Although non-volatile memory devices such as NAND-type memories (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells have been described, memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] Memory subsystem controller 115 (or simply controller 115) can communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130 and other such operations (e.g., in response to commands queued on a command bus by controller 115). Memory subsystem controller 115 can include hardware such as, for example, one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. Memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0029] The memory subsystem controller 115 can include a processing device 117 (processor) configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, the local memory 119 can include memory registers for storing memory pointers, fetching data, etc. The local memory 119 can also include a read-only memory (ROM) for storing microcode. Although Figure 1 the illustrated memory subsystem 110 has been shown as including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115, but instead can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem 110).

[0031] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130 and / or the memory devices 140. The memory subsystem controller 115 can be responsible for other operations such as wear-leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between the logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory devices 130. The memory subsystem controller 115 can further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130 and / or the memory devices 140 and convert responses associated with the memory devices 130 and / or the memory devices 140 into information for the host system 120.

[0032] The memory subsystem 110 can also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory devices 130.

[0033] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (such as the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device that is an original memory device combined with a local controller (such as the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 includes a boot manager 121 that may initialize the serial and high-speed interface controllers during the boot process. In some embodiments, the controller 115 includes at least a portion of the boot manager 121. For example, the controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in the local memory 119 to perform the operations described herein. In some embodiments, the boot manager 121 is part of the host system 120, an application, or an operating system. More details regarding the operation of the boot manager 121 are described below.

[0035] Figure 2 is a block diagram of an example computing system 100 shown in more detail according to some embodiments. In some embodiments, the memory subsystem 110 includes a high-speed data buffer 210 coupled to each of the high-speed interface controller 116 and the memory subsystem controller 115. The high-speed data buffer 210 temporarily stores data transferred between the high-speed interface controller 116 and the memory subsystem controller 115. In some embodiments, the memory subsystem 110 includes a serial data buffer 212 coupled to each of the serial interface controller 118 and the memory subsystem controller 115. The serial data buffer 212 temporarily stores data transferred between the serial interface controller 118 and the memory subsystem controller 115. In some embodiments, data transferred between the host system 120 and the memory subsystem 110 may be sent along an optimized path that includes one of the high-speed data buffer 210 and the serial data buffer 212, while commands from the host system 120 to the memory subsystem 110 may be sent to the memory subsystem controller 115 without passing through the high-speed data buffer 210 or the serial data buffer 212.

[0036] In some embodiments, the memory subsystem 110 includes a boot ROM 216 integrated into the memory subsystem controller 115. The boot ROM 216 stores code that is executed by the memory subsystem control program 115 to initialize the memory subsystem 110. In some embodiments, the memory subsystem 110 also includes a RAM 218 coupled to the memory subsystem controller 115. For example, the RAM 218 may include one or more of the memory devices 140.

[0037] In some embodiments, the memory subsystem 110 includes an NVM 220. For example, the NVM 220 may include one or more of the memory devices 130. In an exemplary embodiment, the NVM 220 is a NAND flash memory device. The primary boot loader 142 is stored in the logical boot partition 137 of the NVM 220.

[0038] Reference will now be made to Figure 2 describe an example multi-stage boot process. The multi-stage boot process includes a primary boot loader (e.g., BIOS, etc.) and a second-stage boot loader (e.g., kernel). Power is applied to the computing system 100 to cause the memory subsystem controller 115 to execute the code in the ROM 216, which loads the memory subsystem firmware code from the non-mapped area of the NVM 220 into the RAM 218. The memory subsystem firmware code includes a boot manager 121. The memory subsystem controller 115 executes the memory subsystem firmware code, causing the boot manager 121 to initialize the memory subsystem software and hardware and peripherals including the serial interface 114. Initializing the serial interface 114 may include reading timing settings (i.e., timing parameters and associated values) from the NVM 220 and using the timing settings to set the timing configuration of the serial interface controller 118. The boot manager 121 also initializes the high-speed interface controller 116 in parallel with setting the timing configuration of the serial interface controller 118.

[0039] When the high-speed interface controller 116 is initialized (or before its initialization), the serial interface controller 118 completes initialization and the serial interface 114 becomes available for transferring data between the memory subsystem 110 and the host system 120. The controller of the host system 120 sends a command to retrieve the primary boot loader 142 along the serial interface 114. The memory subsystem controller 115 interprets the command, retrieves the primary boot loader 142 from the logical boot partition 137, and sends the primary boot loader 142 to the host system 120 through the serial interface 114.

[0040] The host system 120 executes the primary boot loader 142. For example, the primary boot loader 142 performs initialization of hardware (such as peripherals) and protocols and loads the secondary boot loader or the operating system kernel by passing commands to the memory subsystem 110 along the initialized high-speed interface 112. The memory subsystem controller 115 interprets the commands, retrieves the secondary boot loader or the operating system kernel from the logical user partition 138 of the NVM 220, and sends the secondary boot loader or the operating system kernel to the host system 120 along the high-speed interface 112. The host system 120 controller executes the secondary boot loader or the operating system kernel to complete the boot process.

[0041] Although the exemplary boot process is described above, it should be understood that many different variations are also within the scope of the present disclosure. For example, instead of the memory subsystem controller 115 waiting for a command from the host system 120 to retrieve the primary boot loader 142, the memory subsystem controller 115 may send the primary boot loader 142 to the host system 120 without waiting for a command (e.g., in response to completion of the initialization of the serial interface 114). As another example, the secondary boot loader or the operating system kernel may reside in the logical user partition 138 instead of the logical boot partition 137 in some cases.

[0042] In some exemplary embodiments, the computing system 100 is a SOC, the host system 120 is the controller of the SOC, the high-speed host interface 112 is PCIe, and the serial host interface 114 is QSPI. The QSPI interface is initialized faster than the PCIe interface but transfers data at a slower rate than the PCIe interface. Thus, the QSPI interface is used to transfer out a relatively small primary boot loader (i.e., to the host system 120 controller) with less latency (compared to the PCIe interface) after power is applied, while the PCIe interface transfers out the larger secondary boot loader.

[0043] In some embodiments, the QSPI interface may be a simplified version of QSPI that supports a reduced number of features, namely, boot code programming and update, interface timing and waveforms, and boot timing configuration. Initializing the QSPI interface may include reading timing parameters from the NVM 220 and setting the timing parameters in the serial interface controller 118.

[0044] Figure 3is a flowchart of an example method for booting an embedded computing system that includes an SSD memory subsystem, illustrating operations performed by a memory subsystem in accordance with some embodiments of the present disclosure. The method may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method is performed by Figure 1 the memory subsystem controller 115 (e.g., using the boot manager 121). Although shown in a particular sequence or order, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0045] At operation 305, the memory subsystem controller 115 receives power and in response retrieves timing settings from the NVM 220. More specifically, the memory subsystem controller 115 executes code stored in the boot ROM 216, which causes the memory subsystem firmware to be loaded into the RAM 218. The memory subsystem controller 115 then executes the firmware to cause the memory subsystem controller 115 to retrieve the timing settings from the non-mapped region of the NVM 220.

[0046] At operation 310, the memory subsystem controller 115 sets the timing configuration of the serial interface controller 118 using the retrieved timing settings. Setting the timing configuration includes setting one or more timing parameters. In some instances, the timing parameters that may be set are, for example, clock frequency, clock active edge (rising or falling), single data rate (SDR) or double data rate (DDR), initial read latency, number of serial channels (1, 2, or 4), auto data out (yes or no), data source (boot partition or user partition). The timing configuration of the serial interface controller 118 is set by writing the timing parameter values to the registers of the serial interface controller 118. The retrieved timing settings include the parameter values to be set.

[0047] At operation 315, at least partially in parallel with setting the timing configuration of the serial interface controller 118, the memory subsystem controller 115 initializes the high-speed interface controller 116. Initializing the high-speed interface controller 116 includes, for example, initializing the PHY interface (e.g., using a PHY Init command written to the base address register (BAR) of the high-speed interface controller 116) and / or initializing the protocol interface of the high-speed interface controller 116 (e.g., using a protocol Init command).

[0048] At operation 320, the memory subsystem controller 115 transfers the primary boot loader 142 from the NVM 220 to the host system 120 via the serial host interface 114. In some embodiments, the primary boot loader 142 is transferred from the logical boot partition 137 of the NVM 220. In some embodiments, in response to a command received from the host system 120, the memory subsystem controller 115 transfers the primary boot loader 142 to the host system 120. Before the high-speed interface is initialized and available for transferring data from the memory device, the memory subsystem controller 115 transfers the primary boot loader 142 via the serial interface. The host system 120 executes the primary boot loader 142, which causes the discovery and initialization of hardware components (e.g., peripherals) connected to the host system 120.

[0049] At operation 325, the memory subsystem controller 115 receives a request for the secondary boot loader from the host system 120, e.g., in response to the host system 120 executing the primary boot loader 142 that includes an invocation to execute the secondary boot loader.

[0050] At operation 330, in response to a request from the host system 120, the memory subsystem controller 115 transfers the secondary boot loader 142 from the NVM 220 (i.e., the logical boot partition 137 or the logical user partition 138) to the host system 120 via the high-speed interface 112.

[0051] Figure 4 is a flowchart of another example method for booting an embedded computing system that includes a memory subsystem, illustrating operations performed by the memory subsystem, in accordance with some embodiments of the present disclosure.

[0052] At operation 400, the memory subsystem controller 115 receives a "write start" command for the boot partition that includes the data payload size as a parameter of the command via the high-speed interface 112. For example, the memory subsystem receives a command from the host system (of the embedded computing system) to initiate the programming or update of the primary boot loader.

[0053] At operation 402, the memory subsystem controller 115 receives data representing the primary boot loader via the high-speed interface 112.

[0054] At operation 404, the memory subsystem controller receives a "write data commit" command via the high-speed interface 112 and writes the data representing the primary boot loader to the logical boot partition 137 of the NVM 220.

[0055] Operations 400 to 402 may be repeated for the second-stage boot loader, except when the SSD memory subsystem controller receives a "write start" command for the boot partition (if the second-stage boot loader is to be stored in the logical boot partition) or a "write start" command for the user partition (if the second-stage boot loader is to be stored in the logical user partition), and the data being transferred represents the second-stage boot loader.

[0056] At operation 405, the memory subsystem controller 115 receives power and in response retrieves timing settings from the NVM 220. For example, the memory subsystem controller 115 loads and executes the memory subsystem firmware as described above with reference to operation 305.

[0057] At operation 410, the memory subsystem controller 115 uses the retrieved timing settings to set the timing configuration of the QSPI interface controller. For example, the memory subsystem controller 115 sets one or more timing parameters as described above with reference to operation 310.

[0058] At operation 415, at least partially in parallel with setting the timing configuration of the QSPI controller, the memory subsystem controller 115 initializes the PCIe, SATA, or UniPro interface controller. Initializing the PCIe, SATA, or UniPro controller includes, for example, initializing the PHY interface and / or the protocol interface as described above with reference to operation 315.

[0059] At operation 420, in response to a command received from the host system 120, the memory subsystem controller 115 transfers the primary boot loader 142 from the logical boot partition 137 of the NVM 220 to the host system 120 via the QSPI interface 114.

[0060] At operation 425, the memory subsystem controller 115 receives a request for the second-stage boot loader from the host system 120, for example in response to the host system 120 executing the primary boot loader 142 that includes an invocation to execute the second-stage boot loader.

[0061] At operation 430, in response to a request from the host system 120, the memory subsystem controller 115 transfers the second-stage boot loader 142 from the NVM 220 (i.e., the logical boot partition 137 or the logical user partition 138) to the host system 120 via the PCIe, SATA, or UniPro interface.

[0062] Figure 5 An example machine of the computer system 500 is illustrated, within which a set of instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 500 may correspond to a host system (e.g.,Figure 1 of the host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 of the memory subsystem 110) or can be used to perform operations of the controller (e.g., executing an operating system to perform operations corresponding to Figure 1 of the boot manager 121). In alternative embodiments, the machine can be connected (e.g., networked) to other machines on a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0063] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by the machine. Further, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0064] Example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0065] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or a number of processors implementing a combination of instruction sets. The processing device 502 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 can further include a network interface device 508 for communicating via a network 520.

[0066] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or the processing device 502 during execution by the computer system 500, which also constitutes a machine-readable storage medium. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 the memory subsystem 110.

[0067] In one embodiment, the instructions 526 include instructions that implement the functionality corresponding to a boot manager 121 (such as Figure 1 the boot manager 121). Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include (but not be limited to) solid-state memory, optical media, and magnetic media.

[0068] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0069] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers or other such information storage systems of the computer system.

[0070] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. For example, a computer system or other data processing system such as the memory subsystem controller 115 may implement the Figures 3 to 4 computer-implemented method shown in. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to the computer system bus.

[0071] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structure of various such systems will appear as will be set forth in the description below. Additionally, the present disclosure has not been described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure described herein.

[0072] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (such as a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0073] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. Obviously, various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A memory subsystem, comprising: A non-volatile memory device, which includes a boot partition and a user partition; A first host interface; A serial interface controller, which provides host access to the boot partition using the first host interface; A second host interface; and A high-speed interface controller, which provides host access to the user partition using the second host interface.

2. The memory subsystem according to claim 1, wherein the first host interface is a four-channel Serial Peripheral Interface (QSPI) interface.

3. The memory subsystem according to claim 1, wherein the second host interface is one of a Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA), and Unified Protocol (UniPro) interface.

4. The memory subsystem according to claim 1, wherein the memory device includes timing settings and firmware code that uses the timing settings to set the timing configuration of the serial interface controller.

5. The memory subsystem according to claim 4, wherein the firmware code further initializes the high-speed interface controller.

6. The memory subsystem according to claim 1, wherein the boot partition includes a primary boot loader transmitted to the host system through the serial interface.

7. The memory subsystem according to claim 6, wherein the memory device includes a second-stage boot loader transmitted to the host system through the high-speed interface controller.

8. The memory subsystem according to claim 7, wherein the second-stage boot loader is transmitted to the host system in response to a request from the host system.

9. The memory subsystem according to claim 7, wherein when power is applied to the memory subsystem, the serial interface controller and the high-speed interface controller are initialized at least partially in parallel.

10. The memory subsystem according to claim 9, wherein after receiving power, before the second host interface is initialized and available for transmitting data from the memory device, the memory subsystem transmits the primary boot loader from the boot partition memory to the host system along the first host interface.

11. A computing system, comprising: A controller; And A non-volatile memory subsystem, which is coupled to the controller through a first interface that is a serial interface and a second interface that is a high-speed interface, and the memory subsystem includes: A memory device, which includes a boot partition and a user partition, A serial interface controller, which transmits data from the boot partition to the controller using the serial interface, and A high-speed interface controller, which transmits data from the memory device to the controller using the high-speed interface.

12. The computing system according to claim 11, wherein the serial interface is a four-channel Serial Peripheral Interface (QSPI) interface.

13. The computing system according to claim 11, wherein the high-speed interface is one of a Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA), and Unified Protocol (UniPro) interface.

14. The computing system according to claim 11, wherein the memory device includes timing settings and firmware code that uses the timing settings to set a timing configuration of the serial interface controller.

15. The computing system according to claim 14, wherein the firmware code initializes the high-speed interface controller.

16. The computing system according to claim 11, wherein the memory subsystem uses the serial interface to transfer a primary boot loader from the boot partition to the controller.

17. The computing system according to claim 11, wherein the memory subsystem uses the high-speed interface to transfer a second-stage boot loader from the memory device to the controller.

18. The computing system according to claim 17, wherein the memory subsystem transfers the second-stage boot loader in response to receiving a request for the second-stage boot loader from the controller.

19. The computing system according to claim 11, wherein after receiving power, before the high-speed interface is initialized and available to transfer data from the memory device to the controller, the memory subsystem transfers the primary boot loader from the boot partition to the controller along the serial interface.

20. The computing system according to claim 11, wherein after receiving power, the memory subsystem initializes the serial interface controller, initializes the high-speed interface controller, transfers the primary boot loader from the boot partition to the controller along the serial interface before the high-speed interface controller completes initialization, and transfers the second-stage boot loader from the memory device to the controller along the high-speed interface when the high-speed interface controller completes initialization.

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