Controller function abnormity dynamic repair method, system, equipment, medium and product

Abstract

The invention discloses a controller function abnormity dynamic restoration method, system, device, medium and product, a processor sends a to-be-processed signal to a signal processing component, the signal processing component analyzes the to-be-processed signal, obtains an instruction type of the to-be-processed signal and signal content of the to-be-processed signal, and stores the instruction type and the signal content of the to-be-processed signal. And when the instruction type of the to-be-processed signal is the instruction type corresponding to the target functional defect, intercepting the to-be-processed signal, generating first response data according to the signal content of the to-be-processed signal, and sending the first response data to the controller. The signal processing component can dynamically determine whether to intercept the signal according to different instruction types and repair the signal content to generate the response data, so that the system can flexibly cope with various functional abnormalities of the controller. When a system needs to add a new function or repair a new defect, only the logic of the signal processing component needs to be updated, and the whole controller does not need to be replaced or a hardware architecture does not need to be redesigned.

Description

Technical Field

[0001] This application relates to the technical field of servers, and particularly to a method, system, device, medium, and product for dynamically repairing abnormal controller functions. Background Art

[0002] In the field of servers, currently, the CPU (Central Processing Unit) and the BMC (Baseboard Management Controller) interact through the eSPI interface (Enhanced Serial Peripheral Interface), and the eSPI provides the vgpio (virtual GPIO, to reduce the number of pins) function to complete the handshake work for the CPU power-on timing.

[0003] In related technologies, the BMC is connected to the CS0 (chip select 0) of the CPU through the eSPI (Enhanced Serial Peripheral Interface) to implement the basic eSPI protocol function. The enhanced serial peripheral interface bus includes a peripheral channel, a virtual GPIO channel, an out-of-band management channel, a flash access channel, etc. At the same time, the CPLD (Complex Programmable Logic Device) is connected to the CS1 (chip select 1) of the CPU to assist in implementing simple functions, mainly the virtual GPIO channel. However, when there are functional defects in the BMC chip itself, since functions such as power-on timing interaction control (key function) must be implemented on CS0, the key function completely depends on the BMC chip. Also, due to the relatively fixed function division between CS0 and CS1, it is difficult to flexibly expand functions through software or simple hardware adjustments. Therefore, it is impossible to expand through CS1 or other channels to implement the same key function as CS0. Thus, once the BMC chip fails, the system may not be able to start or run normally.

[0004] Therefore, how to ensure the normal operation of the system in the case of BMC function loss is an urgent problem to be solved currently. Summary of the Invention

[0005] This application provides a method, system, device, medium, and product for dynamically repairing abnormal controller functions to at least solve the problem in related technologies of how to ensure the normal operation of the system in the case of BMC function loss.

[0006] The present application provides a method for dynamically repairing controller function anomalies, which is applied to a system for dynamically repairing controller function anomalies. The system for dynamically repairing controller function anomalies includes a processor, a signal processing component, and a controller. The processor is connected to the signal processing component, and the signal processing component is connected to the controller. The controller has a target function defect. The method includes: The processor sends a signal to be processed to the signal processing component; The signal processing component receives the signal to be processed sent by the processor, analyzes the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, intercept the signal to be processed, generate first response data according to the signal content of the signal to be processed, and send the first response data to the controller.

[0007] The present application also provides a system for dynamically repairing controller function anomalies, which includes: a processor, a signal processing component, and a controller. The processor is connected to the signal processing component, and the signal processing component is connected to the controller. The controller has a target function defect; The processor is configured to: send a signal to be processed to the signal processing component; The signal processing component is configured to: receive the signal to be processed sent by the processor, analyze the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, intercept the signal to be processed, generate first response data according to the signal content of the signal to be processed, and send the first response data to the controller.

[0008] The present application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above methods for dynamically repairing controller function anomalies when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods for dynamically repairing controller function anomalies are implemented.

[0010] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above methods for dynamically repairing controller function anomalies are implemented.

[0011] With this application, a signal to be processed is sent to a signal processing component by a processor. The signal processing component parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to a target functional defect, the signal to be processed is intercepted, and first response data is generated based on the signal content of the signal to be processed, and the first response data is sent to a controller. Since the signal processing component can dynamically determine whether to intercept a signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly handle various functional abnormalities of the controller without large-scale modification of the hardware. When the system needs to add new functions or repair new defects, only the logic of the signal processing component needs to be updated, without replacing the entire controller or redesigning the hardware architecture. By dynamically repairing a controller with functional defects through the signal processing component, the deficiencies of the controller can be effectively made up, ensuring that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional abnormalities and improve the overall stability of the system. For example, in a server system, there are some functional defects in the BMC (Baseboard Management Controller), such as the failure of the Virtual Wire Channel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to Virtual Wire, repair the signal content, and generate a response signal to be returned to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly illustrate the embodiments of this application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 FIG. [ID] is a schematic diagram of the architecture of a dynamic repair system for controller functional abnormalities provided by an embodiment of this application; Figure 2 FIG. [ID] is a schematic diagram of the process of a dynamic repair method for controller functional abnormalities provided by an embodiment of this application. DETAILED IMPLEMENTATION MANNER

[0014] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0015] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0017] Term Explanation: BMC: Baseboard Management Controller, the baseboard management controller.

[0018] IPMI: Intelligent Platform Management Interface, the intelligent platform management interface.

[0019] eSPI: Enhanced Serial Peripheral Interface, the enhanced serial peripheral interface.

[0020] SPI: Serial Peripheral Interface, the serial peripheral interface.

[0021] BIOS: Basic Input Output System, the basic input output system.

[0022] I2C: Inter-Integrated Circuit, the serial integrated circuit bus. I2C is a synchronous serial communication protocol used to connect low-speed devices and is commonly used for communication between a microcontroller and peripherals (such as sensors, EEPROMs, etc.). I2C uses two lines (the clock line SCL and the data line SDA) for communication and supports a multi-master multi-slave architecture.

[0023] UART: Universal Asynchronous Receiver / Transmitter, a general asynchronous transceiver. UART is a common serial communication protocol used for asynchronous communication. It allows devices to transfer data at variable baud rates and is often used for communication between a computer and a modem, or between an embedded system and its peripherals. The UART interface typically consists of two lines: RX (receive) and TX (transmit).

[0024] GPIO: General Purpose Input / Output, a programmable digital interface used to enable simple digital signal interaction between a microcontroller or processor and external devices. GPIO pins can be configured as input or output modes to control devices such as LEDs, buttons, and relays, or to read digital signals from sensors.

[0025] CPLD (Complex Programmable Logic Device) is a programmable logic device and is part of the Field Programmable Gate Array (FPGA) and Programmable Logic Device (PLD) families. A CPLD is a general-purpose digital logic chip that can be programmed to implement various digital circuit functions. Its main features are its flexibility and reconfigurability, enabling it to quickly customize logic functions according to user requirements and is widely used in digital circuit design.

[0026] Abnormal eSPI (Enhanced Serial Peripheral Interface) functions of the BMC (Baseboard Management Controller) may lead to system crashes or malfunctions. For example, the following are common types of abnormal eSPI functions: 1) Internal BMC failures, i.e., due to faults within the BMC itself, resulting in abnormal eSPI functions; 2) Or, due to an overly large log file in the BMC, it may occupy too much storage space and affect eSPI functions; 3) Communication failures: Abnormal communication of the bus master device. The eSPI bus master device (such as the BMC) may encounter errors when communicating with slave devices. For example, situations such as an unfinished transaction, data overflow, or transmission interruption. Or, channel link errors. When the two channels of eSPI are linked, if an error occurs in the main channel 1 during the transmission of channel 2, it may cause a communication interruption.

[0027] In the server field, currently, the CPU (Central Processing Unit) and the BMC (Baseboard Management Controller) interact through the eSPI interface (Enhanced Serial Peripheral Interface). The eSPI provides the vgpio (virtual GPIO, to reduce the number of pins) function to complete the handshake work for the CPU power-on timing.

[0028] In the related art, the BMC is connected to the CS0 (chip select 0) of the CPU through the eSPI (Enhanced Serial Peripheral Interface) to implement the basic eSPI protocol function. The enhanced serial peripheral interface bus includes a peripheral channel, a virtual GPIO channel, an out-of-band management channel, a flash access channel, etc. At the same time, the CPLD (Complex Programmable Logic Device) is connected to the CS1 (chip select 1) of the CPU to assist in implementing simple functions, mainly the virtual GPIO channel. However, when there are functional defects in the BMC chip itself, since key functions such as power-on timing interaction control (key function) must be implemented on CS0, the key function completely depends on the BMC chip. Also, because the functional division of CS0 and CS1 is relatively fixed, it is difficult to flexibly expand functions through software or simple hardware adjustment. Therefore, it is impossible to expand through CS1 or other channels to implement the same key function as CS0. Thus, once the BMC chip fails, the system may not be able to start or run normally.

[0029] Therefore, how to ensure the normal operation of the system in the case of BMC function loss is an urgent problem to be solved currently.

[0030] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the controller function exception dynamic repair method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0031] Embodiments of the present application provide a controller function exception dynamic repair system. Refer to Figure 1As shown, the system includes: a processor 11, a signal processing component 12, and a controller 13. Among them, the processor 11 is connected to the signal processing component 12, the signal processing component 12 is connected to the controller 13, and the controller 13 has a target functional defect. In the embodiments of the present disclosure, the processor 11 may include, but is not limited to, a processor with data processing functions such as a CPU, a CPU, an MCU, etc. The signal processing component 12 may include, but is not limited to, programmable logic devices such as a CPLD, an FPGA, etc. The programmable characteristics of the CPLD, FPGA, etc. allow for dynamic updates of the repair logic to adapt to different application requirements and newly emerging problems. The controller 13 may include, but is not limited to, various BMC chips. A CPLD is inserted between the CPU and the BMC to form a cascaded structure of CPU-CPLD-BMC. The CPLD connects to the CPU and the BMC through the eSPI interface to implement functions such as data interception and parsing, dynamic repair, and transparent forwarding. Hardware-level repair is achieved through the CPLD, avoiding delays and limitations at the software level, enabling real-time interception and processing of eSPI communication data, and ensuring the efficiency of repair. Through the hardware-level automatic repair function, the need for manual intervention is reduced, and the system maintenance cost is lowered. Among them, the target functional defect includes: one of abnormal peripheral channel function, virtual GPIO channel function failure, out-of-band management channel function abnormality, and flash access channel function abnormality. It should be noted that after a BMC chip is selected, its functional defect is known, and the CPLD expands and repairs the eSPI function according to the known functional defect. For example, the Virtual Wire Channel (vgpio) function of the BMC fails, resulting in the BMC being unable to be compatible with certain peripherals or protocols. In this system, the processor 11 sends a signal to be processed to the signal processing component 12; the signal processing component 12 receives the signal to be processed sent by the processor 11; parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, intercepts the signal to be processed, and generates first response data according to the signal content of the signal to be processed; sends the first response data to the controller 13. Since the signal processing component can dynamically determine whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly handle various functional abnormalities of the controller without large-scale modification of the hardware. When the system needs to add new functions or repair new defects, only the logic of the signal processing component needs to be updated, without replacing the entire controller or redesigning the hardware architecture. By dynamically repairing the controller with functional defects through the signal processing component, the deficiencies of the controller can be effectively made up, ensuring that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional abnormalities and improve the overall stability of the system.For example, in a server system, there are certain functional defects in the BMC (Baseboard Management Controller), such as the failure of the Virtual Wire Channel (virtual GPIO) function. Through this dynamic repair method, the CPLD (Signal Processing Component) can intercept signals related to Virtual Wire, repair the signal content, and generate response signals to be returned to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0032] Embodiments of the present application provide a method for dynamically repairing abnormal controller functions, which is applied to a system for dynamically repairing abnormal controller functions. Combining with the execution process of the method for dynamically repairing abnormal controller functions, the method will be described in detail.

[0033] Referring to Figure 2 As shown, the method for dynamically repairing abnormal controller functions provided by the embodiments of the present invention includes the following steps: S21. The processor sends a signal to be processed to the signal processing component.

[0034] Among them, the processor is the main control unit of the system, responsible for generating and sending the signal to be processed.

[0035] The signal processing component is used to receive and process the signal to be processed sent. The signal processing component may include but is not limited to CPLD, FPGA, ASIC or other dedicated hardware modules.

[0036] Exemplarily, the processor generates the signal to be processed according to system requirements. The signal to be processed may be a control signal, a data signal or other types of signals. For example, the processor may need to send a command for the Virtual Wire Channel to read or write a certain register.

[0037] Optionally, the processor and the signal processing component are communicatively connected through a preset protocol bus interface.

[0038] Among them, the preset protocol bus interface is the communication bridge between the processor and the signal processing component, used for transmitting signals.

[0039] In some embodiments, the above step S21 can be implemented in the following manner: The processor sends the signal to be processed to the signal processing component through the preset protocol bus interface.

[0040] Specifically, the processor sends the signal to be processed to the signal processing component through a preset protocol bus interface (such as eSPI).

[0041] Exemplarily, the processor sends a GET_VWIRE command with a command code of 0x01 via the eSPI bus. The GET_VWIRE command is a command in the eSPI (Enhanced Serial Peripheral Interface) protocol for reading the status of Virtual Wire signals. The Virtual Wire channel is used to transmit simple control signals and status information, similar to the traditional GPIO function but implemented via the eSPI bus. The data format of this command includes a signal index (Index) and a signal value (Data).

[0042] Optionally, the preset protocol bus is an enhanced serial peripheral interface bus.

[0043] In the embodiments of the present disclosure, the preset protocol bus interface can be eSPI.

[0044] S22. The signal processing component receives the signal to be processed sent by the processor; parses the signal to be processed to obtain the instruction type and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, intercepts the signal to be processed, and generates first response data according to the signal content of the signal to be processed; and sends the first response data to the controller.

[0045] Among them, the target function defects include: one of abnormal peripheral channel function, virtual GPIO channel function failure, out-of-band management channel function abnormality, and flash access channel function abnormality.

[0046] Exemplarily, when the target function defect is an abnormal peripheral channel function, the signal processing component can intercept the command of the Peripheral Channel and generate a correct response. When the target function defect is a virtual GPIO channel function failure, the signal processing component can intercept the command of the Virtual Wire Channel and generate a correct response. When the target function defect is an out-of-band management channel function abnormality, the signal processing component can intercept the command of the OOB Channel and generate a correct response. When the target function defect is a flash access channel function abnormality, the signal processing component can intercept the command of the Run-timeFlash Access Channel and generate a correct response.

[0047] In the embodiments of the present disclosure, by dynamically repairing the eSPI function abnormality of the BMC, system crashes or malfunctions caused by abnormalities are avoided. The use of a hardware-level repair mechanism improves the reliability of the repair and reduces system failures caused by software errors.

[0048] Protocol parsing can identify the transaction types (such as read, write, configuration) in the eSPI protocol and extract address, data, and control information.

[0049] Through the above steps, the signal processing component can effectively receive, parse, process, and respond to the signals sent by the processor, thus making up for the functional deficiencies of the BMC or other controllers. This method is applicable to complex systems that require high reliability and flexibility, such as servers, embedded systems, etc.

[0050] Through this application, the processor sends the signal to be processed to the signal processing component. The signal processing component parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, the signal to be processed is intercepted, and the first response data is generated according to the signal content of the signal to be processed, and the first response data is sent to the controller. Since the signal processing component can dynamically determine whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly handle various functional abnormalities of the controller without large-scale modification of the hardware. When the system needs to add new functions or repair new defects, only the logic of the signal processing component needs to be updated, without replacing the entire controller or redesigning the hardware architecture. By dynamically repairing the controller with functional defects through the signal processing component, the deficiencies of the controller can be effectively made up, ensuring that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional abnormalities and improve the overall stability of the system. For example, in a server system, the BMC (Baseboard Management Controller) has some functional defects, such as the failure of the Virtual Wire Channel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept the signals related to Virtual Wire, repair the signal content, and generate response signals to return to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0051] Correspondingly, since the processor and the signal processing component are communicatively connected through a preset protocol bus interface, the above step S22 (the signal processing component receives the signal to be processed sent by the processor) can be implemented in the following manner: The signal processing component receives the signal to be processed sent by the processor through the preset protocol bus interface.

[0052] Specifically, the signal processing component receives the signal to be processed sent by the processor through a preset protocol bus interface (such as eSPI), that is, the signal processing component monitors the signals on the eSPI bus and receives the signal when a new transaction is detected. The signal processing component parses the received signal and extracts the instruction type and signal content.

[0053] Exemplarily, the signal processing component parses the Command instruction on the eSPI bus to determine the instruction type. According to the instruction type, relevant data content is extracted, such as register address, data value, etc.

[0054] The signal processing component determines whether to intercept the signal according to predefined rules. If the instruction type corresponds to a target function defect (such as the failure of the Virtual GPIO channel function), interception processing is performed. The signal processing component processes the signal content according to predefined repair logic. For example, if the Virtual GPIO channel function fails, the signal processing component can read data from or write data to internal registers. Correct response data is generated according to the repair result. The signal processing component sends the generated first response data back to the processor through the preset protocol bus interface.

[0055] In some embodiments, the signal processing component is connected to the controller through a preset protocol bus interface. The above step S12 (sending the first response data to the controller) can be implemented in the following manner: The signal processing component sends the first response data to the processor through the preset protocol bus interface.

[0056] Through the communication between the processor and the signal processing component, and the dynamic processing of the signal by the signal processing component, the functional defect problem in the system can be effectively solved. This architecture is particularly suitable for complex systems that require high reliability and flexibility, such as servers, embedded systems, etc.

[0057] Optionally, the signal processing component is also connected to the controller through a preset communication interface.

[0058] When the preset protocol bus interface fails, the above step S12 (sending the first response data to the controller) can also be implemented in the following manner: The signal processing component sends the first response data to the processor through the preset communication interface.

[0059] Further, in some embodiments, the preset communication interface includes: a serial integrated circuit bus interface, a general-purpose input / output interface, and a universal asynchronous receiver / transmitter interface.

[0060] When a failure occurs in the preset protocol bus interface, the above step S12 (sending the first response data to the controller) can also be implemented in the following manner: The signal processing component sends the first response data to the processor through at least one of the serial integrated circuit bus interface, the general-purpose input / output interface, and the universal asynchronous receiver / transmitter interface.

[0061] In the embodiments of the present disclosure, the processor is used to generate and send a signal to be processed, and receive the response data sent by the processing component; the signal processing component is used to receive the signal to be processed sent by the processor, parse the signal content, and process the signal according to predefined logic to generate response data, and send the response data back to the processor; the controller is a BMC, which is used to receive the response data sent by the signal processing component. The preset protocol bus interface is the main communication interface, such as the eSPI bus, which is used for communication between the processor and the signal processing component. The preset communication interface is the backup communication interface, such as I2C, SPI, UART, etc., which is used to provide a backup communication path when the main communication interface fails. For example, when the preset protocol bus interface fails, the signal processing component sends the response data to the processor through the preset communication interface (such as I2C, SPI, UART). For example, the GPIO interface is used to notify the BMC to obtain data after the CPLD finishes processing the data. Another example is the I2C interface. When the CPU needs to use the eSPI to set or query the status of a certain GPIO, but the BMC has a functional defect and cannot implement the corresponding function, the CPLD needs to be used for processing. Since the number of VGPIOs may be relatively large, if physical GPIOs are used, too many GPIO numbers need to be occupied. Using I2C can be more convenient for expansion and reduce the IO occupation.

[0062] Exemplarily, the signal processing component detects whether the eSPI bus fails through a heartbeat mechanism or an error detection mechanism. If a failure is detected, the eSPI_fault flag is set. When the eSPI_fault flag is set, the signal processing component switches to the backup communication interface (such as I2C). Initialize the backup communication interface to ensure its normal operation. The signal processing component sends the response data to the processor through the backup communication interface (such as I2C). For example, send the value of the Virtual Wire register through the I2C bus.

[0063] By introducing the backup communication interface, the signal processing component can send the response data through the backup communication interface (such as I2C, SPI, UART) when the main communication interface (such as the eSPI bus) fails, so as to ensure that the system can still operate normally when the main communication interface fails. The backup communication interface can be selected according to specific requirements, such as I2C, SPI, UART, etc.

[0064] With this application, a signal to be processed is sent to a signal processing component by a processor. The signal processing component parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, the signal to be processed is intercepted, and first response data is generated based on the signal content of the signal to be processed, and the first response data is sent to the controller. Since the signal processing component can dynamically determine whether to intercept a signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly handle various functional anomalies of the controller without large-scale modification of the hardware. When the system needs to add new functions or repair new defects, only the logic of the signal processing component needs to be updated, without replacing the entire controller or redesigning the hardware architecture. By dynamically repairing a controller with functional defects through the signal processing component, the deficiencies of the controller can be effectively compensated, ensuring that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional anomalies and improve the overall stability of the system. For example, in a server system, the BMC (Baseboard Management Controller) has some functional defects, such as the failure of the Virtual Wire Channel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to Virtual Wire, repair the signal content, and generate a response signal to be returned to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0065] In some embodiments, before intercepting the signal to be processed when the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, the following steps may further be performed: According to a preset interception instruction database, determine whether the instruction type of the signal to be processed is the instruction type corresponding to the target function defect; the preset interception instruction database includes: multiple instruction types corresponding to the target function defects of the controller.

[0066] Among them, the preset interception instruction database is a set that stores all known instruction types corresponding to target function defects, and is used to help the signal processing component quickly determine whether the received signal needs to be intercepted. This database can be a simple look-up table (LUT) or a more complex storage structure, depending on the complexity and requirements of the system.

[0067] Exemplarily, if the target functional defect includes the failure of the Virtual GPIO channel function, then the database will include instruction types related to Virtual GPIO, such as GET_VWIRE (0x01) and PUT_VWIRE (0x02).

[0068] Further, in some embodiments, the above step (judging whether the instruction type of the to-be-processed signal is the instruction type corresponding to the target functional defect according to the preset interception instruction database) can be implemented in the following manner: Compare the instruction type of the to-be-processed signal with the preset interception instruction database; If the instruction type of the to-be-processed signal matches the target interception instruction type in the preset interception instruction database, it is determined that the instruction type of the to-be-processed signal is the instruction type corresponding to the target functional defect; the target interception instruction type is the instruction type corresponding to the target functional defect.

[0069] Specifically, after the signal processing component receives the to-be-processed signal, it parses the signal to obtain the instruction type. Then, the signal processing component judges whether this instruction type corresponds to the target functional defect according to the preset interception instruction database. The signal processing component receives the signal through the preset protocol bus interface and parses out the instruction type and data content. The signal processing component looks up the parsed instruction type in the preset interception instruction database to judge whether this instruction needs to be intercepted. If the instruction type corresponds to the target functional defect, the signal processing component will intercept this signal, and its interception logic is: the signal processing component prevents the signal from being directly transmitted to the controller, but performs local processing on it and executes the predefined repair logic. The signal processing component sends the generated response data back to the processor to complete the entire processing process.

[0070] Through the preset interception instruction database, the signal processing component can more accurately judge which signals need to be intercepted and processed without modifying the hardware logic. In addition, it is also possible to easily add or delete the instruction types to be intercepted to adapt to different functional defects and application scenarios.

[0071] Through this application, a signal to be processed is sent to a signal processing component by a processor. The signal processing component parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, the signal to be processed is intercepted, and first response data is generated according to the signal content of the signal to be processed, and the first response data is sent to the controller. Since the signal processing component can dynamically determine whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly handle various function abnormalities of the controller without large-scale modification of the hardware. When the system needs to add new functions or repair new defects, only the logic of the signal processing component needs to be updated, rather than replacing the entire controller or redesigning the hardware architecture. By dynamically repairing the controller with functional defects through the signal processing component, the deficiencies of the controller can be effectively compensated, ensuring that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller function abnormalities and improve the overall stability of the system. For example, in a server system, the BMC (Baseboard Management Controller) has some functional defects, such as the failure of the Virtual Wire Channel (Virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to Virtual Wire, repair the signal content, and generate a response signal to return to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0072] In some embodiments, the above step (generating the first response data according to the signal content of the signal to be processed) can be implemented in the following manner: Obtain a preset repair strategy corresponding to the instruction type of the signal to be processed; According to the preset repair strategy, repair or process the signal content of the signal to be processed to generate the first response data.

[0073] It can be understood that the preset repair strategy can be stored in a lookup table, which stores a set of repair logics corresponding to all known target function defects, and is used to assist the signal processing component to perform corresponding repair or processing operations according to different instruction types and signal contents. For example, the repair strategy for CMD_GET_VWIRE is to read the Virtual Wire register, and the repair strategy for CMD_PUT_VWIRE is to write to the Virtual Wire register.

[0074] Specifically, after the signal processing component obtains the preset repair strategy corresponding to the instruction type of the signal to be processed from the lookup table, it repairs or processes the signal content according to the preset repair strategy. For example, for the GET_VWIRE command, the signal processing component reads data from the internal register; for the PUT_VWIRE command, the signal processing component writes data to the internal register. After the repair or processing is completed, the signal processing component generates the first response data and sends it back to the processor via the eSPI bus.

[0075] Through the preset repair strategy, the signal processing component can execute corresponding repair or processing logic according to different instruction types and signal contents, so as to generate correct response data.

[0076] In some embodiments, when the instruction type of the signal to be processed is not the instruction type corresponding to the target function defect, the signal processing component sends the signal to be processed to the controller; The controller responds to the signal to be processed, obtains the second response data of the signal to be processed; sends the second response data to the signal processing component; The signal processing component receives the second response data sent by the controller; forwards the second response data to the processor.

[0077] Specifically, the signal processing component looks up the instruction type parsed in the preset interception instruction database to determine whether the instruction needs to be intercepted. If the instruction type does not belong to the instruction type corresponding to the target function defect, the signal processing component directly forwards the received signal to the controller without any processing. After receiving the signal, the controller processes the signal according to the normal logic, generates the second response data, sends the second response data to the signal processing component, and the signal processing component receives the second response data sent by the controller and feeds back the second response data to the processor.

[0078] The signal processing component can flexibly decide whether to intervene according to different instruction types. The signal processing component only intervenes when necessary, and keeps the normal transmission of the signal in other cases.

[0079] Optionally, before forwarding the second response data to the processor, the following steps can also be executed: The signal processing component processes the second response data according to the preset data format to obtain the processed second response data.

[0080] Specifically, before forwarding the second response data to the processor, according to the preset data format, the signal processing component performs operations such as format conversion, verification, or encryption on the response data to obtain the processed second response data. Among them, signal escaper refers to converting one signal format or protocol into another format or protocol. A CPLD is added between the BMC and the CPU, and the CPLD can serve as the core component for signal escaper. Through its programmable logic resources, the CPLD can implement the conversion of multiple signal formats. For example, converting an SPI signal to an I2C signal, or converting a parallel signal to a serial signal. The CPLD can intercept signals sent from the CPU to the BMC, or signals sent from the BMC to the CPU.

[0081] Through the preset data format, the signal processing component can flexibly process response data in different formats without modifying the hardware logic, and ensure that the format of the response data meets the requirements of the processor, improving the compatibility of the system.

[0082] In addition, when the CPLD detects that the BMC is working abnormally (after power-on, it has not sent a heartbeat to the CPLD), the CPLD can take over the power-on timing control function of the BMC and the CPU, and force a return so that the CPU can be powered on normally. If the BMC supports forced repair under the system, the firmware of the BMC can be repaired under the system to enhance reliability.

[0083] The dynamic repair method for controller function anomalies provided by the embodiments of the present disclosure sends a signal to be processed to a signal processing component through a processor. The signal processing component parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, the signal to be processed is intercepted, and first response data is generated based on the signal content of the signal to be processed and sent to the controller. Since the signal processing component can dynamically determine whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly handle various function anomalies of the controller without large-scale modification of the hardware. When the system needs to add new functions or repair new defects, only the logic of the signal processing component needs to be updated, without replacing the entire controller or redesigning the hardware architecture. By dynamically repairing the controller with function defects through the signal processing component, the deficiencies of the controller can be effectively compensated, ensuring that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller function anomalies and improve the overall stability of the system. For example, in a server system, there are some function defects in the BMC (Baseboard Management Controller), such as the failure of the Virtual Wire Channel (Virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to Virtual Wire, repair the signal content, and generate a response signal to return to the CPU. In this way, even if the BMC has function defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0084] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0085] Figure 1 It is a schematic diagram of the architecture of a dynamic repair system for controller function anomalies provided by the present disclosure. Refer to Figure 1 As shown, the dynamic repair system for controller function anomalies includes: a processor 11, a signal processing component 12, and a controller 13. The processor 11 is connected to the signal processing component 12, the signal processing component 12 is connected to the controller 13, and the controller 13 has a target function defect; The processor 11 is configured to: send a signal to be processed to the signal processing component; The signal processing component 12 is configured to: receive the signal to be processed sent by the processor; parse the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, intercept the signal to be processed, and generate first response data according to the signal content of the signal to be processed; send the first response data to the controller 13.

[0086] As an optional implementation manner of the embodiment of the present disclosure, the signal processing component is further configured to: when the instruction type of the signal to be processed is not the instruction type corresponding to the target function defect, send the signal to be processed to the controller; The controller is configured to: respond to the signal to be processed to obtain second response data of the signal to be processed; send the second response data to the signal processing component; The signal processing component is further configured to: receive the second response data sent by the controller; forward the second response data to the processor.

[0087] As an optional implementation manner of the embodiment of the present disclosure, the signal processing component is further configured to: the signal processing component processes the second response data according to a preset data format to obtain the processed second response data.

[0088] As an optional implementation manner of the embodiment of the present disclosure, the target function defect includes one of abnormal peripheral channel function, virtual GPIO channel function failure, out-of-band management channel function abnormality, and flash access channel function abnormality.

[0089] As an optional implementation manner of the embodiment of the present disclosure, the signal processing component is further configured to: According to a preset interception instruction database, determine whether the instruction type of the signal to be processed is the instruction type corresponding to the target function defect; the preset interception instruction database includes: multiple instruction types corresponding to the target function defect of the controller.

[0090] As an optional implementation manner of the embodiment of the present disclosure, the signal processing component is further specifically configured to: compare the instruction type of the signal to be processed with the preset interception instruction database; If the instruction type of the signal to be processed matches the target interception instruction type in the preset interception instruction database, determine that the instruction type of the signal to be processed is the instruction type corresponding to the target function defect; the target interception instruction type is the instruction type corresponding to the target function defect.

[0091] As an alternative implementation manner of an embodiment of the present disclosure, the signal processing component is further specifically configured to: obtain a preset repair strategy corresponding to the instruction type of the signal to be processed; According to the preset repair strategy, repair or process the signal content of the signal to be processed to generate first response data.

[0092] As an alternative implementation manner of an embodiment of the present disclosure, the processor is communicatively connected to the signal processing component through a preset protocol bus interface; The processor is specifically configured to: the processor sends the signal to be processed to the signal processing component through the preset protocol bus interface; The signal processing component is specifically configured to: the signal processing component receives the signal to be processed sent by the processor through the preset protocol bus interface.

[0093] As an alternative implementation manner of an embodiment of the present disclosure, the signal processing component is connected to the controller through a preset protocol bus interface; The signal processing component is further specifically configured to: the signal processing component sends the first response data to the processor through the preset protocol bus interface.

[0094] As an alternative implementation manner of an embodiment of the present disclosure, the signal processing component is further connected to the controller through a preset communication interface; When the preset protocol bus interface fails, the signal processing component is further specifically configured to: the signal processing component sends the first response data to the processor through the preset communication interface.

[0095] As an alternative implementation manner of an embodiment of the present disclosure, the preset communication interface includes: a serial integrated circuit bus interface, a general-purpose input / output interface, and a universal asynchronous receiver / transmitter interface; When the preset protocol bus interface fails, the signal processing component is further specifically configured to: the signal processing component sends the first response data to the processor through at least one of the serial integrated circuit bus interface, the general-purpose input / output interface, and the universal asynchronous receiver / transmitter interface.

[0096] For the description of the features in the corresponding embodiment of the controller function abnormal dynamic repair system, reference may be made to the relevant description in the corresponding embodiment of the controller function abnormal dynamic repair method, which will not be elaborated here one by one.

[0097] The controller function anomaly dynamic repair system provided by the embodiments of the present disclosure includes: a processor, a signal processing component, and a controller. Among them, the processor is connected to the signal processing component, and the signal processing component is connected to the controller. The controller has a target function defect. The processor sends a signal to be processed to the signal processing component. The signal processing component parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, the signal to be processed is intercepted, and first response data is generated according to the signal content of the signal to be processed and sent to the controller. Since the signal processing component can dynamically determine whether to intercept a signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly handle various function anomalies of the controller without large-scale modification of the hardware. When the system needs to add new functions or repair new defects, only the logic of the signal processing component needs to be updated, without replacing the entire controller or redesigning the hardware architecture. By dynamically repairing the controller with function defects through the signal processing component, the deficiencies of the controller can be effectively compensated, ensuring that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller function anomalies and improve the overall stability of the system. For example, in a server system, the BMC (Baseboard Management Controller) has some function defects, such as the failure of the Virtual Wire Channel (Virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to Virtual Wire, repair the signal content, and generate a response signal to be returned to the CPU. In this way, even if the BMC has function defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0098] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the controller function anomaly dynamic repair method.

[0099] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the controller function anomaly dynamic repair method when running.

[0100] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media that can store computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs.

[0101] An embodiment of the present application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the method for dynamically repairing abnormal controller functions.

[0102] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the method for dynamically repairing abnormal controller functions.

[0103] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0104] The above has introduced in detail a method for dynamically repairing abnormal controller functions provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A dynamic repair method for controller function anomalies, characterized in that, Applied to a controller function abnormal dynamic repair system, the controller function abnormal dynamic repair system includes a processor, a signal processing component, and a controller. The processor is connected to the signal processing component, and the signal processing component is connected to the controller. The controller has a target function defect. The method includes: The processor sends a signal to be processed to the signal processing component. The signal processing component receives the signal to be processed sent by the processor, parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed. When the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, intercept the signal to be processed, and generate first response data according to the signal content of the signal to be processed, and send the first response data to the controller.

2. The method for dynamically repairing abnormal controller functions according to claim 1, characterized in that The method further includes: When the instruction type of the signal to be processed is not the instruction type corresponding to the target function defect, the signal processing component sends the signal to be processed to the controller. The controller responds to the signal to be processed, obtains second response data of the signal to be processed, and sends the second response data to the signal processing component. The signal processing component receives the second response data sent by the controller and forwards the second response data to the processor.

3. The method for dynamically repairing abnormal controller functions according to claim 2, wherein Before forwarding the second response data to the processor, the method further includes: The signal processing component processes the second response data according to a preset data format to obtain the processed second response data.

4. The method for dynamically repairing abnormal controller functions according to claim 1, wherein The target function defect includes one of abnormal peripheral channel function, virtual GPIO channel function failure, out-of-band management channel function abnormal, and flash access channel function abnormal.

5. The method for dynamically repairing abnormal controller functions according to claim 1, wherein Before intercepting the signal to be processed when the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, the method further includes: The signal processing component determines whether the instruction type of the signal to be processed is the instruction type corresponding to the target function defect according to a preset interception instruction database. The preset interception instruction database includes multiple instruction types corresponding to the target function defect of the controller.

6. The method for dynamically repairing abnormal controller functions according to claim 5, wherein The determining whether the instruction type of the signal to be processed is the instruction type corresponding to the target function defect according to the preset interception instruction database includes: Comparing the instruction type of the signal to be processed with the preset interception instruction database. If the instruction type of the signal to be processed matches the target interception instruction type in the preset interception instruction database, it is determined that the instruction type of the signal to be processed is the instruction type corresponding to the target function defect. The target interception instruction type is the instruction type corresponding to the target function defect.

7. The method for dynamically repairing abnormal controller functions according to claim 1, characterized in that, The generating first response data according to the signal content of the signal to be processed includes: Obtaining a preset repair strategy corresponding to the instruction type of the signal to be processed. Repairing or processing the signal content of the signal to be processed according to the preset repair strategy to generate first response data.

8. The method for dynamically repairing abnormal controller functions according to claim 1, wherein The processor is communicatively connected to the signal processing component through a preset protocol bus interface; The processor sends a signal to be processed to the signal processing component, including: The processor sends the signal to be processed to the signal processing component through the preset protocol bus interface; The signal processing component receives the signal to be processed sent by the processor, including: The signal processing component receives the signal to be processed sent by the processor through the preset protocol bus interface.

9. The method for dynamically repairing abnormal controller functions according to claim 1, characterized in that The signal processing component is connected to the controller through a preset protocol bus interface; Sending the first response data to the controller, including: The signal processing component sends the first response data to the processor through the preset protocol bus interface.

10. The dynamic repair method for controller function anomalies according to claim 9, characterized in that The signal processing component is also connected to the controller through a preset communication interface; When the preset protocol bus interface fails, sending the first response data to the controller further includes: The signal processing component sends the first response data to the processor through the preset communication interface.

11. The method for dynamically repairing abnormal controller functions according to claim 10, characterized in that, The preset communication interface includes: a serial integrated circuit bus interface, a general-purpose input / output interface, and a universal asynchronous receiver / transmitter interface; When the preset protocol bus interface fails, sending the first response data to the controller further includes: The signal processing component sends the first response data to the processor through at least one of the serial integrated circuit bus interface, the general-purpose input / output interface, and the universal asynchronous receiver / transmitter interface.

12. A dynamic repair system for controller function anomalies, characterized in that, The controller function abnormal dynamic repair system includes: a processor, a signal processing component, and a controller. The processor is connected to the signal processing component, the signal processing component is connected to the controller, and the controller has a target function defect; The processor is configured to: send a signal to be processed to the signal processing component; The signal processing component is configured to: receive the signal to be processed sent by the processor; parse the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target function defect, intercept the signal to be processed, and generate first response data according to the signal content of the signal to be processed; send the first response data to the controller.

13. The system according to claim 12, characterized in that, The system further includes: The signal processing component is further configured to: when the instruction type of the signal to be processed is not the instruction type corresponding to the target function defect, send the signal to be processed to the controller; The controller is configured to: respond to the signal to be processed, obtain second response data of the signal to be processed; send the second response data to the signal processing component; The signal processing component is further configured to: receive the second response data sent by the controller; forward the second response data to the processor.

14. The system according to claim 12, wherein The processor is communicatively connected to the signal processing component through a preset protocol bus interface; the signal processing component is connected to the controller through the preset protocol bus interface, and / or, a preset communication interface.

15. The system according to claim 14, characterized in that The preset protocol bus is an enhanced serial peripheral interface bus.

16. The system according to claim 14, wherein The preset communication interface includes: a serial integrated circuit bus interface, a general-purpose input / output interface, and a universal asynchronous receiver / transmitter interface.

17. The system according to claim 14, wherein, When a fault occurs in the preset protocol bus interface, the signal processing component and the controller are connected through the preset communication interface.

18. An electronic device, characterized in that, Comprising: a memory for storing a computer program; a processor for implementing the steps of the method for dynamically repairing abnormal controller functions according to any one of claims 1 to 11 when executing the computer program.

19. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the method for dynamically repairing abnormal controller functions according to any one of claims 1 to 11.

20. A computer program product, comprising a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the method for dynamically repairing abnormal controller functions according to any one of claims 1 to 11.

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