A verification test method, device and medium for UFS commands

Abstract

The present invention discloses a verification test method for UFS commands, comprising the following steps: 1) dynamically generating UFS commands, wherein the UFS commands are a set of operation commands for managing UFS devices; 2) a transmitter adding a CRC checksum flag to the UFS commands; 3) injecting predefined CRC errors into the UFS commands; 4) setting clock frequency, command response time, and data transmission delay parameters, as well as the frequency of error injection, and then sending the UFS commands; 5) the UFS device receiving UFS commands with erroneous CRC values ​​and performing a CRC check upon receiving these commands, with the checksum result being: detecting a CRC check failure and recording an error message; or reporting a timeout; 6) setting the number of test cycles and analyzing the error detection capability of the UFS device based on CRC value comparison results and timeout events. The present invention provides a verification method for UFS devices based on CRC checksums, which comprehensively verifies the data integrity and reliability of the UFS device.

Description

Technical Field

[0001] The present invention relates to semiconductor memory technology, and in particular to a verification test method, device and medium for UFS commands. Background Art

[0002] In computer storage systems, data transmission and storage integrity are crucial. CRC, a widely used error detection method, effectively detects bit errors during data transmission. As high-performance storage devices, UFS (Universal Flash Storage) devices require reliable error detection and correction mechanisms during command and data transmission. CRC is widely used in various communication protocols and storage devices, such as Modbus, RTU, and ASCII mode.

[0003] Testing methods for UFS devices are primarily defined by protocols from standards organizations such as JEDEC, covering aspects such as protocol conformance, performance, physical layer, and functional testing. These testing methods ensure the high performance and interoperability of UFS devices. However, due to hardware or software compatibility issues and limitations of test tools, the testing methods for UFS devices specified by relevant standard protocols can lead to inaccurate test results. This paper proposes a CRC-based error injection and verification testing method. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a verification test method, device and medium for UFS commands in view of the defects in the prior art.

[0005] The technical solution adopted by the present invention to solve the technical problem is: a verification test method for UFS commands, comprising the following steps:

[0006] 1) Dynamically generate UFS commands, where UFS commands are a set of operation commands for managing UFS devices;

[0007] 2) The sending end adds a CRC check flag to the UFS command;

[0008] 2.1) Get the version of the UFS device;

[0009] 2.2) Use the standard CRC-16 or CRC-32 algorithm to generate a checksum based on the UFS protocol requirements for obtaining the UFS device version;

[0010] 3) Injecting predefined CRC errors into UFS commands;

[0011] Among them, the ways to inject errors include:

[0012] Inject byte flip errors, such as flipping 0xAA bytes to 0x55, to simulate byte-level errors in data transmission;

[0013] Timing perturbation: Modify specific bytes of UFS commands to simulate CRC errors;

[0014] Modify certain bits of the CRC value to generate an incorrect CRC value;

[0015] 4) Set the clock frequency, command response time, data transmission delay parameters, and error injection frequency, and the sender sends the UFS command;

[0016] 5) The receiving UFS device receives a UFS command with an incorrect CRC value. After receiving these commands, the receiving end performs a CRC check. The check result is: detecting that the CRC check fails and recording an error message; or reporting a timeout;

[0017] 6) Set the number of test cycles and analyze the error detection capability of the UFS device based on the CRC value verification results.

[0018] According to the above scheme, in step 2.2), the parallel CRC check algorithm is implemented using FPGA, as follows:

[0019] 2.2.1) Use linear feedback shift register (LFSR) to generate pseudo-random sequence;

[0020] 2.2.2) XOR the input data with the polynomial corresponding to the UFS device version, and gradually update the LFSR state;

[0021] 2.2.3) The obtained LFSR state is the CRC check code.

[0022] According to the above solution, in step 3), a UFS command with a CRC error is generated by FPGA:

[0023] After generating the CRC value, the FPGA records the location of the CRC field and modifies certain bits of the CRC value, thereby generating an incorrect CRC value.

[0024] According to the above scheme, in step 2.2), the calculation process of the CRC check code is as follows:

[0025] Initialize the CRC register to FFFFh;

[0026] Perform an XOR operation on the first 8-bit byte of the UFS command and the low byte of the CRC register, and store the result in the CRC register;

[0027] Process the subsequent bytes of the UFS command according to the above steps until all bytes are processed;

[0028] The final CRC register value is used as the CRC check code.

[0029] According to the above solution, in step 3), a CRC error is simulated by modifying specific bytes of the UFS command.

[0030] According to the above solution, in step 3), the UFS command is intercepted at the Linux driver layer and the CRC field is dynamically modified.

[0031] The present invention further provides an electronic device, comprising:

[0032] one or more processors;

[0033] as well as

[0034] a storage device for storing one or more programs,

[0035] When the one or more programs are executed by the one or more processors, the one or more processors execute the method described in any one of the above solutions.

[0036] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in any one of the above solutions is implemented.

[0037] The beneficial effects produced by the present invention are:

[0038] 1. The present invention provides a verification method for a UFS device based on CRC check;

[0039] 2. This invention comprehensively verifies the data integrity and reliability of UFS devices by simulating multiple error injection scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0041] Figure 1 It is a flow chart of a method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] like Figure 1 As shown, a verification test method for UFS commands includes the following steps:

[0044] 1) Dynamically generate UFS commands, where UFS commands are a set of operation commands for managing UFS devices;

[0045] 2) The sending end adds a CRC check flag to the UFS command;

[0046] 2.1) Get the version of the UFS device;

[0047] 2.2) Use the standard CRC-16 or CRC-32 algorithm to generate a checksum based on the UFS protocol requirements for obtaining the UFS device version;

[0048] 3) Injecting predefined CRC errors into UFS commands;

[0049] Among them, the ways to inject errors include:

[0050] Inject byte flip errors, such as flipping 0xAA bytes to 0x55, to simulate byte-level errors in data transmission;

[0051] Timing perturbation: Modify specific bytes of UFS commands to simulate CRC errors;

[0052] Modify certain bits of the CRC value to generate an incorrect CRC value;

[0053] 4) Set the clock frequency, command response time, data transmission delay parameters, and error injection frequency, and the sender sends the UFS command;

[0054] 5) The UFS device (receiver) receives a UFS command with an incorrect CRC value. After receiving these commands, the receiver performs a CRC check. The check result is: CRC check failure is detected and an error message is recorded; or a timeout is reported;

[0055] 6) Set the number of test cycles and analyze the error detection capability of the UFS device based on the CRC value comparison results and timeout events.

[0056] Example 1: CRC check test based on UART interface;

[0057] A verification test method for UFS commands, comprising the following steps:

[0058] A) Dynamically generate UFS commands;

[0059] B) In UART communication, send the UFS command with CRC check code;

[0060] In UART communication, the sender needs to attach a CRC checksum to the UFS command. The CRC checksum is usually calculated by the sender and attached to the command.

[0061] After receiving the command, the receiving end recalculates the CRC value and compares it with the received CRC value.

[0062] The calculation process of the CRC check code is as follows:

[0063] Initialize the CRC register to FFFFh.

[0064] Perform an XOR operation on the first 8-bit byte of the command message and the low byte of the CRC register, and store the result in the CRC register.

[0065] The above steps are repeated for each subsequent byte until all bytes have been processed. The final CRC value is the checksum.

[0066] C) Modify the data packets in UART communication through the error simulation module:

[0067] When using the UART communication interface, the error simulation module modifies specific bytes in the data packet to inject a CRC error. For example, you can change a byte in the data packet from 0x01 to 0x02, thereby changing its CRC value.

[0068] D) Setting the clock frequency, command response time, data transmission delay parameters, and error injection frequency, the sender sends the UFS command;

[0069] E) The modified data packet will trigger a CRC check failure at the receiving end, thereby verifying the error detection capability of the UFS device.

[0070] F) Verify the error detection capability of the UFS device:

[0071] When the receiving end receives a data packet with an incorrect CRC value, it detects the CRC check failure and logs the error information. In this way, the error detection capability of the UFS device in UART communication can be evaluated.

[0072] Example 2: Parallel CRC check test based on FPGA;

[0073] A verification test method for UFS commands, comprising the following steps:

[0074] a) Dynamically generate UFS commands;

[0075] b) Add CRC checksum to UFS commands based on FPGA;

[0076] b1) Get the version of the UFS device;

[0077] b2) Using FPGA to implement parallel CRC check algorithm:

[0078] FPGAs can implement parallel CRC check algorithms through hardware, significantly improving test efficiency. Parallel CRC checks leverage the FPGA's parallel processing capabilities to complete CRC calculations for multiple bytes within each clock cycle.

[0079] The CRC check code is generated as follows:

[0080] b2.1) Generate a pseudo-random sequence using a linear feedback shift register (LFSR);

[0081] b2.2) XOR the input data with the polynomial corresponding to the UFS device version, gradually updating the LFSR state;

[0082] b2.3) The final LFSR state is the CRC check code.

[0083] c) Generate UFS command with CRC error via FPGA:

[0084] FPGAs can not only generate correct CRC values, but can also intentionally introduce CRC errors through hardware logic. For example, certain bits can be modified during the CRC value generation process to generate an incorrect CRC value.

[0085] This error injection method can simulate CRC errors that may occur in actual communications, thereby verifying the error detection capability of UFS devices in high-speed data transmission.

[0086] d) Setting the clock frequency, command response time, and data transmission delay parameters, as well as the frequency of error injection, the sender sends the UFS command;

[0087] e) The receiving end verifies the error detection capability of the UFS device during high-speed data transmission:

[0088] The UFS commands generated by the FPGA with incorrect CRC values ​​are sent to the UFS device. When the receiving UFS device receives the commands with incorrect CRC values, it detects the CRC check failure and logs the error information.

[0089] f) Set the number of test cycles and analyze the error detection capability of the UFS device based on the CRC value verification results;

[0090] When the receiving end receives a data packet with an incorrect CRC value, it detects the CRC check failure and logs the error message or reports a timeout. In this way, the error detection capability and robustness of the UFS device in high-speed data transmission can be evaluated.

[0091] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A verification test method for UFS commands, characterized in that: The following steps are involved: 1) Dynamically generate UFS commands, where UFS commands are a set of operation commands for managing UFS devices; 2) The sending end adds a CRC check flag to the UFS command; 2.1) Get the version of the UFS device; 2.2) Generate a verification code according to the UFS protocol requirements for obtaining the version of the UFS device; 3) Injecting predefined CRC errors into UFS commands; Among them, the method of injecting errors uses the following methods: Inject byte flip errors to simulate byte-level errors in data transmission; Timing perturbation: Modify specific bytes of UFS commands to simulate CRC errors; Modify one or more bits of the CRC value to generate an incorrect CRC value; 4) Set the clock frequency, command response time, data transmission delay parameters, and error injection frequency, and the sender sends the UFS command; 5) The UFS device receives a UFS command with an incorrect CRC value. After receiving these commands, it performs a CRC check. The check result is: detecting that the CRC check fails and recording an error message; or reporting a timeout; 6) Set the number of test cycles and analyze the error detection capability of the UFS device based on the CRC value comparison results and timeout events.

2. The verification test method for UFS commands according to claim 1, wherein: In step 2.2), FPGA is used to generate the CRC check code, as follows: 2.2.1) Use linear feedback shift register (LFSR) to generate pseudo-random sequence; 2.2.2) XOR the input data with the polynomial corresponding to the UFS device version, and gradually update the LFSR state; 2.2.3) The final LFSR state is the CRC check code.

3. The verification test method for UFS commands according to claim 1, wherein: In step 3), a UFS command with a CRC error is generated by the FPGA: After generating the CRC value, the FPGA records the location of the CRC field and modifies certain bits of the CRC value, thereby generating an incorrect CRC value.

4. The verification test method for UFS commands according to claim 1, wherein: In step 2.2), the calculation process of the CRC check code is as follows: Initialize the CRC register to FFFFh; Perform an XOR operation on the first 8-bit byte of the UFS command and the low byte of the CRC register, and store the result in the CRC register; Process the subsequent bytes of the UFS command according to the above steps until all bytes are processed; The final CRC register value is used as the CRC check code.

5. The verification test method for UFS commands according to claim 1, wherein: In step 3), a CRC error is simulated by modifying specific bytes of the UFS command.

6. The verification test method for UFS commands according to claim 1, wherein: In step 3), the UFS command is intercepted at the Linux driver layer and the CRC field is dynamically modified.

7. An electronic device, characterized in that: include: one or more processors; as well as a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors are enabled to perform the method according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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