Data processing method, CXL controller, computing device and CXL memory device

Abstract

The invention discloses a data processing method, a CXL controller, computing equipment and CXL memory equipment, relates to the field of computing equipment, and can effectively avoid leakage of data in a CXL memory. Specifically, the CXL controller obtains encoded target data from the CXL memory in response to a data reading instruction. And obtaining a target decoding parameter, decoding the encoded target data based on the target decoding parameter, obtaining the target data under the condition that the target decoding parameter is correct, and returning the target data according to the data reading instruction.

Description

Technical Field

[0001] This application relates to the field of computing devices, and in particular, to a data processing method, a CXL controller, a computing device, and a CXL memory device. Background Art

[0002] Compute Express Link (CXL) memory can be connected to a computing device to provide additional memory space for the computing device. CXL memory can enable memory sharing among multiple processes running on the same computing device, and can also enable memory sharing among multiple computing devices.

[0003] After any process of a certain computing device writes data to the CXL memory, other processes of the same computing device or other computing devices can also read the data from the CXL memory, that is, obtain the plaintext data from the CXL memory. Thus, when the CXL memory is accessed by an insecure process or computing device, the data in the CXL memory may be leaked. Summary of the Invention

[0004] Embodiments of this application provide a data processing method, a CXL controller, a computing device, and a CXL memory device, which can effectively avoid data leakage in the CXL memory.

[0005] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a data processing method is provided, which is applied to a CXL controller. The CXL controller is connected to a CXL memory and a computing device (such as the first computing device and the second computing device in this application). The method includes: in response to a read data instruction, obtaining encoded target data from the CXL memory; obtaining target decoding parameters, and based on the target decoding parameters, decoding the encoded target data. When the target decoding parameters are correct, obtaining the target data, and returning the target data for the read data instruction.

[0007] Among them, the read data instruction is used to indicate reading the target data.

[0008] It can be seen from the above technical solutions that the entity generating the read data instruction cannot directly read the original data (or called plaintext data, such as the target data in this application) from the CXL memory. What is read is the encoded target data, and the encoded target data read needs to be decoded using the target decoding parameters. Thus, only when the encoded target data is correct can the target data be obtained from the CXL memory. It is possible to avoid the phenomenon that an insecure process, application, or computing device obtains plaintext data from the CXL memory, effectively improve the security of CXL memory access, and avoid data leakage in the CXL memory.

[0009] In addition, a CXL controller can be connected to multiple computing devices simultaneously. By improving a CXL controller, even if the CXL controller has decoding capabilities to decode the encoded target data, it is possible to avoid multiple computing devices (or processes or applications running in multiple computing devices) from directly obtaining plaintext data from the CXL memory at the same time. In this way, the deployment difficulty of this solution can be reduced, and the compatibility and feasibility of this solution can be improved.

[0010] In an alternative embodiment, the CXL controller stores decoding parameters. Correspondingly, the obtaining of the target decoding parameters may specifically include: determining the target decoding parameters based on the decoding parameters stored in the CXL controller.

[0011] In this embodiment, it is described that decoding parameters can be stored in the CXL controller. The CXL controller can quickly determine the target decoding parameters from the decoding parameters stored in itself to improve the processing efficiency of the CXL controller.

[0012] In an alternative embodiment, the CXL controller is connected to a computing device, and processes and applications can run in the computing device. On this basis, a first correspondence can be stored in the CXL controller, and the first correspondence is used to indicate at least one of the decoding parameters corresponding to the upper computing device, the decoding parameters corresponding to the above process, or the decoding parameters corresponding to the above application.

[0013] On this basis, the obtaining of the target decoding parameters may specifically include: obtaining, from the first correspondence, the target decoding parameters corresponding to the entity that generates the read data instruction. Wherein, the entity that generates the read data instruction is at least one of the above computing device, the above process, or the above application.

[0014] In this embodiment, it is described that different decoding parameters can be stored in the CXL controller, such as the decoding parameters corresponding to the computing device connected to the CXL controller, the decoding parameters corresponding to the process or application running in the computing device connected to the CXL controller, etc. In this way, the CXL controller can quickly obtain the target decoding parameters from the decoding parameters stored in itself to improve the processing efficiency of the CXL controller.

[0015] In an alternative embodiment, the first correspondence can be stored in the memory controller of the CXL controller. The obtaining of the target decoding parameters may specifically include: obtaining the first correspondence from the memory controller, and determining the target decoding parameters based on the first correspondence. Correspondingly, the decoding of the encoded target data may specifically include: decoding the encoded target data through the memory controller.

[0016] In this embodiment, the first correspondence can be stored in the memory controller of the CXL controller, and the decoding operation of the data can be implemented through the memory controller of the CXL controller. Among the multiple components included in the CXL controller (such as the CXL physical layer (PHY), memory controller, etc.), the distance between the memory controller and the CXL memory is closer, and the encoded target data can be quickly decoded after being read out from the CXL memory. In this way, the decoding rate of the encoded target data can be improved.

[0017] In an alternative embodiment, the first correspondence can be stored in the CXL peripheral component interconnect express (PCIe) PHY of the CXL controller. The obtaining of the target decoding parameters can specifically include: obtaining the first correspondence from the CXL PCIe PHY, and determining the target decoding parameters based on the first correspondence. Correspondingly, the decoding of the encoded target data can specifically include: sending the target decoding parameters to the memory controller of the CXL controller, and decoding the encoded target data through the memory controller.

[0018] In this embodiment, it is described that the decoding parameters in the CXL PCIe PHY can be sent to the memory controller. In this way, the encoded target data can be decoded by the memory controller subsequently. The distance between the memory controller and the CXL memory is closer, and the encoded target data can be quickly decoded after being read out from the CXL memory. In this way, the decoding rate of the encoded target data can be improved.

[0019] In an alternative embodiment, the CXL controller can periodically obtain the first correspondence from the above-mentioned computing device.

[0020] In this embodiment, it is described that the CXL controller can update the first correspondence stored in itself based on the first correspondence stored in the computing device, which can avoid the leakage of decoding parameters, further improve the security of CXL memory access, and prevent the data in the CXL memory from being leaked.

[0021] In an alternative embodiment, the target decoding parameters can be carried in the read data instruction.

[0022] In this embodiment, it is described that the target decoding parameters can be carried in the read data instruction. In this way, the CXL controller can directly parse the read data instruction to obtain the target decoding parameters, which can further improve the processing efficiency of the CXL controller.

[0023] In an alternative embodiment, the CXL controller can be connected to a first computing device and a second computing device. Correspondingly, when the main body of the read data instruction is a first process, the first process can run in the first computing device, or the first process can run in the second computing device. When the main body of the read data instruction is a first application, the first application can run in the first computing device, or the first application can run in the second computing device.

[0024] In this embodiment, the main body of the generated read data instruction is described. The main body can be a process or application running in the first computing device, or a process or application running in other computing devices (such as the second computing device) except the first computing device. In this way, the compatible scenarios of this application can be expanded.

[0025] In an alternative embodiment, the above method may further include: decoding the encoded target data based on target decoding parameters, and obtaining garbled data when the target decoding parameters are incorrect. For the read data instruction, return the garbled data.

[0026] In this embodiment, when the decoding parameters are incorrect, the obtained data is garbled data. It can avoid the phenomenon that an insecure process, application, or device obtains plaintext data from the CXL memory. In this way, the security of CXL memory access can be effectively improved, and the data in the CXL memory can be prevented from being leaked.

[0027] In an alternative embodiment, the above method may further include: in response to a write data instruction, obtaining target data. Obtaining target encoding parameters, encoding the target data based on the target encoding parameters to obtain the encoded target data, and writing the encoded target data into the CXL memory.

[0028] Among them, the write data instruction is used to indicate writing target data into the CXL memory.

[0029] In this embodiment, the data stored in the CXL is encoded data (such as the encoded target data), rather than plaintext data (such as the target data). In this way, an insecure process, application, or device cannot directly read plaintext data from the CXL memory, which can further prevent an insecure process from obtaining plaintext data from the CXL memory, thereby improving the security of CXL memory access and preventing the data in the CXL memory from being leaked.

[0030] In addition, a CXL controller can be connected to multiple computing devices at the same time. By improving a CXL controller, it is possible to avoid the phenomenon that multiple computing devices (or processes or applications running in multiple computing devices) directly obtain plaintext data from the CXL memory. In this way, the compatibility and feasibility of this solution can be improved.

[0031] In an alternative embodiment, the write data instruction includes a target encoding parameter.

[0032] In this embodiment, it is described that the target encoding parameter can be carried in the write data instruction. In this way, the CXL controller can directly parse the write data instruction to obtain the target encoding parameter, which can effectively improve the processing efficiency of the CXL controller.

[0033] In an alternative embodiment, the CXL controller stores an encoding parameter. Accordingly, the above-mentioned obtaining of the target encoding parameter may specifically include: determining the target encoding parameter based on the encoding parameter stored in the CXL controller.

[0034] In this embodiment, it is described that an encoding parameter can be stored in the CXL controller. The CXL controller can quickly determine the target encoding parameter from the encoding parameters stored in itself to improve the processing efficiency of the CXL controller.

[0035] In an alternative embodiment, the CXL controller is connected to a computing device, and a process and an application are running in the computing device. A second correspondence is stored in the CXL controller, and the second correspondence is used to indicate at least one of: the encoding parameter corresponding to the type of the target data, the encoding parameter corresponding to the computing device, the encoding parameter corresponding to the process, and the encoding parameter corresponding to the application.

[0036] On this basis, the above-mentioned obtaining of the target encoding parameter may specifically include: obtaining, from the second correspondence, the target encoding parameter corresponding to the entity that generates the write data instruction, where the entity that generates the write data instruction is at least one of the above-mentioned computing device, the above-mentioned process, or the above-mentioned application.

[0037] In this embodiment, it is described that different encoding parameters can be stored in the CXL controller, such as the encoding parameter corresponding to the computing device connected to the CXL controller, the encoding parameter corresponding to the process or application running in the computing device connected to the CXL controller, etc. In this way, the CXL controller can quickly obtain the target decoding parameter from the encoding parameters stored in itself to improve the processing efficiency of the CXL controller.

[0038] In an alternative embodiment, the second correspondence can be stored in the memory controller of the CXL controller. The above-mentioned obtaining of the target encoding parameter may specifically include: obtaining the second correspondence from the memory controller, and determining the target encoding parameter based on the second correspondence. Accordingly, the above-mentioned encoding of the target data may specifically include: encoding the target data through the memory controller.

[0039] In this embodiment, the second correspondence can be stored in the memory controller of the CXL controller, and the target data can be encoded through the memory controller of the CXL controller. Among the multiple components included in the CXL controller (such as CXL PCIe PHY, memory controller, etc.), the distance between the memory controller and the CXL memory is closer. Before writing the target data into the CXL memory, the target data can be encoded to obtain the encoded target data, and the encoded target data is written into the CXL memory. In this way, the encoding rate of the target data can be improved.

[0040] In an alternative embodiment, the second correspondence can be stored in the CXL PCIe PHY of the CXL controller. The above-mentioned obtaining of the target encoding parameters may specifically include: obtaining the second correspondence from the CXL PCIe PHY, and determining the target encoding parameters based on the second correspondence. Correspondingly, the above-mentioned encoding of the target data may specifically include: sending the target encoding parameters to the memory controller of the CXL controller, and encoding the target data through the memory controller.

[0041] In this embodiment, it is described that the encoding parameters in the CXL PCIe PHY can be sent to the memory controller. In this way, subsequently, the target data can be encoded through the memory controller. The distance between the memory controller and the CXL memory is closer. Before writing the target data into the CXL memory, the target data can be encoded to obtain the encoded target data, and the encoded target data is written into the CXL memory. In this way, the encoding rate of the target data can be improved.

[0042] In an alternative embodiment, the CXL controller can periodically obtain the second correspondence from the above-mentioned computing device.

[0043] In this embodiment, it is described that the CXL controller can update its own stored second correspondence based on the second correspondence stored in the management computing device, which can avoid leakage of encoding parameters, can further improve the security of CXL memory access, and prevent data in the CXL memory from being leaked.

[0044] In a second aspect, a data processing apparatus is provided. The apparatus includes: functional units for performing the functions of any of the methods provided in the first aspect, and the actions performed by each functional unit are implemented by hardware or by hardware executing corresponding software. For example, the data processing apparatus may include: an acquisition unit, a decoding unit, and a sending unit. Among them, the acquisition unit is configured to, in response to a read data instruction, acquire encoded target data from the CXL memory and acquire target decoding parameters. The decoding unit is configured to decode the encoded target data based on the target decoding parameters, and obtain the target data when the target decoding parameters are correct. The sending unit is configured to return the target data in response to the read data instruction.

[0045] In a third aspect, a CXL controller is provided, including a processor, the processor is coupled to a memory, and the memory is used to store programs or instructions. When the programs or instructions are executed by the processor, the CXL controller is caused to execute any of the methods provided in the first aspect.

[0046] In a fourth aspect, a chip is provided. The chip includes: a processor and an interface circuit; the interface circuit is configured to receive code instructions and transmit them to the processor; the processor is configured to run the code instructions to execute any of the methods provided in the first aspect above.

[0047] In a fifth aspect, a computer-readable storage medium is provided, storing computer-executable instructions. When the computer-executable instructions are run on a computer, the computer is caused to execute any of the methods provided in the first aspect above.

[0048] In a sixth aspect, a computer program product is provided, including computer-executable instructions. When the computer-executable instructions are run on a computer, the computer is caused to execute any of the methods provided in the first aspect above.

[0049] In a seventh aspect, a computing device is provided, including a CXL controller, a CXL memory, a memory, and a processor. The CXL controller, the CXL memory, the memory, and the processor are coupled, and the CXL controller is configured to execute any of the methods provided in the first aspect.

[0050] In an eighth aspect, a CXL memory device is provided, including a CXL controller and a CXL memory. The CXL controller and the CXL memory are coupled, and the CXL controller is configured to execute any of the methods provided in the first aspect.

[0051] Among them, for the technical effects brought by any implementation manner in the second aspect to the eighth aspect, reference may be made to the technical effects brought by different implementation manners in the first aspect, which will not be elaborated here. Description of the Drawings

[0052] Figure 1Schematic diagram of CXL memory shared between server CXL244 and server CXL248;

[0053] Figure 2 Schematic diagram of the architecture of a computing cluster provided by an embodiment of the present application;

[0054] Figure 3 Another schematic diagram of the architecture of a computing cluster provided by an embodiment of the present application;

[0055] Figure 4 Another schematic diagram of the architecture of a computing cluster provided by an embodiment of the present application;

[0056] Figure 5 Schematic diagram of the process of a data processing method provided by an embodiment of the present application;

[0057] Figure 6 Schematic diagram of a CXL PCIe PHY and a memory controller provided by an embodiment of the present application;

[0058] Figure 7 Another schematic diagram of a CXL PCIe PHY and a memory controller provided by an embodiment of the present application;

[0059] Figure 8 Another schematic diagram of the architecture of a computing cluster provided by an embodiment of the present application;

[0060] Figure 9 Schematic diagram of the process of storing encoded target data in CXL memory provided by an embodiment of the present application;

[0061] Figure 10 Schematic diagram of the structure of a data processing device provided by an embodiment of the present application. Detailed implementation manners

[0062] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application.

[0063] Among them, in the description of the present application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship. For example, A / B may represent A or B; "and / or" in the present application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. These three situations, where A and B can be singular or plural.

[0064] Furthermore, in the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0065] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0066] The following is an introduction to the terms involved in the embodiments of the present application.

[0067] CXL: is a high-speed interconnect technology standard designed for high-performance data center computers. It can quickly and reliably transmit data between different components inside computing devices, such as central processing unit (CPU), accelerator, memory, smart network interface card (Smart NIC), etc. CXL is built on the physical and electrical interface of the serial peripheral component interconnect express (PCIe). CXL protocols can include input / output protocols (CXL.io), access cache protocols (CXL.cache), and access memory protocols (CXL.mem).

[0068] Direct Access (DAX) Device: DAX technology is a technology that enables an application (hereinafter simply referred to as an app) to directly access a persistent memory device without reading and writing to the persistent memory device through the block input / output (I / O) operations of the file system, thereby effectively reducing the latency of data access. When accessing CXL memory based on DAX technology, the CXL memory can be created as a DAX device (or referred to as a CXL-DAX device).

[0069] The following introduces the application scenarios of the embodiments of this application.

[0070] With the rapid development of technologies such as big data, artificial intelligence, and cloud computing, traditional interconnection technologies have become difficult to meet the growing data transmission and data processing requirements. Compared with traditional interconnection technologies, CXL can provide higher bandwidth, lower latency, and stronger expansion capabilities, thus meeting the efficient interconnection between components such as processors (e.g., CPUs), memories, and accelerators. In future data centers, high-performance computing, and edge computing fields, CXL will become one of the key technologies for achieving high-performance and low-latency data processing.

[0071] CXL memory refers to a memory device connected to a computing device through the CXL protocol. When accessing CXL memory based on DAX technology, the CXL memory can be created as a DAX device. The DAX device can include two application modes, one is the system memory mode at the operating system (OS) control level, and the other is the direct access device (device DAX) mode at the application control level.

[0072] In the system memory mode at the operating system control level, the CXL memory can be used as an extension of the system memory and be controlled and managed by the operating system, that is: the control right of the CXL memory is concentrated at the operating system end. In this mode, the operating system can uniformly schedule the resource allocation of the CXL memory. For example: the operating system decides how much memory space to allocate for each process (or service) in the CXL memory, etc. Thus, flexible allocation of the CXL memory cannot be achieved.

[0073] In the direct access device mode at the application control level, the app is allowed to access the data stored in the CXL memory without operating through the operating system. The following will describe the process of the app accessing the CXL memory in the direct access device mode at the application control level.

[0074] CXL memory can achieve memory sharing among multiple processes running on the same computing device, and can also achieve memory sharing among multiple computing devices. Exemplarily, Figure 1 is a schematic diagram of CXL memory sharing between server CXL244 and server CXL248. As Figure 1 shown, process A and process B are running on server CXL244, and process C is running on server CXL248. In this way, CXL memory can be shared among process A, process B, and process C. On this basis, assume that process A is the writeCXLMemPattern process, and process A is used to store natural numbers in the CXL memory based on the CXL.mem protocol. After process A writes natural numbers in the CXL memory, both process B running in server CXL244 and process C running in server CXL248 can obtain the natural numbers stored by process A in the CXL memory from the CXL memory.

[0075] Based on this, an embodiment of the present application provides a data processing method applied to a CXL controller. Specifically, in response to a read data instruction, the CXL controller obtains encoded target data from the CXL memory. Obtain target decoding parameters, and based on the target decoding parameters, decode the encoded target data. When the target decoding parameters are correct, obtain the target data, and return the target data for the read data instruction.

[0076] It can be seen from the above technical solution that the entity (process, application, or computing device) that generates the read data instruction cannot directly read the original data (or called plaintext data, such as the target data) from the CXL memory. What is read is the encoded target data, and the encoded target data read needs to be decoded using the target decoding parameters. In this way, only when the encoded target data is correct can the target data be obtained from the CXL memory. In this way, it is possible to avoid the phenomenon that an insecure process, application, or computing device obtains plaintext data from the CXL memory, effectively improve the security of CXL memory access, and avoid the leakage of data in the CXL memory.

[0077] In addition, a CXL controller can be connected to multiple computing devices at the same time. By improving a CXL controller, even if the CXL controller has the decoding ability to decode the encoded target data, it is possible to avoid multiple computing devices (or processes or applications running in multiple computing devices) from directly obtaining plaintext data from the CXL memory at the same time. In this way, the deployment difficulty of this solution can be reduced, and the compatibility and feasibility of this solution can be improved.

[0078] Next, an exemplary introduction to the system architecture of the embodiment of the present application will be given.

[0079] Figure 2The figure is a schematic diagram of the architecture of a computing cluster provided by an embodiment of this application. As Figure 2 shown, the computing cluster includes at least one computing device (which can also be referred to as a host) 100 and a CXL memory device 200. Exemplarily, Figure 2 three computing devices are shown, namely a first computing device 101, a second computing device 102, and a third computing device 103.

[0080] The CXL memory device 200 communicates with the computing device 100 based on the CXL protocol.

[0081] The CXL memory device 200 may include a CXL controller 201 and a CXL memory 202 connected to the CXL controller.

[0082] It should be noted that the CXL controller 201, also known as the CXL chip, can connect the CXL memory 202 to at least one computing device 100 based on CXL technology to increase the memory capacity of the computing device 100.

[0083] The CXL memory 202 can be a storage particle (such as a dynamic random access memory (DRAM) flash particle), or a memory module (such as a dual in-line memory module (DIMM) memory module), or other types of memory. The embodiments of this application do not limit this.

[0084] The computing device 100 may include a processor and a memory.

[0085] The processor can be a CPU or other components with processing capabilities. Among them, the CPU, as the operation and control core of the computing device, is the final execution unit for information processing and program operation. The CPU is a very large-scale integrated circuit composed of an arithmetic unit, a controller, registers, etc., and its main task is to process and process various data.

[0086] The memory can be a hard disk or other memories that store data and do not lose data after power-off.

[0087] It should also be noted that the computing devices provided by the embodiments of this application (such as the first computing device 101, the second computing device 102, and the third computing device 103) can be network devices or terminal devices. Network devices can include servers, etc. Among them, the server can be a physical server, or two or more physical servers sharing different responsibilities and cooperating with each other to implement the various functions of the server, or a virtual server (which can also be called a virtual machine) running in a physical server.

[0088] Exemplarily, the server may be a blade server, a high-density server, a rack server, a tower server, etc. The terminal device may include a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a laptop computer, a netbook, a desktop computer, an all-in-one computer, etc.

[0089] In the embodiments of the present application, the relationship between the CXL memory device 200 and the computing device 100 is not limited. In one example, the CXL memory device 200 may be a memory device independent of the computing device 100, such as Figure 2 shown in (a) of Figure 2 Another example, the CXL memory device 200 may be integrated in the computing device 100, such as

[0090] In the case where the CXL memory device 200 is a memory device independent of the computing device 100, in the embodiments of the present application, the connection manner between the CXL memory device 200 and the computing device 100 is not limited.

[0091] The following will be introduced by A. The CXL memory device 200 and the computing device 100 are connected through a CXL multi-head controller (CXL multi-head expander) (which may also be referred to as CXL MH), and B. The CXL memory device 200 and the computing device 100 are connected through a CXL switch (SW).

[0092] A. The CXL memory device 200 and the computing device 100 are connected through a CXL multi-head controller.

[0093] In this embodiment, the above CXL controller 201 may be implemented as a CXL multi-head controller, so that the CXL controller can be directly connected to multiple computing devices. For example, the CXL controller may be connected to three computing devices through three ports. Another example, the CXL controller may be connected to four computing devices through four ports. Another example, the CXL controller may be connected to eight computing devices through eight ports.

[0094] Figure 3 It is a schematic diagram of the architecture of another computing cluster provided by the embodiments of the present application.

[0095] As shown in Figure 3 the computing cluster includes at least one computing device 100 and a CXL memory device 200.

[0096] The CXL memory device 200 includes a CXL controller 201 and a CXL memory 202 connected to the CXL controller.

[0097] The CXL controller 201 includes multiple ports, at least one cache coherence maintenance (Home Directory Management, HDM) decoder, and a memory controller. Exemplarily, Figure 3 Three HDM decoders are shown, namely HDM decoder 201-A, HDM decoder 201-B, and HDM decoder 201-C. The HDM decoder 201-A is connected to the first computing device 101. The HDM decoder 201-B is connected to the second computing device 102. The HDM decoder 201-C is connected to the second computing device 103.

[0098] The memory controller is connected to the CXL memory 202 and is used to access the CXL memory 202. Exemplarily, the memory controller fetches a certain data from the CXL memory 202, or the memory controller writes a certain data into the CXL memory 202.

[0099] For each computing device, the computing device can connect its root port (RP) to a port of the CXL controller 201 based on the CXL protocol to form a CXL link. When the computing device intends to fetch or write a certain data (hereinafter referred to as the target data) in the CXL memory, the computing device can send a read / write instruction for the CXL memory (such as the read data instruction or write data instruction in this application) to the corresponding HDM decoder through the CXL link. After receiving the read / write instruction, the HDM decoder can determine the storage location of the target data in the CXL memory, and the HDM decoder can send this storage location to the memory controller. The memory controller can fetch or write the target data in the CXL memory based on this storage location.

[0100] Among them, the CXL protocol may include CXL.io, CXL.cache, and CXL.mem.

[0101] Exemplarily, taking the first computing device 101 and the target data being data q as an example, when the first computing device 101 intends to obtain data q from the CXL memory, it can generate a read data instruction requesting to obtain data q from the CXL memory. The first computing device 101 can send this read data instruction to the HDM decoder 201-A through the CXL link. After receiving the read data instruction, the HDM decoder 201-A can parse the read data instruction to obtain the storage location of data q in the CXL memory. The HDM decoder 201-A can send the storage location of data q to the memory controller, and the memory controller can read data q from the CXL memory based on this storage location.

[0102] B. The CXL memory device 200 and the computing device 100 are connected through a CXL switch.

[0103] The CXL switch is a switch that follows the CXL protocol.

[0104] The CXL memory device 200 can be connected to the computing device 100 through the CXL switch based on the CXL protocol.

[0105] Figure 4 This is another schematic diagram of the architecture of the computing cluster provided by the embodiments of the present application.

[0106] As Figure 4 shown, the computing cluster includes at least one computing device 100, at least one CXL memory device 200, and a CXL switch 300. Exemplarily, Figure 4 three computing devices (the first computing device 101, the second computing device 102, and the third computing device 103 respectively) and two CXL memory devices 200 (the CXL memory device 203 and the CXL memory device 204 respectively) are shown.

[0107] Each CXL memory device 200 includes a CXL controller and a CXL memory connected to the CXL controller. The CXL controller includes an HDM decoder, a memory controller, and a port.

[0108] The CXL switch 300 includes a plurality of upstream ports (upstream switch port, USP) and a plurality of downstream ports (downstream switch port, DSP). Exemplarily, Figure 4 three upstream ports (the upstream port 301, the upstream port 302, and the upstream port 303 respectively) and three downstream ports (the downstream port 304, the downstream port 305, and the downstream port 306 respectively) are shown.

[0109] Each upstream port is used to connect a computing device 100. Accordingly, the CXL switch 300 communicates with the computing device 100 through the upstream port. Exemplarily, as Figure 4 shown, the CXL switch 300 can receive read and write instructions sent by the first computing device 101 through the upstream port 301, and can also send data to the first computing device 101 through the upstream port 301.

[0110] Each downstream port is used to connect a CXL memory device 200. Accordingly, the CXL switch 300 communicates with the CXL memory device 200 through the downstream port. Exemplarily, as Figure 4 shown, the CXL switch 300 can send read and write instructions to the CXL memory device 203 through the downstream port 304, and can also receive data sent by the CXL memory device 203 through the downstream port 304.

[0111] Virtual channel signaling (VCS) can be deployed between the upstream port and the downstream port of the CXL switch 300. VCS can send instructions received from the upstream port (such as the read data instruction or the write data instruction in this application) to the downstream port. Exemplarily, Figure 4 shows three VCSs, namely VCS1, VCS2, and VCS3. VCS1 can send the instructions received from the upstream port 301 to the downstream port 304. VCS2 can send the instructions received from the upstream port 302 to the downstream port 305. VCS3 can send the instructions received from the upstream port 303 to the downstream port 306.

[0112] In the embodiment of this application, after receiving a read data instruction requesting to read target data from the CXL memory, the CXL controller can read the encoded target data from the CXL memory, obtain the target decoding parameters, and then decode the encoded target data based on the target decoding parameters. When the target decoding parameters are correct, the target data can be obtained after decoding, and the CXL controller can return the target data.

[0113] In addition, before responding to the above read data instruction, the CXL controller can also, after receiving a write data instruction to write target data into the CXL memory, obtain the target data and the target encoding parameters, encode the target data based on the target encoding parameters to obtain the encoded target data, and write the encoded target data into the CXL memory.

[0114] The following takes the Figure 3 architecture schematic diagram shown as an example to introduce in detail the data processing method provided in the embodiment of this application.

[0115] Figure 5The flowchart of a data processing method provided by an embodiment of this application. This method is applied to Figure 2 the CXL controller in Figure 5 As shown, this method includes S501 - S504.

[0116] S501, in response to a read data instruction, obtain the encoded target data from the CXL memory.

[0117] The read data instruction is used to indicate reading the target data.

[0118] This application embodiment does not specifically limit the entity that generates the read data instruction (hereinafter simply referred to as the first entity).

[0119] The CXL controller can be connected to a computing device, and processes and applications can run in the computing device. On this basis, the first entity can be at least one of the computing device connected to the CXL controller, the process running in the computing device connected to the CXL controller, or the application running in the computing device connected to the CXL controller.

[0120] This application embodiment does not limit the number of computing devices connected to the CXL controller. For example, the number of computing devices connected to the CXL controller can be 1, 2, 4, or more.

[0121] In the case where the number of computing devices connected to the CXL controller includes multiple, the processes running in the computing devices connected to the CXL controller include the processes running in each computing device connected to the CXL controller, and the applications running in the computing devices connected to the CXL controller include the applications running in each computing device connected to the CXL controller.

[0122] This application embodiment does not limit the number of processes running in each computing device connected to the CXL controller. For example, the number of processes running in each computing device connected to the CXL controller can be several, hundreds, or thousands, etc.

[0123] This application embodiment does not limit the number of applications running in each computing device connected to the CXL controller. For example, the number of applications running in each computing device connected to the CXL controller can be several, hundreds, or thousands, etc.

[0124] In this application embodiment, a process can be a process started during the running of a certain application installed in the computing device (such as a game application, a browser application, or a video playback application, etc.), that is, an application process. It can also be a process started during the running of the operating system of the computing device, that is, a system process. It can also be a process related to the kernel of the operating system, that is, a kernel process.

[0125] A computing device connected to a CXL controller includes Figure 2 Taking the first computing device and the second computing device shown as an example, when the first entity is a computing device, the first entity can be the first computing device or the second computing device. When the first entity is a process (hereinafter referred to as the first process), the first process can run in the first computing device or in the second computing device. When the first entity is an application (hereinafter referred to as the first application), the first application can run in the first computing device or in the second computing device.

[0126] Specifically, taking the first entity as the first computing device as an example. When the first computing device intends to obtain a certain data (hereinafter referred to as the target data) from the CXL memory, it can generate a read data request for reading the target data from the CXL memory and send the read data request to the CXL controller. After receiving the read data request, the CXL controller can first determine the memory address of the encoded target data, and then based on this memory address, read the encoded target data from the CXL memory.

[0127] The memory address refers to the storage location of the encoded target data in the CXL memory.

[0128] The embodiments of the present application do not specifically limit the manner in which the CXL controller determines the memory address of the encoded target data.

[0129] In one example, the read data instruction may include the memory address of the encoded target data. Accordingly, after receiving the read data instruction, the CXL controller can parse the read data instruction to obtain the memory address of the encoded target data.

[0130] In another example, the CXL controller may store the correspondence between the data identifiers of each data stored in the CXL memory and the memory addresses of the data after encoding each data in the CXL memory (hereinafter simply referred to as the address correspondence). Accordingly, after receiving the read data instruction, the CXL controller can parse the read data instruction to obtain the data identifier of the target data, and based on the data identifier of the target data, determine the memory address of the encoded target data from the address correspondence stored in itself.

[0131] In an optional implementation manner, the CXL controller may include a transceiver module, a CXL PCIe PHY, and a memory controller. The transceiver module is used to communicate with the computing device. The CXL PCIe PHY is used to determine the memory address of the encoded target data. The memory controller is used to read the encoded target data from the CXL memory. Among them, the CXL PCIe PHY is the physical layer of CXL PCIe, which refers to the lowest layer of the data link and is responsible for the transceiver and processing of physical signals.

[0132] The transceiver module may include at least one transmit module (TX) and at least one receive module (RX). Exemplarily, Figure 6 two transmit modules (transmit module A and transmit module B respectively) and two receive modules (receive module A and receive module B respectively) are shown. The transmit module may be connected to the computing device through a lane to send the data read from the CXL memory to the computing device through the lane. The receive module may be connected to the computing device 100 through the lane to receive the read and write instructions (such as the read data instruction and the write data instruction in the present application) sent by the computing device through the lane.

[0133] The following will continue to take the first entity as the first computing device as an example to illustrate the above S501 through the interaction between the first computing device, the receive module, the CXL PCIe PHY, the memory controller, and the CXL memory.

[0134] As Figure 6 shown, after the first computing device generates a read data request to read target data from the CXL memory, it may send the read data request to the receive module of the CXL controller through the lane. After the receive module of the CXL controller receives the read data request, it may send the read data request to the CXL PCIe PHY through the mail-box (MB) channel. After the CXL PCIe PHY receives the read data request, it may determine the memory address of the encoded target data and send the memory address to the memory controller. After the memory controller receives the memory address, it may read the encoded target data from the CXL memory based on the memory address.

[0135] S502, obtain the target decoding parameter.

[0136] The embodiments of the present application do not specifically limit the manner in which the CXL controller obtains the target decoding parameter. The following will respectively introduce: one, obtaining the target decoding parameter from the read data instruction; two, determining the target decoding parameter based on the decoding parameter stored in the CXL controller; and three, obtaining the target decoding parameter from the first correspondence stored in the CXL controller.

[0137] One, obtaining the target decoding parameter from the read data instruction.

[0138] In this embodiment, the read data instruction may carry the target decoding parameter. Correspondingly, after the CXL controller receives the read data instruction, it may parse the read data instruction to obtain the target decoding parameter.

[0139] Two, determining the target decoding parameter based on the decoding parameter stored in the CXL controller.

[0140] In this embodiment, decoding parameters can be stored in the CXL controller. Correspondingly, the above CXL controller obtaining the target decoding parameters can specifically include: determining the target decoding parameters based on the decoding parameters stored in the CXL controller.

[0141] The embodiment of the present application does not limit the number of decoding parameters stored in the CXL controller. For example, the number of decoding parameters stored in the CXL controller can be 1, 2, 4 or more, etc.

[0142] Taking the number of decoding parameters stored in the CXL controller being 1 as an example, the CXL controller can use the decoding parameter stored by itself as the target decoding parameter.

[0143] Taking the number of decoding parameters stored in the CXL controller being multiple as an example, the CXL controller can randomly select one decoding parameter from the decoding parameters stored by itself as the target decoding parameter.

[0144] Third, obtaining the target decoding parameters from the first correspondence stored in the CXL controller.

[0145] In this embodiment, a first correspondence can be stored in the CXL controller, and the first correspondence is used to indicate at least one of: the decoding parameter corresponding to the computing device connected to the CXL controller, the decoding parameter corresponding to the process running in the computing device connected to the CXL controller, or the decoding parameter corresponding to the application running in the computing device connected to the CXL controller. Correspondingly, after receiving the read data instruction, the CXL controller can obtain the target decoding parameter corresponding to the entity that generates the read data instruction from the first correspondence.

[0146] The embodiment of the present application does not specifically limit the storage form of the first correspondence. For example, the first correspondence can be stored in the CXL controller in the form of a table, or can be stored in the CXL controller in the form of a function.

[0147] It can be understood that in the case where the above first correspondence relationship is used to indicate multiple items among the decoding parameters corresponding to the computing device connected to the CXL controller, the decoding parameters corresponding to the process running in the computing device connected to the CXL controller, or the decoding parameters corresponding to the application running in the computing device connected to the CXL controller, the decoding parameters corresponding to the multiple items can be the same or different. For example, taking the above first correspondence relationship as an example to indicate the decoding parameters corresponding to the computing device connected to the CXL controller, the decoding parameters corresponding to the process running in the computing device connected to the CXL controller, and the decoding parameters corresponding to the application running in the computing device connected to the CXL controller, the decoding parameters corresponding to the computing device connected to the CXL controller, the decoding parameters corresponding to the process running in the computing device connected to the CXL controller, and the decoding parameters corresponding to the application running in the computing device connected to the CXL controller can be the same or different.

[0148] In the case where there are multiple computing devices connected to the CXL controller, the decoding parameters corresponding to each computing device can be the same or different. In one example, taking the first computing device and the second computing device included in the multiple computing devices connected to the CXL controller as an example, the decoding parameters corresponding to the first computing device and the decoding parameters corresponding to the second computing device can be the same or different.

[0149] In the case where there are multiple computing devices connected to the CXL controller, the decoding parameters corresponding to the processes running in the computing devices connected to the CXL controller may include: the decoding parameters corresponding to multiple processes running in each computing device connected to the CXL controller. For example, taking the first computing device and the second computing device included in the multiple computing devices connected to the CXL controller as an example, the decoding parameters corresponding to the processes running in the computing devices connected to the CXL controller include: the decoding parameters corresponding to each process running in the first computing device, and the decoding parameters corresponding to each process running in the second computing device.

[0150] It should be noted that the decoding parameters corresponding to different processes can be the same or different.

[0151] Taking the decoding parameters corresponding to different processes as different as an example, assuming that the processes running in the first computing device include process A and process B, and the processes running in the second computing device include process 1 and process 2, then the decoding parameters corresponding to the processes running in the computing devices connected to the CXL controller include: the decoding parameters corresponding to process A, the decoding parameters corresponding to process B, and the decoding parameters corresponding to process 1, the decoding parameters corresponding to process 2.

[0152] In the case where there are multiple computing devices connected to the CXL controller, the decoding parameters corresponding to the applications running in the computing devices connected to the CXL controller may include: the decoding parameters corresponding to multiple applications running in each computing device connected to the CXL controller. For example, taking the computing devices connected to the CXL controller including a first computing device and a second computing device as an example, the decoding parameters corresponding to the applications running in the computing devices connected to the CXL controller include: the decoding parameters corresponding to each application running in the first computing device, and the decoding parameters corresponding to each application running in the second computing device.

[0153] It should be noted that the decoding parameters corresponding to different applications may be the same or different. The decoding parameters corresponding to the same application installed in different computing devices may be the same or different. For example, assuming that application C is installed in both the first computing device and the second computing device, the decoding parameters corresponding to application C installed in the first computing device and the decoding parameters corresponding to application C installed in the second computing device may be the same or different.

[0154] Taking the decoding parameters corresponding to different applications being different as an example, assuming that the applications running in the first computing device include application A and application B, and the applications running in the second computing device include application C and application D, the decoding parameters corresponding to the applications running in the computing devices connected to the CXL controller include: the decoding parameters corresponding to application A, the decoding parameters corresponding to application B, and the decoding parameters corresponding to application C, the decoding parameters corresponding to application D.

[0155] Specifically, taking the first entity as the first computing device as an example, after the processor receives the read data instruction sent by the first computing device, it can determine the device identifier of the first computing device, and then based on the device identifier of the first computing device, determine the decoding parameters corresponding to the first computing device from the first corresponding relationship stored in itself, which are the target decoding parameters.

[0156] From the foregoing content, it can be seen that the first computing device may include a CXL PCIe PHY and a memory controller. Correspondingly, the above first corresponding relationship may be stored in the CXL PCIe PHY or in the memory controller.

[0157] In the case where the first corresponding relationship is stored in the memory controller, the above S502, that is, the CXL controller obtains the target decoding parameters, may be replaced by: obtaining the first corresponding relationship from the memory controller and determining the target decoding parameters based on the first corresponding relationship.

[0158] In the case where the first correspondence can be stored in the CXL PCIe PHY, the above S502, that is, the CXL controller obtains the target decoding parameter, can be replaced by: obtaining the first correspondence from the CXL PCIe PHY, and determining the target decoding parameter based on the first correspondence.

[0159] In the above technical solution, the first correspondence can be stored in different locations, so that the compatibility of this application can be expanded and the feasibility of this application can be improved.

[0160] In an optional implementation manner, the CXL controller may include a decoding parameter management module (which can be called a key manager), and the decoding parameter management module is used to store the first correspondence. Correspondingly, the decoding parameter management module may be located in the CXL PCIe PHY of the CXL controller or in the memory controller of the CXL controller.

[0161] S503, decode the encoded target data based on the target decoding parameter, and obtain the target data when the target decoding parameter is correct.

[0162] After obtaining the encoded target data and the target decoding parameter in the above manner, the CXL controller can use the target decoding parameter to decode the encoded target data to obtain the decoded data. When the target decoding parameter is correct, the obtained decoded data is the target data. When the target decoding parameter is incorrect, the obtained decoded data is garbled data or remains the encoded target data.

[0163] In an optional implementation manner, both the CXL PCIe PHY and the memory controller in the CXL controller can perform the step of decoding the encoded target data based on the target decoding parameter.

[0164] The following will separately introduce: 1. The CXL PCIe PHY decodes the encoded target data based on the target decoding parameter; 2. The memory controller decodes the encoded target data based on the target decoding parameter.

[0165] 1. The CXL PCIe PHY decodes the encoded target data based on the target decoding parameter.

[0166] After the memory controller reads the encoded target data from the CXL memory, it can send the encoded target data to the CXL PCIe PHY. After receiving the encoded target data, the CXL PCIe PHY can use the target decoding parameter to decode the encoded target data to obtain the decoded data.

[0167] In an alternative embodiment, a first decoding module (or called decode) may be included in the CXL PCIe PHY, such as Figure 6 the first decoding module 601 shown. The first decoding module 601 may be used to decode the encoded target data using the target decoding parameters to obtain the decoded data.

[0168] II. The memory controller decodes the encoded target data based on the target decoding parameters.

[0169] After the memory controller reads the encoded target data from the CXL memory, it may use the target decoding parameters to decode the encoded target data to obtain the decoded data.

[0170] In an alternative embodiment, a second decoding module may be included in the drive module, such as Figure 7 the second decoding module 701 shown. The second decoding module 701 may be used to decode the encoded target data using the target decoding parameters to obtain the decoded data.

[0171] Compared with the CXL PCIe PHY, the distance between the memory controller and the CXL memory is closer. After the encoded target data is read out from the CXL memory, it can be quickly decoded, effectively improving the decoding rate of the encoded target data. Therefore, in the embodiments of the present application, preferably, the memory controller in the CXL controller decodes the encoded target data based on the target decoding parameters. On this basis, after the target decoding parameters are determined in the CXL PCIe PHY, the target decoding parameters need to be sent to the memory controller.

[0172] S504. For the read data instruction, return the target data.

[0173] Specifically, after the CXL controller obtains the decoded data through S503, it may send the decoded data to the first entity. Correspondingly, when the decoded data is the target data, the CXL controller may send the target data to the first entity. When the decoded data is garbled data or the encoded target data, the CXL controller may send the garbled data or the encoded target data to the first entity.

[0174] As can be seen from the above technical solution, the main body that generates the read data instruction cannot directly read the plaintext data from the CXL memory. Instead, the encoded data is read. Therefore, it is necessary to use the decoding parameters to decode the read encoded data. Only when the decoding parameters are correct can the target data be obtained. When the decoding parameters are incorrect, the target data cannot be obtained. In this way, the phenomenon that an insecure process obtains plaintext data from the CXL memory can be avoided, effectively improving the security of CXL memory access and preventing the data in the CXL memory from being leaked.

[0175] In addition, a CXL controller can be connected to multiple computing devices simultaneously. By improving a CXL controller, the phenomenon that multiple computing devices (or processes or applications running on multiple computing devices) directly obtain plaintext data from the CXL memory can be avoided. In this way, the compatibility and feasibility of this solution can be improved.

[0176] In an alternative embodiment, the CXL controller can periodically obtain the first correspondence from the computing devices connected to itself.

[0177] Specifically, in some embodiments, the CXL controller can obtain the first correspondence from the computing devices connected to itself at a periodic interval through the I2C (which can also be referred to as IRC) interface or the I3C interface in the configuration interface (config interface).

[0178] In other embodiments, the CXL controller can obtain the first correspondence from the computing devices connected to itself at a periodic interval through the transceiver module.

[0179] The embodiments of the present application do not limit the period for the CXL controller to obtain the first correspondence from the computing devices. For example, the period can be 5 days, that is, the CXL controller can obtain the first correspondence from the computing devices once every 5 days. Another example is that the period can be 1 day, that is, the CXL controller can obtain the first correspondence from the computing devices once every 1 day.

[0180] In the embodiments of the present application, there is no limitation on the computing device storing the first correspondence. For example, the computing device storing the first correspondence can be Figure 2 the first computing device or the second computing device shown. Another example is that the computing device storing the first correspondence can be Figure 8 the management computing device 800 shown. The management computing device 800 is used to manage multiple computing devices, such as Figure 8 the first computing device 101, the second computing device 102, and the third computing device 103 shown in

[0181] Such as Figure 8As shown, the management computing device 800 may include a processor and a memory. The processor may be a CPU or other components with processing capabilities. Among them, the CPU, as the operation and control core of the computing device, is the final execution unit for information processing and program operation. The CPU is a very large-scale integrated circuit composed of an arithmetic unit, a controller, registers, etc., and its main task is to process and handle various data. The memory may be a disk or other memory that stores data and does not lose data after power-off.

[0182] Through the above technical solution, the first correspondence relationship in the first computing device can be updated based on the first correspondence relationship stored in the computing device, the decoding parameters in the first correspondence relationship can be prevented from leaking, the security of CXL memory access can be further improved, and the data in the CXL memory can be prevented from leaking.

[0183] In an alternative embodiment, before executing Figure 5 the data processing method shown, the CXL controller may also store the encoded target data in the CXL memory. The process of the CXL controller storing the encoded target data in the CXL memory will be described below.

[0184] Figure 9 FIG. is a schematic flow chart of a method for storing encoded target data in a CXL memory provided by an embodiment of the present application. This method is applied to Figures 2 - 4 the CXL controller in, as Figure 9 shown, this method includes S901-S904.

[0185] S901, in response to a write data instruction, obtain the target data.

[0186] The write data instruction is used to indicate writing the target data to the CXL memory.

[0187] The present application embodiment does not specifically limit the entity (hereinafter simply referred to as the second entity) that generates the write data instruction. The second entity may be at least one of a computing device connected to the CXL controller, a process running in the computing device connected to the CXL controller, or an application running in the computing device connected to the CXL controller.

[0188] The second entity and the first entity may be the same or different.

[0189] Taking the computing devices connected to the CXL controller, including the first computing device and the second computing device as an example, when the second entity is a computing device, the second entity can be the first computing device or the second computing device. When the second entity is a process (hereinafter referred to as the second process), the second process can run in the first computing device or in the second computing device. When the second entity is an application (hereinafter referred to as the second application), the second application can run in the first computing device or in the second computing device.

[0190] Specifically, taking the second entity as the second computing device as an example. When the second computing device intends to write target data to the CXL memory, it can generate a write data request for writing the target data to the CXL memory, and the target data is carried in the write data request. The second computing device can send the write data request to the CXL controller. After receiving the write data request, the CXL controller can parse the write data request to obtain the target data.

[0191] The following will continue to take the second entity as the second computing device as an example to illustrate the above S901 through the interaction between the first computing device, the receiving module, the CXL PCIe PHY, the memory controller, and the CXL memory.

[0192] After the first computing device generates a write data request for writing the target data to the CXL memory, it can send the write data request to the receiving module of the CXL controller through the link. After receiving the write data request, the receiving module of the CXL controller can send the write data request to the CXL PCIe PHY through the MB channel. After receiving the write data request, the CXL PCIe PHY can parse the write data request to obtain the target data. Alternatively, after receiving the write data request, the CXL PCIe PHY can send the write data request to the memory controller, and the memory controller can parse the write data request to obtain the target data.

[0193] S902, obtain the target encoding parameter.

[0194] The embodiments of the present application do not specifically limit the manner in which the CXL controller obtains the target encoding parameter. The following will separately introduce: one, obtaining the target encoding parameter from the write data instruction; two, determining the target encoding parameter based on the encoding parameter stored in the CXL controller; and three, obtaining the target encoding parameter from the second correspondence stored in the CXL controller.

[0195] One, obtaining the target encoding parameter from the write data instruction.

[0196] In this embodiment, the write data instruction may carry a target encoding parameter. Correspondingly, after receiving the write data instruction, the CXL controller may parse the write data instruction to obtain the target encoding parameter.

[0197] 2. Determine the target encoding parameter based on the encoding parameter stored in the CXL controller.

[0198] In this embodiment, the CXL controller may store an encoding parameter. Correspondingly, the above-mentioned CXL controller obtaining the target encoding parameter may specifically include: determining the target encoding parameter based on the encoding parameter stored in the CXL controller.

[0199] The embodiment of the present application does not limit the number of encoding parameters stored in the CXL controller. For example, the number of encoding parameters stored in the CXL controller may be 1, 2, 4, or more.

[0200] Taking the number of encoding parameters stored in the CXL controller as 1 as an example, the CXL controller may use the encoding parameter stored by itself as the target encoding parameter.

[0201] Taking the number of encoding parameters stored in the CXL controller as multiple as an example, the CXL controller may randomly select an encoding parameter from the encoding parameters stored by itself as the target encoding parameter.

[0202] 3. Obtain the target encoding parameter from the second corresponding relationship stored in the CXL controller.

[0203] In this embodiment, the CXL controller may store a second corresponding relationship, and the second corresponding relationship is used to indicate at least one of the encoding parameter corresponding to the type of target data, the encoding parameter corresponding to the computing device connected to the CXL controller, the encoding parameter corresponding to the process running in the computing device connected to the CXL controller, or the encoding parameter corresponding to the application running in the computing device connected to the CXL controller.

[0204] Among them, the type of target data is used to indicate the security level of the target data, and different security levels may correspond to different encoding parameters. For example, assuming that there are a total of 3 security levels, namely the first security level, the second security level, and the third security level, the encoding parameters corresponding to the first security level, the second security level, and the third security level are different.

[0205] The embodiment of the present application does not specifically limit the storage form of the second corresponding relationship. For example, the second corresponding relationship may be stored in the CXL controller in the form of a table, or may be stored in the CXL controller in the form of a function.

[0206] It can be understood that in the case where the above-mentioned second correspondence is used to indicate multiple items among the encoding parameters corresponding to the type of target data, the encoding parameters corresponding to the computing device connected to the CXL controller, the encoding parameters corresponding to the process running in the computing device connected to the CXL controller, or the encoding parameters corresponding to the application running in the computing device connected to the CXL controller, the decoding parameters corresponding to the multiple items can be the same or different. For example, taking the above-mentioned second correspondence as an example to indicate the encoding parameters corresponding to the type of target data, the encoding parameters corresponding to the computing device connected to the CXL controller, the encoding parameters corresponding to the process running in the computing device connected to the CXL controller, and the encoding parameters corresponding to the application running in the computing device connected to the CXL controller, the encoding parameters corresponding to the type of target data, the encoding parameters corresponding to the computing device connected to the CXL controller, the encoding parameters corresponding to the process running in the computing device connected to the CXL controller, and the encoding parameters corresponding to the application running in the computing device connected to the CXL controller can be the same or different.

[0207] In the case where there are multiple computing devices connected to the CXL controller, the encoding parameters corresponding to each computing device can be the same or different. In one example, taking the computing devices connected to the CXL controller including a first computing device and a second computing device as an example, the encoding parameters corresponding to the first computing device and the encoding parameters corresponding to the second computing device can be the same or different.

[0208] In the case where there are multiple computing devices connected to the CXL controller, the encoding parameters corresponding to the processes running in the computing devices connected to the CXL controller can include the encoding parameters corresponding to multiple processes running in each computing device connected to the CXL controller. For example, taking the computing devices connected to the CXL controller including a first computing device and a second computing device as an example, the encoding parameters corresponding to the processes running in the computing devices connected to the CXL controller include the encoding parameters corresponding to each process running in the first computing device and the encoding parameters corresponding to each process running in the second computing device.

[0209] It should be noted that the encoding parameters corresponding to different processes can be the same or different.

[0210] Taking the encoding parameters corresponding to different processes as different as an example, assuming that the processes running in the first computing device include process A and process B, and the processes running in the second computing device include process 1 and process 2, then the encoding parameters corresponding to the processes running in the computing devices connected to the CXL controller include the encoding parameters corresponding to process A, the encoding parameters corresponding to process B, and the encoding parameters corresponding to process 1 and the encoding parameters corresponding to process 2.

[0211] In the case where there are multiple computing devices connected to the CXL controller, the encoding parameters corresponding to the applications running in the computing devices connected to the CXL controller may include: the encoding parameters corresponding to multiple applications running in each computing device connected to the CXL controller. For example, taking the computing devices connected to the CXL controller including a first computing device and a second computing device as an example, the encoding parameters corresponding to the applications running in the computing devices connected to the CXL controller include: the encoding parameters corresponding to each application running in the first computing device, and the encoding parameters corresponding to each application running in the second computing device.

[0212] It should be noted that the encoding parameters corresponding to different applications may be the same or different. The encoding parameters corresponding to the same application installed in different computing devices may be the same or different. For example, assuming that application C is installed in both the first computing device and the second computing device, the encoding parameters corresponding to application C installed in the first computing device and the encoding parameters corresponding to application C installed in the second computing device may be the same or different.

[0213] Taking the encoding parameters corresponding to different applications being different as an example, assuming that the applications running in the first computing device include application A and application B, and the applications running in the second computing device include application C and application D, the encoding parameters corresponding to the applications running in the computing devices connected to the CXL controller include: the encoding parameters corresponding to application A, the encoding parameters corresponding to application B, and the encoding parameters corresponding to application C, the encoding parameters corresponding to application D.

[0214] In some embodiments, taking the second entity as the second computing device and the second correspondence relationship being used to indicate the encoding parameters corresponding to the type of target data as an example, after the CXL controller receives the write data instruction sent by the second computing device, it can determine the type of target data, and then based on the type of target data, determine the encoding parameters corresponding to the type of target data from the second correspondence relationship stored in itself, which is the target encoding parameter.

[0215] The embodiments of the present application do not specifically limit the manner in which the CXL controller determines the type of target data. For example, the type of target data may be carried in the write data instruction. Correspondingly, after the CXL controller receives the write data instruction, it can parse the write data instruction to obtain the type of target data.

[0216] In other embodiments, taking the second entity as the second computing device and the second correspondence relationship being used to indicate the encoding parameters corresponding to different devices as an example. After the processor receives the write data instruction sent by the second computing device, it can determine the device identifier of the second computing device, and based on the device identifier of the second computing device, determine the encoding parameters corresponding to the second computing device from the second correspondence relationship stored in itself, which is the target encoding parameter.

[0217] The above second correspondence relationship can be stored in the CXL PCIe PHY or in the memory controller.

[0218] When the second correspondence relationship is stored in the memory controller, the above S902, that is, the CXL controller obtains the target encoding parameter, can be replaced with: obtaining the second correspondence relationship from the memory controller and determining the target encoding parameter based on the second correspondence relationship.

[0219] When the second correspondence relationship can be stored in the CXL PCIe PHY, the above S902, that is, the CXL controller obtains the target encoding parameter, can be replaced with: obtaining the second correspondence relationship from the CXL PCIe PHY and determining the target encoding parameter based on the second correspondence relationship.

[0220] In the above technical solution, the second correspondence relationship can be stored in different locations, so that the compatibility of the present application can be expanded and the feasibility of the present application can be improved.

[0221] In an alternative embodiment, the CXL controller may include an encoding parameter management module for storing the second correspondence relationship. Correspondingly, the encoding parameter management module may be located in the CXL PCIe PHY of the CXL controller or in the memory controller of the CXL controller.

[0222] It should be noted that the encoding parameter management module and the decoding parameter management module may be the same software module or different software modules.

[0223] S903, encoding the target data based on the target encoding parameter to obtain the encoded target data.

[0224] After obtaining the target data and the target encoding parameter in the above manner, the CXL controller may encode the target data using the target encoding parameter to obtain the encoded target data.

[0225] In an alternative embodiment, both the CXL PCIe PHY and the memory controller in the CXL controller may encode the target data based on the target encoding parameter.

[0226] On the basis of encoding the target data through the CXL PCIe PHY, the CXL PCIe PHY may include a first encoding module (or called encode), such as Figure 6 the first encoding module 602 shown in. The first encoding module 602 may be used to encode the target data using the target encoding parameter to obtain the encoded target data.

[0227] On the basis of encoding the target data through the memory controller, the memory controller may include a second encoding module (or referred to as encode), such as Figure 7 the second encoding module 702 shown in. The second encoding module 702 may be used to encode the target data by using the target encoding parameters to obtain the encoded target data.

[0228] Compared with the CXL PCIe PHY, the distance between the memory controller and the CXL memory is closer. Before writing the target data into the CXL memory, the target data can be encoded to obtain the encoded target data, and the encoded target data is written into the CXL memory. In this way, the encoding rate of the target data can be improved. On this basis, after determining the target encoding parameters in the CXL PCIe PHY, it is also necessary to send the target encoding parameters to the memory controller.

[0229] S904, write the encoded target data into the CXL memory.

[0230] Specifically, after obtaining the encoded target data through the above method, the CXL controller can write the encoded target data into the CXL memory.

[0231] It can be seen from the above technical solution that the data stored in the CXL is encoded data (such as the encoded target data), rather than plaintext data (such as the target data). In this way, an insecure process, application, or device cannot directly read the plaintext data from the CXL memory, which can further prevent an insecure process from obtaining the plaintext data from the CXL memory, thereby improving the security of CXL memory access and preventing the data in the CXL memory from being leaked.

[0232] In an alternative embodiment, after storing the encoded target data in the CXL memory, the CXL controller may store the data identifier of the target data and the memory address of the encoded target data in a corresponding manner. In this way, when the CXL controller subsequently receives a read data instruction to read the target data from the CXL memory, it can obtain the memory address of the encoded target data based on the data identifier of the target data, and quickly read the encoded target data from the CXL memory based on the memory address of the encoded target data, so as to effectively improve the data reading efficiency of the processor.

[0233] In an alternative embodiment, the CXL controller may periodically obtain a second correspondence relationship from the computing device connected to itself.

[0234] Specifically, in some embodiments, the CXL controller may obtain the second corresponding relationship from the computing device connected to itself at intervals through the I2C (which may also be referred to as IRC) interface or the I3C interface in the config interface.

[0235] In other embodiments, the CXL controller may obtain the second corresponding relationship from the computing device connected to itself at intervals through the transceiver module.

[0236] In the embodiments of the present application, the computing device storing the second corresponding relationship is not limited. For example, the computing device storing the second corresponding relationship may be Figure 2 the first computing device or the second computing device shown. Again, for example, the computing device storing the second corresponding relationship may be Figure 8 the management computing device 800 shown.

[0237] Through the above technical solution, the second corresponding relationship in the first computing device can be updated based on the second corresponding relationship stored in the management computing device, the encoding parameters in the second corresponding relationship can be prevented from leaking, the security of CXL memory access can be further improved, and the data in the CXL memory can be prevented from leaking.

[0238] The above mainly introduces the data processing method provided by the embodiments of the present application from the perspective of the method. To implement the above functions, the data processing device includes the corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, combining the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving the hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0239] The embodiments of the present application can, according to the above method, exemplarily divide the function modules of the data processing device. For example, the data processing device may include each function module corresponding to each function division, or two or more functions may be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of a software function module. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there may be other division methods in actual implementation.

[0240] Exemplarily, Figure 10FIG. 0 shows a possible structural diagram of the data processing device (denoted as data processing device 1000) involved in the above embodiments. The data processing device 1000 includes an acquisition unit 1001, a decoding unit 1002, and a sending unit 1003.

[0241] Among them, the acquisition unit 1001 is configured to obtain the encoded target data from the CXL memory in response to a read data instruction. It is also used to obtain target decoding parameters. Among them, the read data instruction is used to indicate reading the target data.

[0242] The decoding unit 1002 is configured to decode the encoded target data based on the target decoding parameters, and obtain the target data when the target decoding parameters are correct.

[0243] The sending unit 1003 is configured to return the target data in response to the read data instruction.

[0244] Optionally, the CXL controller is connected to a computing device, and a process and an application can run in the computing device. On this basis, a first correspondence can be stored in the CXL controller, and the first correspondence is used to indicate at least one of the following: the decoding parameters corresponding to the above computing device, the decoding parameters corresponding to the above process, or the decoding parameters corresponding to the above application. Correspondingly, the above decoding unit 1002 is specifically configured to: obtain the target decoding parameters corresponding to the entity that generates the read data instruction from the first correspondence. Among them, the entity that generates the read data instruction is at least one of the above computing device, the above process, or the above application.

[0245] Optionally, the first correspondence can be stored in the memory controller of the CXL controller. Correspondingly, the acquisition unit 1001 is specifically configured to: obtain the first correspondence from the memory controller, and determine the target decoding parameters based on the first correspondence. Correspondingly, the above decoding unit 1002 is specifically configured to: decode the encoded target data through the memory controller.

[0246] Optionally, the first correspondence can be stored in the CXL PCIe PHY of the CXL controller. Correspondingly, the acquisition unit 1001 is specifically configured to: obtain the first correspondence from the CXL PCIe PHY, and determine the target decoding parameters based on the first correspondence. Correspondingly, the above decoding unit 1002 is specifically configured to: send the target decoding parameters to the memory controller of the CXL controller, and decode the encoded target data through the memory controller.

[0247] Optionally, the acquisition unit 1001 can also be used to: periodically obtain the first correspondence from the computing device.

[0248] Optionally, the target decoding parameters can be carried in the read data instruction.

[0249] Optionally, the CXL controller may connect a first computing device and a second computing device. Correspondingly, when the main body of the read data instruction is a first process, the first process may run in the first computing device, or the first process may run in the second computing device. When the main body of the read data instruction is a first application, the first application may run in the first computing device, or the first application may run in the second computing device.

[0250] Optionally, the decoding unit 1002 is further configured to: decode the encoded target data based on the target decoding parameter, and obtain scrambled data when the target decoding parameter is incorrect. Correspondingly, the sending unit 1003 is further configured to: return the scrambled data for the read data instruction.

[0251] Optionally, the obtaining unit 1001 is further configured to: in response to a write data instruction, obtain target data and obtain a target encoding parameter. The above data processing apparatus 1000 further includes an encoding module and a storage module. The encoding module is specifically configured to: encode the target data based on the target encoding parameter to obtain the encoded target data. The storage module is specifically configured to: write the encoded target data into the CXL memory. Wherein, the write data instruction is used to indicate writing the target data into the CXL memory.

[0252] Optionally, the write data instruction includes a target encoding parameter.

[0253] Optionally, the CXL controller is connected to a computing device, and a process and an application are running in the computing device. The CXL controller stores a second correspondence relationship, and the second correspondence relationship is used to indicate at least one of: the encoding parameter corresponding to the type of the target data, the encoding parameter corresponding to the computing device, the encoding parameter corresponding to the process, and the encoding parameter corresponding to the application. Correspondingly, the encoding module is specifically configured to: obtain the target encoding parameter corresponding to the main body of the generated write data instruction from the second correspondence relationship, where the main body of the generated write data instruction is at least one of the above computing device, the above process, or the above application.

[0254] Optionally, the second correspondence relationship may be stored in the memory controller of the CXL controller. The obtaining unit 1001 is specifically configured to: obtain the second correspondence relationship from the memory controller, and determine the target encoding parameter based on the second correspondence relationship. Correspondingly, the encoding module is specifically configured to: encode the target data through the memory controller.

[0255] Optionally, the second corresponding relationship can be stored in the CXL PCIe PHY of the CXL controller. The obtaining unit 1001 is specifically configured to: obtain the second corresponding relationship from the CXL PCIe PHY, and determine the target encoding parameter based on the second corresponding relationship. Accordingly, the encoding module is specifically configured to: send the target encoding parameter to the memory controller of the CXL controller, and encode the target data through the memory controller.

[0256] Optionally, the CXL controller can periodically obtain the second corresponding relationship from the computing device.

[0257] For the specific description of the above optional manner, reference may be made to the foregoing method embodiments, which will not be elaborated herein. In addition, the explanations and beneficial effects of any of the above-provided data processing devices can be referred to the corresponding method embodiments above, and will not be elaborated.

[0258] An embodiment of the present application further provides a CXL controller, which includes a processor and a memory. The processor is connected to the memory, and the memory stores computer-executable instructions. When the processor executes the computer-executable instructions, the data processing method in the above embodiment is implemented.

[0259] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program runs on a computer, the computer is enabled to execute the method executed by any of the above-provided computer devices.

[0260] For the explanations and beneficial effects of the relevant content in any of the above-provided computer-readable storage media, reference may be made to the corresponding embodiments above, which will not be elaborated herein.

[0261] An embodiment of the present application further provides a chip. The chip integrates a control circuit for implementing the functions of the above computer device and one or more ports. Optionally, the functions supported by the chip can be referred to above, which will not be elaborated herein.

[0262] An embodiment of the present application further provides a computing device. The computing device includes a CXL controller, a CXL memory, a memory, and a processor. The CXL controller, the CXL memory, the memory, and the processor are coupled, and the CXL controller is used to implement the data processing method in the above embodiment.

[0263] An embodiment of the present application further provides a CXL memory device. The CXL memory device includes a CXL controller and a CXL memory. The CXL controller and the CXL memory are coupled, and the CXL controller is used to implement the data processing method in the above embodiment.

[0264] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a random access memory, etc. The above-mentioned processing unit or processor can be a central processing unit, a general-purpose processor, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0265] The embodiments of the present application also provide a computer program product containing instructions. When the instructions run on a computer, the computer is caused to execute any one of the methods in the above embodiments. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a server, or a data center to another website, a computer, a server, or a data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access, or a data storage device such as a server or a data center that includes one or more integrated media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as an SSD), etc.

[0266] It should be noted that the above-mentioned devices for storing computer instructions or computer programs provided in the embodiments of the present application, such as but not limited to, the above-mentioned memory, computer-readable storage medium, and communication chip, etc., are all non-transitory.

[0267] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that contains one or more media integrated therein. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0268] Although the present application has been described in connection with various embodiments, however, in the process of implementing the claimed present application, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0269] Although the present application has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present application. Accordingly, the present specification and the drawings are merely exemplary illustrations of the present application defined by the appended claims and are considered to have covered any and all modifications, variations, combinations, or equivalents within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A data processing method, characterized in that, Applied to a Compute Express Link (CXL) controller, the method includes: In response to a read data instruction, obtaining encoded target data from a CXL memory; the read data instruction is used to indicate reading the target data; Obtaining target decoding parameters; Based on the target decoding parameters, decoding the encoded target data, and obtaining the target data when the target decoding parameters are correct; Returning the target data in response to the read data instruction.

2. The method according to claim 1, wherein The CXL controller is connected to a computing device, in which a process and an application are running. The computing device includes one or more. A first correspondence is stored in the CXL controller, and the first correspondence is used to indicate at least one of the following: Decoding parameters corresponding to the computing device; Decoding parameters corresponding to the process; Decoding parameters corresponding to the application; The obtaining of the target decoding parameters includes: Obtaining the target decoding parameters corresponding to the entity that generates the read data instruction from the first correspondence; The entity that generates the read data instruction is at least one of the computing device, the process, or the application.

3. The method according to claim 2, wherein The first correspondence is stored in the memory controller of the CXL controller. The obtaining of the target decoding parameters includes: Obtaining the first correspondence from the memory controller; Determining the target decoding parameters based on the first correspondence; The decoding of the encoded target data includes: Decoding the encoded target data through the memory controller.

4. The method according to claim 2, wherein The first correspondence is stored in the CXL PCIe physical layer (PHY) of the CXL controller. The obtaining of the target decoding parameters includes: Obtaining the first correspondence from the CXL PCIe PHY; Determining the target decoding parameters based on the first correspondence; The decoding of the encoded target data includes: Sending the target decoding parameters to the memory controller of the CXL controller; Decoding the encoded target data through the memory controller.

5. The method according to any one of claims 2-4, characterized in that, The method further includes: Periodically obtaining the first correspondence from the computing device.

6. The method according to claim 1, wherein The target decoding parameters are carried in the read data instruction.

7. The method according to claim 1, wherein The CXL controller is connected to a first computing device and a second computing device; The entity that generates the read data instruction is a first process; the first process runs in the first computing device or the first process runs in the second computing device; or, The entity that generates the read data instruction is a first application; The first application runs in the first computing device or the first application runs in the second computing device.

8. The method according to claim 1, wherein The method further includes: Based on the target decoding parameters, decoding the encoded target data, and obtaining garbled data when the target decoding parameters are incorrect; Returning the garbled data in response to the read data instruction.

9. The method according to claim 1, wherein The method further includes: In response to a write data instruction, obtaining the target data; the write data instruction is used to indicate writing the target data to the CXL memory; Obtaining target encoding parameters; Encode the target data based on the target encoding parameter to obtain the encoded target data; Write the encoded target data into the CXL memory.

10. The method according to claim 9, wherein The write data instruction includes the target encoding parameter.

11. The method according to claim 9, wherein The CXL controller is connected to a computing device. Each computing device runs a process and an application. The CXL controller stores a second correspondence relationship, which is used to indicate at least one of the following: The encoding parameter corresponding to the type of the target data; The encoding parameter corresponding to the computing device; The encoding parameter corresponding to the process; The encoding parameter corresponding to the application; The obtaining of the target encoding parameter includes: Obtain the target encoding parameter corresponding to the entity that generates the write data instruction from the second correspondence relationship; The entity that generates the write data instruction is at least one of the computing device, the process, or the application.

12. The method according to claim 11, wherein The second correspondence relationship is stored in the memory controller of the CXL controller. The obtaining of the target encoding parameter includes: Obtain the second correspondence relationship from the memory controller; Determine the target encoding parameter based on the second correspondence relationship; The encoding of the target data includes: Encode the target data through the memory controller.

13. The method according to claim 11, wherein The second correspondence relationship is stored in the CXL PCIe PHY of the CXL controller. The obtaining of the target encoding parameter includes: Obtain the second correspondence relationship from the CXL PCIe PHY; Determine the target encoding parameter based on the second correspondence relationship; The encoding of the target data includes: Send the target encoding parameter to the memory controller of the CXL controller; Encode the target data through the memory controller.

14. The method according to any one of claims 9 - 13, characterized in that, The method further includes: Periodically obtain the second correspondence relationship from the computing device.

15. A CXL controller, characterized in that, It includes a processor, and the processor is coupled to a memory. The memory is used to store programs or instructions. When the programs or instructions are executed by the processor, the CXL controller executes the method according to any one of claims 1-14.

16. A computing device, characterized in that, It includes: A CXL controller, a CXL memory, a memory, and a processor. The CXL controller, the CXL memory, the memory, and the processor are coupled; The CXL controller is used to execute the method according to any one of claims 1-14.

17. A CXL memory device, characterized in that, It includes: A CXL controller and a CXL memory. The CXL controller and the CXL memory are coupled; the CXL controller is used to execute the method according to any one of claims 1-14.

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