Information acquisition and electric signal transmission board card based on 32-bit RISC-V processor

Abstract

The invention discloses an information acquisition and electric signal transmission board card based on a 32-bit RISC-V processor, which relates to the technical field of processor information acquisition and electric signal transmission, and comprises an information acquisition module, an electromagnetic interference monitoring module, an electric signal transmission module, a storage module, a power supply module and an RISC-V processor core module, the RISC-V processor is connected with the information acquisition module through a data bus and a control bus; the RISC-V processor is connected with the electric signal transmission module through an internal high-speed data bus; the multi-channel parallel ADC technology, the electromagnetic interference monitoring and processing technology and the modern information technology are closely combined, sensor information, board card posture information and electromagnetic interference information are captured, and the core is that according to a control command transmitted by the electric signal transmission module, the control command is sent to the RISC-V processor, and the control command is sent to the RISC-V processor through an address bus, a data bus and a control bus. The equipment or the aircraft can realize hovering or accurate flight attitude, and after relevant information returned by the sensor is collected, accurate return is realized under the condition of anti-electromagnetic interference.

Description

Technical Field

[0001] The present invention relates to the technical field of processor information acquisition and electrical signal transmission, and specifically relates to an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor. Background Art

[0002] In the current era of rapid digital and intelligent development, the demand for various information acquisition and electrical signal transmission is increasing day by day. Traditional information acquisition and electrical signal transmission boards have many limitations, such as limited processing power, high power consumption, insufficient scalability, etc., and it is difficult to meet the requirements of complex and changeable application scenarios. The emergence of 32-bit RISC-V processors has brought new opportunities to this field. RISC-V is an open-source instruction set architecture with advantages such as simplicity, flexibility, and customizability. An information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor can quickly process a large amount of acquired data with its high instruction execution efficiency. Moreover, its low-power consumption characteristic can extend the usage time of the board, and it has obvious advantages in some occasions with strict power consumption requirements, such as portable devices, field monitoring devices, etc. At the same time, the customizability of the RISC-V architecture allows developers to flexibly configure and expand the functions of the board according to specific application requirements to adapt to different information acquisition and electrical signal transmission tasks, showing broad application prospects in the fields of industrial automation, medical equipment, environmental monitoring, etc.;

[0003] Although there have been great advancements in the prior art in the direction of processor information acquisition and electrical signal transmission, there are still some problems to be optimized. ADC conversion will limit the speed of information acquisition, making the information acquisition of an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor unable to be synchronized with analog-to-digital conversion, resulting in information loss and signal waveform distortion; during the electrical signal transmission process, electromagnetic interference will occur, causing errors in the transmitted electrical signals. Summary of the Invention

[0004] To achieve the above objectives, the present invention is realized through the following technical solutions: An information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor, characterized in that it includes an information acquisition module, an electromagnetic interference monitoring module, an electrical signal transmission module, a storage module, a power supply module, and a RISC-V processor core module;

[0005] Among them, the RISC-V processor is connected to the information acquisition module through a data bus and a control bus; the data bus is used to read the digital signals converted by the ADC, and the control bus is used to control the operation of the information acquisition module; the RISC-V processor is connected to the electrical signal transmission module through an internal high-speed data bus; the RISC-V processor is connected to the storage module through an address bus, a data bus and a control bus; the output of the power supply module is connected to the power pin of the RISC-V processor;

[0006] The information acquisition module uses an oscilloscope to collect relevant data on voltage peaks, providing data support for monitoring electromagnetic interference conditions;

[0007] The electromagnetic interference monitoring module obtains the degree of influence of electromagnetic interference on electrical signal transmission and uses the random forest algorithm to construct an electromagnetic interference monitoring model.

[0008] A further improvement in the technical solution of the present invention is that: the information acquisition module includes a sensor interface module, a MEMS inertial module, a signal conditioning module and an analog-to-digital conversion module:

[0009] Among them, the sensor interface module and the MEMS inertial module are connected to the input end of the signal conditioning module through wires, and the analog-to-digital conversion module is connected to the output end of the signal conditioning module through wires;

[0010] The sensor interface module consists of a physical interface and a protocol controller. The physical interface is used to adapt to different types of sensors. The protocol controller includes an IC2 controller, an SPI controller and a UART controller. Among them, the IC2 controller manages data transmission on the IC2 bus, the SPI controller controls data synchronization and data transmission between the master and slave devices, and the UART controller converts parallel data into serial data for transmission. An oscilloscope is equipped in the sensor interface module to collect voltage peaks, and the change of voltage peaks describes electromagnetic interference;

[0011] The MEMS inertial module consists of a micro-accelerometer structure and a micro-gyroscope structure. Among them, the micro-accelerometer structure includes a mass block, an elastic support structure and a detection electrode. Based on Newton's second law, it collects the acceleration of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor; the micro-gyroscope structure includes a driving electrode, a vibrating mass block and a detection electrode. Based on the Coriolis force principle, it collects the angular velocity of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor. The MEMS inertial module uses the micro-accelerometer structure and the micro-gyroscope structure to monitor the attitude information of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor;

[0012] The signal conditioning module includes an amplifier and a filter. Among them, the amplifier consists of an operational amplifier, resistors, and capacitors. The signal conditioning module dynamically adjusts the gain of the amplifier according to the strength of the acquired electrical signal. The filter consists of a low-pass filter, a high-pass filter, a band-pass filter, and a band-stop filter. The signal conditioning module calls the filter according to the data acquisition scenario.

[0013] A further improvement of the technical solution of the present invention lies in: The process of the analog-to-digital conversion module adopting the multi-channel parallel ADC technology includes:

[0014] The analog-to-digital conversion module adopts the multi-channel parallel ADC technology, integrates multiple ADC chips, each ADC chip has an independent analog input channel, converts multiple analog signals, selects the resolution of the ADC chip according to application requirements, the ADC chip is connected to the RISC-V processor through a high-speed parallel bus, and a data cache unit is set between the ADC chip and the RISC-V processor, using a FIFO queue to temporarily store the data after ADC conversion in the data cache unit.

[0015] A further improvement of the technical solution of the present invention lies in: The electromagnetic interference monitoring module, obtaining the influence degree of electromagnetic interference on the transmission of electrical signals, and the process of constructing an electromagnetic interference monitoring model using the random forest algorithm includes:

[0016] It is set that in the digital signal, the voltage range corresponding to logic 0 is V1 to V2, and the voltage range corresponding to logic 1 is V1 to V3. When the voltage peak exceeds the normal range of the logic level, the wrong logic signal level is received, and according to the voltage peak, the number of wrong logic signal levels and the total number of logic signal levels are recorded;

[0017] The process of calculating the influence degree of electromagnetic interference on the transmission of electrical signals is as follows:

[0018]

[0019] Among them, BER is the bit error rate, describing the influence degree of electromagnetic interference on the transmission of electrical signals; n is the number of wrong logic signal levels, and N is the total number of logic signal levels;

[0020] Using the random forest algorithm, taking the voltage peak and BER as the data set, dividing them into a training set and a test set according to the ratio of 7:3, and setting the random forest model parameters;

[0021] Using the training set data to train the random forest model, learning the non-linear relationship between the voltage peak and BER through the decision tree, taking the voltage peak as the input and BER as the output, to obtain the random forest model;

[0022] Use the test set data to evaluate the performance of the trained random forest model. According to the performance evaluation results, optimize the random forest model by adjusting the random forest model parameters, and deploy the random forest model to an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor to obtain an electromagnetic interference monitoring model.

[0023] A further improvement of the technical solution of the present invention is that: the electrical signal transmission module includes a driving module and a communication interface module:

[0024] The information acquisition module is connected to the electrical signal transmission module through a PCB board. Among them, the driving module provides power for the information acquisition module and sends control instructions to the information acquisition module to control the working mode of the information acquisition module. The information acquisition module transmits the collected data to the communication interface module; the output end of the communication interface module is connected to the input end of the driving module, and the output end of the driving module is connected to an external communication module;

[0025] The driving module includes a power amplification unit and a level conversion unit. Among them, the power amplification unit is composed of a transistor and an operational amplifier. The output stage of the power amplification unit adopts a push-pull structure, and the output signal of the power amplification unit is conducted by different transistors in the positive and negative half-cycles respectively; the level conversion unit includes a transistor and a resistor, and converts the output level of the RISC-V processor into the level required by the communication interface according to different communication interface standards.

[0026] A further improvement of the technical solution of the present invention is that: the communication interface module includes:

[0027] The communication interface module is composed of an IC2 chip, an SPI chip, a UART chip and an electromagnetic shielding unit. Among them, the IC2 chip includes a master-slave mode selection component, a data shift register and a clock generator. The master device generates a clock signal through the SCK line and exchanges data on the MOSI and MISO lines; the SPI chip uses the SCL line and the SDA line to realize two-wire communication between multiple devices; the UART chip includes a transmitter, a receiver and a baud rate generator. The transmitter converts the parallel data output by the RISC-V processor into serial data, adds a start bit, a stop bit and a parity bit to the serial data, and sends the serial data through the TX pin. The receiver receives the serial data from the RX pin, removes the start bit, stop bit and parity bit in the serial data, and converts the serial data into parallel data;

[0028] The electromagnetic shielding unit uses a metal shielding cover to wrap the IC2 chip, the SPI chip and the UART chip, grounds the metal shielding cover, and conducts the induced electromagnetic interference into the ground.

[0029] A further improvement of the technical solution of the present invention is that: the storage module includes a program memory and a data memory:

[0030] Among them, the program memory and the data memory are independent storage units;

[0031] The program memory consists of a flash memory chip and a storage controller. The flash memory chip is the storage medium of the program memory, stores program codes in bytes, and is connected to the RISC-V processor through address lines, data lines, and control lines. The address lines are used to select storage locations, the data lines are used to transmit data, and the control lines are used to control the read, write, and erase operations of the flash memory chip. The physical address of the flash memory chip corresponds to the logical address of the RISC-V processor; the storage controller connects the RISC-V processor and the flash memory chip, converts the logical address sent by the RISC-V processor into the physical address in the flash memory chip, and controls and manages the read, write, and erase of the flash memory chip;

[0032] The data memory consists of a static random access memory and a dynamic random access memory. The static random access memory is SRAM, and the dynamic random access memory is DEAM. Among them, SRAM consists of an array of multiple storage units, each storage unit stores 1 bit of data, and the storage units are accessed through address lines. SRAM is connected to the RISC-V processor through a data bus, an address bus, and a control bus; DRAM consists of a storage unit array, a row decoder, a column decoder, and a read / write amplifier. The data in DRAM is stored in a capacitor in the form of charge, and the storage unit array is selected through a row address strobe signal and a column address strobe signal.

[0033] A further improvement of the technical solution of the present invention lies in that: the power supply module includes a power management module and a filter capacitor module:

[0034] The power supply module is connected to the information acquisition module, the electrical signal transmission module, and the storage module through output power lines;

[0035] The power management module includes a DC-DC converter, a low-dropout linear regulator, and a power monitoring unit. The DC-DC converter consists of a power switch transistor, an inductor, a capacitor, and a control chip. The DC-DC converter is divided into buck type, boost type, and buck-boost type. Based on the energy storage and release characteristics of the inductor, the DC-DC converter detects the output voltage, compares it with the reference voltage, generates a PWM signal, controls the on and off times of the power switch transistor, and adjusts the magnitude and stability of the output voltage. The low-dropout linear regulator consists of a power transistor, an error amplifier, a reference voltage source, and a feedback resistor network. Based on the feedback mechanism, it outputs the input voltage after passing through the power transistor, feeds the output voltage back to the input terminal of the error amplifier through the feedback resistor network, compares it with the reference voltage source, and the error amplifier adjusts the conduction degree of the power transistor according to the comparison result to keep the voltage stable. The power monitoring unit includes voltage monitoring, current detection, and temperature monitoring, which respectively monitor the input voltage, output voltage, the magnitude of the current in the power line, and the temperatures of the power switch transistor and the power transistor in the power module.

[0036] The filter capacitor module consists of electrolytic capacitors and ceramic capacitors. The electrolytic capacitors have a large capacitance and are composed of metal foils, electrolytes, and separator papers. They utilize the energy storage characteristics of the capacitors to filter out the low-frequency ripples in the power supply, charging when the power supply voltage rises and discharging when the power supply voltage drops. The ceramic capacitors have a small capacitance and filter out the high-frequency noise in the power supply based on the low impedance characteristics of the capacitors to high-frequency signals.

[0037] A further improvement of the technical solution of the present invention lies in that: the RISC-V processor core module includes a core logic module, a cache module, and an interrupt control module:

[0038] The core logic module includes an ALU, a CU, and a register bank. The ALU incorporates a combinational logic unit, receives operands from the register bank, and performs addition, subtraction, multiplication, division, logical AND, logical NOT, and shift operations according to the operation code of the instruction. The CU consists of a finite state machine and a decoder, reads instructions from the memory module, decodes the instructions, obtains the operation code and function code of the instructions, and generates control signals to control the operation of the RISC-V processor according to the operation code and function code of the instructions. The register bank is a high-speed storage unit in the RISC-V processor, composed of 32-bit registers, and is used to store data during the operation of the RISC-V processor.

[0039] The cache module includes an instruction cache and a data cache. The instruction cache uses SRAM to store instructions; the data cache uses SRAM to store data;

[0040] The interrupt control module includes an interrupt request register, an interrupt mask register, an interrupt priority encoder, and an interrupt service program pointer. Among them, the interrupt request register is used to store interrupt requests; the interrupt mask register is used to mask and allow interrupt requests to be responded to by the RISC-V processor; the interrupt priority encoder sorts the interrupt requests according to a preset priority; the interrupt service program pointer stores the entry address of the interrupt service program corresponding to the interrupt source.

[0041] A further improvement of the technical solution of the present invention lies in that: the process of calling the RISC-V processor includes:

[0042] The RISC-V processor uses an internal clock generator to monitor the information acquisition rate. When the actual information acquisition rate is lower than the expected rate, the RISC-V processor core module issues an instruction, the CU reads the instruction, and based on the Nyquist sampling theorem, sets the sampling frequency. The RISC-V processor core module applies for a buffer in the data memory to store the data after ADC conversion, and calls the multi-channel parallel ADC technology of the analog-to-digital conversion module; when the information acquisition rate cannot be synchronized with the analog-to-digital conversion, the RISC-V processor adds a timestamp to the acquired information points, and according to the time information carried by the timestamp, drives the analog-to-digital conversion module with a synchronous clock signal. After the analog-to-digital conversion is completed, the RISC-V processor core module checks the completion situation of the ADC conversion through the interrupt control module. When the ADC conversion is completed, the current ADC conversion task is terminated through the interrupt control module;

[0043] Combined with the electromagnetic interference monitoring model, evaluate the degree of influence of electromagnetic interference on the transmission of electrical signals. When the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is lower than 10 -9 , the electromagnetic interference has a low impact on the transmission of electrical signals, and continuously monitor the voltage peak value describing the electromagnetic interference; when the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is between 10 -6 and 10 -9 , the electromagnetic interference has a medium impact on the transmission of electrical signals. The RISC-V processor adjusts the parameters of the communication interface module, reduces the electrical signal transmission rate, and reduces the impact of electromagnetic interference on the electrical signal; when the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is higher than 10 -6 , the electromagnetic interference has a high impact on the transmission of electrical signals. The RISC-V processor checks the integrity and grounding condition of the metal shielding cover of the communication interface module, and controls the RISC-V processor core module to issue an electromagnetic interference alarm instruction to remind the user to check and repair the metal shielding cover.

[0044] The beneficial effects of the present invention are as follows: In the present invention, an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor, compared with the traditional information acquisition and electrical signal transmission board of a 32-bit RISC-V processor, the multi-channel parallel ADC technology, electromagnetic interference monitoring and processing technology in the method of the present invention are closely combined with modern information technology to accurately capture sensor information, board attitude information and electromagnetic interference-related data, obtain the degree of influence of electromagnetic interference on electrical signal transmission, and achieve the attitude stability of the board according to the board attitude information transmitted by the electrical signal transmission module, thus achieving real-time and comprehensive monitoring of information acquisition and electrical signal transmission. By reasonably invoking each module to work through the RISC-V processor, using the internal clock generator to monitor the information acquisition rate and adopting the multi-channel parallel ADC technology and synchronous clock signal of the analog-to-digital conversion module to control the information acquisition rate and the analog-to-digital conversion synchronization process, and taking corresponding measures according to the degree of influence of electromagnetic interference on electrical signal transmission, it solves the problems that ADC conversion will limit the speed of information acquisition, making the information acquisition rate unable to be synchronized with analog-to-digital conversion, resulting in information loss and signal waveform distortion, and electromagnetic interference causing errors in transmitted electrical signals, ensuring that the method in the present invention can refine the dynamic monitoring standard for information acquisition and electrical signal transmission of 32-bit RISC-V processors within a more accurate range, making the monitored data more accurate indicators under the same conditions. The research and application of this method significantly enhance the degree of intelligence in the process of information acquisition and electrical signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings.

[0046] Figure 1 It is a structural block diagram of an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor of the present invention;

[0047] Figure 2 It is a structural block diagram of the RISC-V processor core module of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0049] As Figure 1 shown, the present invention provides an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor, characterized in that it includes an information acquisition module, an electromagnetic interference monitoring module, an electrical signal transmission module, a storage module, a power supply module, and a RISC-V processor core module;

[0050] Among them, the RISC-V processor is connected to the information acquisition module through a data bus and a control bus; the data bus is used to read the digital signal converted by the ADC, and the control bus is used to control the operation of the information acquisition module; the RISC-V processor is connected to the electrical signal transmission module through an internal high-speed data bus; the RISC-V processor is connected to the storage module through an address bus, a data bus, and a control bus; the output of the power supply module is connected to the power supply pin of the RISC-V processor;

[0051] The information acquisition module uses an oscilloscope to collect relevant data on voltage peaks, providing data support for monitoring electromagnetic interference conditions;

[0052] The electromagnetic interference monitoring module obtains the degree of influence of electromagnetic interference on electrical signal transmission and uses the random forest algorithm to construct an electromagnetic interference monitoring model.

[0053] Preferably, the information acquisition module includes a sensor interface module, a MEMS inertial module, a signal conditioning module, and an analog-to-digital conversion module:

[0054] Among them, the sensor interface module and the MEMS inertial module are connected to the input end of the signal conditioning module through wires, and the analog-to-digital conversion module is connected to the output end of the signal conditioning module through wires;

[0055] The sensor interface module consists of a physical interface and a protocol controller. The physical interface is used to adapt to different types of sensors. The protocol controller includes an IC2 controller, an SPI controller, and a UART controller. Among them, the IC2 controller manages data transmission on the IC2 bus, the SPI controller controls data synchronization and data transmission between the master and slave devices, and the UART controller converts parallel data into serial data for transmission; an oscilloscope is equipped in the sensor interface module to collect the voltage peak, and the change of the voltage peak describes electromagnetic interference;

[0056] The MEMS inertial module consists of a micro-accelerometer structure and a micro-gyroscope structure. Among them, the micro-accelerometer structure includes a mass block, an elastic support structure, and detection electrodes. Based on Newton's second law, it collects the acceleration of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor; the micro-gyroscope structure includes drive electrodes, a vibrating mass block, and detection electrodes. Based on the Coriolis force principle, it collects the angular velocity of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor. The MEMS inertial module uses the micro-accelerometer structure and the micro-gyroscope structure to monitor the attitude information of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor;

[0057] The signal conditioning module includes an amplifier and a filter. Among them, the amplifier consists of an operational amplifier, resistors, and capacitors. The signal conditioning module dynamically adjusts the gain of the amplifier according to the strength of the collected electrical signal; the filter consists of a low-pass filter, a high-pass filter, a band-pass filter, and a band-stop filter. The signal conditioning module calls the filter according to the data acquisition scenario.

[0058] Preferably, the process of the analog-to-digital conversion module adopting the multi-channel parallel ADC technology includes:

[0059] The analog-to-digital conversion module adopts the multi-channel parallel ADC technology, integrates multiple ADC chips, each ADC chip has an independent analog input channel, converts multiple analog signals, selects the resolution of the ADC chip according to the application requirements, the ADC chip is connected to the RISC-V processor through a high-speed parallel bus, and a data cache unit is set between the ADC chip and the RISC-V processor, using a FIFO queue to temporarily store the data after ADC conversion in the data cache unit.

[0060] Preferably, for the electromagnetic interference monitoring module, the process of obtaining the influence degree of electromagnetic interference on electrical signal transmission and constructing an electromagnetic interference monitoring model using the random forest algorithm includes:

[0061] It is set that in the digital signal, the voltage range corresponding to logic 0 is V1~V2, and the voltage range corresponding to logic 1 is V1~V3. When the voltage peak exceeds the normal range of the logic level, an incorrect logic signal level is received, and according to the voltage peak, the number of incorrect logic signal levels and the total number of logic signal levels are recorded;

[0062] The process of calculating the influence degree of electromagnetic interference on electrical signal transmission is as follows:

[0063]

[0064] Among them, BER is the bit error rate, which describes the influence degree of electromagnetic interference on electrical signal transmission; n is the number of incorrect logic signal levels, and N is the total number of logic signal levels;

[0065] Using the random forest algorithm, taking the voltage peak and BER as the dataset, dividing them into a training set and a test set according to a ratio of 7:3, and setting the random forest model parameters;

[0066] Using the training set data to train the random forest model, learning the non-linear relationship between the voltage peak and BER through decision trees, taking the voltage peak as the input and BER as the output, to obtain the random forest model;

[0067] Using the test set data to evaluate the performance of the trained random forest model, according to the performance evaluation results, optimizing the random forest model by adjusting the random forest model parameters, and deploying the random forest model to an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor to obtain an electromagnetic interference monitoring model.

[0068] Preferably, the electrical signal transmission module includes a driving module and a communication interface module:

[0069] The information acquisition module is connected to the electrical signal transmission module through a PCB board. Among them, the driving module provides power for the information acquisition module and sends control instructions to the information acquisition module to control the working mode of the information acquisition module. The information acquisition module transmits the collected data to the communication interface module; the output end of the communication interface module is connected to the input end of the driving module, and the output end of the driving module is connected to an external communication module;

[0070] The driving module includes a power amplification unit and a level conversion unit. Among them, the power amplification unit is composed of a transistor and an operational amplifier. The output stage of the power amplification unit adopts a push-pull structure, and the output signal of the power amplification unit is conducted by different transistors in the positive and negative half-cycles respectively; the level conversion unit includes a transistor and a resistor, and converts the output level of the RISC-V processor into the level required by the communication interface according to different communication interface standards.

[0071] Preferably, the communication interface module includes:

[0072] The communication interface module is composed of an IC2 chip, an SPI chip, a UART chip and an electromagnetic shielding unit. Among them, the IC2 chip includes a master-slave mode selection component, a data shift register and a clock generator. The master device generates a clock signal through the SCK line and conducts data exchange on the MOSI and MISO lines; the SPI chip uses the SCL line and the SDA line to achieve two-wire communication between multiple devices; the UART chip includes a transmitter, a receiver and a baud rate generator. The transmitter converts the parallel data output by the RISC-V processor into serial data, adds a start bit, a stop bit and a parity bit to the serial data, and sends the serial data through the TX pin. The receiver receives the serial data from the RX pin, removes the start bit, stop bit and parity bit in the serial data, and converts the serial data into parallel data;

[0073] The electromagnetic shielding unit uses a metal shielding cover to wrap the IC2 chip, SPI chip, and UART chip, grounds the metal shielding cover, and conducts the induced electromagnetic interference into the ground.

[0074] Preferably, the storage module includes a program memory and a data memory:

[0075] Among them, the program memory and the data memory are independent storage units;

[0076] The program memory consists of a flash memory chip and a storage controller. The flash memory chip is the storage medium of the program memory, stores program codes in bytes, and is connected to the RISC-V processor through address lines, data lines, and control lines. The address lines are used to select storage locations, the data lines are used to transmit data, and the control lines are used to control the read, write, and erase operations of the flash memory chip. The physical address of the flash memory chip corresponds to the logical address of the RISC-V processor; the storage controller connects the RISC-V processor and the flash memory chip, converts the logical address sent by the RISC-V processor into the physical address in the flash memory chip, and controls and manages the read, write, and erase of the flash memory chip;

[0077] The data memory consists of a static random access memory and a dynamic random access memory. The static random access memory is SRAM, and the dynamic random access memory is DEAM. Among them, SRAM consists of an array of multiple storage units, each storage unit stores 1 bit of data, and the storage units are accessed through address lines. SRAM is connected to the RISC-V processor through a data bus, an address bus, and a control bus; DRAM consists of a storage unit array, a row decoder, a column decoder, and a read / write amplifier. The data in DRAM is stored in a capacitor in the form of charge, and the storage unit array is selected through a row address strobe signal and a column address strobe signal.

[0078] Preferably, the power supply module includes a power management module and a filter capacitor module:

[0079] The power supply module is connected to the information acquisition module, the electrical signal transmission module, and the storage module through output power lines;

[0080] The power management module includes a DC-DC converter, a low-dropout linear regulator, and a power monitoring unit. The DC-DC converter consists of a power switch transistor, an inductor, a capacitor, and a control chip. The DC-DC converter is divided into buck type, boost type, and buck-boost type. Based on the energy storage and release characteristics of the inductor, the DC-DC converter detects the output voltage, compares it with the reference voltage, generates a PWM signal, controls the on and off times of the power switch transistor, and adjusts the magnitude and stability of the output voltage. The low-dropout linear regulator consists of a power transistor, an error amplifier, a reference voltage source, and a feedback resistor network. Based on the feedback mechanism, it outputs the input voltage after passing through the power transistor, feeds the output voltage back to the input terminal of the error amplifier through the feedback resistor network, compares it with the reference voltage source, and the error amplifier adjusts the conduction degree of the power transistor according to the comparison result to keep the voltage stable. The power monitoring unit includes voltage monitoring, current detection, and temperature monitoring, which respectively monitor the input voltage, output voltage, the magnitude of the current in the power line, and the temperatures of the power switch transistor and the power transistor in the power module.

[0081] The filter capacitor module consists of electrolytic capacitors and ceramic capacitors. The electrolytic capacitors have a large capacitance and are composed of metal foils, electrolytes, and separator papers. They utilize the energy storage characteristics of the capacitors to filter out low-frequency ripples in the power supply, charging when the power supply voltage rises and discharging when the power supply voltage drops. The ceramic capacitors have a small capacitance and, based on the low-impedance characteristics of capacitors for high-frequency signals, filter out high-frequency noise in the power supply.

[0082] As Figure 2 shown, preferably, the RISC-V processor core module includes a core logic module, a cache module, and an interrupt control module:

[0083] The core logic module includes an ALU, a CU, and a register file. The ALU has built-in combinational logic units that receive operands from the register file and perform addition, subtraction, multiplication, division, logical AND, logical NOT, and shift operations according to the operation codes of the instructions. The CU consists of a finite state machine and a decoder, reads instructions from the memory module, decodes the instructions to obtain the operation codes and function codes of the instructions, and generates control signals according to the operation codes and function codes of the instructions to control the operation of the RISC-V processor. The register file is a high-speed storage unit in the RISC-V processor, composed of 32-bit registers, and is used to store data during the operation of the RISC-V processor.

[0084] The cache module includes an instruction cache and a data cache. The instruction cache uses SRAM to store instructions; the data cache uses SRAM to store data.

[0085] The interrupt control module includes an interrupt request register, an interrupt mask register, an interrupt priority encoder, and an interrupt service program pointer. Among them, the interrupt request register is used to store interrupt requests; the interrupt mask register is used to mask and allow interrupt requests to be responded to by the RISC-V processor; the interrupt priority encoder sorts interrupt requests according to preset priorities; the interrupt service program pointer stores the entry address of the interrupt service program corresponding to the interrupt source.

[0086] Preferably, the process of calling the RISC-V processor includes:

[0087] The RISC-V processor uses an internal clock generator to monitor the information acquisition rate. When the actual information acquisition rate is lower than the expected rate, the RISC-V processor core module issues an instruction. The CU reads the instruction and, based on the Nyquist sampling theorem, sets the sampling frequency. The RISC-V processor core module applies for a buffer in the data memory to store the data after ADC conversion and calls the multi-channel parallel ADC technology of the analog-to-digital conversion module. When the information acquisition rate cannot be synchronized with the analog-to-digital conversion, the RISC-V processor adds timestamps to the collected information points. According to the time information carried by the timestamps, it drives the analog-to-digital conversion module with a synchronous clock signal. After the analog-to-digital conversion is completed, the RISC-V processor core module checks the completion status of the ADC conversion through the interrupt control module. When the ADC conversion is completed, the current ADC conversion task is terminated through the interrupt control module;

[0088] Combined with the electromagnetic interference monitoring model, evaluate the degree of influence of electromagnetic interference on the transmission of electrical signals. When the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is lower than 10 -9 , the electromagnetic interference has a low impact on the transmission of electrical signals, and continuously monitor the voltage peak value describing the electromagnetic interference; when the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is between 10 -6 and 10 -9 , the electromagnetic interference has a medium impact on the transmission of electrical signals. The RISC-V processor adjusts the parameters of the communication interface module to reduce the electrical signal transmission rate and reduce the impact of electromagnetic interference on the electrical signal; when the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is higher than 10 -6 , the electromagnetic interference has a high impact on the transmission of electrical signals. The RISC-V processor checks the integrity and grounding of the metal shielding cover of the communication interface module and controls the RISC-V processor core module to issue an electromagnetic interference alarm instruction to remind the user to check and repair the metal shielding cover;

[0089] Select a suitable RISC-V development board. In order to obtain the attitude information of the PVDF flexible film, connect the inertial sensor to the corresponding interface of the RISC-V development board, and connect the flexible actuator to the GPIO interface of the RISC-V development board so that the RISC-V processor can control its movement, adjust the vibration frequency of the PVDF flexible film, and then control its flight attitude. Observe whether the attitude change of the PVDF flexible film meets the expectation, and adjust and optimize the interface parameters of the RISC-V development board, the parameters of the inertial sensor, and the parameters of the flexible actuator according to the test results to achieve more precise flight attitude control.

[0090] As described above, it is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, which should be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. An information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor, characterized in that: It includes an information acquisition module, an electromagnetic interference monitoring module, an electrical signal transmission module, a storage module, a power supply module, and a RISC-V processor core module; Among them, the RISC-V processor is connected to the information acquisition module through a data bus and a control bus; the data bus is used to read the digital signal converted by the ADC, and the control bus is used to control the operation of the information acquisition module; the RISC-V processor is connected to the electrical signal transmission module through an internal high-speed data bus; the RISC-V processor is connected to the storage module through an address bus, a data bus, and a control bus; the output of the power supply module is connected to the power pin of the RISC-V processor; The information acquisition module uses an oscilloscope to collect relevant data of the voltage peak value; The electromagnetic interference monitoring module obtains the influence degree of electromagnetic interference on the electrical signal transmission, and uses the random forest algorithm to construct an electromagnetic interference monitoring model.

2. The information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 1, wherein: The information acquisition module includes a sensor interface module, a MEMS inertial module, a signal conditioning module, and an analog-to-digital conversion module: Among them, the sensor interface module and the MEMS inertial module are connected to the input end of the signal conditioning module through wires, and the analog-to-digital conversion module is connected to the output end of the signal conditioning module through wires; The sensor interface module consists of a physical interface and a protocol controller. The physical interface is used to adapt to different types of sensors. The protocol controller includes an IC2 controller, an SPI controller, and a UART controller. Among them, the IC2 controller manages the data transmission on the IC2 bus, the SPI controller controls the data synchronization and data transmission between the master and slave devices, and the UART controller converts parallel data into serial data for transmission; An oscilloscope is equipped in the sensor interface module to collect the voltage peak value, and the change of the voltage peak value describes the electromagnetic interference; The MEMS inertial module consists of a micro-accelerometer structure and a micro-gyroscope structure. Among them, the micro-accelerometer structure includes a mass block, an elastic support structure, and a detection electrode. Based on Newton's second law, it collects the acceleration of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor; the micro-gyroscope structure includes a drive electrode, a vibrating mass block, and a detection electrode. Based on the Coriolis force principle, it collects the angular velocity of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor. The MEMS inertial module uses the micro-accelerometer structure and the micro-gyroscope structure to monitor the attitude information of the information acquisition and electrical signal transmission board of the 32-bit RISC-V processor; The signal conditioning module includes an amplifier and a filter. Among them, the amplifier consists of an operational amplifier, resistors, and capacitors. The signal conditioning module dynamically adjusts the gain of the amplifier according to the strength of the collected electrical signal; the filter consists of a low-pass filter, a high-pass filter, a band-pass filter, and a band-stop filter. The signal conditioning module calls the filter according to the data acquisition scenario.

3. The information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 2, wherein: The process of the analog-to-digital conversion module adopting multi-channel parallel ADC technology includes: The analog-to-digital conversion module adopts multi-channel parallel ADC technology, integrates multiple ADC chips, each ADC chip has an independent analog input channel, converts multiple analog signals, selects the resolution of the ADC chip according to application requirements, the ADC chip is connected to the RISC-V processor through a high-speed parallel bus, and a data cache unit is set between the ADC chip and the RISC-V processor, using a FIFO queue to temporarily store the data after ADC conversion in the data cache unit.

4. The information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 3, characterized in that: The electromagnetic interference monitoring module obtains the influence degree of electromagnetic interference on the transmission of electrical signals. The process of constructing an electromagnetic interference monitoring model using the random forest algorithm includes: It is set that in the digital signal, the voltage range corresponding to logic 0 is V1 to V2, and the voltage range corresponding to logic 1 is V1 to V3. When the voltage peak exceeds the normal range of the logic level, an incorrect logic signal level is received. According to the voltage peak, the number of incorrect logic signal levels and the total number of logic signal levels are recorded; The process of calculating the influence degree of electromagnetic interference on the transmission of electrical signals is as follows: Among them, BER is the bit error rate, which describes the influence degree of electromagnetic interference on the transmission of electrical signals; n is the number of incorrect logic signal levels, and N is the total number of logic signal levels; Using the random forest algorithm, taking the voltage peak and BER as the data set, dividing them into a training set and a test set according to a ratio of 7:3, and setting the parameters of the random forest model; Using the training set data to train the random forest model, learning the non-linear relationship between the voltage peak and BER through decision trees, taking the voltage peak as the input and BER as the output to obtain the random forest model; Using the test set data to evaluate the performance of the trained random forest model, according to the performance evaluation results, optimizing the random forest model by adjusting the parameters of the random forest model, and deploying the random forest model to an information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor to obtain an electromagnetic interference monitoring model.

5. An information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 4, characterized in that: The electrical signal transmission module includes a driving module and a communication interface module: The information acquisition module is connected to the electrical signal transmission module through a PCB board. Among them, the driving module provides power for the information acquisition module and sends control instructions to the information acquisition module to control the working mode of the information acquisition module. The information acquisition module transmits the collected data to the communication interface module; the output end of the communication interface module is connected to the input end of the driving module, and the output end of the driving module is connected to an external communication module; The driving module includes a power amplification unit and a level conversion unit. Among them, the power amplification unit is composed of a transistor and an operational amplifier. The output stage of the power amplification unit adopts a push-pull structure, and the output signal of the power amplification unit is conducted by different transistors in the positive and negative half-cycles respectively; the level conversion unit includes a transistor and a resistor, and converts the output level of the RISC-V processor into the level required by the communication interface according to different communication interface standards.

6. The information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 5, wherein: The communication interface module includes: The communication interface module consists of an IC2 chip, an SPI chip, a UART chip, and an electromagnetic shielding unit. Among them, the IC2 chip includes a master-slave mode selection component, a data shift register, and a clock generator. The master device generates a clock signal through the SCK line and exchanges data on the MOSI and MISO lines; the SPI chip uses the SCL line and the SDA line to achieve two-wire communication between multiple devices; the UART chip includes a transmitter, a receiver, and a baud rate generator. The transmitter converts the parallel data output by the RISC-V processor into serial data, adds a start bit, a stop bit, and a parity bit to the serial data, and sends the serial data through the TX pin. The receiver receives the serial data from the RX pin, removes the start bit, stop bit, and parity bit in the serial data, and converts the serial data into parallel data; The electromagnetic shielding unit uses a metal shielding cover to wrap the IC2 chip, the SPI chip, and the UART chip, grounds the metal shielding cover, and conducts the induced electromagnetic interference into the ground.

7. An information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 6, characterized in that: The storage module includes a program memory and a data memory: The program memory consists of a flash memory chip and a storage controller. The flash memory chip is the storage medium of the program memory, stores program codes in bytes, and is connected to the RISC-V processor through address lines, data lines, and control lines. The address lines are used to select storage locations, the data lines are used to transmit data, and the control lines are used to control the read, write, and erase operations of the flash memory chip. The physical address of the flash memory chip corresponds to the logical address of the RISC-V processor; the storage controller connects the RISC-V processor and the flash memory chip, converts the logical address sent by the RISC-V processor into the physical address in the flash memory chip, and controls and manages the read, write, and erase of the flash memory chip; The data memory consists of a static random access memory and a dynamic random access memory. The static random access memory is SRAM, and the dynamic random access memory is DEAM. Among them, SRAM consists of an array of multiple storage units, each storage unit stores 1 bit of data, and the storage units are accessed through address lines. SRAM is connected to the RISC-V processor through a data bus, an address bus, and a control bus; DRAM consists of a storage unit array, a row decoder, a column decoder, and a read-write amplifier. Data in DRAM is stored in a capacitor in the form of electric charge, and the storage unit array is selected through a row address strobe signal and a column address strobe signal.

8. An information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 7, characterized in that: The power supply module includes a power management module and a filter capacitor module: The power supply module is connected to the information acquisition module, the electrical signal transmission module, and the storage module through output power lines; The power management module includes a DC-DC converter, a low-dropout linear regulator, and a power supply monitoring unit. The DC-DC converter consists of a power switch tube, an inductor, a capacitor, and a control chip. The DC-DC converter is divided into buck type, boost type, and buck-boost type. Based on the energy storage and release characteristics of the inductor, the DC-DC converter detects the output voltage, compares the output voltage with the reference voltage, generates a PWM signal, controls the on and off time of the power switch tube, and adjusts the magnitude and stability of the output voltage; The low-dropout linear regulator consists of a power transistor, an error amplifier, a reference voltage source, and a feedback resistor network. Based on the feedback mechanism, it outputs the input voltage after passing through the power transistor, feeds back the output voltage to the input terminal of the error amplifier through the feedback resistor network, compares it with the reference voltage source, and the error amplifier adjusts the conduction degree of the power transistor according to the comparison result to keep the voltage stable; the power supply monitoring unit includes voltage monitoring, current detection, and temperature monitoring, which respectively monitor the input voltage, output voltage, the magnitude of the current in the power supply line, and the temperatures of the power switch transistor and the power transistor in the power supply module; The filter capacitor module consists of an electrolytic capacitor and a ceramic capacitor. The electrolytic capacitor has a large capacitance and is composed of a metal foil, an electrolyte, and an insulating paper. It filters out the low-frequency ripples in the power supply by using the energy storage characteristic of the capacitor, charging when the power supply voltage rises and discharging when the power supply voltage drops; the ceramic capacitor has a small capacitance and filters out the high-frequency noise in the power supply based on the low-impedance characteristic of the capacitor to high-frequency signals.

9. The information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 8, wherein: The RISC-V processor core module includes a core logic module, a cache module, and an interrupt control module: The core logic module includes an ALU, a CU, and a register file. The ALU has built-in combinational logic units that receive operands from the register file and perform addition, subtraction, multiplication, division, logical AND, logical NOT, and shift operations according to the operation code of the instruction; the CU consists of a finite state machine and a decoder, reads instructions from the memory module, decodes the instructions to obtain the operation code and function code of the instructions, and generates control signals to control the operation of the RISC-V processor according to the operation code and function code of the instructions; the register file is a high-speed storage unit in the RISC-V processor, composed of 32-bit registers, and is used to store data during the operation of the RISC-V processor; The cache module includes an instruction cache and a data cache. The instruction cache uses SRAM to store instructions; the data cache uses SRAM to store data; The interrupt control module includes an interrupt request register, an interrupt mask register, an interrupt priority encoder, and an interrupt service routine pointer. Among them, the interrupt request register is used to store interrupt requests; the interrupt mask register is used to mask and allow interrupt requests to be responded to by the RISC-V processor; the interrupt priority encoder sorts the interrupt requests according to the preset priority; the interrupt service routine pointer stores the entry address of the interrupt service routine corresponding to the interrupt source.

10. The information acquisition and electrical signal transmission board based on a 32-bit RISC-V processor according to claim 9, characterized in that: The process of calling the RISC-V processor includes: The RISC-V processor uses an internal clock generator to monitor the information acquisition rate. When the actual information acquisition rate is lower than expected, the RISC-V processor core module issues an instruction, the CU reads the instruction, and based on the Nyquist sampling theorem, sets the sampling frequency. The RISC-V processor core module applies for a buffer in the data memory to store the data after ADC conversion, and calls the multi-channel parallel ADC technology of the analog-to-digital conversion module; when the information acquisition rate cannot be synchronized with the analog-to-digital conversion, the RISC-V processor adds a timestamp to the acquired information points, and according to the time information carried by the timestamp, uses a synchronous clock signal to drive the analog-to-digital conversion module. After the analog-to-digital conversion is completed, the RISC-V processor core module checks the ADC conversion completion status through the interrupt control module. When the ADC conversion is completed, the current ADC conversion task is terminated through the interrupt control module; Combined with the electromagnetic interference monitoring model, evaluate the degree of influence of electromagnetic interference on the transmission of electrical signals. When the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is less than 10 -9 , the electromagnetic interference has a low impact on the transmission of electrical signals, and continuously monitor the voltage peak value describing the electromagnetic interference; when the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is between 10 -6 and 10 -9 , the electromagnetic interference has a medium impact on the transmission of electrical signals, and the RISC-V processor adjusts the parameters of the communication interface module to reduce the electrical signal transmission rate and reduce the impact of electromagnetic interference on the electrical signal; when the evaluated degree of influence of electromagnetic interference on the transmission of electrical signals is higher than 10 -6 , the electromagnetic interference has a high impact on the transmission of electrical signals, and the RISC-V processor checks the integrity and grounding of the metal shielding cover of the communication interface module, and controls the RISC-V processor core module to issue an electromagnetic interference alarm instruction to remind the user to check and repair the metal shielding cover.

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