Hard disk control circuit, method, equipment, medium and program product

Abstract

The invention discloses a hard disk control circuit, a hard disk control method, hard disk control equipment, a medium and a program product in the technical field of computers. In the hard disk control circuit, a first port of a processor is connected with a first uplink port of a communication bridge, and a first downlink port, corresponding to the first uplink port, in the communication bridge is connected with a hard disk; a second port of the processor is connected with a second uplink port of the communication bridge through the main logic control device, and a second downlink port, corresponding to the second uplink port, in the communication bridge is connected with the hard disk through the slave logic control device. According to the circuit connection mode, the main logic control device can execute related operations such as processor port state identification and the like, identification of the processor port state by means of a backboard CPLD through a long communication link is not needed, the transmission time of the port state is saved, and therefore the identification efficiency of the processor port state is improved; transmission of a traditional long communication link is omitted, a multi-module joint debugging problem is converted into a single-node diagnosis problem, and the error rate is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technologies, and particularly to a hard disk control circuit, method, device, medium and program product. Background Art

[0002] Generally, in the POST (Power-On Self-Test) stage of a server system, when the processor has not completed the enumeration of PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) devices, it will issue an uncalibrated and invalid hard disk lighting instruction. After the processor completes the enumeration of PCIe devices, it will issue a normal and valid hard disk lighting instruction. In order to identify the validity of the hard disk lighting instruction, the BIOS (Basic Input Output System) needs to report the processor port status to the BMC (Baseboard Management Controller) through the eSPI (Enhanced Serial Peripheral Interface) bus, and then the BMC issues it to the backplane CPLD (Complex Programmable Logic Device) through the I2C (Inter-Integrated Circuit) bus. The backplane CPLD performs operations such as identifying the processor port status. The long communication link results in slow execution of related operations.

[0003] Therefore, how to improve the processing efficiency of related operations performed by the backplane CPLD is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide a hard disk control circuit, method, device, medium and program product to improve the processing efficiency of related operations performed by the backplane CPLD.

[0005] In a first aspect, the present application provides a hard disk control circuit, including: a processor, a main logic control device, a communication bridge, a slave logic control device and a hard disk; wherein, a first port of the processor is connected to a first upstream port of the communication bridge, and a first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; a second port of the processor is connected to a second upstream port of the communication bridge through the main logic control device, and a second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device.

[0006] In a second aspect, the present application provides a hard disk control method, including: a processor generates a hard disk lighting instruction, and transmits the hard disk lighting instruction to a main logic control device connected to the processor through a target processor port; after the main logic control device detects that the volume management device corresponding to the target processor port is enabled, it splits the hard disk lighting instruction into multiple sub-instructions, and transmits the multiple sub-instructions to a communication bridge connected to the main logic control device; the communication bridge transmits the multiple sub-instructions to a slave logic control device connected to the communication bridge; the slave logic control device performs a hard disk lighting operation according to the multiple sub-instructions.

[0007] In a third aspect, the present application provides an electronic device, including: the hard disk control circuit according to any one of the foregoing.

[0008] In a fourth aspect, the present application provides an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the hard disk control method disclosed above.

[0009] In a fifth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the hard disk control method disclosed above.

[0010] In a sixth aspect, the present application provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the hard disk control method disclosed above.

[0011] As can be seen from the above solutions, the present application provides a hard disk control circuit, including: a processor, a main logic control device, a communication bridge, a slave logic control device, and a hard disk; wherein, a first port of the processor is connected to a first upstream port of the communication bridge, and a first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; a second port of the processor is connected to a second upstream port of the communication bridge through the main logic control device, and a second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device.

[0012] It can be seen that the beneficial effects of this application are as follows: The hard disk control circuit includes: a processor, a main logic controller device, a communication bridge, a slave logic controller device, and a hard disk. The first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; the second port of the processor is connected to the second upstream port of the communication bridge through the main logic controller device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic controller device. According to this circuit connection method, relevant operations such as processor port status recognition can be performed by the main logic controller device, without the need to use a long communication link to identify the processor port status with the help of the backplane CPLD, saving the transmission time of the port status, thereby improving the recognition efficiency of the processor port status, eliminating the transmission of the traditional long communication link, transforming the multi-module joint debugging problem into a single-node diagnosis problem, and reducing the error rate.

[0013] Correspondingly, a hard disk control device, medium, and program product provided by this application also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0015] Figure 1 Schematic diagram of a hard disk control circuit disclosed in this application; Figure 2 Schematic diagram of a communication bridge disclosed in this application; Figure 3 Schematic diagram of the second communication bridge disclosed in this application; Figure 4 Flowchart of a hard disk control method disclosed in this application; Figure 5 Schematic diagram of the second hard disk control circuit disclosed in this application; Figure 6 Schematic diagram of the third hard disk control circuit disclosed in this application; Figure 7 Flowchart of the second hard disk control method disclosed in this application; Figure 8 Structure diagram of a server provided by this application; Figure 9 Structure diagram of a terminal provided by this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0017] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0018] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0019] With the rapid development of big data processing, cloud computing and artificial intelligence technologies, server storage systems are facing multiple challenges of high concurrency, low latency and high bandwidth. Traditional SAS / SATA interface hard disks are limited by the protocol stack efficiency and physical bandwidth, and significant performance bottlenecks are exposed in multi-queue access scenarios. Against this background, the all-flash technology based on the PCIe bus and the NVMe protocol has rapidly emerged. Current mainstream NVMe hard disks already support the PCIe 6.0 interface, with the theoretical transmission rate increased to 64 GT / s (the two-way bandwidth reaches 256 Gbps), and the sequential read and write performance of a single disk breaking through 14 GB / s, significantly improving the throughput capacity of the data center storage system. However, in the design of the server multi-disk backplane, there are still technical bottlenecks in hardware management and status monitoring. Taking the hard disk working status indication (lighting management) as an example, the traditional solution has the following defects: 1) The traditional polling mechanism relies on the CPU interrupt service routine. When mounting 24 NVMe hard disks, the monitoring thread occupancy rate reaches 12.7%, and the standard deviation of the event response delay reaches 47 ms, which cannot meet the 100 ms-level real-time response required by the UEFI specification. 2) The dual-master control architecture (such as BMC + CPU) lacks a unified interface standard, and the backplane CPLD needs to determine the upstream HOST entity, significantly increasing the risk of operation and maintenance misjudgment.

[0020] Currently, during the POST stage of the server system, when the processor has not completed the enumeration of PCIe devices, it will issue an uncalibrated and invalid hard disk lighting instruction. After the processor completes the enumeration of PCIe devices, it will issue a normal and valid hard disk lighting instruction. In order to identify the validity of the hard disk lighting instruction, the BIOS needs to report the processor port status to the BMC via the eSPI bus, and then the BMC sends it to the backplane CPLD via the I2C bus. The backplane CPLD performs operations such as identifying the processor port status. The relatively long communication link results in slow execution of related operations. Therefore, this application provides a hard disk control solution that can convert the multi-module joint debugging problem into a single-node diagnosis problem, reduce the error rate, and improve the execution efficiency of operations such as identifying the processor port status.

[0021] See Figure 1 As shown, an embodiment of this application discloses a hard disk control circuit, including: a processor, a main logic controller, a communication bridge, a slave logic controller, and a hard disk.

[0022] Among them, the first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; the second port of the processor is connected to the second upstream port of the communication bridge through the main logic controller, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic controller. Specifically, the slave logic controller is connected to the hard disk and the indicator light of the corresponding hard disk through a hard disk connector. Multiple hard disk connectors can be connected downstream of the slave logic controller, and one hard disk can be plugged into one hard disk connector. The hard disk can be an NVME disk or other types.

[0023] Based on Figure 1 the above circuit, the corresponding hard disk lighting process can include: the processor generates a hard disk lighting instruction and transmits the hard disk lighting instruction to the main logic controller connected to the processor through the target processor port (such as the second port); after the main logic controller detects that the volume management device corresponding to the target processor port is enabled, it splits the hard disk lighting instruction into multiple sub-instructions and transmits the multiple sub-instructions to the communication bridge connected to the main logic controller; the communication bridge transmits the multiple sub-instructions to the slave logic controller connected to the communication bridge; the slave logic controller performs the hard disk lighting operation according to the multiple sub-instructions.

[0024] In one embodiment, the third port of the processor is connected to the main logic controller through a management controller. That is: the third port of the processor is connected to the management controller, and the management controller is also connected to the main logic controller. For details, please refer to Figure 5 or Figure 6, the third port of the processor is connected to the BMC serving as a management controller, and the management controller is also connected to the CPLD serving as the main logic control device. Moreover, a level conversion module Levelshit can be connected between the second port and the main logic control device for voltage adjustment.

[0025] Please refer to Figure 2 , the communication bridge includes: an upstream connector and a downstream connector that are interconnected and have equal numbers; a first upstream port and a second upstream port are provided on the upstream connector; a first downstream port and a second downstream port are provided on the downstream connector. Among them, the connection method between the upstream connector and the downstream connector can refer to the common circuit connection of the corresponding connector, and both the upstream connector and the downstream connector can be MCIO connectors.

[0026] In one implementation, the processor, the main logic control device, the management controller, and the upstream connector are provided on the main board; the slave logic control device, the hard disk, and the downstream connector are provided on the backplane. Among them, the main board can be connected to multiple backplanes.

[0027] Please refer to Figure 3 , the communication bridge includes: an upstream connector, a switching device, and a downstream connector that are sequentially connected; a first upstream port and a second upstream port are provided on the upstream connector; a first downstream port and a second downstream port are provided on the downstream connector. Correspondingly, the switching device includes: a first connector, a switching module, and a second connector that are sequentially connected; the first connector is connected to the upstream connector and has the same number as the upstream connector; the second connector is connected to the downstream connector and has the same number as the downstream connector; the first connector is also connected to the second connector through a bridge controller; the first connector and the second connector have the same number. The number of sub-instructions received by the bridge controller is in a proportional relationship with its downstream channel number. Correspondingly, the main logic control device is used to: synchronize the status of the target processor port to the slave logic control device and / or the bridge controller.

[0028] It should be noted that the connection path from the processor to the hard disk includes: processor ports (such as the second port, the first port), the main logic control device, the communication bridge, the slave logic control device, and the hard disk. Accordingly, the main logic control device can automatically construct and record the physical topology relationship between the processor port and the hard disk when powered on. Then, in the case where the processor, the main logic control device, the management controller, and the upstream connector are provided on the main board, the slave logic control device, the hard disk, and the downstream connector are provided on the backplane, and the main board is connected to multiple backplanes, the main logic control device can clarify the connection path (i.e., the physical topology relationship) from any processor port to any hard disk.

[0029] In this embodiment, the hard disk control circuit includes: a processor, a main logic control device, a communication bridge, a slave logic control device, and a hard disk. The first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk. The second port of the processor is connected to the second upstream port of the communication bridge through the main logic control device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device. According to this circuit connection method, the main logic control device can execute related operations such as identifying the processor port status, without using a long communication link to identify the processor port status with the help of the backplane CPLD, saving the transmission time of the port status, thereby improving the identification efficiency of the processor port status, eliminating the transmission of the traditional long communication link, transforming the multi-module joint debugging problem into a single-node diagnosis problem, and reducing the error rate.

[0030] See Figure 4 As shown, an embodiment of the present application discloses a hard disk control method, which is applied to the hard disk control circuit described in other embodiments, including: S401. The processor generates a hard disk lighting instruction and transmits the hard disk lighting instruction to the main logic control device connected to the processor through the target processor port.

[0031] S402. After the main logic control device detects that the volume management device corresponding to the target processor port is enabled, it splits the hard disk lighting instruction into multiple sub-instructions and transmits the multiple sub-instructions to the communication bridge connected to the main logic control device.

[0032] Among them, before transmitting the multiple sub-instructions to the communication bridge, the downstream channel corresponding to the target processor port is activated. After detecting that the volume management device corresponding to the target processor port is not enabled, the hard disk lighting instruction is discarded.

[0033] S403. The communication bridge transmits the multiple sub-instructions to the slave logic control device connected to the communication bridge.

[0034] S404. The slave logic control device performs a hard disk lighting operation according to the multiple sub-instructions.

[0035] Specifically, the slave logic control device is used to: detect whether the corresponding hard disk is in place according to the multiple sub-instructions, and perform a hard disk lighting operation on the hard disk in place.

[0036] In this embodiment, the main logic control device and the slave logic control device may specifically be CPLD or others. The main logic control device is arranged on the server motherboard, and the slave logic control device is arranged on the backplane.

[0037] In one embodiment, the hard disk control circuit further includes: a management controller (such as BMC) connected to both the processor and the main logic controller device; correspondingly, the main logic controller device is configured to: capture the interaction signals between the processor and the management controller, and detect whether the volume management device corresponding to the target processor port is enabled through the interaction signals. Specifically, the main logic controller device is configured to: when it is determined through the interaction signals that the state of the target processor port is the first target value, determine that the volume management device corresponding to the target processor port is enabled; when it is determined through the interaction signals that the state of the target processor port is the second target value, determine that the volume management device corresponding to the target processor port is not enabled.

[0038] In one example, the main logic controller device is configured to: if it receives a hard disk lighting instruction sent by the management controller, mask the hard disk lighting instruction transmitted by the processor. Correspondingly, the main logic controller device is configured to: set the bus receive port corresponding to the processor to a high impedance state to mask the hard disk lighting instruction transmitted by the processor. Correspondingly, the main logic controller device is configured to: if it receives a lighting control right abandonment instruction or a restart instruction sent by the management controller, set the bus receive port corresponding to the management controller to a high impedance state to mask the hard disk lighting instruction transmitted by the management controller; set the bus receive port corresponding to the processor to a low impedance state to receive the hard disk lighting instruction transmitted by the processor.

[0039] In this embodiment, the slave logic controller device is configured to: report the detected hard disk status to the main logic controller device. Correspondingly, the main logic controller device is configured to: report the received hard disk status to the processor.

[0040] In one embodiment, the main logic controller device is configured to: when powering on, automatically construct a mapping relationship between the processor port and the connector port in the communication bridge according to the connector state in the communication bridge and the hard disk presence signal detected by the slave logic controller device. The main logic controller device determines a corresponding downstream channel for the received hard disk lighting instruction according to this mapping relationship. That is: the connection path from the processor to the hard disk.

[0041] In this embodiment, the main logic controller device directly connected to the processor can detect whether the volume management device corresponding to the processor port is enabled (i.e., detect the processor port state) nearby, so there is no need to identify the processor port state through a long communication link with the help of the backplane CPLD, saving the transmission time of the port state, thereby improving the identification efficiency of the processor port state, eliminating the transmission of the traditional long communication link, transforming the multi-module joint debugging problem into a single-node diagnosis problem, and reducing the error rate; moreover, the main logic controller device can split the hard disk lighting instruction into multiple sub-instructions and transmit the multiple sub-instructions to the downstream communication bridge and the slave logic controller device, enabling more idle pins in the connectors in the communication bridge, which is beneficial to the extended monitoring of other types of data such as temperature.

[0042] It should be noted that the current dual-master control architecture can be adopted to dynamically switch the control right of the lighting signal between the CPU and the BMC. Please refer to Figure 5 , where the main board is provided with a CPU, a BMC, a main board CPLD, and an MCIO connector; the backplane is provided with a backplane CPLD, an MCIO connector, and a large number of hard disk connectors. The MCIO connectors on the main board and the MCIO connectors on the backplane form a communication bridge. When the CPU is used as the main controller, the whole-system hard disk lighting instruction is sent down through the SCL / SDA bus matrix of the VPP (VMD Port Physical) protocol. The main board CPLD (i.e., the main logic control device) receives the hard disk lighting instruction sent by the CPU through the VPP bus, parses the CPU port number (PORT_ID) and the corresponding lighting status code carried in the command. The command is 1 bit, and the lighting status code occupies 2 bits of it; when the VMD_ENABLE status of the corresponding CPU port is enabled, based on the pre-stored truth table (recording the hardware connection relationship between the CPU port number and the MCIO connector on the main board), the global lighting instruction is split into MCIO port sub-instructions, and then the sub-instructions are transmitted through the SMBus (System Management Bus) bus via the downstream MCIO connector (the MCIO connector on the backplane) to the backplane CPLD (i.e., the slave logic control device) for reception and execution. When the system switches to the BMC control mode, the BMC obtains the lighting control right and then performs the lighting operation. Among them, VMD (Volume Management Device) is a volume management device.

[0043] In this example, 2 groups of 8-bit lighting data are allocated to each MCIO port of the x8 specification, and the address bit of each group of lighting data is fixed at 0x40. The unification of the addresses ensures the decoupling of the backplane CPLD code. Further, when the I / O pin resources of the main board CPLD are insufficient, an I2C SWITCH chip (such as PCA9546) can be used to expand a single SMBus into multiple independent channels through address decoding. That is: an I2C SWITCH chip is set between the main board CPLD and the main board MCIO connector to expand a single SMBus into multiple independent channels.

[0044] And Figure 5In it, the main board CPLD establishes a communication link with the CPU through the eSPI bus, captures the interaction signals (CPU port status) between the CPU and the BMC in real time, and parses the VMD enable status data packet of the CPU port transmitted by the eSPI. When it detects that the CPU port VMD_STATUS = 1, it activates the corresponding MCIO downstream channel of the port and sends the lighting instruction to the target backplane CPLD; if VMD_STATUS == 0, it discards all pending lighting instructions of the port.

[0045] When the main board CPLD receives the lighting instruction sent by the BMC through the SMBus bus, it immediately sets the VPP bus receiving port of the CPU to the high-impedance state to mask the lighting instruction sent by the CPU. It will not return to the normal state until it receives the lighting control right abandonment instruction sent by the BMC or the system restarts and restores the default settings.

[0046] The backplane upstream MCIO interface corresponds one-to-one with the I2C bus. Each MCIO interface corresponds to a group of I2C buses, which contains the lighting information of two hard disks. After the backplane CPLD parses the lighting information sent by the I2C bus, it detects the presence status of the hard disk. If the hard disk is present, it executes the lighting instruction; if the hard disk is not present, it masks the lighting instruction.

[0047] Each group of lighting information corresponds to 8-bit data. In this example, the hard disk lighting instruction only uses bits 0 and 1, which control the same light to shine in different colors respectively. Among them, the red light indicates an error, the blue light indicates that the hard disk is present, and if both lights are on at the same time, it indicates reconstruction recovery. The unused Bit2 - Bit7 can be redefined. For example, Bit4 indicates the hard disk presence status (PRSNT), Bit5 controls the independent power-on of the hard disk (POWEREN), and Bit6 triggers the hard disk power-saving mode (PWRDIS). Through the custom function, when the backplane CPLD responds to the main board status query, it returns the current presence, power and other status information.

[0048] The I2C bus signal pins between the main board CPLD and the backplane CPLD are configured in the open-drain (OD) mode. A 1kΩ pull-up resistor is integrated at the backplane end, and a 100kΩ pull-down resistor is integrated at the main board end. During the boot process, the main board CPLD switches the SDA / SCL pins of the downstream I2C to the input mode to detect their level status. If it is detected that the levels of the SDA / SCL pins of the I2C bus are constantly low, it is determined that the corresponding MCIO port is not connected to the backplane. If they are constantly high or there are high-level pulses, it is determined that the MCIO port is connected to the backplane, and this port is recorded as a valid topology node. Combining the connection status of the MCIO port and the hard disk presence signal (PRSNT) returned by the backplane CPLD, a dynamic truth table is constructed to automatically map the physical topology relationship of CPU → MCIO connector → backplane → hard disk. If it is detected that the MCIO port is connected but there is no hard disk present, it is marked as a to-be-expanded state, and the lighting instruction for this port is masked in the operating system.

[0049] Please refer to Figure 6 , there is a CPU, a BMC, a main board CPLD, and an MCIO connector on the main board; there is a backplane CPLD, an MCIO connector, and numerous hard disk connectors on the backplane; there is an MCIO X8 connector (i.e., the first connector), a PCIE SWITCH (i.e., the switching module), and another MCIO X8 connector (the second connector) on the PCIE SWITCH board (i.e., the switching device). The MCIO connector on the main board, the MCIO connector on the backplane, the MCIO X8 connector on the PCIE SWITCH board, the PCIE SWITCH (bridging controller), and the other MCIO X8 connector form a communication bridge. When the main board CPLD detects that the number of lighting command data groups issued by the CPU PORT corresponding to an MCIO X8 interface exceeds two groups, it triggers the downstream link type determination mechanism to determine that the downstream is connected to the backplane after passing through the PCIE SWITCH board. In this case, when the VMD corresponding to this CPU PORT is in the ENABLE state, the main board CPLD directly transmits the lighting data corresponding to this CPU PORT to the lower-level CPLD. Taking the downstream link as an example of the PCIE SWITCH board (SW board), the number of lighting data received by the SW board CPLD is in a proportional relationship with the number of MCIO ports expanded by the SW board. For example, if there is one MCIO X8 connector on the upstream of the SW board and four MCIO X8 connectors on the downstream, the SW board CPLD receives 8 groups of lighting data and distributes the data to each downstream port based on the hardware connection topology; through the hierarchical transparent transmission and topology adaptation mechanism, the hardware compatibility of the backplane for the two scenarios of the upstream of the main board and the upstream of the Switch board is realized, ensuring the consistency of the backplane design.

[0050] Please refer to Figure 7 , a hard disk control method includes: ① When the server boots up, the motherboard CPLD receives the full-system lighting information sent by the CPU and binds the lighting commands corresponding to the CPU PORT to the corresponding MCIO X8 interface based on the truth table.

[0051] ② The motherboard CPLD traverses each group of lighting information and determines whether the CPU PORT corresponding to each group of lighting information is in the VMDENABLE state. If VMD ENABLE = 1, it distributes / passthroughs the lighting information to the downstream board; if VMD ENABLE = 0, it masks the lighting information corresponding to the CPU PORT to avoid the transmission of invalid signals.

[0052] ③ The motherboard CPLD detects the lighting data volume of the CPU PORT associated with each MCIO X8 interface. If the current PORT corresponds to two groups of lighting information, it determines that the downstream is a direct-connected hard disk backplane. It repackages the two groups of lighting information corresponding to the CPU PORT and unifies the address bit to 0x40, and then sends it to the backplane CPLD through the MCIO port. If the current PORT corresponds to more than two groups of lighting information, it is determined that the downstream link is transferred through the PCIe Switch board, and the original lighting data is directly passthrough to the Switch board CPLD.

[0053] ④ For the SW board, the SW board CPLD distributes the data to the I2C bus corresponding to each downstream MCIO port according to the hardware connection relationship, and the data content format is the same as the lighting command format sent by the motherboard CPLD in the scenario where the motherboard is directly connected to the backplane.

[0054] ⑤ For the backplane, it parses the lighting data in each group of I2C buses (each group contains 2 instructions) and detects whether the target hard disk is present: if the hard disk is present, it drives the corresponding LED to perform the lighting / extinguishing operation; if the hard disk is not present, it discards the group of instructions and records the abnormal state.

[0055] In this embodiment, through the state determination and data transparent transmission mechanism at the CPLD level, the plug-and-play compatibility of heterogeneous motherboard platforms on the same backplane is achieved, eliminating the adaptation problems caused by different VPP / CPU ADDRs on different platforms. The pin assignment strategy of the MCIO connector is optimized: the original VPP / CPU ADDR signal requires 7 pins, but now only 2 pins are needed to achieve equivalent functions. The saved 5 pins can be configured for function expansion interfaces (such as temperature sensors), improving the utilization rate of hardware resources and the scalability of the system. The motherboard CPLD integrates self-awareness of the topology state, which can parse the lighting instructions and VMD enable status sent by the CPU in real time and synchronously map them to downstream devices (such as the backplane or Switch board). At the same time, key state information (such as lighting instruction distribution count, hard disk presence status) is exposed through the CPLD register, supporting direct reading of the register to locate the cause of the exception (such as VMD not enabled or link interruption), transforming the traditional multi-module joint debugging problem into a single-node diagnosis problem and reducing the debug workload.

[0056] Next, an electronic device provided by an embodiment of the present application will be introduced. The electronic device described below can be referred to each other with other embodiments described in this article. The electronic device in this embodiment can be any device mentioned in the foregoing embodiments, such as: a processor, a main logic control device, a communication bridge, a slave logic control device, etc.

[0057] An embodiment of the present application discloses an electronic device, which may include: a hard disk control circuit as described in other embodiments.

[0058] An embodiment of the present application discloses an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the method disclosed in any of the foregoing embodiments.

[0059] In one example, an electronic device includes: at least one hard disk control circuit described in any of the foregoing embodiments. The hard disk control circuit includes: a processor, a main logic controller device, a communication bridge, and a slave logic controller device. Among them, a plurality of hard disk connectors are connected downstream of the slave logic controller device, and one hard disk can be plugged into one hard disk connector. The hard disk can be an NVME disk or other types. In the electronic device, the main logic controller device directly connected to the processor can detect whether the volume management device corresponding to the processor port is enabled (i.e., detect the processor port status) nearby, so that there is no need to identify the processor port status through a long communication link with the help of the backplane CPLD, saving the transmission time of the port status, thereby improving the identification efficiency of the processor port status, eliminating the transmission of the traditional long communication link, converting the multi-module joint debugging problem into a single-node diagnosis problem, and reducing the error rate; moreover, the main logic controller device can split the hard disk lighting instruction into multiple sub-instructions and transmit the multiple sub-instructions to the downstream communication bridge and the slave logic controller device, enabling more idle pins in the connectors within the communication bridge, which is beneficial to the extended monitoring of other types of data such as temperature.

[0060] The processor is configured to generate a hard disk lighting instruction and transmit the hard disk lighting instruction to the main logic controller device connected to the processor through the target processor port.

[0061] The main logic controller device is configured to, after detecting that the volume management device corresponding to the target processor port is enabled, split the hard disk lighting instruction into multiple sub-instructions and transmit the multiple sub-instructions to the communication bridge connected to the main logic controller device. Among them, before transmitting the multiple sub-instructions to the communication bridge, activate the downstream channel corresponding to the target processor port. After detecting that the volume management device corresponding to the target processor port is not enabled, discard the hard disk lighting instruction.

[0062] The communication bridge is configured to transmit the multiple sub-instructions to the slave logic controller device connected to the communication bridge.

[0063] The slave logic controller device is configured to perform a hard disk lighting operation according to the multiple sub-instructions. Specifically, the slave logic controller device is configured to: detect whether the corresponding hard disk is present according to the multiple sub-instructions and perform a hard disk lighting operation on the present hard disk.

[0064] In one embodiment, the hard disk control circuit further includes: a management controller (such as BMC) connected to both the processor and the main logic control device; correspondingly, the main logic control device is configured to: capture the interaction signals between the processor and the management controller, and detect whether the volume management device corresponding to the target processor port is enabled through the interaction signals. Specifically, the main logic control device is configured to: when determining that the state of the target processor port is the first target value through the interaction signals, determine that the volume management device corresponding to the target processor port is enabled; when determining that the state of the target processor port is the second target value through the interaction signals, determine that the volume management device corresponding to the target processor port is not enabled.

[0065] In one example, the main logic control device is configured to: if receiving a hard disk lighting instruction sent by the management controller, mask the hard disk lighting instruction transmitted by the processor. Correspondingly, the main logic control device is configured to: set the bus receiving port corresponding to the processor to a high impedance state to mask the hard disk lighting instruction transmitted by the processor. Correspondingly, the main logic control device is configured to: if receiving a lighting control right abandonment instruction or a restart instruction sent by the management controller, set the bus receiving port corresponding to the management controller to a high impedance state to mask the hard disk lighting instruction transmitted by the management controller; set the bus receiving port corresponding to the processor to a low impedance state to receive the hard disk lighting instruction transmitted by the processor.

[0066] In this embodiment, the slave logic control device is configured to: report the detected hard disk status to the main logic control device. Correspondingly, the main logic control device is configured to: report the received hard disk status to the processor.

[0067] In one embodiment, the main logic control device is configured to: when powering on, automatically construct the mapping relationship between the processor port and the connector port in the communication bridge according to the connector state in the communication bridge and the hard disk presence signal detected by the slave logic control device. The main logic control device determines the corresponding downstream channel for the received hard disk lighting instruction according to this mapping relationship.

[0068] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after detecting that the volume management device corresponding to the target processor port of the processor is enabled, split the hard disk lighting instruction sent by the processor into multiple sub-instructions; transmit the multiple sub-instructions to the slave logic control device through the communication bridge, so that the slave logic control device performs the hard disk lighting operation according to the multiple sub-instructions.

[0069] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after detecting that the volume management device corresponding to the target processor port is not enabled, discard the hard disk lighting instruction.

[0070] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: capture the interaction signal between the processor and the management controller, and detect whether the volume management device corresponding to the target processor port is enabled through the interaction signal.

[0071] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when it is determined through the interaction signal that the state of the target processor port is the first target value, it is determined that the volume management device corresponding to the target processor port is enabled; when it is determined through the interaction signal that the state of the target processor port is the second target value, it is determined that the volume management device corresponding to the target processor port is not enabled.

[0072] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: if a hard disk lighting instruction sent by the management controller is received, the hard disk lighting instruction transmitted by the processor is masked.

[0073] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: set the bus receiving port corresponding to the processor to a high impedance state to mask the hard disk lighting instruction transmitted by the processor.

[0074] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: if a lighting control right abandonment instruction or a restart instruction sent by the management controller is received, set the bus receiving port corresponding to the management controller to a high impedance state to mask the hard disk lighting instruction transmitted by the management controller; set the bus receiving port corresponding to the processor to a low impedance state to receive the hard disk lighting instruction transmitted by the processor.

[0075] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: before transmitting multiple sub-instructions to the communication bridge, activate the downstream channel corresponding to the target processor port.

[0076] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: detect whether the corresponding hard disk is in place according to multiple sub-instructions, and perform a hard disk lighting operation on the hard disk in place.

[0077] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: synchronize the state of the target processor port to the slave logic control device and / or the bridge controller.

[0078] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: reporting the detected hard disk status to the main logic controller device.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: reporting the received hard disk status to the processor.

[0080] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when powering on, automatically constructing a mapping relationship between the processor port and the connector port in the communication bridge according to the connector status in the communication bridge and the hard disk presence signal detected by the slave logic controller device.

[0081] Further, an embodiment of the present application further provides an electronic device. Among them, the above electronic device may be, for example, Figure 8 the server shown, or may be, for example, Figure 9 the terminal shown. Figure 8 and Figure 9 are both structural diagrams of electronic devices shown according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of the present application.

[0082] Figure 8 A structural schematic diagram of a server provided by an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. Among them, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the hard disk control disclosed in any of the foregoing embodiments.

[0083] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed on it here; the input / output interface is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0084] In addition, as a carrier for resource storage, the memory may be a read-only memory, a random access memory, a disk, or an optical disc, etc., and the resources stored thereon include an operating system, a computer program, and data, etc., and the storage method may be short-term storage or permanent storage.

[0085] Among them, the operating system is used to manage and control each hardware device and computer program on the server to enable the processor to perform operations and processing on the data in the memory, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the hard disk control method disclosed in any of the foregoing embodiments, the computer program can further include computer programs that can be used to complete other specific tasks. In addition to data such as update information of the application program, the data can also include data such as developer information of the application program.

[0086] Figure 9 The figure is a schematic structural diagram of a terminal provided by an embodiment of the present application. The terminal may specifically include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.

[0087] Generally, the terminal in this embodiment includes a processor and a memory.

[0088] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor can also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor can be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor can also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0089] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, as well as non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory is at least used to store the following computer programs. After the computer programs are loaded and executed by the processor, the relevant steps in the hard disk control method executed by the terminal side disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of application programs.

[0090] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, sensors, a power supply, and a communication bus.

[0091] Those skilled in the art can understand that Figure 9 the structure shown in does not constitute a limitation on the terminal, and may include more or fewer components than those shown in the figure.

[0092] Next, a non-volatile storage medium provided by an embodiment of the present application will be introduced. The non-volatile storage medium described below may be referred to each other with other embodiments described in this article.

[0093] A non-volatile storage medium is used to store a computer program. When the computer program is executed by a processor, the hard disk control method disclosed in the foregoing embodiments is implemented. Among them, the non-volatile storage medium is a computer-readable non-volatile storage medium. As a carrier for storing resources, it may be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system, a computer program, and data, etc., and the storage method may be transient storage or permanent storage.

[0094] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after detecting that the volume management device corresponding to the target processor port of the processor is enabled, split the hard disk lighting instruction sent by the processor into multiple sub-instructions; transmit the multiple sub-instructions to the slave logic control device through the communication bridge, so that the slave logic control device performs the hard disk lighting operation according to the multiple sub-instructions.

[0095] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after detecting that the volume management device corresponding to the target processor port is not enabled, discard the hard disk lighting instruction.

[0096] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: capture the interaction signal between the processor and the management controller, and detect whether the volume management device corresponding to the target processor port is enabled through the interaction signal.

[0097] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when it is determined through the interaction signal that the state of the target processor port is the first target value, it is determined that the volume management device corresponding to the target processor port is enabled; when it is determined through the interaction signal that the state of the target processor port is the second target value, it is determined that the volume management device corresponding to the target processor port is not enabled.

[0098] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: if a hard disk lighting instruction sent by the management controller is received, the hard disk lighting instruction transmitted by the processor is masked.

[0099] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: set the bus receive port corresponding to the processor to a high impedance state to mask the hard disk lighting instruction transmitted by the processor.

[0100] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: if a lighting control right abandonment instruction or a restart instruction sent by the management controller is received, set the bus receive port corresponding to the management controller to a high impedance state to mask the hard disk lighting instruction transmitted by the management controller; set the bus receive port corresponding to the processor to a low impedance state to receive the hard disk lighting instruction transmitted by the processor.

[0101] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: before transmitting multiple sub-instructions to the communication bridge, activate the downstream channel corresponding to the target processor port.

[0102] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: detect whether the corresponding hard disk is present according to multiple sub-instructions, and perform a hard disk lighting operation on the present hard disk.

[0103] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: synchronize the state of the target processor port to the slave logic control device and / or the bridge controller.

[0104] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: reporting the detected hard disk status to the main logic controller device.

[0105] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: reporting the received hard disk status to the processor.

[0106] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when powering on, automatically constructing a mapping relationship between the processor port and the connector port in the communication bridge according to the connector status in the communication bridge and the hard disk presence signal detected by the slave logic controller device.

[0107] Next, a computer program product provided by an embodiment of the present application will be introduced. A computer program product described below can be referred to each other with other embodiments described herein.

[0108] A computer program product includes a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the foregoing disclosed hard disk control method are implemented.

[0109] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium for storing a computer program. When the computer program is executed by a processor, the steps in any of the foregoing embodiments are implemented.

[0110] In this specification, the embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0111] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of non-volatile storage medium known in the technical field.

[0112] Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A hard disk control circuit, characterized in that, Comprising: a processor, a main logic control device, a communication bridge, a slave logic control device, and a hard disk; wherein, a first port of the processor is connected to a first upstream port of the communication bridge, and a first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; a second port of the processor is connected to a second upstream port of the communication bridge through the main logic control device, and a second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device.

2. The hard disk control circuit according to claim 1, wherein A third port of the processor is connected to the main logic control device through a management controller.

3. The hard disk control circuit according to claim 2, wherein The communication bridge includes: upstream connectors and downstream connectors that are interconnected and equal in number; the first upstream port and the second upstream port are provided on the upstream connectors; the first downstream port and the second downstream port are provided on the downstream connectors.

4. The hard disk control circuit according to claim 3, wherein The processor, the main logic control device, the management controller, and the upstream connectors are provided on a main board; the slave logic control device, the hard disk, and the downstream connectors are provided on a backplane.

5. The hard disk control circuit according to claim 4, wherein, The main board is connected to a plurality of backplanes.

6. The hard disk control circuit according to claim 1, wherein A level conversion module is connected between the second port and the main logic control device.

7. The hard disk control circuit according to claim 1, characterized in that The communication bridge includes: an upstream connector, a switching device, and a downstream connector that are sequentially connected; the first upstream port and the second upstream port are provided on the upstream connector; the first downstream port and the second downstream port are provided on the downstream connector.

8. The hard disk control circuit according to claim 7, characterized in that, The switching device includes: a first connector, a switching module, and a second connector that are sequentially connected; the first connector is connected to the upstream connector and is equal in number to the upstream connector; the second connector is connected to the downstream connector and is equal in number to the downstream connector; the first connector is further connected to the second connector through a bridge controller; the first connector and the second connector are equal in number.

9. The hard disk control circuit according to any one of claims 1 to 8, characterized in that, The main logic control device is configured to: automatically construct and record the physical topology relationship between the processor port and the hard disk when powering on.

10. A hard disk control method, characterized in that, Comprising: The processor generates a hard disk lighting instruction and transmits the hard disk lighting instruction to the main logic control device connected to the processor through a target processor port; after detecting that the volume management device corresponding to the target processor port is enabled, the main logic control device splits the hard disk lighting instruction into a plurality of sub-instructions and transmits the plurality of sub-instructions to the communication bridge connected to the main logic control device; the communication bridge transmits the plurality of sub-instructions to the slave logic control device connected to the communication bridge; the slave logic control device performs a hard disk lighting operation according to the plurality of sub-instructions.

11. The hard disk control method according to claim 10, characterized in that, After detecting that the volume management device corresponding to the target processor port is not enabled, the main logic control device discards the hard disk lighting instruction.

12. The hard disk control method according to claim 10, characterized in that, The hard disk control circuit further includes: a management controller connected to both the processor and the main logic control device; correspondingly, the main logic control device captures the interaction signal between the processor and the management controller and detects whether the volume management device corresponding to the target processor port is enabled through the interaction signal; Accordingly, when the main logic control device determines that the state of the target processor port is the first target value through the interaction signal, it determines that the volume management device corresponding to the target processor port is enabled; when it determines that the state of the target processor port is the second target value through the interaction signal, it determines that the volume management device corresponding to the target processor port is not enabled.

13. The hard disk control method according to claim 12, wherein If the main logic control device receives the hard disk lighting instruction sent by the management controller, it sets the bus receiving port corresponding to the processor to a high impedance state to shield the hard disk lighting instruction transmitted by the processor.

14. The hard disk control method according to claim 13, wherein If the main logic control device receives the lighting control right abandonment instruction or restart instruction sent by the management controller, it sets the bus receiving port corresponding to the management controller to a high impedance state to shield the hard disk lighting instruction transmitted by the management controller; it sets the bus receiving port corresponding to the processor to a low impedance state to receive the hard disk lighting instruction transmitted by the processor. The slave logic control device detects whether the corresponding hard disk is in place according to the multiple sub-instructions, and performs a hard disk lighting operation on the hard disk in place.

15. The hard disk control method according to any one of claims 10 to 14, characterized in that, The communication bridge includes: an upstream connector and a downstream connector that are connected to each other and have the same number; the upstream connector is connected to the main logic control device and the processor, and the downstream connector is connected to the slave logic control device. Alternatively, the communication bridge includes: an upstream connector, a switching device, and a downstream connector connected in sequence; the upstream connector is connected to the main logic control device and the processor, and the downstream connector is connected to the slave logic control device; the switching device includes: a first connector, a switching module, and a second connector connected in sequence; the first connector is connected to the upstream connector and has the same number as the upstream connector; the second connector is connected to the downstream connector and has the same number as the downstream connector; the first connector is also connected to the second connector through a bridge controller; the number of the first connector and the second connector is equal; the number of sub-instructions received by the bridge controller is in a proportional relationship with its number of downstream channels.

16. The hard disk control method according to claim 15, characterized in that, The main logic control device synchronizes the state of the target processor port to the slave logic control device and / or the bridge controller. The slave logic control device reports the detected hard disk state to the main logic control device; accordingly, the main logic control device reports the received hard disk state to the processor. When powered on, the main logic control device automatically constructs and records the physical topology relationship between the processor port and the hard disk according to the connector state in the communication bridge and the hard disk in-place signal detected by the slave logic control device.

17. An electronic device, characterized in that, Including: The hard disk control circuit according to any one of claims 1 to 9.

18. An electronic device, characterized in that, Including: A memory for storing a computer program. A processor for executing the computer program to implement the hard disk control method according to any one of claims 10 to 16.

19. A non-volatile storage medium, characterized in that, For saving a computer program, wherein the computer program, when executed by a processor, implements the hard disk control method according to any one of claims 10 to 16.

20. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, the hard disk control method described in any one of claims 10 to 16 is implemented.

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