Data processing method and device, interface circuit and chip

Abstract

The invention belongs to the technical field of equipment inspection, and provides a data processing method and device, an interface circuit and a chip, and the method comprises the steps that an NOR type flash memory chip interface circuit receives instruction information sent by an MCU (Microprogrammed Control Unit), synchronizes the instruction information in an N-stage trigger sampling mode, and judges whether the values of different stages of triggers are equal or not by comparing whether the values of the different stages of triggers are equal or not; the method comprises the steps of receiving instruction information sent by an eFlash chip, filtering burrs of the instruction information, determining the type and data operation time of an eFlash IP by utilizing configuration information in an IP mode register after circuit decoding is carried out on the instruction information, and realizing data processing based on the type and the data operation time. The anti-interference performance and the compatibility of the NOR type flash memory chip are improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of storage technology, and particularly relates to a data processing method, apparatus, interface circuit, and chip. Background Art

[0002] As a core component for data storage, flash memory chips have the advantages of long data retention time, low power consumption, fast read and write speeds, etc., and play a crucial role in various electronic devices. Currently, the flash memory chips occupying the mainstream market are divided into two categories: NOR flash and NAND flash. Among them, NOR flash is widely used in the boot memories of embedded systems.

[0003] When a flash memory chip interacts with a microcontroller unit (MCU) for data, such as data reading and writing, the MCU generally controls the flash memory chip to perform various operations by inputting instructions. Specifically, the MCU sends instruction information to the flash memory chip, the interface circuit in the flash memory chip receives the instruction information, and after decoding the instruction information, it sends it to the embedded flash IP (eFlash IP) in the flash memory chip. The eFlash IP will complete data processing operations such as reading and writing. Among them, the eFlash IP is an embedded IP core or module for implementing the function of an external flash memory.

[0004] In practical applications, the eFlash IP and the interface circuit are vulnerable to the influence of noise coupling, power supply ripple, electromagnetic interference, etc. during signal transmission, resulting in glitches. The glitch interference not only affects the integrity of the data but may also cause system misoperations. Existing technologies usually use filter circuits to reduce signal noise, but in the face of high-frequency signals and complex interference environments, the filtering effect is limited. In addition, the eFlash IP has various different types, and the interface standards, communication protocols, and timing requirements of various types are all different, so the same interface circuit of the flash memory chip cannot be compatible with different types of eFlash IP.

[0005] Therefore, how to improve the anti-interference ability and compatibility of flash memory chips simultaneously is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] To solve the above problems, the present disclosure provides a data processing method, apparatus, interface circuit, and chip, aiming to improve the anti-interference ability and compatibility of flash memory chips.

[0007] To achieve the above object, the present disclosure mainly provides the following technical solutions: In a first aspect, the present disclosure provides a data processing method, which is applied to the interface circuit of a NOR flash memory chip and includes: Receive the instruction information sent by the microcontroller unit, where the instruction information includes an enable signal, as well as an address and data corresponding to the enable signal; Synchronize the enable signal, address, and data through an N-stage flip-flop sampling method, where N is an integer greater than or equal to 3; Filter out the glitches of the enable signal, address, and data by comparing whether the values of different-stage flip-flops are equal, and obtain the filtered enable signal, address, and data; Perform decoding according to the filtered enable signal, address, and data by combining a state machine and an indication bit signal, and respectively generate corresponding IP operation signals, IP addresses, and IP data; Based on the IP operation signal, determine the type and IP operation time of the embedded flash memory IP in the configuration information of the IP mode register, where the IP mode register is used to store relevant information of the embedded flash memory IP; Use the type of the embedded flash memory IP and the IP operation time to respectively input the IP operation signal, IP address, and IP data to each input port of the embedded flash memory IP, so that the embedded flash memory IP realizes data processing operations.

[0008] In a second aspect, the present disclosure provides a data processing device applied to a NOR flash memory chip interface circuit, and the device includes: A receiving unit for receiving the instruction information sent by the microcontroller unit, where the instruction information includes an enable signal, as well as an address and data corresponding to the enable signal; A synchronization unit for synchronizing the enable signal, address, and data through an N-stage flip-flop sampling method, where N is an integer greater than or equal to 3; A filtering unit for filtering out the glitches of the enable signal, address, and data by comparing whether the values of different-stage flip-flops are equal, and obtaining the filtered enable signal, address, and data; A decoding unit for performing decoding according to the filtered enable signal, address, and data by combining a state machine and an indication bit signal, and respectively generating corresponding IP operation signals, IP addresses, and IP data; A determination unit for determining the type and IP operation time of the embedded flash memory IP in the configuration information of the IP mode register based on the IP operation signal, where the IP mode register is used to store relevant information of the embedded flash memory IP; Use the type of the embedded flash memory IP and the IP operation time to respectively input the IP operation signal, IP address, and IP data to each input port of the embedded flash memory IP, so that the embedded flash memory IP realizes data processing operations.

[0009] On the other hand, the present disclosure also provides a NOR flash chip interface circuit, characterized in that the interface circuit is used to execute the method of the first aspect.

[0010] On the other hand, the present disclosure also provides a NOR flash chip, characterized in that the flash chip includes an interface circuit and an embedded flash IP, and the interface circuit is used to execute the method of the first aspect.

[0011] On the other hand, the present disclosure also provides a storage medium for storing a computer program, wherein when the computer program runs, it controls the device where the storage medium is located to execute the method of the first aspect described above.

[0012] On the other hand, the present disclosure also provides an electronic device, which includes at least one processor, at least one memory connected to the processor, and a bus; wherein the processor and the memory complete communication with each other through the bus; the processor is used to call program instructions in the memory to execute the method of the first aspect as described above.

[0013] Compared with the prior art, the present disclosure has the following advantages: The NOR flash chip interface circuit of the present disclosure receives instruction information sent by the MCU, synchronizes each instruction information through an N-stage flip-flop sampling method, and compares whether the values of different-stage flip-flops are equal one by one to filter out the glitches of the instruction information. After decoding the instruction information, using the configuration information in the IP mode register, the type and data operation time of the eFlash IP are determined, and data processing is realized based on this type and this data operation time. The interface circuit of the present disclosure not only filters out the glitches in the signal, but also is compatible with different types of eFlash IP, and the present disclosure improves the anti-interference performance and compatibility of the flash chip.

[0014] Other features and advantages of the present disclosure will be described in the subsequent specification, and, in part, will be obvious from the specification, or will be understood by implementing the present disclosure. The objectives and other advantages of the present disclosure can be realized and obtained through the structures pointed out in the specification, the claims, and the drawings. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1Shows a schematic structural diagram of a NOR flash chip interface circuit according to an embodiment of the present disclosure; Figure 2 Shows a schematic flowchart of a data processing method according to an embodiment of the present disclosure; Figure 3 Shows a glitch-free write cycle timing diagram; Figure 4 Shows a write cycle timing diagram with glitches; Figure 5 Shows a write cycle timing diagram with glitch filtering according to an embodiment of the present disclosure; Figure 6 Shows a handshake feedback type IP writing operation timing diagram according to an embodiment of the present disclosure; Figure 7 Shows a time-controlled steady state type IP writing operation timing diagram according to an embodiment of the present disclosure; Figure 8 Shows a schematic flowchart of glitch filtering according to an embodiment of the present disclosure; Figure 9 Shows a schematic structural diagram of a data processing device according to an embodiment of the present disclosure. Detailed implementation manners

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0018] Existing flash chips are difficult to meet the requirements for memories in modern application systems such as rail transit and train control systems. The requirements are specifically reflected in two aspects. One is the demand for anti-interference signal communication, and the other is the demand for compatibility with various types of eFlash IP.

[0019] Regarding the anti-interference requirement, in existing electronic application systems, flash chips often need to work in cooperation with MCUs, static random-access memories (SRAMs), etc. Their signal communication is easily affected by aspects such as noise coupling, power supply ripple, and electromagnetic interference, resulting in glitches. Existing technologies often use traditional filter circuits to reduce signal noise. This method has limited filtering effects in high-frequency signals and complex interference environments and may introduce additional time delays, increasing unnecessary overheads. Modern application systems require flash chips to have strong anti-glitch interference capabilities to ensure fast and stable signal communication.

[0020] In terms of the requirement of being compatible with multiple types of eFlash IP, modern application systems usually need to support multiple different types of eFlash IP to meet different application scenarios and performance requirements. Different types of eFlash IP include, for example, handshake feedback type eFlash IP and time-controlled steady state type eFlash IP. The handshake feedback type eFlash IP has a signal interface indicating the internal busy state, which can perform handshake feedback on the signals of the interface circuit. The IP control circuit of the flash memory chip can determine whether the current operation (such as write, erase operation, etc.) is completed by monitoring this signal; Another type of time-controlled steady state type eFlash IP has no interface for status indication, and the IP control circuit of the flash memory chip needs to calculate regularly whether the current operation is completed. Moreover, there are also differences in the interface timing requirements of the two types of eFlash IP for the input of the interface circuit. Therefore, it is difficult to support multiple types of eFlash IP, which brings challenges to the design and integration of application systems, limits the flexibility and scalability of application systems, and is not conducive to the extended development of complex systems.

[0021] Therefore, modern application systems urgently need a flash memory chip that can be compatible with multiple eFlash IP and accurately filter out glitch interference. Based on this, the embodiments of the present disclosure provide a NOR type flash memory chip interface circuit, which is a sequential logic circuit and can connect an asynchronous MCU and eFlash IP. As Figure 1 shown, the NOR type flash memory chip interface circuit in the embodiments of the present disclosure receives instruction information from the MCU. The instruction information specifically includes enable signals such as chip select enable, output enable, write enable, etc. and the corresponding addresses and data. After synchronous processing, the occurrence and propagation of metastability are reduced; each stabilized instruction information is then subjected to glitch filtering to eliminate the influence of high and low level glitches on the signal logic; Then, a state machine and an indication bit signal are combined to perform instruction decoding to quickly process the instruction information. Then, IP control is performed according to the configuration information of the IP mode register to be compatible with different types of eFlash IP, and finally, clear IP operation signals such as write and erase and their addresses and data are sent to the flash memory storage unit. It should be noted that when the MCU reads the addresses and control signals of the flash memory chip, they also go through similar synchronous and glitch filtering processes and then are sent to the interface circuit. Then, the interface circuit obtains specific data from the flash memory storage unit to complete the reading process of the flash memory chip.

[0022] Correspondingly, the embodiments of the present disclosure provide a data processing method applied to a NOR type flash memory chip interface circuit. As Figure 2 shown, the data processing method in the embodiments of the present disclosure includes: 101. Receive instruction information sent by a microcontroller unit, where the instruction information includes enable signals, and addresses and data corresponding to the enable signals.

[0023] Among them, the instruction information is used to instruct the flash memory chip to execute corresponding instruction operations. The enable signal enables operations such as reading, writing, sector erasing, full-chip erasing, erase pause, erase resume, bypass writing, etc.

[0024] In this step, the interface circuit receives the instruction information sent by the MCU, causing the interface circuit to execute corresponding data operations. For example, if the instruction information instructs to write data to the flash memory chip, the instruction information includes write enable, as well as the corresponding address and data. It should be noted that if the instruction information instructs to read data from the flash memory chip, the instruction information only includes read enable and the corresponding read address, and the address is not included in the instruction information.

[0025] 102. Synchronize the enable signal, address, and data through the N-stage flip-flop sampling method.

[0026] Among them, N is an integer greater than or equal to 3.

[0027] Since the clocks of the MCU and the interface circuit are usually not synchronized, in the embodiments of the present disclosure, the enable signal, address, and data are synchronized respectively through the N-stage flip-flop sampling method to eliminate the metastability impact of external asynchronous signals.

[0028] 103. Filter the glitches of the enable signal, address, and data by comparing whether the values of different-stage flip-flops are equal, and obtain the filtered enable signal, address, and data.

[0029] Among them, different-stage flip-flops refer to other different-stage flip-flops except the first-stage flip-flop. For example, when N = 4, different-stage flip-flops refer to the second-stage flip-flop and the third-stage flip-flop, or the third-stage flip-flop and the fourth-stage flip-flop, or the second-stage flip-flop or the fourth-stage flip-flop, or the second-stage flip-flop, the third-stage flip-flop, and the fourth-stage flip-flop. The filtered enable signal, address, and data are the stable enable signal, address, and data after filtering out the glitch interference.

[0030] Since the flash memory chip needs to receive the instruction information sent by the MCU in a timely manner, usually the instruction information in each cycle needs to be recorded by means of register latching. The following takes the write cycle as an example for specific description. The write cycle timing without glitches is as Figure 3 shown. In the present disclosure, the address Addr is latched to Addr_vld at the falling edge of the enable signal Enable, and the data Data_vld is continuously updated during the period when Enable is low, and the update stops and the data is latched at the rising edge of the enable signal.

[0031] However, the glitch interference that may exist in the enable signal will affect the specific information latched, as Figure 4As shown, the enable signal Enable may generate glitches due to external electromagnetic interference or other influences, and cause fluctuations in the address and data at this time, which may lead to latching of incorrect addresses or data. Specifically, a glitch occurs in the enable signal Enable when it is at a low level. At the moment when the glitch occurs, the glitch affects the address and data respectively. Since the address is latched when the falling edge of the enable signal Enable arrives, after the glitch of the enable signal Enable appears and at the falling edge of the glitch, the address will be latched again, resulting in the incorrect address glitch addr being latched to Addr_vld.

[0032] Embodiments of the present disclosure can filter out glitches in the enable signal, address, and data one by one by comparing whether the values of the Nth-stage and (N - 1)th-stage flip-flops are equal, and obtain the filtered enable signal, address, and data. Exemplarily, when N = 4, it is possible to first determine whether the values of the 4th-stage flip-flop and the 3rd-stage flip-flop of the enable signal are equal; if they are not equal, it indicates that the enable signal is unstable, and the enable signal is discarded, and the enable signal of the next cycle is received for judgment. If they are equal, it indicates that the enable signal is stable. Then, when a specific edge of the enable signal arrives, by comparing whether the values of the 4th-stage flip-flop and the 3rd-stage flip-flop of the address are equal, it is determined whether the corresponding data is stable, and by comparing whether the values of the 4th-stage flip-flop and the 3rd-stage flip-flop of the data are equal, it is determined whether the corresponding address is stable. Embodiments of the present disclosure can ensure that the signal is stable for at least 3 clock cycles through the above comparison and judgment, so as to latch the accurate address and data. The specific edge is, for example, the falling edge or the rising edge. The stable enable signal is the filtered enable signal, and the latched address and data are the filtered address and data.

[0033] Embodiments of the present disclosure effectively filter out glitch interference in the signal transmission process at a relatively small timing cost. The timing of the write cycle after glitch filtering is shown in Figure 5. After a certain delay, the high-level glitch is filtered out, and a stable enable signal Enable_rg is obtained. Based on the stable enable signal Enable_rg, the accurate address and data can be latched. Embodiments of the present disclosure avoid communication errors caused by signal glitches through the latched accurate address Addr_vld and data Data_vld, ensuring the accuracy of data transmission.

[0034] 104. According to the filtered enable signal, address, and data, perform decoding by combining a state machine and an indication bit signal to generate corresponding IP operation signals, IP addresses, and IP data respectively.

[0035] Among them, the state machine is the main part of the decoding circuit in the flash memory chip, and instruction recognition is achieved by controlling state jumps in the state machine. The indication bit signal is used to indicate certain special states, such as the erase pause state indication bit, the bypass write mode indication bit, the user information query indication bit, etc. The indication bit signal records different special states that the decoding circuit is in, and combines with the state machine to jointly control the decoding process and implement the processing of complex instructions. The IP operation signal, IP address, and IP data in the embodiments of the present disclosure are respectively the operation signal, address, and data input to the input port of the eFlash IP. The operation signal is used to indicate the specific operation to be performed by the eFlash IP, and the specific operations include writing, erasing, etc.

[0036] In an implementable manner, the specific methods for generating the IP operation signal, IP address, and IP data are as follows: Step 1: Based on the filtered enable signal, perform state jumps of the state machine according to the filtered address and data.

[0037] Step 2: Use the indication bit signal to respectively generate the corresponding IP operation signal, IP address, and IP data after the last instruction cycle of the instruction information is recognized.

[0038] Since the instruction information sent by the MCU is a multi-cycle instruction, the corresponding address and data need to be sent in several consecutive cycles. Whenever the decoding circuit receives a stable instruction information from the MCU, the state machine will jump according to the specific address and data of the instruction, and generate an operation indication signal indicated by the instruction information after a complete instruction information is recognized, and send the operation indication signal to the eFlash IP. The operation indication signal includes the IP operation signal, IP address, and IP data. In the embodiments of the present disclosure, the specific timing of sending the operation indication signal is determined by the IP mode register and can be adjusted according to different types of IP.

[0039] 105. Determine the type and IP operation time of the eFlash IP in the configuration information of the IP mode register based on the IP operation signal.

[0040] Among them, the IP mode register is used to store relevant information of the eFlash IP. When the type of the eFlash IP is time-controlled steady state type, the IP operation time is the time for the eFlash IP to perform the corresponding operation. When the type of the eFlash IP is handshake feedback type, the IP operation time is the timeout time for the eFlash IP to perform the corresponding operation.

[0041] The decoding circuit includes an IP control circuit in addition to the state machine. The IP control circuit in the embodiments of the present disclosure is a configurable control circuit, which can be flexibly configured and adjusted in the IP mode register according to the interface protocols and timing requirements of different eFlash IPs. Through flexible configuration and adjustment, the embodiments of the present disclosure can be compatible with a variety of different types of eFlash IPs, so as to reduce the complexity and cost during system integration. Specifically, the embodiments of the present disclosure can configure a series of IP mode registers to achieve the output of timing signals for different types of eFlash IPs, thereby controlling the operation of different eFlash IPs.

[0042] Exemplarily, the IP mode registers in the embodiments of the present disclosure are specifically shown in Table 1. Among them, the ip_mode register represents the working type of the eFlash IP, that is, the type of the eFlash IP. ip_mode = 0 represents the handshake feedback type, and ip_mode = 1 represents the time-controlled steady state type. The ip_pg_time register represents the write operation time of the eFlash IP. The meaning of this time is different in different types of eFlash IPs. In the time-controlled steady state type eFlash IP, this time is the time required for the eFlash IP to execute this operation. After this number of clock cycles, the eFlash IP completes this operation, the interface circuit removes the write operation signal and the corresponding address and data on the input port of the eFlash IP, and the decoding state machine jumps back to the initial state. At the same time, it is allowed to receive new write operation signals and the corresponding address and data sent by the MCU side. In the handshake feedback type eFlash IP, this time is the timeout protection time of the interface circuit. The interface circuit will continuously monitor the output port of the eFlash IP within this number of clock cycles, waiting to receive the feedback signal indicating the completion of the eFlash IP operation. Only after successfully receiving the feedback signal does it indicate the completion of this operation. If the feedback signal is not received within the predetermined time (IP write timeout time), it means that the IP operation times out, and the decoding state machine jumps back to the initial state. The ip_se_time and ip_ce_time respectively represent the sector erase time and the full chip erase time of the eFlash IP, and their meanings in different types of eFlash IPs are similar to those of ip_pg_time, which will not be elaborated here.

[0043]

[0044] Table 1 IP Mode Registers In this step, obtain the value in the ip_mode register to determine the type of the eFlash IP, and based on the generated IP operation signal and the type of the eFlash IP, determine the IP operation time in the IP mode register. For example, if ip_mode = 0 and the IP operation signal is the IP full-chip erase operation signal, then obtain the value in the ip_ce_time register, which is the IP full-chip erase operation timeout time.

[0045] After determining the type of the eFlash IP and the corresponding IP operation time, the type of the eFlash IP and the IP operation time can be used to input the IP operation signal, IP address, and IP data to the respective input ports of the eFlash IP, so that the eFlash IP can perform data processing operations.

[0046] 106. If the type of the eFlash IP is handshake feedback type, then after inputting the IP operation signal, IP address, and IP data to the respective input ports of the eFlash IP, monitor the feedback signal of the output port of the eFlash IP within the IP operation time.

[0047] Among them, the feedback signal is used to indicate that the eFlash IP has completed the data processing operation.

[0048] When the IP control circuit of the present disclosure embodiment determines that the type of the eFlash IP is handshake feedback type, after inputting the IP operation signal, IP address, and IP data to the respective input ports of the eFlash IP, it will monitor the feedback signal of the output port of the eFlash IP within the IP operation time.

[0049] Exemplarily, as Figure 6 shown, when the decoding circuit parses an instruction for writing to the eFlash IP once, set the write operation enable signal of the eFlash IP, and input the corresponding IP write operation signal Prog, as well as the corresponding ip addr and ip data, to the respective input ports of the eFlash IP. After receiving the IP write operation signal Prog, ipaddr, and ip data, the eFlash IP starts to write data and sets the busy indication bit to indicate that the eFlash IP is performing a write operation. After the eFlash IP completes the operation, the busy indication bit is reset. After receiving the feedback signal of the reset of the busy indication bit, the IP control circuit immediately cancels the IP write operation signal Prog, ip addr, and ip data on the input port of the eFlash IP, and prepares to receive the next new IP operation signal, as well as the corresponding IP address and IP data.

[0050] It should be noted that if no feedback signal is received within the IP operation time, the state machine jumps back to the initial state, and the IP operation signals, IP addresses, and IP data on each input port are revoked to receive the next instruction information.

[0051] 107. If the type of the eFlash IP is time-controlled steady-state type, when inputting the IP operation signal, IP address, and IP data to each input port of the eFlash IP respectively, start the timer, and after the timer count reaches the IP operation time, stop inputting the IP operation signal, IP address, and IP data, so as to implement data processing operations through the eFlash IP.

[0052] Since the time-controlled steady-state type eFlash IP does not have a busy indication bit representing the internal working state, the embodiments of the present disclosure use the IP operation time for timing to control the corresponding operations of the eFlash IP according to the IP operation time.

[0053] Exemplarily, as Figure 7 shown, the IP control circuit inputs the IP write operation signal Prog, and the corresponding ip addr and ip data to each input port of the eFlash IP respectively, and starts timing internally. When the counter counts to the predetermined value stored in the ip_pg_time register, the IP control circuit revokes the IP write operation signal Prog, ip addr, and ip data to indicate that this write operation is completed and is ready to receive new IP operation signals, and the corresponding IP addresses and IP data.

[0054] The interface circuit of the embodiments of the present disclosure can stably input operation enable and corresponding address, data, etc. information when the eFlash IP is working in two configuration modes (handshake feedback type and time-controlled steady-state type). The embodiments of the present disclosure ensure the integrity and effectiveness of the write and erase processes, and terminate the operations according to signal feedback or internal timing, avoiding the hidden danger of the interface circuit paralysis caused by potential internal errors of the eFlash IP. In addition, the embodiments of the present disclosure provide strong support for the development of high-performance embedded systems by controlling the operation of different types of eFlash IP.

[0055] In order to more specifically illustrate a data processing method proposed by the present disclosure, the process of the interface circuit filtering signal glitches is described in detail below, as Figure 8 shown, this step is specifically: The interface circuit receives an externally input signal. The externally input signal is, for example, instruction information sent by an MCU. The instruction information includes an enable signal, an address, and data. The interface circuit first synchronizes the enable signal, the address, and the data respectively through N - stage flip - flops. Then, it determines whether each piece of instruction information is stable one by one. Specifically, it first compares whether the values of the N - th stage flip - flop and the (N - 1) - th stage flip - flop of the enable signal are equal to determine whether the enable signal is stable. If it is not stable, it continues to judge the stability of the next enable signal. If it is stable, it detects the falling edge of the enable signal. When the falling edge of the enable signal arrives, it compares whether the values of the N - th stage flip - flop and the (N - 1) - th stage flip - flop of the address are equal. If they are not equal, it continues to judge the stability of the next address signal until a stable address is waited for and then latches the address. If they are equal, it directly latches the address, and then detects the rising edge of the enable signal. When the rising edge of the enable signal arrives, it latches the stable data by judgment. The specific judgment process is similar to the execution steps of the address and will not be elaborated here.

[0056] In an implementable manner, the steps of filtering signal glitches are as follows: Judge whether the values of the 3 - rd stage flip - flop and the 2 - nd stage flip - flop of the enable signal are equal; if they are not equal, discard the enable signal; if they are equal, when the falling edge of the enable signal arrives, judge whether the values of the 3 - rd stage flip - flop and the 2 - nd stage flip - flop of the address are equal; if they are equal, latch the address, and when the rising edge of the enable signal arrives, filter the glitches of the data by comparing the values of the 3 - rd stage flip - flop and the 2 - nd stage flip - flop of the data; if they are not equal, discard the address.

[0057] The edge - latch - based glitch filtering method of the interface circuit in the embodiments of the present disclosure effectively ensures the stability and accuracy of the instruction information, enhances the anti - glitch interference ability of the NOR - type flash memory chip; and since the embodiments of the present disclosure only latch the corresponding address and data at the edges of the enable signal, it also greatly reduces the strict requirements for signal timing and pulse width. In addition, compared with using too many stages of flip - flops, the embodiments of the present disclosure can reduce the probability of metastability under the premise that the system performance is not affected (synchronizing too many flip - flops will reduce the system performance) by using 3 - stage flip - flops.

[0058] Based on the above - mentioned method, the embodiments of the present disclosure provide a data processing device, which is used to improve the anti - interference ability and compatibility of the flash memory chip. The embodiments of the device correspond to the foregoing method embodiments. For the convenience of reading, the details in the foregoing method embodiments will not be elaborated one by one in this embodiment, but it should be clear that the device in this embodiment can correspondingly implement all the contents in the foregoing method embodiments. Specifically as Figure 9 shown, applied to the interface circuit of the NOR - type flash memory chip, the device includes: A receiving unit 31, configured to receive instruction information sent by a microcontroller unit, where the instruction information includes an enable signal, as well as an address and data corresponding to the enable signal; A synchronization unit 32, configured to synchronize the enable signal, the address, and the data through an N-stage flip-flop sampling method, where N is an integer greater than or equal to 3; A filtering unit 33, configured to filter out glitches of the enable signal, the address, and the data by comparing whether the values of different-stage flip-flops are equal, and obtain the filtered enable signal, address, and data; A decoding unit 34, configured to perform decoding according to the filtered enable signal, address, and data by combining a state machine and an indication bit signal, and respectively generate corresponding IP operation signals, an IP address, and IP data; A determination unit 35, configured to determine the type and IP operation time of an embedded flash memory IP based on the IP operation signal in configuration information of an IP mode register, where the IP mode register is used to store relevant information of the embedded flash memory IP; An output unit 36, configured to input the IP operation signal, the IP address, and the IP data to respective input ports of the embedded flash memory IP by using the type of the embedded flash memory IP and the IP operation time, so that the embedded flash memory IP implements a data processing operation.

[0059] Further, the output unit includes: A monitoring module, configured to, if the type of the embedded flash memory IP is a handshake feedback type, monitor a feedback signal of an output port of the embedded flash memory IP within the IP operation time after inputting the IP operation signal, the IP address, and the IP data to respective input ports of the embedded flash memory IP, where the feedback signal is used to indicate that the embedded flash memory IP has completed a data processing operation; A counting module, configured to, if the type of the embedded flash memory IP is a time-controlled fixed state type, start a timer when inputting the IP operation signal, the IP address, and the IP data to respective input ports of the embedded flash memory IP, and stop inputting the IP operation signal, the IP address, and the IP data after the timer count reaches the IP operation time, so as to implement a data processing operation through the embedded flash memory IP.

[0060] Further, the monitoring module is specifically configured to: If the feedback signal is not received within the IP operation time, the state machine jumps back to the initial state.

[0061] Further, the monitoring module is also specifically configured to: Cancel the IP operation signal, the IP address, and the IP data on each input port, so as to receive the next instruction information.

[0062] Further, the filtering unit includes: A judgment module, configured to judge whether the values of the Nth-stage flip-flop and the (N-1)th-stage flip-flop of the enable signal are equal; A filtering module, configured to, if the judgment module judges that they are equal, filter out the glitches of the address and the data when a specific edge of the enable signal arrives, so as to obtain a filtered enable signal, address, and data; A discarding module, configured to, if the judgment module judges that they are not equal, discard the enable signal.

[0063] Further, the filtering module is specifically configured to: When a falling edge of the enable signal arrives, judge whether the values of the Nth-stage flip-flop and the (N-1)th-stage flip-flop of the address are equal; If they are equal, latch the address, and when a rising edge of the enable signal arrives, filter out the glitches of the data by comparing the values of the Nth-stage flip-flop and the (N-1)th-stage flip-flop of the data; If they are not equal, discard the address.

[0064] Further, N is equal to 3.

[0065] Further, the decoding unit includes: Based on the filtered enable signal, perform state transition of a state machine according to the filtered address and data; Using an indication bit signal, after recognizing the last instruction cycle of the instruction information, respectively generate corresponding IP operation signals, IP addresses, and IP data; Further, the IP operation time is the number of clock cycles.

[0066] Further, the enable signal is used to indicate one of data reading, writing, sector erasing, whole-chip erasing, erase pause, erase resume, and bypass writing.

[0067] Further, the embodiments of the present disclosure further provide a NOR flash chip interface circuit, characterized in that the interface circuit is used to execute the above Figure 2 method described.

[0068] Further, the embodiments of the present disclosure further provide a NOR flash chip, characterized in that the flash chip includes an interface circuit and an embedded flash IP, and the interface circuit is used to execute the above Figure 2 method described.

[0069] Further, the embodiments of the present disclosure further provide a processor, and the processor is used to run a program, wherein when the program runs, it executes the aboveFigure 2 The method described in

[0070] Furthermore, an embodiment of the present disclosure also provides a storage medium for storing a computer program, wherein when the computer program runs, it controls the device where the storage medium is located to execute the above-mentioned Figure 2 The method described in

[0071] Furthermore, an embodiment of the present disclosure provides an electronic device, which includes at least one processor, at least one memory connected to the processor, and a bus; wherein, the processor and the memory complete communication with each other through the bus; the processor is used to call program instructions in the memory to execute the above-mentioned data processing method. The device herein can be a server, a PC, a PAD, a mobile phone, etc.

[0072] Furthermore, the present disclosure also provides a computer program product, which is adapted to execute a program for initializing the inspection method steps of the network device as described above when executed on a data processing device.

[0073] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A data processing method, characterized in that, Applied to the NOR flash chip interface circuit, the method includes: Receiving instruction information sent by a microcontroller unit, where the instruction information includes an enable signal, as well as an address and data corresponding to the enable signal; Synchronizing the enable signal, address, and data through an N-stage flip-flop sampling method, where N is an integer greater than or equal to 3; Filtering out glitches of the enable signal, address, and data by comparing whether the values of different-stage flip-flops are equal, to obtain filtered enable signal, address, and data; Performing decoding by combining a state machine and an indication bit signal according to the filtered enable signal, address, and data, respectively generating corresponding IP operation signals, IP addresses, and IP data; Based on the IP operation signal, determining the type and IP operation time of the embedded flash IP in the configuration information of the IP mode register, where the IP mode register is used to store relevant information of the embedded flash IP; Using the type of the embedded flash IP and the IP operation time, respectively inputting the IP operation signal, IP address, and IP data to each input port of the embedded flash IP, so that the embedded flash IP realizes data processing operations.

2. The method according to claim 1, wherein Using the type of the embedded flash IP and the IP operation time, respectively inputting the IP operation signal, IP address, and IP data to each input port of the embedded flash IP, so that the embedded flash IP realizes data processing operations, including: If the type of the embedded flash IP is handshake feedback type, after respectively inputting the IP operation signal, IP address, and IP data to each input port of the embedded flash IP, monitoring the feedback signal of the output port of the embedded flash IP within the IP operation time, where the feedback signal is used to indicate that the embedded flash IP has completed data processing operations; Or, If the type of the embedded flash IP is time-controlled steady state type, when respectively inputting the IP operation signal, IP address, and IP data to each input port of the embedded flash IP, starting a timer, and after the timer count reaches the IP operation time, stopping inputting the IP operation signal, IP address, and IP data, so as to realize data processing operations through the embedded flash IP.

3. The method according to claim 1, wherein Filtering out glitches of the enable signal, address, and data by comparing whether the values of different-stage flip-flops are equal, including: Judging whether the values of the Nth-stage flip-flop and the (N-1)th-stage flip-flop of the enable signal are equal; If they are equal, filtering out glitches of the address and the data when a specific edge of the enable signal arrives, to obtain filtered enable signal, address, and data; If they are not equal, discarding the enable signal.

4. The method according to claim 3, wherein Filtering out glitches of the address and the data when a specific edge of the enable signal arrives, including: When the falling edge of the enable signal arrives, judging whether the values of the Nth-stage flip-flop and the (N-1)th-stage flip-flop of the address are equal; If they are equal, latch the address, and when the rising edge of the enable signal arrives, filter out the glitches of the data by comparing the values of the Nth-stage flip-flop and the (N-1)th-stage flip-flop of the data; If they are not equal, discard the address.

5. The method according to claim 4, wherein N is equal to 3.

6. The method according to claim 1, characterized in that, According to the filtered enable signal, address, and data, perform decoding by combining a state machine and an indication bit signal to respectively generate corresponding IP operation signals, IP addresses, and IP data, including: Based on the filtered enable signal, perform state transitions of the state machine according to the filtered address and data; Using the indication bit signal, after recognizing the last instruction cycle of the instruction information, respectively generate corresponding IP operation signals, IP addresses, and IP data; Then after monitoring the feedback signal of the output port of the embedded flash memory IP, the method further includes: If the feedback signal is not received within the IP operation time, the state machine jumps back to the initial state.

7. The method according to claim 6, wherein After the state machine jumps back to the initial state, the method further includes: Cancel the IP operation signals, IP addresses, and IP data on each input port to receive the next instruction information.

8. The method according to claim 1, characterized in that, The IP operation time is the number of clock cycles.

9. The method according to claim 1, wherein The enable signal is used to indicate one of data reading, writing, sector erasing, chip erasing, erase pause, erase resume, and bypass writing.

10. A data processing device, characterized in that, Applied to the NOR flash memory chip interface circuit, the device includes: A receiving unit, configured to receive instruction information sent by a microcontroller unit, where the instruction information includes an enable signal, and an address and data corresponding to the enable signal; A synchronization unit, configured to synchronize the enable signal, address, and data by means of N-stage flip-flop sampling, where N is an integer greater than or equal to 3; A filtering unit, configured to filter out the glitches of the enable signal, address, and data by comparing whether the values of different-stage flip-flops are equal, and obtain the filtered enable signal, address, and data; A decoding unit, configured to perform decoding by combining a state machine and an indication bit signal according to the filtered enable signal, address, and data, and respectively generate corresponding IP operation signals, IP addresses, and IP data; A determination unit, configured to determine the type and IP operation time of the embedded flash memory IP in the configuration information of the IP mode register based on the IP operation signal, where the IP mode register is used to store relevant information of the embedded flash memory IP; An output unit, configured to input the IP operation signals, IP addresses, and IP data to each input port of the embedded flash memory IP by using the type of the embedded flash memory IP and the IP operation time, so that the embedded flash memory IP implements data processing operations.

11. The device according to claim 10, characterized in that, The output unit includes: A monitoring module, configured to, if the type of the embedded flash memory IP is handshake feedback type, after inputting the IP operation signals, IP addresses, and IP data to each input port of the embedded flash memory IP, monitor the feedback signal of the output port of the embedded flash memory IP within the IP operation time, where the feedback signal is used to indicate that the embedded flash memory IP has completed data processing operations; A counting module, which is configured to start a timer when the type of the embedded flash memory IP is time-controlled steady state, and stop inputting the IP operation signal, IP address, and IP data after the timer count reaches the IP operation time when inputting the IP operation signal, IP address, and IP data to each input port of the embedded flash memory IP respectively, so as to implement data processing operations through the embedded flash memory IP.

12. The device according to claim 10, characterized in that, The filtering unit includes: A judging module, which is configured to judge whether the values of the Nth-stage trigger and the (N-1)th-stage trigger of the enabling signal are equal; A filtering module, which is configured to filter out the glitches of the address and the data when a specific edge of the enabling signal arrives if the judging module judges that they are equal, so as to obtain the filtered enabling signal, address, and data; A discarding module, which is configured to discard the enabling signal if the judging module judges that they are not equal.

13. A NOR flash memory chip interface circuit, characterized in that The interface circuit is configured to execute the method according to any one of claims 1-9.

14. A NOR flash memory chip, characterized in that, The flash memory chip includes an interface circuit and an embedded flash memory IP, and the interface circuit is configured to execute the method according to any one of claims 1-9.

Images