Data transmission method, DMA controller, system on chip and storage medium

Abstract

The invention provides a data transmission method, a DMA controller, a system-on-chip and a storage medium, the method is applied to the DMA controller, the DMA controller comprises a plurality of doorbell processing engines and arbitration units connected with the doorbell processing engines, and the arbitration units are connected with the doorbell processing engines after acquiring a plurality of data doorbells. A plurality of doorbell processing engines in an idle state are identified in the doorbell processing engines, each data doorbell is sent to one doorbell processing engine in the idle state, and the doorbell processing engines in the idle state carry out data transmission according to the obtained data doorbells. According to the method, a plurality of doorbell processing engines in the idle state can process a plurality of data doorbells in parallel, and compared with the prior art that a DMA controller can process one data doorbell at a time only through one doorbell processing engine, the processing efficiency of the data doorbells can be effectively improved, and then the data transmission efficiency is improved; and practical application requirements are met.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a data transmission method, a DMA controller, a system on chip, and a storage medium. Background Art

[0002] Traditional DMA (Direct Memory Access) technology offloads data transfer tasks through hardware to reduce the CPU load. However, its implementation depends on device-specific interfaces and privileged software, resulting in limited compatibility in user-mode applications and multi-tenant virtualization scenarios. Although the SDXI (Smart Data Accelerator Interface) protocol solves the problems of virtualization support and multi-context management through a standardized interface, existing DMA controllers that support the SDXI protocol still lack the ability to process data in parallel, and the data transmission efficiency needs to be further improved. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a data transmission method, a DMA controller, a system on chip, and a storage medium, which are used to process data in parallel and improve the data transmission efficiency.

[0004] In a first aspect, this application provides a data transmission method applied to a DMA controller. The DMA controller includes a plurality of doorbell processing engines and an arbitration unit respectively connected to each doorbell processing engine. The method includes the following steps executed by the arbitration unit:

[0005] Obtain a plurality of data doorbells;

[0006] Identify a plurality of doorbell processing engines in an idle state;

[0007] Send each of the data doorbells to an idle doorbell processing engine, so that the idle doorbell processing engine performs data transmission according to the obtained data doorbell.

[0008] The data transmission method provided by this application is applied to a DMA controller. The DMA controller includes multiple doorbell processing engines and an arbitration unit respectively connected to each doorbell processing engine. After obtaining multiple data doorbells, the arbitration unit identifies multiple idle doorbell processing engines among each doorbell processing engine and sends each data doorbell to an idle doorbell processing engine. The idle doorbell processing engine performs data transmission according to the obtained data doorbell. Through this method, multiple idle doorbell processing engines can process multiple data doorbells in parallel. Compared with the prior art where a DMA controller can only process one data doorbell at a time through one doorbell processing engine, the processing efficiency of data doorbells can be effectively improved, thereby improving the data transmission efficiency and meeting the actual application requirements.

[0009] In an alternative implementation, the identifying multiple idle doorbell processing engines includes:

[0010] Obtaining the status information fed back by each of the doorbell processing engines, where the status information is used to indicate that the corresponding doorbell processing engine is in an idle state or an occupied state;

[0011] Identifying the idle doorbell processing engines according to the status information of each of the doorbell processing engines.

[0012] In this application, a specific implementation for identifying idle doorbell processing engines is provided. The idle doorbell processing engines can be accurately identified through the status information fed back by the doorbell processing engines. Since the status information is fed back by the doorbell processing engines themselves, the accuracy and reliability of the identification result can be ensured.

[0013] In an alternative implementation, the number of the idle doorbell processing engines is greater than the number of the data doorbells;

[0014] The sending each of the data doorbells to an idle doorbell processing engine includes:

[0015] Determining a target doorbell processing engine among the multiple idle doorbell processing engines according to a preset call order, so that each of the data doorbells corresponds to a target doorbell processing engine;

[0016] Sending each of the data doorbells to the corresponding target doorbell processing engine.

[0017] In this application, when it is determined that the number of doorbell processing engines in the idle state is greater than the number of data doorbells, the specific implementation of sending data doorbells to the doorbell processing engines is to select a target doorbell processing engine from multiple doorbell processing engines in the idle state according to a preset call order. This not only enables efficient synchronous processing of each data doorbell but also realizes an orderly call of the doorbell processing engines, which helps improve data transmission efficiency.

[0018] In an alternative embodiment, each of the doorbell processing engines corresponds to a device code.

[0019] The step of determining a target doorbell processing engine from multiple doorbell processing engines in the idle state according to a preset call order includes:

[0020] Taking the first N doorbell processing engines in the idle state as the target doorbell processing engines in ascending order of the device code, where N is equal to the number of data doorbells.

[0021] In this application, using the device code of the doorbell processing engine as the basis for formulating the preset call order can simplify the rule for formulating the preset call order by creating the preset call order using the information carried by the doorbell processing engine itself, making full use of the existing information and avoiding waste of software / hardware resources caused by setting additional information.

[0022] In an alternative embodiment, the number of doorbell processing engines in the idle state is less than or equal to the number of data doorbells.

[0023] The step of sending each data doorbell to a doorbell processing engine in the idle state includes:

[0024] Sending one doorbell data to each of the doorbell processing engines in the idle state respectively.

[0025] In this application, when it is determined that the number of doorbell processing engines in the idle state is less than or equal to the number of data doorbells, the specific implementation of sending data doorbells to the doorbell processing engines, that is, sending one data doorbell to each doorbell processing engine in the idle state respectively, can ensure that each doorbell processing engine in the idle state can receive a data doorbell, and then carry out the subsequent data transmission process, making full use of the doorbell processing engine resources and maximizing the data transmission efficiency.

[0026] In an alternative embodiment, when the number of doorbell processing engines in the idle state is less than the number of data doorbells, the method further includes:

[0027] In response to the feedback information, select a target data doorbell from at least one data doorbell to be processed, where the feedback information is used to indicate that the doorbell processing engine is in an idle state;

[0028] Send the target data doorbell to the doorbell processing engine that sent the feedback information.

[0029] In this application, after the doorbell processing engine completes the processing of a data doorbell, it actively reports the feedback information to ensure that it is in an idle state, so that the arbitration unit can timely determine the doorbell processing engine in an idle state and send the target data doorbell to it, thereby starting the next data transmission process and effectively improving the data transmission efficiency.

[0030] In a second aspect, this application provides a DMA controller, including: an arbitration unit and multiple doorbell processing engines, where,

[0031] The arbitration unit is respectively connected to each of the doorbell processing engines;

[0032] The arbitration unit is configured to execute the data transmission method described in any one of the first aspects of this application to provide data doorbells to the doorbell processing engines;

[0033] The doorbell processing engine is used to perform data transmission according to the obtained data doorbell.

[0034] In this application, the arbitration unit can parallelly process multiple data doorbells through multiple doorbell processing engines in an idle state. Compared with the prior art where the DMA controller can only process one data doorbell at a time through one doorbell processing engine, it can effectively improve the processing efficiency of data doorbells, thereby improving the data transmission efficiency and meeting the actual application requirements.

[0035] In an optional implementation manner, the DMA controller provided in the second aspect of this application further includes: a register control unit and a management engine, where,

[0036] The register management unit is respectively connected to the arbitration unit and the management engine;

[0037] The management engine is connected to the arbitration unit;

[0038] The register control unit is used to generate management doorbells and data doorbells according to the configuration information provided by the processor;

[0039] The management engine is used to process the management doorbells and generate data doorbells according to the management doorbells.

[0040] In this application, a register control unit and a management engine are further provided in the DMA controller. The management doorbell and the data doorbell are generated through the register control unit. The data doorbell is sent to the arbitration unit to achieve data transmission, and the management doorbell is sent to the management engine. The management engine can further generate a data doorbell according to the management doorbell, which is also used to achieve data transmission. The DMA controller provides data doorbells through multiple channels, which helps to improve the data transmission efficiency.

[0041] In an optional implementation manner, the DMA controller provided in the second aspect of this application further includes: a data encapsulation unit, where

[0042] the data encapsulation unit is respectively connected to the management engine and each of the doorbell processing engines;

[0043] the data encapsulation unit is used to encapsulate the data provided by the management engine and each of the doorbell processing engines into a message and send the message.

[0044] In this application, encapsulating the data into a message for sending through the data encapsulation unit can not only adapt to the existing data transmission mode, but also increase the amount of data sent in a single time when the data is encapsulated and sent, improving the data transmission efficiency. At the same time, it can also improve the security and reliability of data transmission to a certain extent.

[0045] In a third aspect, this application provides a system on a chip, including: a processor, a system bus, an address translation unit, a storage unit, and the DMA controller according to any one of the second aspects of this application, where

[0046] the processor, the address translation unit, and the storage unit are respectively connected to the system bus;

[0047] the DMA controller is connected to the address translation unit.

[0048] In a fourth aspect, this application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data transmission method according to any one of the first aspects of this application are implemented. Description of the Drawings

[0049] In order to more clearly illustrate the technical solutions of the embodiments of this application, the following will briefly introduce the drawings required to be used in the embodiments of this application. It should be understood that the following drawings only show some embodiments of this application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1Schematic diagram of an architecture of a DMA data transmission system provided by this application.

[0051] Figure 2 Schematic diagram of a structure of a DMA controller provided by this application.

[0052] Figure 3 Flowchart of a data transmission method provided by this application.

[0053] Figure 4 Schematic diagram of a structure of a system on chip provided by this application. Detailed implementation manners

[0054] Next, the technical solutions in the embodiments of this application will be described with reference to the accompanying drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0055] As described above, data can be transmitted through the DMA technology to offload the data transfer task by hardware. Such offloading can free up the CPU execution cycle, that is, reduce the CPU load. However, the existing implementation is mainly limited to privileged software and specific interfaces, which makes it challenging to use user-mode applications in a non-virtualized environment and almost impossible to use in a multi-tenant virtualized environment.

[0056] In recent years, the SDXI protocol proposed by the SNIA organization can achieve virtualization, so that based on this protocol, not only can data transmission between different address spaces in user mode be achieved, but also data transmission between address spaces among multiple users can be controlled and managed.

[0057] See Figure 1 As shown, in the DMA data transmission architecture implemented based on the SDXI protocol, there are three possible access paths. Access path ① represents the path for the CPU to scan the SDXI device. Through this path, each SDXI device mounted on the system bus can be identified, and the SDXI device is a component of the system on chip. Through access path ①, the CPU can perform initialization configuration on the SDXI device; access path ② is the access to memory during the operation of the SDXI device. Through the DMA controller configured inside the SDXI device, data transmission between different memory spaces can be achieved. The specific data transmission process will be elaborated in the subsequent content and will not be described in detail here; access path ③ is when the SDXI device needs to report an interruption after completing a certain task or during the operation process, then the interruption is reported to the interruption processing unit through this access path for processing.

[0058] Based on the above system architecture, the DMA controller supporting the SDXI protocol can overcome the dilemmas faced above and solve the problems of virtualization support and multi-context management. However, the inventors have found through research that since the DMA controller supporting the SDXI protocol is still in the initial stage of development, most of the internal DMA controllers only integrate a doorbell processing engine, which can only process one data doorbell at a time. In other words, the DMA controller provided by the related technology lacks the ability to process data in parallel, and the data transmission efficiency needs to be further improved.

[0059] To solve the above problems, the present application provides a DMA controller, including an arbitration unit and multiple doorbell processing engines. Refer to Figure 2 as shown, which is illustrated by n doorbell processing engines, where n≥2.

[0060] The arbitration unit is respectively connected to each doorbell processing engine. The arbitration unit adopts the data transmission method provided by the present application to provide data doorbells to multiple idle doorbell processing engines in each doorbell processing engine, so that the idle doorbell processing engines perform data transmission according to the obtained data doorbells, realizing parallel processing of doorbell data and improving data transmission efficiency. As for the specific execution process of the data transmission method provided by the present application, it will be elaborated in the subsequent content and will not be described in detail here.

[0061] In the present application, the doorbell processing engine supports the SDXI protocol. Based on this, the doorbell processing engine can also be called SDCM (SDXI DMA Control Module). Correspondingly, the management engine also supports the SDXI protocol and can be defined as SACM (SDXI Admin Control Module).

[0062] Furthermore, in Figure 2 the DMA controller provided in the illustrated embodiment further includes a register control unit and a management engine.

[0063] Specifically, the register control unit (Register Control Module, RCM) includes a register bank, a context control unit, and a doorbell control unit. In practical applications, the processor can access the registers in the register bank through the APB bus and complete the transmission of configuration information by writing registers, that is, configure each register in the register bank. The context control unit is respectively connected to the register bank, the doorbell control unit, and the management engine. The context control unit can generate management doorbells and data doorbells based on the configuration information in the register bank, send the management doorbells to the management engine, and send the data doorbells to the doorbell control unit. The doorbell control unit is connected to the arbitration unit and provides data doorbells to the arbitration unit.

[0064] The management engine is used to process the management doorbells provided by the register control unit and perform transaction processing related to the management doorbells. As for the specific processing process of the management doorbells, it can be implemented with reference to the related technologies and will not be elaborated here. Further, the management engine is also connected to the arbitration unit, generates data doorbells based on some management doorbells, and feeds them back to the arbitration unit. The specific process of the management engine providing data doorbells to the arbitration unit based on the management doorbells can also be implemented with reference to the related technologies and will not be elaborated here either.

[0065] Thus, it can be seen that in practical applications, the data doorbells received by the arbitration unit come from two sources, namely the doorbell control unit and the management engine. As mentioned above, after obtaining the data doorbells, the arbitration unit sends the data doorbells to the doorbell processing engine in the spatial state to achieve concurrent processing of the data doorbells.

[0066] Further, the DMA controller provided in this application further includes a data encapsulation unit.

[0067] Combined with Figure 2 As shown, the data encapsulation unit is respectively connected to the management engine and each doorbell processing engine. In practical applications, the data encapsulation unit encapsulates the data provided by the management engine and each doorbell processing engine into a message and sends the message to the processor. In Figure 2 In the shown example, the data encapsulation unit is connected to the AXI bus. Therefore, the data encapsulation unit encapsulates the obtained data into an AXI message for transmission. Of course, if the data encapsulation unit is connected to other forms of buses, it can also encapsulate the obtained data into a message that matches the format of the actual connected bus, which will not be elaborated one by one here.

[0068] As another alternative implementation, the DMA controller provided in this application further includes an error recording unit and an interrupt control unit. Combined with Figure 2 As shown, the error recording unit is connected to the data encapsulation unit. The error recording unit is used to store the error information of the management engine and any doorbell processing engine, and send the obtained error information to the data encapsulation unit, which is then encapsulated into a corresponding message and output. In practical applications, the message carrying the error information can be stored in a preset storage device, or directly sent to the processor, and the processor executes corresponding processing measures according to the obtained error information, such as sending an alarm message or executing a preset error handling logic, etc.

[0069] In practical applications, the management engine and the doorbell processing engine parse the obtained doorbells (including management doorbells and data doorbells) to obtain the pointer information in the doorbells, access the memory according to the pointer information, and obtain the corresponding descriptors. There are many types of descriptors, including interrupt descriptors. The management engine and any doorbell processing engine will generate multiple interrupts during the process of processing interrupt descriptors. The interrupt control unit converts the interrupts generated by the management engine and the doorbell processing engine into corresponding interrupt signals, and reports the interrupt signals to the processor in a preset order, so that the processor can respond to the interrupt signals and start the corresponding interrupt processing process.

[0070] Based on the above content, it can be seen that the external ports of the DMA controller provided in this application are relatively simple, mainly including a configuration port for receiving configuration information, a data transfer port for obtaining descriptors and transferring data, and an interrupt port for sending interrupt signals. As an alternative implementation, the configuration port can be implemented based on the APB (Advanced Peripheral Bus) bus port, the data transfer port can be implemented based on the AXI (Advanced eXtensible Interface) bus port, and the interrupt port can be implemented with reference to related technologies, which will not be elaborated here.

[0071] The following combines Figure 2 The overall architecture of the DMA controller shown to introduce the general process of data transfer by the DMA controller provided in this application. The specific implementation of the arbitration unit involved in executing the data transfer method provided in this application will be elaborated in detail in the subsequent content.

[0072] S11. The processor ( Figure 2 (not shown in the figure) initializes and configures the DMA controller through the APB bus, that is, performs a write operation on the register group of the register control unit (RCM), writes relevant configuration information, and starts the DMA controller after the configuration is completed. The context management unit accesses the registers to obtain the configuration information, controls the processing and stopping of the context (context) according to the obtained configuration information, and sends an administrative doorbell (Admin Doorbell, AdminDB) to the management engine (SACM), while the doorbell control unit issues data doorbells according to the started context. In an alternative implementation, considering the large number of data doorbells, a doorbell queue (Doorbell Queue, DB queue) can also be created to cache the data doorbells.

[0073] S12. The management doorbell is passed to the internal management engine for processing. The management engine obtains the corresponding descriptor according to the doorbell information (the doorbell information mainly includes some pointer information of the descriptor, and the management engine can access the descriptor through the pointer information), and executes the instructions of the corresponding descriptor according to the descriptor, such as starting the context, stopping the context, and updating the context, etc.

[0074] It should be noted that in practical applications, the management engine may generate corresponding data doorbells during the process of processing the management doorbell. Therefore, the management engine is also communicatively connected to the arbitration unit to provide the data doorbell to the arbitration unit.

[0075] S13. The arbitration unit obtains multiple data doorbells according to the preset arbitration logic, and respectively sends the obtained data doorbells to the doorbell processing engines in the idle state. The doorbell processing engines in the idle state can perform data transmission according to the obtained data doorbells. The data transmission method provided in this application is applied here to realize the synchronous processing of multiple data doorbells, thereby improving the data transmission efficiency. For the specific implementation of the preset arbitration logic and the specific processing process of the data doorbell, reference can be made to the relevant content in the subsequent data transmission method section.

[0076] S14. The error information generated during the operation of the management engine and the doorbell processing engine can be written into the memory according to requirements through the error recording unit. Specifically, the management engine and the doorbell processing engine are communicatively connected to the error recording unit ( Figure 2 not shown in the figure). The error recording unit can store the error information of the management engine and any doorbell processing engine, and send the obtained error information to the data encapsulation unit. The data encapsulation unit encapsulates it into the corresponding message and stores it in the memory.

[0077] It should be noted that whether it is a management doorbell or a data doorbell, both include pointer information for obtaining the descriptor. After the management engine and the doorbell processing engine parse the obtained doorbell to get the corresponding pointer information, they need to access the memory according to the obtained pointer information to obtain the corresponding descriptor, and access the memory according to the obtained descriptor to complete the corresponding data transmission operation. That is to say, the relevant content of the foregoing S2, S3, and S4 all involves accessing the memory. For this reason, a data encapsulation unit is also provided in the DMA controller provided in this application. The data encapsulation unit is used to encapsulate the data provided by the management engine and each doorbell processing engine into a message and send the message to the processor. In an optional implementation manner, the data encapsulation unit is connected to the AXI bus and encapsulates the obtained data into an AXI message for transmission. In practical applications, since the AXI bus supports outstanding, multiple AXI transactions can be initiated continuously. When the number of AXI transactions initiated by the DMA controller is equal to the outstanding number, the bandwidth of the AXI bus can be maximally utilized.

[0078] In summary, compared with the DMA controller in the related art that only sets one doorbell processing engine to process data doorbells one by one, in the DMA controller provided in this application, multiple doorbell processing engines are set, which can realize the parallel processing of data doorbells, thus significantly improving the data transmission efficiency.

[0079] Based on the specific composition of the above DMA controller, the specific execution process of the data transmission method provided in this application will be introduced below. The data transmission method provided in this application is executed by the arbitration unit. Refer to Figure 3 As shown, the data transmission method provided in this application includes the following steps.

[0080] S100. Obtain multiple data doorbells.

[0081] Based on Figure 2 As shown in the DMA controller hardware architecture, both the doorbell control unit and the management engine can provide data doorbells to the arbitration unit. Therefore, in practical applications, the arbitration unit can access the data doorbell queue maintained by the doorbell control unit or the data doorbell queue maintained by the management engine, and obtain multiple data doorbells from the corresponding data doorbell queue according to the preset arbitration logic. As mentioned above, the data doorbell mainly includes a context sequence number for indicating the context corresponding to the data doorbell, ID information related to address translation, and pointer information for indicating the descriptor storage address. Of course, the data doorbell can also include other information, which can be implemented with reference to the related art and will not be elaborated here one by one.

[0082] Based on the above content, as an optional implementation manner, the preset arbitration logic can be implemented based on the storage order of each data doorbell in the data doorbell queue, that is, according to the order in which the data doorbells are stored in the data doorbell queue, obtain the first m data doorbells in the data doorbell queue, where m≥2. In another optional implementation manner, a doorbell code can also be assigned to each data doorbell, and the preset arbitration logic is implemented based on the doorbell code. For example, multiple data doorbells can be obtained in the order of the doorbell code from large to small or from small to large. In another optional implementation manner, based on the urgency of the data doorbell being processed, the priorities of each data doorbell are configured, and the preset arbitration rule is formulated based on the priorities of the data doorbells. The arbitration unit can obtain multiple data doorbells in the order of the priorities from high to low. Of course, the arbitration unit can also use other preset arbitration logics to obtain multiple data doorbells, which will not be elaborated here one by one.

[0083] S110. Identify multiple doorbell processing engines in the idle state.

[0084] As described above, the DMA controller provided in this application includes multiple doorbell processing engines. Each doorbell processing engine can independently process data doorbells. In practical applications, it is possible that some doorbell processing engines are in an idle state and some are in an occupied state (i.e., data transmission is being performed based on the obtained data doorbells). Therefore, after obtaining multiple data doorbells, the arbitration unit first needs to identify the operating states of each doorbell processing engine and determine the doorbell processing engines in the idle state from them.

[0085] Combined with Figure 2 As shown, each doorbell processing engine is communicatively connected to the arbitration unit. Based on this, the arbitration unit can obtain the status information of each doorbell processing engine based on this connection relationship. Among them, the status information is used to represent that the corresponding doorbell processing engine is in an idle state or an occupied state, so as to identify the doorbell processing engines in the idle state according to the status information of each doorbell processing engine.

[0086] In an optional implementation manner, the arbitration unit and each doorbell processing engine are connected by a hard wire. If the arbitration unit determines that the hard wire corresponding to any doorbell processing engine is pulled low to a low level, it can be determined that the corresponding doorbell processing engine is in an idle state; on the contrary, if the arbitration unit determines that the hard wire corresponding to any doorbell processing engine is configured to a high level, it can be determined that the corresponding doorbell processing engine is in an occupied state. Based on this, the arbitration unit can identify the status of each doorbell processing engine by identifying the level of the hard wire corresponding to each doorbell processing engine.

[0087] S120: Send each data doorbell to a doorbell processing engine in an idle state, so that the doorbell processing engine in an idle state performs data transmission according to the obtained data doorbell.

[0088] After the arbitration unit identifies multiple doorbell processing engines in an idle state, it sends each data doorbell to a doorbell processing engine in an idle state, so that the doorbell processing engine in an idle state performs data transmission according to the obtained data doorbell. As described above, the data doorbell includes pointer information. After obtaining the data doorbell, the doorbell processing engine extracts the pointer information in the data doorbell, accesses the memory according to the pointer information to obtain the corresponding descriptor, and further completes the data transmission operation according to the obtained descriptor. As for the specific process of the doorbell processing engine performing data transmission according to the descriptor, it can be implemented with reference to related technologies and will not be elaborated here.

[0089] In practical applications, there are two possible relationships between the number of data doorbells and the number of doorbell processing engines in the idle state. One is that the number of doorbell processing engines in the idle state is greater than the number of the data doorbells. The other is that the number of doorbell processing engines in the idle state is less than or equal to the number of the data doorbells. Under different quantity relationships, the specific process of allocating data doorbells will vary. The following is a specific elaboration:

[0090] In one embodiment, the number of doorbell processing engines in the idle state is greater than the number of data doorbells. For example, there are 6 doorbell processing engines in the idle state, and the arbitration unit obtains 4 data doorbells. In this case, it means that not all doorbell processing engines in the idle state can be allocated a data doorbell. In other words, after sending the data doorbells, there are still some doorbell processing engines remaining in the idle state. Based on this, the arbitration unit can determine the target doorbell processing engine among multiple doorbell processing engines in the idle state according to the preset call order. It can be understood that in order to effectively improve the processing efficiency of doorbell data, the number of target doorbell processing engines should be equal to the number of data doorbells, so that each data doorbell corresponds to a target doorbell processing engine, and each data doorbell is sent to the corresponding target doorbell processing engine, and the target doorbell processing engine performs data transmission according to the obtained data doorbell.

[0091] In an alternative implementation, each doorbell processing engine corresponds to a device code. Based on this, the first N doorbell processing engines in the idle state can be used as the target doorbell processing engines in the order of increasing device code, where N is equal to the number of data doorbells.

[0092] In another alternative implementation, it is also possible to count the cumulative occupied time of each doorbell processing engine, and use the first N doorbell processing engines in the idle state as the target doorbell processing engines in the order of increasing cumulative time, so as to balance the load among the doorbell processing engines.

[0093] Furthermore, in another embodiment, the number of doorbell processing engines in the idle state is less than or equal to the number of data doorbells. For example, there are 4 doorbell processing engines in the idle state, and the arbitration unit obtains 6 data doorbells. In this case, it means that not all data doorbells can be allocated a doorbell processing engine for processing. Based on this, a doorbell data can be sent to each doorbell processing engine in the idle state respectively, so that each doorbell processing engine in the idle state can obtain a doorbell data and thus be converted into the occupied state, making full use of the hardware resources of the doorbell processing engines in the DMA controller and maximizing the data transmission efficiency.

[0094] As described above, there may still be some data doorbells that have not been processed in the above situation. Based on this, when any doorbell processing engine (currently in an occupied state) completes the data transmission process of a certain data doorbell (converted to an idle state), it sends feedback information indicating its idle state to the arbitration unit. For example, the hard wire connected to the arbitration unit mentioned above can be pulled low to a low level. In response to the obtained feedback information, the arbitration unit determines that there is currently a doorbell processing engine in an idle state, and further selects a target data doorbell from at least one data doorbell to be processed, and sends the target data doorbell to the doorbell processing engine that sent the feedback information, so that the doorbell processing engine can start processing the next data doorbell in a timely manner. After completing the processing of a data doorbell, the doorbell processing engine actively reports the feedback information to ensure that it is in an idle state, so that the arbitration unit can timely determine the doorbell processing engine in an idle state and send the target data doorbell to it, thereby starting the next data transmission process and effectively improving the data transmission efficiency.

[0095] In summary, in the related art, the DMA controller can only process one data doorbell at a time through one doorbell processing engine, and the data processing efficiency is low. Compared with the prior art, the data transmission method provided in this application is applied to the DMA controller, which includes multiple doorbell processing engines and an arbitration unit respectively connected to each doorbell processing engine. After obtaining multiple data doorbells, the arbitration unit identifies multiple doorbell processing engines in an idle state among each doorbell processing engine, and sends each data doorbell to a doorbell processing engine in an idle state. The doorbell processing engine in an idle state performs data transmission according to the obtained data doorbell. Through this method, multiple data doorbells can be processed in parallel by multiple doorbell processing engines in an idle state, which can effectively improve the processing efficiency of data doorbells, and then improve the data transmission efficiency to meet the actual application requirements.

[0096] Furthermore, this application also provides a system-on-chip, which includes a processor, a system bus, an address translation unit, a storage unit, and the DMA controller provided in the foregoing embodiments of this application.

[0097] See Figure 4As shown, the processor, address translation unit, and storage unit are respectively connected to the system bus. The DMA controller is connected to the address translation unit and is connected to the system bus through the address translation unit. In practical applications, the processor can access the storage unit through the system bus and write data to the storage unit. For example, descriptors can be created and maintained in the storage unit. Correspondingly, the processor can also read data from the storage unit. For example, in response to the status update of the descriptor, the data in the storage space corresponding to the descriptor can be obtained. Further, based on the address translation unit, the conversion between virtual addresses and physical addresses is implemented. The processor can also perform data interaction with the DMA controller through the address translation unit, such as identifying the DMA controller or performing initialization configuration on the DMA controller. Further, the DMA controller can also finally access the storage unit through the address translation unit and the system bus, and unload the data transfer task of the processor based on the DMA technology, so as to reduce the load of the processor. As for the specific process of the address translation unit implementing the conversion between virtual addresses and physical addresses to ensure the DMA data transfer of the system-on-chip, it can be implemented with reference to related technologies and will not be elaborated here.

[0098] It should be noted that the address translation unit is a hardware module of the system-on-chip. All external accesses of the DMA controller to the system bus need to go through this module for address translation. Of course, other modules in the system-on-chip can also share this address translation unit. As for the specific implementation of the address translation unit, it can be implemented with reference to related technologies and will not be elaborated here.

[0099] Next, taking the transfer of data in storage space 0 to storage space 1 as an example, in combination with the data transfer method provided in this application, a simple introduction will be given Figure 4 to the interaction process of each relevant component in the hardware structure of the DMA controller shown.

[0100] S21. The processor scans the devices mounted on the system bus and identifies the DMA controller. As mentioned above, in this process, the conversion between virtual addresses and physical addresses is implemented through the address translation unit to ensure that the processor can access the corresponding physical address according to the virtual address, so as to identify the DMA controller.

[0101] S22, the processor performs initialization operations, initializes the DMA controller, and divides the storage space for storing data in the storage unit, namely, storage space 0 and storage space 1. Specifically, the processor can directly access the storage unit through the system bus, and when initializing the DMA controller, it is necessary to use the address translation unit to convert between virtual addresses and physical addresses. At the same time, the processor creates descriptors corresponding to each storage space, writes the aforementioned configuration information into the register group in the DMA controller, and starts the DMA controller. Of course, in actual applications, the processor will also perform other related operations, which will not be described in detail here, and can be specifically implemented with reference to related technologies.

[0102] S23, the DMA controller starts working, generates corresponding doorbell data according to the configuration information, and searches for the descriptor in the memory according to the pointer information in the data doorbell according to the data transmission method provided by the present application, obtains the corresponding descriptor and performs the corresponding DMA data transmission operation. That is, the data in storage space 0 is read through the source address provided in the descriptor, and the read data is written into storage space 1 through the destination address provided in the descriptor, so as to realize the data copy from storage space 0 to storage space 1.

[0103] S24. After the data is transmitted, the interrupt control unit in the DMA controller sends an interrupt request to the processor.

[0104] S25. The processor receives the interrupt request signal and starts to execute the interrupt processing program and perform subsequent processing, such as checking whether the data is correct, whether to continue to use the DMA controller, etc.

[0105] Furthermore, in some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the data transmission method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0106] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the data transmission method according to various embodiments of the present application described in the above content of this specification.

[0107] A computer program product may be written in any combination of one or more programming languages for programming code to perform the operations of the embodiments of the present application. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The programming code may be executed entirely on a user computing device, partially on the user device, executed as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0108] Those skilled in the art can understand that the content disclosed in the present disclosure may have various variations and improvements. For example, the various devices or components described above may be implemented by hardware, or may be implemented by software, firmware, or some or all combinations of the three.

[0109] In addition, although the present disclosure makes various references to certain units in the system according to the embodiments of the present disclosure, any number of different units may be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method may use different units.

[0110] Flowcharts are used in the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily have to be carried out precisely in sequence. On the contrary, they may be carried out in reverse order or various steps may be processed simultaneously. At the same time, other operations may also be added to these processes.

[0111] Those of ordinary skill in the art can understand that all or part of the steps in the above methods can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium such as a read-only memory, etc. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, the various modules / units in the above embodiments can be implemented in the form of hardware or in the form of software function modules. The present disclosure is not limited to any specific form of combination of hardware and software.

[0112] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0113] The foregoing is a description of the present disclosure and should not be construed as limiting thereof. Although several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily appreciate that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing is a description of the present disclosure and should not be considered limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A data transmission method, characterized in that, Applied to a DMA controller, the DMA controller includes a plurality of doorbell processing engines and an arbitration unit respectively connected to each of the doorbell processing engines. The method includes the following steps performed by the arbitration unit: Obtain a plurality of data doorbells; Identify a plurality of doorbell processing engines in an idle state; Send each of the data doorbells to a doorbell processing engine in an idle state, so that the doorbell processing engine in the idle state performs data transmission according to the obtained data doorbell.

2. The data transmission method according to claim 1, wherein The identifying a plurality of doorbell processing engines in an idle state includes: Obtain the status information fed back by each of the doorbell processing engines, where the status information is used to represent that the corresponding doorbell processing engine is in an idle state or an occupied state; Identify the doorbell processing engines in an idle state according to the status information of each of the doorbell processing engines.

3. The data transmission method according to claim 1, wherein The number of doorbell processing engines in an idle state is greater than the number of data doorbells; The sending each of the data doorbells to a doorbell processing engine in an idle state includes: Determine a target doorbell processing engine among a plurality of doorbell processing engines in an idle state according to a preset call order, so that each of the data doorbells corresponds to a target doorbell processing engine; Send each of the data doorbells to the corresponding target doorbell processing engine.

4. The data transmission method according to claim 3, wherein Each of the doorbell processing engines corresponds to a device code; The determining a target doorbell processing engine among a plurality of doorbell processing engines in an idle state according to a preset call order includes: In the order of the device codes from small to large, take the first N doorbell processing engines in an idle state as the target doorbell processing engines, where N is equal to the number of data doorbells.

5. The data transmission method according to claim 1, wherein The number of doorbell processing engines in an idle state is less than or equal to the number of data doorbells; The sending each of the data doorbells to a doorbell processing engine in an idle state includes: Send one of the doorbell data to each of the doorbell processing engines in an idle state respectively.

6. The data transmission method according to claim 5, wherein The number of doorbell processing engines in an idle state is less than the number of data doorbells, and the method further includes: In response to the feedback information, select a target data doorbell from at least one data doorbell to be processed, where the feedback information is used to represent that the doorbell processing engine is in an idle state; Send the target data doorbell to the doorbell processing engine that sends the feedback information.

7. A DMA controller, characterized in that, Includes: An arbitration unit and a plurality of doorbell processing engines, where The arbitration unit is respectively connected to each of the doorbell processing engines; The arbitration unit is configured to execute the data transmission method according to any one of claims 1 to 6 to provide data doorbells to the doorbell processing engines; The doorbell processing engine is used to perform data transmission according to the obtained data doorbell.

8. The DMA controller according to claim 7, wherein Further includes: A register control unit and a management engine, where The register management unit is respectively connected to the arbitration unit and the management engine; The management engine is connected to the arbitration unit; The register control unit is used to generate management doorbells and data doorbells according to configuration information provided by a processor; The management engine is used to process the management doorbell and generate a data doorbell based on the management doorbell.

9. The DMA controller according to claim 8, wherein, It further includes: A data encapsulation unit, wherein, The data encapsulation unit is respectively connected to the management engine and each of the doorbell processing engines; The data encapsulation unit is used to encapsulate the data provided by the management engine and each of the doorbell processing engines into a message and send the message.

10. A system on a chip, characterized in that, It includes: A processor, a system bus, an address translation unit, a storage unit, and a DMA controller according to any one of claims 7 to 9, wherein, The processor, the address translation unit, and the storage unit are respectively connected to the system bus; The DMA controller is connected to the address translation unit.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the data transmission method according to any one of claims 1 to 6.

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