Verification method based on storage and calculation integrated chip network-on-chip NOC system

Abstract

The invention belongs to the technical field of storage and calculation integrated chips, and particularly relates to a verification method based on a network-on-chip NOC system of a storage and calculation integrated chip. Comprising the following steps: writing picture data into an NOC system through an AXI bus; the weight data is directly written into a FLASH digital model of each node in the NOC system through initialization; the configuration information of the register configures each node in the NOC system through an APB bus; in the NOC system simulation process, final data read through an AXI bus, an output result of each node participating in calculation and an intermediate result of each step of operators subjected to convolution, bias value adding, quantization, activation and pooling in each node are stored and output at the same time. According to the invention, neural network calculation under different models carried out by software can be quickly and effectively mapped to a hardware circuit of the NOC system, so that the function verification of the hardware circuit of the NOC system of the storage and calculation integrated chip is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of in-memory computing chips, and particularly relates to a verification method for a network-on-chip (NOC) system based on an in-memory computing chip. Background Art

[0002] In recent years, with the rapid development of the fields of computational science and information technology, and the rise of fields such as big data, artificial intelligence, and deep learning, people's demand for high-performance computing platforms has been increasing. The core idea of in-memory computing is to integrate the computing function and data storage, and the computing operation is directly executed in the memory, which greatly reduces the need for data transmission, thereby reducing the burden on the memory bandwidth and significantly improving the computing efficiency. Based on this, in-memory computing provides new possibilities for large-scale data processing in applications such as neural network computing, medical image processing, and the Internet of Things.

[0003] Although the performance of computers has been continuously improving with the progress of semiconductor technology, the speed difference between the memory and the processor has gradually widened, resulting in data transmission becoming a performance bottleneck. This memory wall limitation is widely known as the von Neumann bottleneck. The von Neumann computing architecture essentially faces the bottlenecks of the "memory wall" and the "power wall". In recent years, the slowdown of Moore's law has further exacerbated the above bottlenecks. The new in-memory computing chip technology, through the collaborative innovation of devices, architectures, circuits, and processes, integrates data storage and computing, greatly reducing data transfer and its overhead, and is regarded as one of the important technical directions for breaking through the von Neumann architecture bottleneck in the post-Moore era. At the same time, the in-memory computing chip achieves high computing power through large-scale parallel computing methods, which can alleviate the process scaling pressure to a certain extent, and has important strategic significance and application value for China to break through the computing power dilemma in the new round of artificial intelligence revolution. Summary of the Invention

[0004] The purpose of the present invention is to provide a verification method for a network-on-chip (NOC) system based on an in-memory computing chip. The present invention can quickly and effectively map the neural network computing under different models performed by software to the NOC system hardware circuit, so as to realize the hardware circuit function verification of the NOC system of the in-memory computing chip.

[0005] To solve the above technical problems, the present invention provides a verification method for a network-on-chip (NOC) system based on an in-memory computing chip, including: Inputting picture data, and writing the picture data into the NOC system through the AXI bus; Inputting weight data, and directly writing the weight data into the FLASH digital model of each node Node in the NOC system through initialization; Write the configuration information to the register, and configure each node Node in the NOC system through the APB bus with the configuration information of the register; Compare the intermediate results and the final output results, and save and output the final data read through the AXI bus, the output results of each node Node participating in the calculation, and the intermediate results after each operator of convolution, bias addition, quantization, activation, and pooling in each node Node during the NOC system simulation at the same time.

[0006] Preferably, the process of inputting the picture data includes: Train the neural network algorithm model; After the training is completed, print the used picture data and store it in a text file; the format of the text file is the width times the height lines of the picture data, and each line is a combination of 8-bit data of 16 channels; Declare an array at the top of the verification environment, use the language features of System Verilog to read the text file into the array, generate the corresponding AXI timing in the verification environment, and write the picture data to the NOC system through the AXI bus.

[0007] Preferably, the initialization process of the weight data includes: Train the neural network algorithm model; After the training is completed, print the weight information used by each node Node, that is, the different convolutional layers in the corresponding neural network calculation, and the number of weights used is related to the data width and height and the number of input and output channels of the current convolutional layer.

[0008] Preferably, each node Node includes a FLASH digital model for simulating the behavior of the FLASH device, and the scale of the FLASH digital model is 256 rows and 1152 columns, and the weight value is 8 bits.

[0009] Preferably, the training of the neural network algorithm model includes: Train the neural network algorithm model in the software platform MapTools; the neural network algorithm model includes ResNet, MobileNet, and object detection.

[0010] Preferably, according to the neural network algorithm model in the software platform MapTools, directly initialize the weight information to the corresponding FLASH digital model, that is, the row and column positions for placing the weights.

[0011] Preferably, the configuration process of the register includes: The configuration information of the registers is written through the APB bus. Each node is assigned a corresponding base address, and each register has its own corresponding offset address. The position and corresponding value of the registers of each node are determined by the base address and the offset address. Through a script and the software platform MapTools, the key information of the neural network algorithm model used by the software platform MapTools is mapped to the corresponding registers to generate two text files, namely an address file and a register value file, and the two are in one-to-one correspondence.

[0012] Preferably, by declaring an array at the top level of the verification environment and using the language features of System Verilog, the text files are read into the array, and the corresponding APB control timing is generated in the verification environment, and the configuration information of the registers is written into each corresponding node to implement the mapping of the neural network algorithm model.

[0013] Preferably, the key information includes: picture size, direction path of the routing network, data flow type, input and output channels, sliding window size, and sliding window step.

[0014] Preferably, there are 30 nodes inside the NoC system, with 6 nodes in each row and a total of 5 rows. The register configuration of each node occupies 32KB of space.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The method of the present invention is for the design of the NOC system of the in-memory computing chip, and a verification platform including four major components: picture data input, weight data input, register information writing, and comparison of intermediate results and final output results is built. The picture data is written through the AXI bus, the weight data is directly written into the FLASH digital model of each node in the NOC system through initialization, and the register configuration information configures each node in the NOC system through the APB bus. This method can complete the mapping of different neural network algorithm models by changing different input, weight, and register configuration information in the hardware circuit architecture of the in-memory computing chip NOC system, and can achieve comprehensive coverage of functions and effectively improve the verification efficiency. Description of the Drawings

[0016] Figure 1 is a flowchart of a verification method for a network-on-chip (NOC) system based on an in-memory computing chip provided by the present invention.

[0017] Figure 2 is a schematic diagram of the Node interconnection array in the NOC system provided by the present invention. Detailed Embodiments

[0018] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0019] As Figure 1 shown, the embodiment of the present invention specifically provides a verification method for a Network-on-Chip (NOC) system based on a memory-compute integrated chip. For the design of the NOC system of the in-memory computing chip, a verification platform including four major components: picture data input, weight data input, register information writing, and comparison of intermediate results and final output results is built. The picture data is written through the AXI bus, the weight data is directly written into the FLASH digital model of each node Node in the NOC system through initialization, and the register configuration information configures each Node in the NOC system through the APB bus respectively. Taking the input picture data of 32*32 as an example for detailed description.

[0020] The process of picture data input is as follows: After training the neural network algorithm models such as ResNet, MobileNet, and object detection in the self-developed software platform MapTools, save 32*32, that is, 1024 rows of picture data. Each row is a combination of 16-channel 8-bit data, that is, 128-bit data per row, and 1024 rows of 128-bit data. Through the AXI end as Figure 2 shown, it is input through the conversion of the AXI bridge (using the XBridge chip) and input to the first node Node in the upper left corner of the NOC system. When the data input meets the data required for a sliding window, this window starts corresponding convolution calculations, and at most 16-channel convolution sliding windows can be calculated simultaneously.

[0021] The process of weight initialization is as follows: After training the neural network algorithm models such as ResNet, MobileNet, and object detection in the self-developed software platform MapTools, print the weight information used by each Node, that is, for different convolution layers in the corresponding neural network calculation, the number of weights used is related to the data width and height of the current layer and the number of input and output channels. To improve the simulation speed and efficiency, each Node contains a FLASH digital model to simulate the behavior of the FLASH device, with a scale of 256 rows and 1152 columns. Therefore, the initialization of weights is to directly initialize the weight information to the corresponding row and column positions in the corresponding Node and the corresponding FLASH digital model for storing weights according to the algorithm model of the software.

[0022] The register configuration is through Figure 2Configure the shown APB0. There are 30 Nodes inside the NoC, with 6 Nodes in a row and a total of 5 rows. Each Node has an APB0 interface, and the configuration register of each Node occupies 32 KB of space. The specific operation of APB0 configuration is as follows: Divide the corresponding address space for the Output_Port of the selection circuit externally output by each Node. Connect the output signals of the distributor one and the distributor two to the APB0 interface inside each Node in sequence through the APB0 bus. The distributor one has a structure of 1 input and 2 outputs, and the distributor two has a structure of 1 input and 30 outputs. The register configuration is responsible through the APB0 interface, and write to each register of each Node one by one. Each Node is assigned a corresponding base address, and each register has its own corresponding offset address. The base address + offset address can determine the position and corresponding value of each register of each Node. The calculation result of the NoC system is output by selecting the 3 Nodes in the lower right corner. The register in the Output_Port of the selection circuit outside the NoC is responsible for determining the output information (i.e., information such as which Node and which virtual channel are selected). The APB0 bus outputs another signal to the register configuration circuit CFG_RF_NOC through the distributor one, and configures the register in the Output_Port of the selection circuit through the register configuration circuit CFG_RF_NOC. Each register in the Output_Port circuit is also assigned a corresponding address space. Through the MapTools tool jointly developed independently by the script, the key information of the algorithm model used by the software tool, such as the picture size, the direction path of the routing network, the type of data flow, the input and output channels, the size of the sliding window, the sliding window step, etc., can be mapped to the corresponding registers, generating two text files, one is the address information and the other is the information of the register value, and the two correspond one by one. By declaring an array at the top layer of the verification environment and using the language features of System Verilog, read the text files into the array, generate the corresponding APB control timing in the environment, and write the value of the configuration register into each corresponding Node to achieve the mapping of the network model.

[0023] To confirm the correctness of the circuit calculation result, it is necessary to record and compare the output result. The comparison process is to save and output the final data read through AXI during the simulation process of the NOC system, the output result of each Node participating in the calculation, and the intermediate result after each operator of convolution, adding bias value, quantization, activation, and pooling in each Node, which greatly improves the debugging efficiency and locates the problem position.

[0024] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A verification method for a Network-on-Chip (NOC) system based on a memory-compute integrated chip, characterized in that, Including: Input the picture data, and write the picture data into the NOC system through the AXI bus; Input the weight data, and directly write the weight data into the FLASH digital model of each node Node in the NOC system through initialization; Write the configuration information of the register, and configure each node Node and the NOC system output strobe circuit in the NOC system through the APB bus with the configuration information of the register; Compare the intermediate result and the final output result, and save and output simultaneously the final data read through the AXI bus, the output result of each node Node participating in the calculation, and the intermediate result after each operator of convolution, adding bias value, quantization, activation, and pooling in each node Node during the NOC system simulation process.

2. The verification method of a network-on-chip (NOC) system based on a memory-compute integrated chip as claimed in claim 1, wherein The process of inputting the picture data includes: Train the neural network algorithm model; After completing the training, print out the used picture data and store it in a text file; the format of the text file is the width times the height rows of picture data, and each row is a combination of 8-bit data of 16 channels; Declare an array at the top layer of the verification environment, use the language features of System Verilog to read the text file into the array, generate the corresponding AXI timing in the verification environment, and write the picture data into the NOC system through the AXI bus.

3. The verification method of an on-chip network NOC system based on a memory-compute integrated chip according to claim 2, wherein, The initialization process of the weight data includes: Train the neural network algorithm model; After completing the training, print the weight information used by each node Node, that is, the different convolutional layers corresponding to the neural network calculation, and the number of weights used is related to the data width and height and the number of input and output channels of the current convolutional layer.

4. The verification method of a network-on-chip (NOC) system based on a memory-compute integrated chip according to claim 3, wherein Each node Node includes a FLASH digital model for simulating the behavior of the FLASH device. The scale of the FLASH digital model is 256 rows and 1152 columns, and the weight value is 8 bits.

5. The verification method of a network-on-chip (NOC) system based on a memory-compute integrated chip as claimed in claim 3, wherein The training of the neural network algorithm model includes: Train the neural network algorithm model in the software platform MapTools; the neural network algorithm model includes ResNet, MobileNet, and object detection.

6. The verification method of a network-on-chip (NOC) system based on a memory-compute integrated chip as claimed in claim 5, wherein According to the neural network algorithm model in the software platform MapTools, directly initialize the weight information into the corresponding FLASH digital model, that is, the row and column positions for placing the weights.

7. The verification method of an on-chip network NOC system based on a memory-computation integrated chip according to claim 5, wherein, The configuration process of the register includes: The configuration information of the register is written through the APB bus. Each node Node is assigned a corresponding base address, and each register has its own corresponding offset address. The position and corresponding value of the register of each node Node are determined through the base address and the offset address; Through the script and the software platform MapTools, map the key information of the neural network algorithm model used by the software platform MapTools to the corresponding register to generate two text files, which are the address file and the register value file respectively, and the two are in one-to-one correspondence.

8. A verification method for a network-on-chip (NOC) system based on a memory-compute integrated chip, as claimed in claim 7, wherein, By declaring an array at the top of the verification environment and leveraging the language features of System Verilog, the text file is read into the array, and the corresponding APB control timing is generated in the verification environment. The configuration information of the registers is written into each corresponding Node to achieve the mapping of the neural network algorithm model.

9. The verification method of an on-chip network (NOC) system based on a memory-computation integrated chip according to claim 7, characterized in that The key information includes: picture size, direction path of the routing network, data flow type, input / output channels, sliding window size, and sliding window step.

10. A verification method for a network-on-chip (NOC) system based on a memory-compute integrated chip, as claimed in any one of claims 1 to 9, characterized in that, There are 30 Nodes inside the NoC system, with 6 Nodes in each row and a total of 5 rows. The register configuration of each Node occupies 32KB of space.

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