Redundant through hole layout method, related device and storage medium

Abstract

The invention provides a redundant through hole layout method, a related device and a storage medium. The method comprises the steps of obtaining a plurality of single through holes located between adjacent metal layers in an original chip physical layout; determining candidate redundant through holes of each single through hole according to a preset chip design rule and the wiring condition of the metal wires connected with the plurality of single through holes; for the single through hole, selecting a redundant through hole which has the highest priority of the layout position of the redundant through hole and accords with the preset chip design rule from candidate redundant through holes of the single through hole, the arrangement position priorities of the redundant through holes are in a line lower-layer metal wire direction, a line upper-layer metal wire direction, an offline upper-layer metal wire direction and an offline lower-layer metal wire direction from high to low in sequence; and arranging the selected redundant through holes in the physical layout of the original chip. According to the invention, the insertion rate of redundant through holes is improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of integrated circuit design, and particularly relates to a method for arranging redundant vias, related devices, and storage media. Background Art

[0002] With the continuous progress of chip manufacturing technology, the integration density of transistors has been increasing day by day, the feature size has been gradually reduced, and the number of transistors integrated per unit area has increased significantly, which poses greater challenges to chip design and manufacturing. Inevitable process defects in the manufacturing process may lead to an increase in the resistance of a single via, or even via defects related to electronic migration (EM), current distribution, and voltage drop. And via defects will affect chip functions and reduce chip yield and reliability. Currently, in order to reduce via defects, a common method is to insert redundant vias (also known as double vias). However, the existing method of manually inserting redundant vias is not only time-consuming and laborious, but also lacks consistency, resulting in a low insertion rate of redundant vias. In addition, although some automatic placement and routing tools provide the function of inserting redundant vias, these tools usually cannot insert redundant vias in all possible areas, which limits the insertion rate of redundant vias. Summary of the Invention

[0003] In view of the above problems, embodiments of the present disclosure provide a method for arranging redundant vias, related devices, and storage media, aiming to improve the insertion rate of redundant vias.

[0004] According to a first aspect of embodiments of the present disclosure, a method for arranging redundant vias is provided, including: Obtaining a plurality of single vias located between adjacent metal layers in the original chip physical layout; Determining candidate redundant vias for each of the single vias according to preset chip design rules and the routing conditions of the metal lines connected by the plurality of single vias; For the single via, selecting a redundant via with the highest priority for redundant via layout position and meeting the preset chip design rules from the candidate redundant vias of the single via, and the priority order of the redundant via layout positions from high to low is the direction of the lower-layer metal line along the line, the direction of the upper-layer metal line along the line, the direction of the upper-layer metal line away from the line, and the direction of the lower-layer metal line away from the line; Arranging the selected redundant vias in the original chip physical layout.

[0005] Optionally, the step of, for the single via, selecting a redundant via with the highest priority for redundant via layout position and meeting the preset chip design rules from the candidate redundant vias of the single via includes: According to the metal wire routing of adjacent metal layers in the original chip physical layout, select the redundant vias along the wire routing direction from the candidate redundant vias of the multiple single vias. Assume that the redundant vias along the wire are disposed in the original chip physical layout. According to the metal wire routing of adjacent metal layers in the assumed chip physical layout, select the redundant vias off the wire routing direction from the candidate redundant vias of the single vias that have not been selected as redundant vias yet.

[0006] Optionally, the wire routing direction along the wire includes the wire routing direction of the lower metal layer along the wire and the wire routing direction of the upper metal layer along the wire. The step of selecting the redundant vias along the wire routing direction from the candidate redundant vias of the multiple single vias according to the metal wire routing of adjacent metal layers in the original chip physical layout includes: According to the metal wire routing of the metal wires connected by the multiple single vias in the original chip physical layout, select the candidate redundant vias of the lower metal layer along the wire from the candidate redundant vias of the multiple single vias. Select the redundant vias of the lower metal layer along the wire that meet the preset chip design rules from the candidate redundant vias of the lower metal layer along the wire, cover the upper metal layer for the redundant vias of the lower metal layer along the wire, so that the redundant vias of the lower metal layer along the wire are connected to the adjacent upper and lower metal layers.

[0007] Optionally, the step of selecting the redundant vias along the wire routing direction from the candidate redundant vias of the multiple single vias according to the metal wire routing of adjacent metal layers in the original chip physical layout further includes: Assume that the redundant vias of the lower metal layer along the wire are disposed in the original chip physical layout. According to the metal wire routing of the metal wires connected by the single vias in the assumed chip physical layout, select the candidate redundant vias of the upper metal layer along the wire from the candidate redundant vias of the single vias that have not been selected as redundant vias yet. Select the redundant vias of the upper metal layer along the wire that meet the preset chip design rules from the candidate redundant vias of the upper metal layer along the wire, cover the lower metal layer for the redundant vias of the upper metal layer along the wire, so that the redundant vias of the upper metal layer along the wire are connected to the adjacent upper and lower metal layers.

[0008] Optionally, the wire routing direction off the wire includes the wire routing direction of the upper metal layer off the wire and the wire routing direction of the lower metal layer off the wire. It is assumed that the redundant vias along the line are arranged in the original chip physical layout. According to the metal wire routing conditions of the adjacent metal layers in the assumed chip physical layout, an off-line redundant via in the off-line metal wire routing direction is selected from the candidate redundant vias of the single via for which redundant vias have not been selected yet, including: It is assumed that the redundant vias along the line are arranged in the original chip physical layout. According to the metal wire routing conditions of the metal wires connected by the single via in the assumed chip physical layout, an off-line upper metal wire candidate redundant via in the off-line upper metal wire routing direction is selected from the candidate redundant vias of the single via for which redundant vias have not been selected yet; An off-line upper metal wire redundant via that conforms to the preset chip design rules is selected from the off-line upper metal wire candidate redundant vias, and the upper metal layer and the lower metal layer are covered for the off-line upper metal wire redundant via, so that the off-line upper metal wire redundant via is connected to the adjacent upper metal layer and lower metal layer.

[0009] Optionally, it is assumed that the redundant vias along the line are arranged in the original chip physical layout. According to the metal wire routing conditions of the adjacent metal layers in the assumed chip physical layout, an off-line redundant via in the off-line metal wire routing direction is selected from the candidate redundant vias of the single via for which redundant vias have not been selected yet, and it further includes: It is assumed that the redundant vias along the line and the off-line upper metal wire redundant vias are arranged in the original chip physical layout. According to the metal wire routing conditions of the metal wires connected by the single via in the assumed chip physical layout, an off-line lower metal wire candidate redundant via in the off-line lower metal wire routing direction is selected from the candidate redundant vias of the single via for which redundant vias have not been selected yet; An off-line lower metal wire redundant via that conforms to the preset chip design rules is selected from the off-line lower metal wire candidate redundant vias, and the upper metal layer and the lower metal layer are covered for the off-line lower metal wire redundant via, so that the off-line lower metal wire redundant via is connected to the adjacent upper metal layer and lower metal layer.

[0010] Optionally, the candidate redundant vias include candidate redundant vias arranged in at least one of the first direction of the first coordinate axis, the second direction of the first coordinate axis, the first direction of the second coordinate axis, and the second direction of the second coordinate axis with the single via as the coordinate axis center, and the second coordinate axis direction is the off-line lower metal wire routing direction. Selecting an off-line lower metal wire redundant via that conforms to the preset chip design rules from the off-line lower metal wire candidate redundant vias, and covering the upper metal layer for the off-line lower metal wire redundant via, so that the off-line lower metal wire redundant via is connected to the adjacent upper metal layer and lower metal layer, includes: Traverse the candidate redundant vias of the underlying metal lines along the first direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the original chip physical layout, select the first redundant via of the underlying metal line along the line that meets the preset chip design rules for the multiple single vias, and cover the upper metal layer for the first redundant via of the underlying metal line along the line; Assume that the first redundant via of the underlying metal line along the line is disposed in the original chip physical layout. Traverse the candidate redundant vias of the underlying metal lines along the line set in the second direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select the second redundant via of the underlying metal line along the line that meets the preset chip design rules for the single vias for which redundant vias have not been selected currently, and cover the upper metal layer for the second redundant via of the underlying metal line along the line; Assume that the first redundant via of the underlying metal line along the line and the second redundant via of the underlying metal line along the line are disposed in the original chip physical layout. Traverse the candidate redundant vias of the underlying metal lines along the line set in the first direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select the third redundant via of the underlying metal line along the line that meets the preset chip design rules for the single vias for which redundant vias have not been selected currently, and cover the upper metal layer for the third redundant via of the underlying metal line along the line; Assume that the first redundant via of the underlying metal line along the line, the second redundant via of the underlying metal line along the line, and the third redundant via of the underlying metal line along the line are disposed in the original chip physical layout. Traverse the candidate redundant vias of the underlying metal lines along the line set in the second direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select the fourth redundant via of the underlying metal line along the line that meets the chip design rules for the single vias for which redundant vias have not been selected currently, and cover the upper metal layer for the fourth redundant via of the underlying metal line along the line.

[0011] Optionally, the step of selecting the redundant via of the upper metal line along the line that meets the preset chip design rules from the candidate redundant vias of the upper metal line along the line and covering the lower metal layer for the redundant via of the upper metal line along the line so that the redundant via of the upper metal line along the line is connected to the adjacent upper and lower metal layers includes: Assume that the redundant via of the underlying metal line along the line is disposed in the original chip physical layout. Traverse the candidate redundant vias of the upper metal line along the line set in the first direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select the first redundant via of the upper metal line along the line that meets the preset chip design rules for the single vias for which redundant vias have not been selected currently, and cover the lower metal layer for the first redundant via of the upper metal line along the line; Assume that the redundant vias of the underlying metal lines along the line and the redundant vias of the upper metal lines along the first line are arranged in the original chip physical layout. Traverse the redundant via candidates of the upper metal lines along the line set in the second direction of the second coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select the redundant vias of the upper metal lines along the second line that meet the preset chip design rules for the single via that has not yet selected a redundant via, and cover the lower metal layer for the redundant vias of the upper metal lines along the second line; Assume that the redundant vias of the underlying metal lines along the line, the redundant vias of the upper metal lines along the first line, and the redundant vias of the upper metal lines along the second line are arranged in the original chip physical layout. Traverse the redundant via candidates of the upper metal lines along the line set in the first direction of the first coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select the redundant vias of the upper metal lines along the third line that meet the preset chip design rules for the single via that has not yet selected a redundant via, and cover the lower metal layer for the redundant vias of the upper metal lines along the third line; Assume that the redundant vias of the underlying metal lines along the line, the redundant vias of the upper metal lines along the first line, the redundant vias of the upper metal lines along the second line, and the redundant vias of the upper metal lines along the third line are arranged in the original chip physical layout. Traverse the redundant via candidates of the upper metal lines along the line set in the second direction of the first coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select the redundant vias of the upper metal lines along the fourth line that meet the preset chip design rules for the single via that has not yet selected a redundant via, and cover the lower metal layer for the redundant vias of the upper metal lines along the fourth line.

[0012] Optionally, selecting the redundant vias of the upper metal lines off the line that meet the preset chip design rules from the redundant via candidates of the upper metal lines off the line, and covering the upper metal layer and the lower metal layer for the redundant vias of the upper metal lines off the line, so that the redundant vias of the upper metal lines off the line are connected to the adjacent upper metal layer and lower metal layer, includes: Assume that the redundant vias of the underlying metal lines along the line and the redundant vias of the upper metal lines along the line are arranged in the original chip physical layout. Traverse the redundant via candidates of the upper metal lines off the line set in the first direction of the second coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select the first redundant via of the upper metal lines off the line that meet the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the first redundant via of the upper metal lines off the line; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, and the redundant vias for the first off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the off-line upper-layer metal lines arranged in the second direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a second off-line upper-layer metal line redundant via that complies with the preset chip design rules for the single via for which no redundant via has been selected yet, and cover the upper metal layer and the lower metal layer for the second off-line upper-layer metal line redundant via; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, the redundant vias for the first off-line upper-layer metal lines, and the redundant vias for the second off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the off-line upper-layer metal lines arranged in the first direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a third off-line upper-layer metal line redundant via that complies with the preset chip design rules for the single via for which no redundant via has been selected yet, and cover the upper metal layer and the lower metal layer for the third off-line upper-layer metal line redundant via; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, the redundant vias for the first off-line upper-layer metal lines, the redundant vias for the second off-line upper-layer metal lines, and the redundant vias for the third off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the off-line upper-layer metal lines arranged in the second direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a fourth off-line upper-layer metal line redundant via that complies with the preset chip design rules for the single via for which no redundant via has been selected yet, and cover the upper metal layer and the lower metal layer for the fourth off-line upper-layer metal line redundant via.

[0013] Optionally, selecting a redundant via for the lower-layer metal line that complies with the preset chip design rules from the candidate redundant vias for the lower-layer metal lines off the line, and covering the upper metal layer and the lower metal layer for the redundant via for the lower-layer metal line off the line, so that the redundant via for the lower-layer metal line off the line is connected to the adjacent upper metal layer and lower metal layer, includes: Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, and the redundant vias for the off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower-layer metal lines off the line arranged in the first direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a first redundant via for the lower-layer metal line off the line that complies with the preset chip design rules for the single via for which no redundant via has been selected yet, and cover the upper metal layer and the lower metal layer for the first redundant via for the lower-layer metal line off the line; Assume that the redundant vias for the lower metal lines along the line, the redundant vias for the upper metal lines along the line, the redundant vias for the upper metal lines off the line, and the redundant vias for the lower metal lines of the first off-line are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower metal lines off the line disposed in the second direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a second redundant via for the lower metal lines off the line that meets the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the second redundant via for the lower metal lines off the line; Assume that the redundant vias for the lower metal lines along the line, the redundant vias for the upper metal lines along the line, the redundant vias for the upper metal lines off the line, the redundant vias for the lower metal lines of the first off-line, and the redundant vias for the lower metal lines of the second off-line are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower metal lines off the line disposed in the first direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a third redundant via for the lower metal lines off the line that meets the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the third redundant via for the lower metal lines off the line; Assume that the redundant vias for the lower metal lines along the line, the redundant vias for the upper metal lines along the line, the redundant vias for the upper metal lines off the line, the redundant vias for the lower metal lines of the first off-line, the redundant vias for the lower metal lines of the second off-line, and the redundant vias for the lower metal lines of the third off-line are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower metal lines off the line disposed in the second direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a fourth redundant via for the lower metal lines off the line that meets the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the fourth redundant via for the lower metal lines off the line.

[0014] Optionally, before disposing the selected redundant vias in the original chip physical layout, the redundant via disposition method further includes: Perform data merging on the selected redundant vias and the original chip physical layout to perform verification of the preset chip design rules and electrical connections, and dispose the selected redundant vias that pass the verification in the original chip physical layout.

[0015] According to a second aspect of the embodiments of the present disclosure, there is provided a redundant via disposition device, including: A single via acquisition unit, configured to acquire a plurality of single vias between adjacent metal layers in an original chip physical layout; A candidate redundant via determination unit, configured to determine a candidate redundant via for each of the single vias according to a preset chip design rule and the routing condition of the metal wires connected by the multiple single vias; A redundant via selection unit, configured to select, for each of the single vias, a redundant via with the highest priority for the redundant via layout position and meeting the preset chip design rule from the candidate redundant vias of the single via. The priority order of the redundant via layout positions from high to low is the direction of the underlying metal wire along the line, the direction of the upper metal wire along the line, the direction of the upper metal wire away from the line, and the direction of the underlying metal wire away from the line; A redundant via layout unit, configured to layout the selected redundant vias in the original chip physical layout.

[0016] According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device, including: a processor, a memory, and a program stored on the memory and executable on the processor. When the program is executed by the processor, the steps of the method described above are implemented.

[0017] According to a fourth aspect of the embodiments of the present disclosure, there is provided a storage medium, on which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the steps of the method described above are implemented.

[0018] The embodiments of the present disclosure bring the following beneficial effects: The redundant via layout method provided by the embodiments of the present disclosure selects, for each of the single vias, a redundant via with the highest priority for the redundant via layout position and meeting the preset chip design rule from the candidate redundant vias of the single via. The priority order of the redundant via layout positions from high to low is the direction of the underlying metal wire along the line, the direction of the upper metal wire along the line, the direction of the upper metal wire away from the line, and the direction of the underlying metal wire away from the line, ensuring that the redundant vias are preferentially laid out along the original metal wire under the premise of meeting the preset chip design rule, without adding additional wire routing, reducing the situation where redundant vias cannot be inserted due to metal wire layout restrictions, increasing the insertion rate of redundant vias, and also being able to effectively utilize the high manufacturing accuracy and high connection reliability of the underlying metal wire, further reducing the risk of single via failure.

[0019] Other features and advantages of the embodiments of the present disclosure will be described in the subsequent description, and some will become obvious from the description, or will be understood by implementing the embodiments of the present disclosure. The objectives and other advantages of the embodiments of the present disclosure are achieved and obtained by the structures specifically pointed out in the description and the drawings.

[0020] To make the above objectives, features, and advantages of the embodiments of the present disclosure more obvious and understandable, the following specific embodiments are given, and in conjunction with the accompanying drawings, the following detailed description is provided. Description of the Drawings

[0021] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the embodiments of the present disclosure will become clearer. In the drawings: Figure 1 It is a schematic flow chart of a redundant via layout method provided according to an embodiment of the present disclosure; Figure 2A It is a layout schematic diagram of a square candidate redundant via provided according to an embodiment of the present disclosure; Figure 2B It is a layout schematic diagram of a rectangular candidate redundant via provided according to an embodiment of the present disclosure; Figure 3A It is a layout schematic diagram of a redundant via along the underlying metal line provided according to an embodiment of the present disclosure; Figure 3B It is a layout schematic diagram of a redundant via along the underlying metal line provided according to another embodiment of the present disclosure; Figure 3C It is a layout schematic diagram of a redundant via along the upper metal line provided according to an embodiment of the present disclosure; Figure 4A It is a layout schematic diagram of a redundant via off the upper metal line provided according to an embodiment of the present disclosure; Figure 4B It is a layout schematic diagram of a redundant via off the upper metal line provided according to another embodiment of the present disclosure; Figure 4C It is a layout schematic diagram of a redundant via off the underlying metal line provided according to an embodiment of the present disclosure; Figure 5 It is a schematic flow chart of a hierarchical traversal for arranging redundant vias for a single via provided according to an embodiment of the present disclosure; Figure 6 It is a schematic structural diagram of a redundant via layout device provided according to an embodiment of the present disclosure; Figure 7 It is a schematic structural diagram of an electronic device provided according to an embodiment of the present disclosure. Detailed implementation manners

[0022] The various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0023] In this document, A single via refers to a single conductive via used to connect different metal layers during the chip manufacturing process.

[0024] A redundant via, also known as a dual via or redundant hole, refers to a via additionally added beside a single via, aiming to improve the manufacturing yield and reliability of a chip and reduce the risk of chip performance degradation or function loss caused by the failure of a single via.

[0025] On track means that in the physical layout of a chip, the insertion position of the redundant via is consistent with the routing direction of the metal wire connected to the single via.

[0026] Off track means that in the physical layout of a chip, the insertion position of the redundant via is inconsistent with the routing direction of the metal wire connected to the single via.

[0027] Figure 1 It is a schematic flowchart of a method for arranging redundant vias according to an embodiment of the present disclosure. As Figure 1 shown, the method for arranging redundant vias in the embodiment of the present disclosure includes: In step S110, a plurality of single vias located between adjacent metal layers in the original chip physical layout are obtained.

[0028] In some embodiments, multiple metal layers are provided in the original chip physical layout (for example, digital or analog back-end layout), and any two adjacent metal layers among the multiple metal layers can be the adjacent metal layers here. The method for arranging redundant vias in the embodiment of the present disclosure can be executed for every two adjacent metal layers in the multiple metal layers provided in the original chip physical layout, and redundant vias are inserted for the single vias provided between every two adjacent metal layers. In some embodiments, in the original chip physical layout, a plurality of single vias between adjacent metal layers are selected according to design rules. It should be noted that the single vias in the embodiment of the present disclosure refer to the vias that need to add redundant vias. Generally, the single vias here include square single vias and do not include rectangular single vias. Since the function of a rectangular single via is equal to or better than that of two square single vias, the rectangular single vias in the original chip physical layout are not selected as the range that needs to add redundant vias.

[0029] In step S120, according to the preset chip design rules and the routing conditions of the metal wires connected to the plurality of single vias, candidate redundant vias for each of the single vias are determined.

[0030] In some embodiments, for each single via hole, redundant via holes can be arranged with the single via hole as the coordinate axis center along the first direction of the first coordinate axis (e.g., the negative x-axis direction), the second direction of the first coordinate axis (e.g., the positive x-axis direction), the first direction of the second coordinate axis (e.g., the positive y-axis direction), and the second direction of the second coordinate axis (e.g., the negative y-axis direction). In some embodiments, according to the chip design rules (e.g., pitch (Space) and side length (Width)) and the routing situation of the metal lines connected to the single via hole, the candidate redundant via holes of the single via hole are determined. The candidate redundant via holes may include the candidate redundant via holes arranged in at least one of the first direction of the first coordinate axis (e.g., the negative x-axis direction), the second direction of the first coordinate axis (e.g., the positive x-axis direction), the first direction of the second coordinate axis (e.g., the positive y-axis direction), and the second direction of the second coordinate axis (e.g., the negative y-axis direction) with the single via hole as the coordinate axis center. In some embodiments, according to the process provided by the foundry, the candidate redundant via holes of the single via hole can be divided into square via holes as shown in Figure 2A and rectangular via holes as shown in Figure 2B . As shown in Figure 2A and Figure 2B, the adjacent metal layers include the lower metal layer Mn and the upper metal layer M(n + 1) (where n is the serial number of the metal layer and n is a positive integer greater than 0). A single via hole is arranged between the lower metal layer Mn and the upper metal layer M(n + 1). With the single via hole as the coordinate axis center, there are a left candidate redundant via hole, a right candidate redundant via hole, an upper candidate redundant via hole, and a lower candidate redundant via hole in the four directions of the negative x-axis direction x-, the positive x-axis direction x+, the positive y-axis direction y+, and the negative y-axis direction y- respectively. As shown in Figure 2A , inserting a square redundant via hole around the single via hole is to insert a via hole of the same size with sufficient pitch beside the single via hole. As shown in Figure 2B , adding a rectangular redundant via hole is formed by inserting via holes of the same size with zero distance beside the single via hole. When permitted by the foundry process, the rectangular redundant via hole is the first choice, occupying less metal line routing space compared to adding a square redundant via hole.

[0031] In step S130, for the single via hole, a redundant via hole with the highest priority for the redundant via hole layout position and meeting the preset chip design rules is selected from the candidate redundant via holes of the single via hole. The priority order of the redundant via hole layout positions from high to low is the direction of the lower metal line along the line, the direction of the upper metal line along the line, the direction of the upper metal line off the line, and the direction of the lower metal line off the line.

[0032] In some embodiments, the metal wire directions in adjacent metal layers are different. For example, the metal wire direction of the lower metal layer is along the horizontal direction or the vertical direction, and the metal wire direction of the upper metal layer is along the vertical direction or the horizontal direction. According to the metal wire routing conditions of adjacent metal layers in the original chip physical layout, the redundant via hole layout position with the highest priority and meeting the preset chip design rules is selected from multiple candidate redundant vias of single vias. Specifically, the metal wire routing direction along the line will be considered first, and further, the metal wire routing direction of the lower metal layer along the line (On track Mn) will be considered first because the lower metal layer usually has higher manufacturing accuracy and connection reliability. Especially in standard cells, RF or analog designs, once the layout of the bottom metal layer (such as M1) is determined, it is often not easy to change. The priority order of the redundant via hole layout position from high to low is the direction of the lower metal layer along the line, the direction of the upper metal layer along the line, the direction of the upper metal layer off the line, and the direction of the lower metal layer off the line.

[0033] In some embodiments, according to the metal wire routing of adjacent metal layers in the original chip physical layout, the redundant vias along the wire routing direction are selected from multiple candidate redundant vias of single vias. The wire routing direction along the metal wire includes the wire routing direction of the lower-layer metal wire along the line (On track Mn) and the wire routing direction of the upper-layer metal wire along the line (On track M(n+1)). In some embodiments, according to the metal wire routing of the metal wires connected by multiple single vias in the original chip physical layout, the candidate redundant vias of the lower-layer metal wire along the line are selected from multiple candidate redundant vias of single vias. The redundant vias of the lower-layer metal wire along the line that meet the preset chip design rules are selected from the candidate redundant vias of the lower-layer metal wire along the line, and the upper metal layer is covered for the redundant vias of the lower-layer metal wire along the line, so that the redundant vias of the lower-layer metal wire along the line are connected to the adjacent upper and lower metal layers. In some embodiments, taking the second coordinate axis direction (for example, the y-axis direction) as the wire routing direction of the lower-layer metal wire along the line as an example, in some embodiments, taking the second coordinate axis direction as the wire routing direction of the lower-layer metal wire along the line, the candidate redundant vias of the lower-layer metal wire along the line set in the first direction of the second coordinate axis are traversed, and according to the metal wire routing of the adjacent metal layers in the original chip physical layout, the first redundant vias of the lower-layer metal wire along the line that meet the preset chip design rules are selected for multiple single vias, and the upper metal layer is covered for the first redundant vias of the lower-layer metal wire along the line. Assuming that the first redundant vias of the lower-layer metal wire along the line are arranged in the original chip physical layout, the candidate redundant vias of the lower-layer metal wire along the line set in the second direction of the second coordinate axis are traversed, and according to the metal wire routing of the adjacent metal layers in the assumed chip physical layout, the second redundant vias of the lower-layer metal wire along the line that meet the preset chip design rules are selected for the single vias for which the redundant vias have not been selected yet, and the upper metal layer is covered for the second redundant vias of the lower-layer metal wire along the line. Assuming that the first redundant vias of the lower-layer metal wire along the line and the second redundant vias of the lower-layer metal wire along the line are arranged in the original chip physical layout, the candidate redundant vias of the lower-layer metal wire along the line set in the first direction of the first coordinate axis are traversed, and according to the metal wire routing of the adjacent metal layers in the assumed chip physical layout, the third redundant vias of the lower-layer metal wire along the line that meet the preset chip design rules are selected for the single vias for which the redundant vias have not been selected yet, and the upper metal layer is covered for the third redundant vias of the lower-layer metal wire along the line. Assuming that the first redundant vias of the lower-layer metal wire along the line, the second redundant vias of the lower-layer metal wire along the line, and the third redundant vias of the lower-layer metal wire along the line are arranged in the original chip physical layout, the candidate redundant vias of the lower-layer metal wire along the line set in the second direction of the first coordinate axis are traversed, and according to the metal wire routing of the adjacent metal layers in the assumed chip physical layout, the fourth redundant vias of the lower-layer metal wire along the line that meet the preset chip design rules are selected for the single vias for which the redundant vias have not been selected yet, and the upper metal layer is covered for the fourth redundant vias of the lower-layer metal wire along the line.

[0034] Figure 3AThe layout schematic diagram of redundant vias for the lower metal lines along the line provided according to an embodiment of the present disclosure. As Figure 3A shown, according to the metal line routing situation connected by the single via in the original chip physical layout, there is enough space in both the routing direction of the lower metal lines along the line and the routing direction of the upper metal lines along the line to arrange redundant vias. Here, the candidate redundant vias for the lower metal lines along the line are preferentially selected, and the redundant vias for the lower metal lines along the line that meet the preset chip design rules are selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the candidate redundant via above the single via arranged in the first direction of the second coordinate axis is selected and covered with the upper metal layer for it. Figure 3B The layout schematic diagram of redundant vias for the lower metal lines along the line provided according to another embodiment of the present disclosure. As Figure 3B shown, according to the metal line routing situation connected by the single via in the original chip physical layout, there is enough space in the routing direction of the lower metal lines along the line to insert redundant vias. Here, the candidate redundant vias for the lower metal lines along the line are preferentially selected, and the redundant vias for the lower metal lines along the line that meet the preset chip design rules are selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the candidate redundant via above the single via arranged in the first direction of the second coordinate axis is selected and covered with the upper metal layer for it.

[0035] In some embodiments, assuming that the redundant vias for the lower metal lines along the line are arranged in the original chip physical layout, according to the metal line routing situation connected by the single via in the assumed chip physical layout, the candidate redundant vias for the upper metal lines along the line in the routing direction of the upper metal lines along the line are selected from the candidate redundant vias of the single via for which the redundant vias have not been selected yet. The redundant vias for the upper metal lines along the line that meet the preset chip design rules are selected from the candidate redundant vias for the upper metal lines along the line, and the lower metal layer is covered for the redundant vias for the upper metal lines along the line, so that the redundant vias for the upper metal lines along the line are connected to the adjacent upper metal layer and lower metal layer.

[0036] In some embodiments, taking the second coordinate axis direction (e.g., the y-axis direction) as the routing direction of the underwire lower-layer metal line as an example, in some embodiments, assuming that the underwire lower-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the on-wire upper-layer metal lines arranged in the first direction of the second coordinate axis. According to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout, select the first on-wire upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not been selected as a redundant via currently, and cover the lower metal layer for the first on-wire upper-layer metal line redundant via. Assuming that the underwire lower-layer metal line redundant vias and the first on-wire upper-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the on-wire upper-layer metal lines arranged in the second direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select the second on-wire upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not been selected as a redundant via currently, and cover the lower metal layer for the second on-wire upper-layer metal line redundant via. Assuming that the underwire lower-layer metal line redundant vias, the first on-wire upper-layer metal line redundant vias, and the second on-wire upper-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the on-wire upper-layer metal lines arranged in the first direction of the first coordinate axis. According to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout, select the third on-wire upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not been selected as a redundant via currently, and cover the lower metal layer for the third on-wire upper-layer metal line redundant via. Assuming that the underwire lower-layer metal line redundant vias, the first on-wire upper-layer metal line redundant vias, the second on-wire upper-layer metal line redundant vias, and the third on-wire upper-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the on-wire upper-layer metal lines arranged in the second direction of the first coordinate axis. According to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout, select the fourth on-wire upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not been selected as a redundant via currently, and cover the lower metal layer for the fourth on-wire upper-layer metal line redundant via.

[0037] Figure 3C FIG. is a layout schematic diagram of the on-wire upper-layer metal line redundant via provided according to an embodiment of the present disclosure. As Figure 3C shown, according to the metal line routing conditions of the single via connected in the original chip physical layout, there is sufficient space in the on-wire upper-layer metal line routing direction to insert redundant vias. Here, the candidate redundant vias of the on-wire upper-layer metal lines are preferentially selected, and the on-wire upper-layer metal line redundant vias that comply with the preset chip design rules are selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, select the left candidate redundant via arranged in the first direction of the first coordinate axis where the single via is disposed, and cover the lower metal layer for it.

[0038] In some embodiments, it is assumed that redundant vias along the line are arranged in the original chip physical layout. According to the metal wire routing conditions of adjacent metal layers in the assumed chip physical layout, off-line redundant vias in the off-line metal wire routing direction are selected from the candidate redundant vias of single vias for which redundant vias have not been selected yet. In some embodiments, the off-line metal wire routing direction includes the off-line upper metal wire routing direction (Off track M(n+1)) and the off-line lower metal wire routing direction (Offtrack Mn). It is assumed that redundant vias along the line are arranged in the original chip physical layout. According to the metal wire routing conditions of the metal wires connected by the single vias in the assumed chip physical layout, off-line upper metal wire candidate redundant vias in the off-line upper metal wire routing direction are selected from the candidate redundant vias of single vias for which redundant vias have not been selected yet. Off-line upper metal wire redundant vias that meet the preset chip design rules are selected from the off-line upper metal wire candidate redundant vias, and the upper metal layer and the lower metal layer are covered for the off-line upper metal wire redundant vias, so that the off-line upper metal wire redundant vias are connected to the adjacent upper metal layer and lower metal layer.

[0039] In some embodiments, taking the second coordinate axis direction (e.g., the y-axis direction) as the routing direction of the offline lower-layer metal lines as an example, assuming that the offline lower-layer metal line redundant vias and the online upper-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the offline upper-layer metal lines set in the first direction of the second coordinate axis. According to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout, select a first offline upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the first offline upper-layer metal line redundant via. Assuming that the offline lower-layer metal line redundant vias, the online upper-layer metal line redundant vias, and the first offline upper-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the offline upper-layer metal lines set in the second direction of the second coordinate axis. According to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout, select a second offline upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the second offline upper-layer metal line redundant via. Assuming that the offline lower-layer metal line redundant vias, the online upper-layer metal line redundant vias, the first offline upper-layer metal line redundant vias, and the second offline upper-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the offline upper-layer metal lines set in the first direction of the first coordinate axis. According to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout, select a third offline upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the third offline upper-layer metal line redundant via. Assuming that the offline lower-layer metal line redundant vias, the online upper-layer metal line redundant vias, the first offline upper-layer metal line redundant vias, the second offline upper-layer metal line redundant vias, and the third offline upper-layer metal line redundant vias are disposed in the original chip physical layout, traverse the candidate redundant vias of the offline upper-layer metal lines set in the second direction of the first coordinate axis. According to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout, select a fourth offline upper-layer metal line redundant via that complies with the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the fourth offline upper-layer metal line redundant via.

[0040] Figure 4A Schematic diagram of the layout of the redundant vias of the offline upper-layer metal lines provided according to an embodiment of the present disclosure. As Figure 4AAs shown, according to the routing of the metal wires connected by the single vias in the original chip physical layout, there is sufficient space in both the off-track lower metal wire routing direction (Off track Mn) and the off-line upper metal wire routing direction to insert redundant vias. Here, the candidate redundant vias for the off-line upper metal wire routing are preferentially selected, and the redundant vias for the on-track lower metal wires that comply with the preset chip design rules are selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the left candidate redundant via set in the first direction of the first coordinate axis for inserting this single via is selected, and the upper and lower metal layers are covered for it. Figure 4B FIG. is a layout schematic diagram of the redundant vias for the off-line upper metal wires provided according to another embodiment of the present disclosure. As Figure 4B shown, according to the routing of the metal wires connected by the single vias in the original chip physical layout, there is sufficient space in the off-line upper metal wire routing direction to insert redundant vias. Here, the candidate redundant vias for the off-line upper metal wire routing are preferentially selected, and the redundant vias for the on-track lower metal wires that comply with the preset chip design rules are selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the left candidate redundant via set in the first direction of the first coordinate axis for inserting this single via is selected, and the upper and lower metal layers are covered for it.

[0041] In some embodiments, assuming that the on-track redundant vias and the redundant vias for the off-line upper metal wires are disposed in the original chip physical layout, according to the routing of the metal wires connected by the single vias in the assumed chip physical layout, the off-line lower metal wire candidate redundant vias in the off-line lower metal wire routing direction are selected from the candidate redundant vias of the single vias for which the redundant vias have not been selected yet. The redundant vias for the off-line lower metal wires that comply with the preset chip design rules are selected from the off-line lower metal wire candidate redundant vias, and the upper metal layer and the lower metal layer are covered for the redundant vias for the off-line lower metal wires, so that the redundant vias for the off-line lower metal wires are connected to the adjacent upper metal layer and lower metal layer.

[0042] In some embodiments, taking the second coordinate axis direction (e.g., the y-axis direction) as the routing direction of the offline lower-layer metal lines as an example, assuming that the offline lower-layer metal line redundant vias, the online upper-layer metal line redundant vias, and the offline upper-layer metal line redundant vias are arranged in the original chip physical layout, traverse the offline lower-layer metal line candidate redundant vias set in the first direction of the second coordinate axis. According to the metal line routing situation of adjacent metal layers in the assumed chip physical layout, select the first offline lower-layer metal line redundant via that meets the preset chip design rules for the single via without a selected redundant via, and cover the upper metal layer and the lower metal layer for the first offline lower-layer metal line redundant via. Assume that the offline lower-layer metal line redundant vias, the online upper-layer metal line redundant vias, the offline upper-layer metal line redundant vias, and the first offline lower-layer metal line redundant vias are arranged in the original chip physical layout. Traverse the offline lower-layer metal line candidate redundant vias set in the second direction of the second coordinate axis. According to the metal line routing situation of adjacent metal layers in the assumed chip physical layout, select the second offline lower-layer metal line redundant via that meets the preset chip design rules for the single via without a selected redundant via, and cover the upper metal layer and the lower metal layer for the second offline lower-layer metal line redundant via. Assume that the offline lower-layer metal line redundant vias, the online upper-layer metal line redundant vias, the offline upper-layer metal line redundant vias, the first offline lower-layer metal line redundant vias, and the second offline lower-layer metal line redundant vias are arranged in the original chip physical layout. Traverse the offline lower-layer metal line candidate redundant vias set in the first direction of the first coordinate axis. According to the metal line routing situation of adjacent metal layers in the assumed chip physical layout, select the third offline lower-layer metal line redundant via that meets the preset chip design rules for the single via without a selected redundant via, and cover the upper metal layer and the lower metal layer for the third offline lower-layer metal line redundant via. Assume that the offline lower-layer metal line redundant vias, the online upper-layer metal line redundant vias, the offline upper-layer metal line redundant vias, the first offline lower-layer metal line redundant vias, the second offline lower-layer metal line redundant vias, and the third offline lower-layer metal line redundant vias are arranged in the original chip physical layout. Traverse the offline lower-layer metal line candidate redundant vias set in the second direction of the first coordinate axis. According to the metal line routing situation of adjacent metal layers in the assumed chip physical layout, select the fourth offline lower-layer metal line redundant via that meets the preset chip design rules for the single via without a selected redundant via, and cover the upper metal layer and the lower metal layer for the fourth offline lower-layer metal line redundant via.

[0043] Figure 4C FIG. is a layout schematic diagram of an offline lower-layer metal line redundant via provided according to an embodiment of the present disclosure. As Figure 4CAs shown, according to the routing of the metal wires connected by the single vias in the original chip physical layout, there is enough space in the routing direction of the offline lower-layer metal wires to insert redundant vias. Here, the candidate redundant vias for the offline lower-layer metal wires are preferentially selected, and in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis, the redundant vias of the offline lower-layer metal wires that meet the preset chip design rules are selected. Therefore, the upper candidate redundant via set in the first direction of the second coordinate axis for inserting this single via is selected, and the upper and lower metal layers are covered for it.

[0044] In step S140, the selected redundant vias are laid out in the original chip physical layout.

[0045] In some embodiments, after redundant vias are selected for multiple single vias in the original chip physical layout, the selected redundant vias (including the redundant vias and the data of the metal layers covering the redundant vias) are merged with the original chip physical layout for preset chip design rule and electrical connection verification, and the selected redundant vias that pass the verification are laid out in the original chip physical layout. This process not only ensures the correct layout of the redundant vias, but also avoids design errors that may be caused by manual operations, improving the automation level and design efficiency of chip design.

[0046] Figure 5 It is a schematic diagram of a hierarchical traversal process for laying out redundant vias for a single via according to an embodiment of the present disclosure. As Figure 5 shown, according to the priority order of the redundant via layout positions in the direction of the offline lower-layer metal wires, the direction of the online upper-layer metal wires, the direction of the offline upper-layer metal wires, and the direction of the offline lower-layer metal wires, the redundant via layout operations are divided into priorities. Taking the second coordinate axis direction (for example, the y-axis direction) as the routing direction of the offline lower-layer metal wires as an example, in each priority category, the redundant vias that meet the preset chip design rules are selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. This process ensures that each single via preferentially inserts redundant vias along the metal wires as much as possible on the premise of meeting the preset chip design rules, thereby improving the manufacturing yield and reliability of the chip.

[0047] It should be noted that in the priority of each redundant via placement position and the placement steps in each coordinate axis direction under each priority category, assuming that the currently selected redundant via and the metal layer it covers are placed in the original chip physical layout, the next step of selecting a redundant via is executed according to the metal wire routing situation of the adjacent metal layers in the assumed chip physical layout. During the process of executing the next step of selecting a redundant via, it is verified whether the placement of the already selected redundant via causes a new chip design rule conflict. Only when the verification passes, will the next traversal and selection continue to ensure that each redundant via placed complies with the preset chip design rules. In this way, not only the insertion rate of the redundant vias is improved, but also the overall consistency and reliability of the chip design are ensured.

[0048] It should be noted that checking whether each candidate redundant via complies with the preset chip design rules includes, but is not limited to, checking whether parameters such as the hole pitch (Space), side length (Width), and metal wire pitch (Metal pitch) comply with the preset chip design rules. Only the redundant vias that comply with the preset chip design rules will be selected and placed in the original chip physical layout, and at the same time, the program will generate the corresponding metal layer to ensure the correct connection of the redundant vias with the upper and lower layer metal wires. It should be noted that after inserting a redundant via for a single via, the single via is no longer a via that needs to add a redundant via, that is, according to the redundant via placement method of the embodiments of the present disclosure, at most one redundant via is inserted for each single via.

[0049] Figure 6 It is a structural schematic diagram of a redundant via placement device provided according to an embodiment of the present disclosure. As Figure 6 shown, the redundant via placement device 600 of the embodiments of the present disclosure includes: a single via acquisition unit 610, a candidate redundant via determination unit 620, a redundant via selection unit 630, and a redundant via placement unit 640.

[0050] The single via acquisition unit 610 is configured to acquire a plurality of single vias located between adjacent metal layers in the original chip physical layout.

[0051] The candidate redundant via determination unit 620 is configured to determine the candidate redundant vias for each of the single vias according to the preset chip design rules and the metal wire routing situation of the metal wires connected by the plurality of single vias.

[0052] The redundant via selection unit 630 is configured to select, for the single via, the redundant via with the highest priority of the redundant via placement position and that complies with the preset chip design rules from the candidate redundant vias of the single via. The priority of the redundant via placement position is, from high to low, the direction of the lower layer metal wire along the line, the direction of the upper layer metal wire along the line, the direction of the upper layer metal wire away from the line, and the direction of the lower layer metal wire away from the line.

[0053] A redundant via placement unit 640 is configured to place the selected redundant vias in the original chip physical layout.

[0054] An embodiment of the present disclosure also provides an electronic device 700, as Figure 7 shown, including a memory 720, a processor 710, a power supply component 730, a network interface 740, an input / output interface 750, and a program stored in the memory 720 and executable on the processor 710. When the program is executed by the processor 710, it can implement the various processes of the above embodiments of the method and achieve the same technical effects. To avoid repetition, details are not described herein again.

[0055] An embodiment of the present disclosure also provides an integrated circuit layout, which can be implemented by using the steps of the method as described above. Here, the integrated circuit layout refers to a three-dimensional configuration of two or more elements and part or all of the interconnecting lines in an integrated circuit, at least one of which is an active element, or the above three-dimensional configuration prepared for manufacturing an integrated circuit.

[0056] Those of ordinary skill in the art can understand that all or part of the steps in the above various methods can be completed by instructions or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. For this reason, an embodiment of the present disclosure also provides a storage medium, on which a computer program or instructions are stored. When the computer program or instructions are executed by a processor, they can implement the various processes of the above embodiments of the method.

[0057] Since the instructions stored in the storage medium can execute the steps in the method provided by the embodiments of the present disclosure, the beneficial effects that can be achieved by the method provided by the embodiments of the present disclosure can be realized. For details, see the previous embodiments, which are not described herein again. The specific implementation of each of the above operations can be seen in the previous embodiments, which are not described herein again.

[0058] In summary, for the single via in the redundant via placement method provided by the embodiments of the present disclosure, a redundant via with the highest priority of the redundant via placement position and meeting the preset chip design rules is selected from the candidate redundant vias of the single via. The priority order of the redundant via placement positions from high to low is along the lower-layer metal line direction, along the upper-layer metal line direction, away from the upper-layer metal line direction, and away from the lower-layer metal line direction. It ensures that the redundant vias are preferentially placed along the original metal line under the premise of meeting the preset chip design rules, without adding extra wiring, reducing the situation where redundant vias cannot be inserted due to metal line layout restrictions, increasing the insertion rate of redundant vias, and effectively utilizing the high manufacturing accuracy and high connection reliability of the lower-layer metal lines, further reducing the risk of single via failure.

[0059] Finally, it should be noted that: Obviously, the above embodiments are merely examples given for clearly illustrating the present disclosure, rather than limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made on the basis of the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present disclosure.

Claims

1. A redundant via layout method, comprising: Obtaining a plurality of single vias between adjacent metal layers in an original chip physical layout; Determining a candidate redundant via for each of the single vias according to a preset chip design rule and the routing conditions of the metal lines connected by the plurality of single vias; For each of the single vias, selecting a redundant via with the highest priority for redundant via layout position and meeting the preset chip design rule from the candidate redundant vias of the single via, and the priority order of the redundant via layout positions from high to low is the direction of the lower-layer metal line along the line, the direction of the upper-layer metal line along the line, the direction of the upper-layer metal line away from the line, and the direction of the lower-layer metal line away from the line; Laying the selected redundant vias in the original chip physical layout.

2. The redundant via hole layout method according to claim 1, wherein, The step of, for each of the single vias, selecting a redundant via with the highest priority for redundant via layout position and meeting the preset chip design rule from the candidate redundant vias of the single via, includes: Selecting an along-line redundant via in the direction of the metal line routing from the candidate redundant vias of the plurality of single vias according to the metal line routing conditions of the adjacent metal layers in the original chip physical layout; Assuming that the along-line redundant via is laid in the original chip physical layout, selecting an off-line redundant via in the direction of the metal line routing from the candidate redundant vias of the single vias for which the redundant via has not been selected yet according to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout.

3. The redundant via hole layout method according to claim 2, wherein, The direction of the metal line routing along the line includes the direction of the lower-layer metal line along the line and the direction of the upper-layer metal line along the line. The step of, according to the metal line routing conditions of the adjacent metal layers in the original chip physical layout, selecting an along-line redundant via in the direction of the metal line routing from the candidate redundant vias of the plurality of single vias, includes: Selecting a candidate redundant via of the lower-layer metal line along the line in the direction of the lower-layer metal line routing from the candidate redundant vias of the plurality of single vias according to the metal line routing conditions of the metal lines connected by the plurality of single vias in the original chip physical layout; Selecting a redundant via of the lower-layer metal line along the line that meets the preset chip design rule from the candidate redundant vias of the lower-layer metal line along the line, covering the upper metal layer for the redundant via of the lower-layer metal line along the line, so that the redundant via of the lower-layer metal line along the line is connected to the adjacent upper metal layer and lower metal layer.

4. The redundant via hole layout method according to claim 3, wherein, The step of, according to the metal line routing conditions of the adjacent metal layers in the original chip physical layout, selecting an along-line redundant via in the direction of the metal line routing from the candidate redundant vias of the plurality of single vias, further includes: Assuming that the redundant via of the lower-layer metal line along the line is laid in the original chip physical layout, selecting a candidate redundant via of the upper-layer metal line along the line in the direction of the upper-layer metal line routing from the candidate redundant vias of the single vias for which the redundant via has not been selected yet according to the metal line routing conditions of the metal lines connected by the single vias in the assumed chip physical layout; Select the redundant vias for the upper metal line along the line that meet the preset chip design rules from the candidate redundant vias for the upper metal line along the line, and cover the lower metal layer for the redundant vias for the upper metal line along the line, so that the redundant vias for the upper metal line along the line are connected to the adjacent upper and lower metal layers.

5. The redundant via hole layout method according to claim 4, wherein The routing direction of the offline metal line includes the routing direction of the upper offline metal line and the routing direction of the lower offline metal line. Assume that the redundant vias along the line are arranged in the original chip physical layout. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select the offline redundant vias in the routing direction of the offline metal line from the candidate redundant vias of the single via for which the redundant vias have not been selected yet, including: Assume that the redundant vias along the line are arranged in the original chip physical layout. According to the metal line routing situation of the metal line connected by the single via in the assumed chip physical layout, select the candidate redundant vias for the upper offline metal line in the routing direction of the upper offline metal line from the candidate redundant vias of the single via for which the redundant vias have not been selected yet. Select the redundant vias for the upper offline metal line that meet the preset chip design rules from the candidate redundant vias for the upper offline metal line, and cover the upper and lower metal layers for the redundant vias for the upper offline metal line, so that the redundant vias for the upper offline metal line are connected to the adjacent upper and lower metal layers.

6. The redundant via hole layout method according to claim 5, wherein, Assume that the redundant vias along the line are arranged in the original chip physical layout. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select the offline redundant vias in the routing direction of the offline metal line from the candidate redundant vias of the single via for which the redundant vias have not been selected yet, and further include: Assume that the redundant vias along the line and the redundant vias for the upper offline metal line are arranged in the original chip physical layout. According to the metal line routing situation of the metal line connected by the single via in the assumed chip physical layout, select the candidate redundant vias for the lower offline metal line in the routing direction of the lower offline metal line from the candidate redundant vias of the single via for which the redundant vias have not been selected yet. Select the redundant vias for the lower offline metal line that meet the preset chip design rules from the candidate redundant vias for the lower offline metal line, and cover the upper and lower metal layers for the redundant vias for the lower offline metal line, so that the redundant vias for the lower offline metal line are connected to the adjacent upper and lower metal layers.

7. The redundant via layout method according to claim 6, wherein, The candidate redundant vias include the candidate redundant vias arranged in at least one of the first direction of the first coordinate axis, the second direction of the first coordinate axis, the first direction of the second coordinate axis, and the second direction of the second coordinate axis with the single via as the coordinate axis center. The second coordinate axis direction is the routing direction of the lower metal line along the line. The selection of the redundant vias for the lower metal line along the line that meet the preset chip design rules from the candidate redundant vias for the lower metal line along the line, and covering the upper metal layer for the redundant vias for the lower metal line along the line, so that the redundant vias for the lower metal line along the line are connected to the adjacent upper and lower metal layers, includes: Traverse the candidate redundant vias of the underlying metal lines along the first direction of the second coordinate axis. According to the metal line routing of the adjacent metal layers in the original chip physical layout, select the first redundant via of the underlying metal lines along the line that meets the preset chip design rules for the multiple single vias, and cover the upper metal layer for the first redundant via of the underlying metal lines along the line; Assume that the first redundant via of the underlying metal lines along the line is disposed in the original chip physical layout. Traverse the candidate redundant vias of the underlying metal lines along the line set in the second direction of the second coordinate axis. According to the metal line routing of the adjacent metal layers in the assumed chip physical layout, select the second redundant via of the underlying metal lines along the line that meets the preset chip design rules for the single vias for which redundant vias have not been selected yet, and cover the upper metal layer for the second redundant via of the underlying metal lines along the line; Assume that the first redundant via of the underlying metal lines along the line and the second redundant via of the underlying metal lines along the line are disposed in the original chip physical layout. Traverse the candidate redundant vias of the underlying metal lines along the line set in the first direction of the first coordinate axis. According to the metal line routing of the adjacent metal layers in the assumed chip physical layout, select the third redundant via of the underlying metal lines along the line that meets the preset chip design rules for the single vias for which redundant vias have not been selected yet, and cover the upper metal layer for the third redundant via of the underlying metal lines along the line; Assume that the first redundant via of the underlying metal lines along the line, the second redundant via of the underlying metal lines along the line, and the third redundant via of the underlying metal lines along the line are disposed in the original chip physical layout. Traverse the candidate redundant vias of the underlying metal lines along the line set in the second direction of the first coordinate axis. According to the metal line routing of the adjacent metal layers in the assumed chip physical layout, select the fourth redundant via of the underlying metal lines along the line that meets the chip design rules for the single vias for which redundant vias have not been selected yet, and cover the upper metal layer for the fourth redundant via of the underlying metal lines along the line.

8. The redundant via layout method according to claim 7, wherein, Selecting the redundant via of the upper metal lines along the line that meets the preset chip design rules from the candidate redundant vias of the upper metal lines along the line, and covering the lower metal layer for the redundant via of the upper metal lines along the line, so that the redundant via of the upper metal lines along the line is connected to the adjacent upper and lower metal layers, includes: Assume that the redundant via of the underlying metal lines along the line is disposed in the original chip physical layout. Traverse the candidate redundant vias of the upper metal lines along the line set in the first direction of the second coordinate axis. According to the metal line routing of the adjacent metal layers in the assumed chip physical layout, select the first redundant via of the upper metal lines along the line that meets the preset chip design rules for the single vias for which redundant vias have not been selected yet, and cover the lower metal layer for the first redundant via of the upper metal lines along the line; Assume that the redundant vias of the underlying metal lines along the line and the redundant vias of the upper metal lines along the first line are disposed in the original chip physical layout. Traverse the redundant via candidates of the upper metal lines along the line set in the second direction of the second coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select a redundant via of the upper metal line along the second line that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the lower metal layer for the redundant via of the upper metal line along the second line; Assume that the redundant vias of the underlying metal lines along the line, the redundant vias of the upper metal lines along the first line, and the redundant vias of the upper metal lines along the second line are disposed in the original chip physical layout. Traverse the redundant via candidates of the upper metal lines along the line set in the first direction of the first coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select a redundant via of the upper metal line along the third line that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the lower metal layer for the redundant via of the upper metal line along the third line; Assume that the redundant vias of the underlying metal lines along the line, the redundant vias of the upper metal lines along the first line, the redundant vias of the upper metal lines along the second line, and the redundant vias of the upper metal lines along the third line are disposed in the original chip physical layout. Traverse the redundant via candidates of the upper metal lines along the line set in the second direction of the first coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select a redundant via of the upper metal line along the fourth line that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the lower metal layer for the redundant via of the upper metal line along the fourth line.

9. The redundant via hole layout method according to claim 8, wherein, Selecting a redundant via of the upper metal line off the line that conforms to the preset chip design rules from the redundant via candidates of the upper metal line off the line, and covering the upper metal layer and the lower metal layer for the redundant via of the upper metal line off the line, so that the redundant via of the upper metal line off the line is connected to the adjacent upper metal layer and lower metal layer, includes: Assume that the redundant vias of the underlying metal lines along the line and the redundant vias of the upper metal lines along the line are disposed in the original chip physical layout. Traverse the redundant via candidates of the upper metal line off the line set in the first direction of the second coordinate axis. According to the metal line routing situation of the adjacent metal layers in the assumed chip physical layout, select a redundant via of the upper metal line off the line that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the redundant via of the upper metal line off the line; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, and the redundant vias for the first off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the off-line upper-layer metal lines arranged in the second direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a second off-line upper-layer metal line redundant via that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the second off-line upper-layer metal line redundant via; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, the redundant vias for the first off-line upper-layer metal lines, and the redundant vias for the second off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the off-line upper-layer metal lines arranged in the first direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a third off-line upper-layer metal line redundant via that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the third off-line upper-layer metal line redundant via; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, the redundant vias for the first off-line upper-layer metal lines, the redundant vias for the second off-line upper-layer metal lines, and the redundant vias for the third off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the off-line upper-layer metal lines arranged in the second direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a fourth off-line upper-layer metal line redundant via that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the fourth off-line upper-layer metal line redundant via.

10. The redundant via hole layout method according to claim 9, wherein, Selecting a redundant via for the lower-layer metal lines off the line that conforms to the preset chip design rules from the candidate redundant vias for the lower-layer metal lines off the line, and covering the upper metal layer and the lower metal layer for the redundant via for the lower-layer metal lines off the line, so that the redundant via for the lower-layer metal lines off the line is connected to the adjacent upper metal layer and lower metal layer, includes: Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, and the redundant vias for the off-line upper-layer metal lines are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower-layer metal lines off the line arranged in the first direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a first redundant via for the lower-layer metal lines off the line that conforms to the preset chip design rules for the single via that has not yet selected a redundant via, and cover the upper metal layer and the lower metal layer for the first redundant via for the lower-layer metal lines off the line; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, the redundant vias for the upper-layer metal lines off the line, and the redundant vias for the lower-layer metal lines of the first off-line are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower-layer metal lines off the line arranged in the second direction of the second coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a redundant via for the lower-layer metal lines of the second off-line that meets the preset chip design rules for the single via without a selected redundant via currently, and cover the upper metal layer and the lower metal layer for the redundant via for the lower-layer metal lines of the second off-line; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, the redundant vias for the upper-layer metal lines off the line, the redundant vias for the lower-layer metal lines of the first off-line, and the redundant vias for the lower-layer metal lines of the second off-line are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower-layer metal lines off the line arranged in the first direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a redundant via for the lower-layer metal lines of the third off-line that meets the preset chip design rules for the single via without a selected redundant via currently, and cover the upper metal layer and the lower metal layer for the redundant via for the lower-layer metal lines of the third off-line; Assume that the redundant vias for the lower-layer metal lines along the line, the redundant vias for the upper-layer metal lines along the line, the redundant vias for the upper-layer metal lines off the line, the redundant vias for the lower-layer metal lines of the first off-line, the redundant vias for the lower-layer metal lines of the second off-line, and the redundant vias for the lower-layer metal lines of the third off-line are disposed in the original chip physical layout. Traverse the candidate redundant vias for the lower-layer metal lines off the line arranged in the second direction of the first coordinate axis. According to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, select a redundant via for the lower-layer metal lines of the fourth off-line that meets the preset chip design rules for the single via without a selected redundant via currently, and cover the upper metal layer and the lower metal layer for the redundant via for the lower-layer metal lines of the fourth off-line.

11. The redundant via hole layout method according to claim 1, wherein, Before disposing the selected redundant vias in the original chip physical layout, the redundant via disposition method further includes: Performing data merging on the selected redundant vias and the original chip physical layout to perform verification of the preset chip design rules and electrical connections, and disposing the verified selected redundant vias in the original chip physical layout.

12. A redundant via disposition device, comprising: A single via acquisition unit, configured to acquire a plurality of single vias between adjacent metal layers in an original chip physical layout; A candidate redundant via determination unit, configured to determine candidate redundant vias for each of the single vias according to preset chip design rules and the metal line routing conditions of the metal lines connected by the plurality of single vias; A redundant via selection unit, configured to select, for the single via, a redundant via with the highest priority of redundant via layout position and meeting the preset chip design rules from the candidate redundant vias of the single via, wherein the priorities of the redundant via layout positions from high to low are the direction of the underlying metal line along the line, the direction of the upper metal line along the line, the direction of the upper metal line away from the line, and the direction of the underlying metal line away from the line; A redundant via layout unit, configured to layout the selected redundant via in the original chip physical layout.

13. An integrated circuit layout, which is implemented by using the steps of the method according to any one of claims 1 to 11.

14. An electronic device, comprising: A processor, a memory, and a program stored on the memory and executable on the processor, wherein when the program is executed by the processor, the steps of the method according to any one of claims 1 to 11 are implemented.

15. A storage medium, on which a computer program or instruction is stored, wherein when the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

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