Redundant via placement method, related apparatus, and storage medium

Abstract

The present disclosure provides a redundant via placement method, related device and storage medium. The method comprises: obtaining a plurality of single vias located between adjacent metal layers in an original chip physical layout; determining a candidate redundant via for each single via according to a preset chip design rule and a metal line routing condition connected by the plurality of single vias; for the single via, selecting a redundant via with the highest priority of redundant via placement position and meeting the preset chip design rule from the candidate redundant via of the single via, and the priority of the redundant via placement position is in a descending order of a direction along a lower layer metal line, a direction along an upper layer metal line, a direction away from the upper layer metal line and a direction away from the lower layer metal line; and placing the selected redundant via in the original chip physical layout. The present disclosure improves the insertion rate of the redundant via.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of integrated circuit design, and particularly relates to a redundant via layout method, related device and storage medium. BACKGROUND

[0002] With the continuous progress of chip manufacturing technology, the integration of transistors is increasingly improved, the feature size is gradually reduced, and the number of integrated transistors per unit area is significantly increased, which makes chip design and manufacturing face greater challenges. The inevitable process defects in the manufacturing process may cause the resistance of a single via to increase, and even cause electronic migration (EM), current distribution and voltage drop related via defects. Via defects will affect the chip function and reduce the chip yield and reliability. At present, in order to reduce via defects, the commonly used method is to insert a redundant via (also known as a double via). However, the existing manual insertion of redundant via method not only consumes time and effort, but also lacks consistency, resulting in a low insertion rate of redundant via. In addition, although some automatic layout and routing tools provide the function of inserting redundant via, these tools usually cannot insert redundant via in all possible areas, which limits the insertion rate of redundant via. SUMMARY

[0003] In view of the above problems, the embodiments of the present disclosure provide a redundant via layout method, related device and storage medium, aiming to improve the insertion rate of redundant via.

[0004] According to a first aspect of the embodiments of the present disclosure, a redundant via layout method is provided, comprising:

[0005] Obtaining a plurality of single vias located between adjacent metal layers in a physical layout of an original chip;

[0006] According to a preset chip design rule and a metal line routing condition connected with the plurality of single vias, determining a candidate redundant via for each single via;

[0007] For the single via, selecting a redundant via with the highest priority of redundant via layout position and meeting the preset chip design rule from the candidate redundant via of the single via, and the priority of redundant via layout position is in a descending order of a direction along a lower layer metal line of the line, a direction along an upper layer metal line of the line, a direction away from the upper layer metal line of the line and a direction away from the lower layer metal line of the line;

[0008] Laying the selected redundant via in the physical layout of the original chip.

[0009] Optionally, the selecting, from the candidate redundant vias of the single via, a redundant via with the highest priority and meeting the preset chip design rule, comprises:

[0010] According to the metal line routing of the adjacent metal layer in the original chip physical layout, selecting, from the candidate redundant vias of the single via, an on-line redundant via in the on-line metal line routing direction.

[0011] Supposing that the on-line redundant via is arranged in the original chip physical layout, according to the metal line routing of the adjacent metal layer in the supposing chip physical layout, selecting, from the candidate redundant vias of the single via, an off-line redundant via in the off-line metal line routing direction.

[0012] Optionally, the on-line metal line routing direction comprises an on-line lower metal line routing direction and an on-line upper metal line routing direction, and the selecting, from the candidate redundant vias of the single via, an on-line redundant via in the on-line metal line routing direction, comprises:

[0013] According to the metal line routing of the adjacent metal layer in the original chip physical layout, selecting, from the candidate redundant vias of the single via, an on-line redundant via in the on-line metal line routing direction.

[0014] According to the metal line routing of the adjacent metal layer in the original chip physical layout, selecting, from the candidate redundant vias of the single via, an on-line redundant via in the on-line metal line routing direction.

[0015] Optionally, the selecting, from the candidate redundant vias of the single via, an on-line redundant via in the on-line metal line routing direction, further comprises:

[0016] Supposing that the on-line redundant via is arranged in the original chip physical layout, according to the metal line routing of the adjacent metal layer in the supposing chip physical layout, selecting, from the candidate redundant vias of the single via, an off-line redundant via in the off-line metal line routing direction.

[0017] selecting, from the candidate redundant via of the single via, an off-line redundant via of an off-line metal line routing direction according to a metal line routing condition of the adjacent metal layer in the assumed chip physical layout;

[0018] Optionally, the off-line metal line routing direction includes an off-line upper metal line routing direction and an off-line lower metal line routing direction,

[0019] The assumption that the on-line redundant via is arranged in the original chip physical layout, according to the metal line routing condition of the single via connected in the assumed chip physical layout, an off-line upper metal line candidate redundant via of an off-line upper metal line routing direction is selected from the candidate redundant via of the single via which is not currently selected.

[0020] The assumption that the on-line redundant via is arranged in the original chip physical layout, according to the metal line routing condition of the single via connected in the assumed chip physical layout, an off-line upper metal line candidate redundant via of an off-line upper metal line routing direction is selected from the candidate redundant via of the single via which is not currently selected.

[0021] The assumption that the on-line redundant via is arranged in the original chip physical layout, according to the metal line routing condition of the single via connected in the assumed chip physical layout, an off-line upper metal line candidate redundant via of an off-line upper metal line routing direction is selected from the candidate redundant via of the single via which is not currently selected.

[0022] Optionally, the assumption that the on-line redundant via is arranged in the original chip physical layout, according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, an off-line redundant via of an off-line metal line routing direction is selected from the candidate redundant via of the single via which is not currently selected.

[0023] The assumption that the on-line redundant via and the off-line upper metal line redundant via are arranged in the original chip physical layout, according to the metal line routing condition of the single via connected in the assumed chip physical layout, an off-line lower metal line candidate redundant via of an off-line lower metal line routing direction is selected from the candidate redundant via of the single via which is not currently selected.

[0024] The assumption that the on-line redundant via and the off-line upper metal line redundant via are arranged in the original chip physical layout, according to the metal line routing condition of the single via connected in the assumed chip physical layout, an off-line lower metal line candidate redundant via of an off-line lower metal line routing direction is selected from the candidate redundant via of the single via which is not currently selected.

[0025] Optionally, the candidate redundant via includes a candidate redundant via arranged in at least one of a first coordinate axis first direction, a first coordinate axis second direction, a second coordinate axis first direction and a second coordinate axis second direction, with the single via as the coordinate axis center, the second coordinate axis direction being along the lower layer metal line trace direction,

[0026] The method further includes: selecting, from the candidate redundant vias along the lower layer metal line, a redundant via along the lower layer metal line that meets the preset chip design rule, and covering the redundant via along the lower layer metal line with an upper metal layer, so that the redundant via along the lower layer metal line is connected with adjacent upper and lower metal layers.

[0027] The method further includes: traversing the candidate redundant vias along the lower layer metal line arranged in the second coordinate axis first direction, and selecting, according to the metal line trace of the adjacent metal layer in the original chip physical layout, a first redundant via along the lower layer metal line that meets the preset chip design rule for the single via, and covering the first redundant via along the lower layer metal line with an upper metal layer.

[0028] The method further includes: assuming that the first redundant via along the lower layer metal line is arranged in the original chip physical layout, traversing the candidate redundant vias along the lower layer metal line arranged in the second coordinate axis second direction, and selecting, according to the metal line trace of the adjacent metal layer in the assumed chip physical layout, a second redundant via along the lower layer metal line that meets the preset chip design rule for the single via that has not been selected as a redundant via, and covering the second redundant via along the lower layer metal line with an upper metal layer.

[0029] The method further includes: assuming that the first redundant via along the lower layer metal line and the second redundant via along the lower layer metal line are arranged in the original chip physical layout, traversing the candidate redundant vias along the lower layer metal line arranged in the first coordinate axis first direction, and selecting, according to the metal line trace of the adjacent metal layer in the assumed chip physical layout, a third redundant via along the lower layer metal line that meets the preset chip design rule for the single via that has not been selected as a redundant via, and covering the third redundant via along the lower layer metal line with an upper metal layer.

[0030] The method further includes: assuming that the first redundant via along the lower layer metal line, the second redundant via along the lower layer metal line and the third redundant via along the lower layer metal line are arranged in the original chip physical layout, traversing the candidate redundant vias along the lower layer metal line arranged in the first coordinate axis second direction, and selecting, according to the metal line trace of the adjacent metal layer in the assumed chip physical layout, a fourth redundant via along the lower layer metal line that meets the preset chip design rule for the single via that has not been selected as a redundant via, and covering the fourth redundant via along the lower layer metal line with an upper metal layer.

[0031] Optionally, the selecting, from the candidate redundant vias along the upper metal lines, a redundant via along the upper metal lines that meets the preset chip design rule, and covering the lower metal layer with the redundant via along the upper metal lines, so that the redundant via along the upper metal lines is connected to the adjacent upper metal layer and the lower metal layer, includes:

[0032] Assuming that the redundant through holes along the lower metal lines are arranged in the original chip physical layout, traversing the candidate redundant through holes along the upper metal lines arranged in the first direction of the second coordinate axis, selecting a first redundant through hole along the upper metal line that meets the preset chip design rules for the single through hole for which no redundant through hole is currently selected, and covering the lower metal layer with the first redundant through hole along the upper metal line;

[0033] Assuming that the redundant through hole along the lower metal line and the first redundant through hole along the upper metal line are arranged in the original chip physical layout, traversing the candidate redundant through holes along the upper metal line arranged in the second direction of the second coordinate axis, selecting a second redundant through hole along the upper metal line that complies with the preset chip design rule for the single through hole for which no redundant through hole is currently selected, and covering the lower metal layer with the second redundant through hole along the upper metal line;

[0034] Assuming that the redundant vias along the lower metal lines, the first redundant vias along the upper metal lines, and the second redundant vias along the upper metal lines are arranged in the original chip physical layout, traversing the candidate redundant vias along the upper metal lines arranged in the first direction of the first coordinate axis, selecting a third redundant via along the upper metal lines that complies with the preset chip design rules for the single via currently unselected, based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, and covering the lower metal layer with the third redundant via along the upper metal lines;

[0035] Assuming that the redundant through holes along the lower metal lines, the first redundant through holes along the upper metal lines, the second redundant through holes along the upper metal lines, and the third redundant through holes along the upper metal lines are arranged in the original chip physical layout, the candidate redundant through holes along the upper metal lines arranged in the second direction of the first coordinate axis are traversed, and according to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, a fourth redundant through hole along the upper metal lines that complies with the preset chip design rules is selected for the single through hole for which a redundant through hole is not currently selected, and the fourth redundant through hole along the upper metal lines covers the lower metal layer.

[0036] Optionally, the selecting the offline upper metal line redundant via candidate that meets the preset chip design rule from the offline upper metal line redundant via candidate, covering the upper metal layer and the lower metal layer for the offline upper metal line redundant via, so that the offline upper metal line redundant via is connected with the adjacent upper metal layer and the lower metal layer, comprises:

[0037] Supposing that the along-line lower metal line redundant via and the along-line upper metal line redundant via are arranged in the original chip physical layout, traversing the offline upper metal line candidate redundant via arranged in the first direction of the second coordinate axis, selecting the first offline upper metal line redundant via that meets the preset chip design rule for the single via of the current unselected redundant via according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, covering the upper metal layer and the lower metal layer for the first offline upper metal line redundant via;

[0038] Supposing that the along-line lower metal line redundant via, the along-line upper metal line redundant via and the first offline upper metal line redundant via are arranged in the original chip physical layout, traversing the offline upper metal line candidate redundant via arranged in the second direction of the second coordinate axis, selecting the second offline upper metal line redundant via that meets the preset chip design rule for the single via of the current unselected redundant via according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, covering the upper metal layer and the lower metal layer for the second offline upper metal line redundant via;

[0039] Supposing that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the first offline upper metal line redundant via and the second offline upper metal line redundant via are arranged in the original chip physical layout, traversing the offline upper metal line candidate redundant via arranged in the first direction of the first coordinate axis, selecting the third offline upper metal line redundant via that meets the preset chip design rule for the single via of the current unselected redundant via according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, covering the upper metal layer and the lower metal layer for the third offline upper metal line redundant via;

[0040] Supposing that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the first off-line upper metal line redundant via, the second off-line upper metal line redundant via and the third off-line upper metal line redundant via are arranged in the original chip physical layout, the off-line upper metal line candidate redundant via arranged in the first direction of the first coordinate axis is traversed, and according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, a fourth off-line upper metal line redundant via meeting the preset chip design rule is selected for the single via of the current unselected redundant via, and the fourth off-line upper metal line redundant via is covered with an upper metal layer and a lower metal layer.

[0041] Optionally, the off-line lower metal line redundant via meeting the preset chip design rule is selected from the off-line lower metal line candidate redundant via, and the off-line lower metal line redundant via is covered with an upper metal layer and a lower metal layer, so that the off-line lower metal line redundant via is connected with adjacent upper and lower metal layers, and the method comprises the following steps.

[0042] Supposing that the along-line lower metal line redundant via, the along-line upper metal line redundant via and the off-line upper metal line redundant via are arranged in the original chip physical layout, the off-line lower metal line candidate redundant via arranged in the first direction of the second coordinate axis is traversed, and according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, a first off-line lower metal line redundant via meeting the preset chip design rule is selected for the single via of the current unselected redundant via, and the first off-line lower metal line redundant via is covered with an upper metal layer and a lower metal layer.

[0043] Supposing that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the off-line upper metal line redundant via and the first off-line lower metal line redundant via are arranged in the original chip physical layout, the off-line lower metal line candidate redundant via arranged in the second direction of the second coordinate axis is traversed, and according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, a second off-line lower metal line redundant via meeting the preset chip design rule is selected for the single via of the current unselected redundant via, and the second off-line lower metal line redundant via is covered with an upper metal layer and a lower metal layer.

[0044] Suppose that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the off-line upper metal line redundant via, the first off-line lower metal line redundant via and the second off-line lower metal line redundant via are arranged in the original chip physical layout, the off-line lower metal line candidate redundant via arranged in the first direction of the first coordinate axis is traversed, and according to the metal line routing of the adjacent metal layer in the assumed chip physical layout, a third off-line lower metal line redundant via meeting the preset chip design rule is selected for the single via of the current unselected redundant via, and the third off-line lower metal line redundant via is covered with an upper metal layer and a lower metal layer.

[0045] Suppose that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the off-line upper metal line redundant via, the first off-line lower metal line redundant via, the second off-line lower metal line redundant via and the third off-line lower metal line redundant via are arranged in the original chip physical layout, the off-line lower metal line candidate redundant via arranged in the second direction of the first coordinate axis is traversed, and according to the metal line routing of the adjacent metal layer in the assumed chip physical layout, a fourth off-line lower metal line redundant via meeting the preset chip design rule is selected for the single via of the current unselected redundant via, and the fourth off-line lower metal line redundant via is covered with an upper metal layer and a lower metal layer.

[0046] Optionally, before the selected redundant via is arranged in the original chip physical layout, the redundant via arrangement method further comprises:

[0047] The selected redundant via is combined with the original chip physical layout for data to verify the preset chip design rule and electrical connection, and the selected redundant via that passes the verification is arranged in the original chip physical layout.

[0048] According to a second aspect of the embodiments of the present disclosure, a redundant via arrangement device is provided, comprising:

[0049] A single via acquisition unit is configured to acquire a plurality of single vias between adjacent metal layers in an original chip physical layout.

[0050] A candidate redundant via determination unit is configured to determine a candidate redundant via of each single via according to a preset chip design rule and a metal line routing connected by the single via.

[0051] The redundant via selection unit is configured to select, for the single via, a redundant via with the highest redundant via layout priority and meeting the preset chip design rule from candidate redundant vias of the single via, the redundant via layout priority being in a descending order of a direction along a lower metal line, a direction along an upper metal line, a direction away from the upper metal line, and a direction away from the lower metal line.

[0052] The redundant via layout unit is configured to layout the selected redundant via in the original chip physical layout.

[0053] According to a third aspect of the embodiments of the present disclosure, an electronic device is provided, which includes a processor, a memory, and a program stored in the memory and executable on the processor, and when the program is executed by the processor, the steps of the method described above are implemented.

[0054] According to a fourth aspect of the embodiments of the present disclosure, a storage medium is provided, which stores a computer program or instructions, and when the computer program or instructions are executed by a processor, the steps of the method described above are implemented.

[0055] The embodiments of the present disclosure have the following beneficial effects:

[0056] The redundant via layout method provided by the embodiments of the present disclosure selects, for a single via, a redundant via with the highest redundant via layout priority and meeting the preset chip design rule from candidate redundant vias of the single via, the redundant via layout priority being in a descending order of a direction along a lower metal line, a direction along an upper metal line, a direction away from the upper metal line, and a direction away from the lower metal line, which ensures that the redundant via is laid out along the original metal line in priority under the premise of meeting the preset chip design rule, without increasing additional wire winding, reduces the situation that the redundant via cannot be inserted due to metal line layout limitation, improves the insertion rate of the redundant via, and effectively utilizes the high manufacturing precision and high connection reliability of the lower metal line, further reducing the risk of single via failure.

[0057] Other features and advantages of the embodiments of the present disclosure will be described in the following description and, in part, will become apparent to those skilled in the art, and will be learned, in part, from the practice of the embodiments of the present disclosure. The purposes and other advantages of the embodiments of the present disclosure will be achieved and obtained by the structures particularly pointed out in the description and the accompanying drawings.

[0058] In order to make the above objectives, features and advantages of the embodiments of the present disclosure more apparent, the following will specifically describe preferred embodiments in combination with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0059] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0060] Figure 1 A flowchart of a method for providing a redundant via according to an embodiment of the present disclosure;

[0061] Figure 2A A layout diagram of a square candidate redundant via according to an embodiment of the present disclosure;

[0062] Figure 2B A layout diagram of a rectangular candidate redundant via according to an embodiment of the present disclosure;

[0063] Figure 3A A layout diagram of a redundant via along an underlayer metal line according to an embodiment of the present disclosure;

[0064] Figure 3B A layout diagram of a redundant via along an underlayer metal line according to another embodiment of the present disclosure;

[0065] Figure 3C A layout diagram of a redundant via along an overlayer metal line according to an embodiment of the present disclosure;

[0066] Figure 4A A layout diagram of a redundant via off an overlayer metal line according to an embodiment of the present disclosure;

[0067] Figure 4B A layout diagram of a redundant via off an overlayer metal line according to another embodiment of the present disclosure;

[0068] Figure 4C A layout diagram of a redundant via off an underlayer metal line according to an embodiment of the present disclosure;

[0069] Figure 5 A flowchart of a layer-by-layer traversal method for providing a redundant via according to an embodiment of the present disclosure;

[0070] Figure 6 A structure diagram of a redundant via providing apparatus according to an embodiment of the present disclosure;

[0071] Figure 7 A structure diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] Various embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals for the sake of clarity.

[0073] In this article,

[0074] Single via, refers to a single conductive via used to connect different metal layers during chip manufacturing process.

[0075] Redundant via, also known as double via or redundant via, refers to an additional via added next to a single via, aiming to improve the manufacturing yield and reliability of the chip, and reduce the risk of performance degradation or loss of function of the chip due to failure of the single via.

[0076] On track, refers to the insertion position of the redundant via in the chip physical layout being consistent with the direction of the metal line connected by the single via.

[0077] Off track, refers to the insertion position of the redundant via in the chip physical layout being inconsistent with the direction of the metal line connected by the single via.

[0078] Figure 1 A flowchart of a redundant via layout method according to an embodiment of the present disclosure is provided. As shown in Figure 1 The redundant via layout method of the embodiment of the present disclosure includes:

[0079] In step S110, a plurality of single vias between adjacent metal layers in the original chip physical layout are obtained.

[0080] In some embodiments, a plurality of metal layers are provided in the original chip physical layout (e.g., digital or analog back-end layout), and the adjacent metal layers here can be any two adjacent metal layers in the plurality of metal layers. The redundant via layout method of the embodiment of the present disclosure can be performed on each two adjacent metal layers provided in the original chip physical layout, and a redundant via is inserted for each single via provided between the two adjacent metal layers. In some embodiments, in the original chip physical layout, a plurality of single vias between adjacent metal layers are selected according to design rules. It should be noted that the single via in the embodiment of the present disclosure refers to a via that needs to add a redundant via. Generally, the single via here includes a square single via, but does not include a rectangular single via. Since the effect of a rectangular single via is equal to or better than that of two square single vias, the rectangular single via in the original chip physical layout is not selected as the range that needs to add a redundant via.

[0081] In step S120, a candidate redundant via for each single via is determined according to a preset chip design rule and a metal line routing condition connected by the single via.

[0082] In some embodiments, for each single through-hole, redundant through-holes can be set along the first direction of the first coordinate axis (for example, the negative direction of the x-axis), the second direction of the first coordinate axis (for example, the positive direction of the x-axis), the first direction of the second coordinate axis (for example, the positive direction of the y-axis), and the second direction of the second coordinate axis (for example, the negative direction of the y-axis) with the single through-hole as the coordinate axis center. In some embodiments, candidate redundant through-holes for the single through-hole are determined based on chip design rules (for example, hole spacing (Space) and side length (Width)) and the routing of metal wires connected to the single through-hole. The candidate redundant through-holes may include candidate redundant through-holes set in at least one direction of the first coordinate axis (for example, the negative direction of the x-axis), the second direction of the first coordinate axis (for example, the positive direction of the x-axis), the first direction of the second coordinate axis (for example, the positive direction of the y-axis), and the second direction of the second coordinate axis (for example, the negative direction of the y-axis) with the single through-hole as the coordinate axis center. In some embodiments, based on the process provided by the wafer fab, the candidate redundant through-holes for the single through-hole can be divided into the following categories: Figure 2A The square through holes shown and Figure 2B As shown in the rectangular through hole. Figure 2A As shown in Figure 2B, adjacent metal layers include a lower metal layer Mn and an upper metal layer M(n+1) (where n is the sequence number of the metal layer and is a positive integer greater than 0), and a single through-hole is provided between the lower metal layer Mn and the upper metal layer M(n+1). With the single through-hole as the center of the coordinate axis, there are four candidate redundant through-holes on the left, right, upper, and lower directions, respectively, in the negative x-axis direction, x+, positive x-axis direction, y+, and negative y-axis direction. Figure 2A As shown in the figure, inserting a square redundant through hole around a single through hole means inserting a through hole of the same size next to the single through hole with sufficient hole spacing. Figure 2B As shown in the figure, adding rectangular redundant vias is done by inserting and merging vias of the same size next to a single via at zero distance. When the fab process allows, rectangular redundant vias are preferred because they take up less metal line routing space than adding square redundant vias.

[0083] In step S130, for the single through hole, a redundant through hole with the highest priority in redundant through hole layout position and complying with the preset chip design rules is selected from the candidate redundant through holes of the single through hole, and the order of priority in redundant through hole layout position from high to low is along the direction of the offline lower metal line, along the direction of the online upper metal line, along the direction of the offline upper metal line and along the direction of the offline lower metal line.

[0084] In some embodiments, the metal lines in adjacent metal layers have different orientations. For example, the lower metal lines have a horizontal or vertical orientation, and the upper metal lines have a vertical or horizontal orientation. According to the orientations of the metal lines in the adjacent metal layers in the original chip physical layout, a redundant via is selected from the candidate redundant vias of the plurality of single vias, which has the highest priority of the layout position and meets the preset chip design rule. Specifically, the on-track metal line orientation is given priority, and the on-track lower metal line (On track Mn) orientation is further given priority, because the lower metal lines usually have higher manufacturing precision and connection reliability, especially in standard cell, RF or analog design. Once the layout of the bottom metal line (such as M1) is determined, it is often difficult to change. The priority of the layout position of the redundant via is in the order of on-track lower metal line, on-track upper metal line, off-track upper metal line, and off-track lower metal line from high to low.

[0085] In some embodiments, according to the metal line routing of the adjacent metal layers in the original chip physical layout, an on-track redundant via is selected from the candidate redundant vias of the plurality of single vias in the on-track metal line routing direction. The on-track metal line routing direction includes an on-track lower metal line routing direction (On track Mn) and an on-track upper metal line routing direction (On track M(n+1)). In some embodiments, according to the metal line routing of the plurality of single vias in the original chip physical layout, an on-track lower metal line candidate redundant via is selected from the candidate redundant vias of the plurality of single vias in the on-track lower metal line routing direction. An on-track lower metal line redundant via that meets the preset chip design rule is selected from the on-track lower metal line candidate redundant via, and an upper metal layer is covered on the on-track lower metal line redundant via, so that the on-track lower metal line redundant via is connected with the adjacent upper metal layer and lower metal layer. In some embodiments, taking the second coordinate axis direction (for example, the y-axis direction) as the on-track lower metal line routing direction, in some embodiments, taking the second coordinate axis direction as the on-track lower metal line routing direction, the on-track lower metal line candidate redundant via arranged in the first direction of the second coordinate axis is traversed, according to the metal line routing of the adjacent metal layers in the original chip physical layout, an first on-track lower metal line redundant via that meets the preset chip design rule is selected for the plurality of single vias, and an upper metal layer is covered on the first on-track lower metal line redundant via. Assuming that the first on-track lower metal line redundant via is arranged in the original chip physical layout, the on-track lower metal line candidate redundant via arranged in the second direction of the second coordinate axis is traversed, according to the metal line routing of the adjacent metal layers in the assumed chip physical layout, a second on-track lower metal line redundant via that meets the preset chip design rule is selected for the single via that is not currently selected as a redundant via, and an upper metal layer is covered on the second on-track lower metal line redundant via. Assuming that the first on-track lower metal line redundant via and the second on-track lower metal line redundant via are arranged in the original chip physical layout, the on-track lower metal line candidate redundant via arranged in the first direction of the first coordinate axis is traversed, according to the metal line routing of the adjacent metal layers in the assumed chip physical layout, a third on-track lower metal line redundant via that meets the preset chip design rule is selected for the single via that is not currently selected as a redundant via, and an upper metal layer is covered on the third on-track lower metal line redundant via. Assuming that the first on-track lower metal line redundant via, the second on-track lower metal line redundant via and the third on-track lower metal line redundant via are arranged in the original chip physical layout, the on-track lower metal line candidate redundant via arranged in the second direction of the first coordinate axis is traversed, according to the metal line routing of the adjacent metal layers in the assumed chip physical layout, a fourth on-track lower metal line redundant via that meets the preset chip design rule is selected for the single via that is not currently selected as a redundant via, and an upper metal layer is covered on the fourth on-track lower metal line redundant via.

[0086] Figure 3AA layout diagram of a redundant via along an under-layer metal line according to one embodiment of the present disclosure is provided. As shown in Figure 3A According to the metal line routing of the single via connected in the original chip physical layout, there is enough space to set up a redundant via along the under-layer metal line routing direction and the over-layer metal line routing direction. Here, the candidate redundant via along the under-layer metal line is selected first, and the redundant via along the under-layer metal line that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the candidate redundant via above the single via set up in the first direction of the second coordinate axis is selected, and the over-layer metal layer is covered for the candidate redundant via. Figure 3B A layout diagram of a redundant via along an under-layer metal line according to another embodiment of the present disclosure is provided. As shown in Figure 3B According to the metal line routing of the single via connected in the original chip physical layout, there is enough space to set up a redundant via along the under-layer metal line routing direction. Here, the candidate redundant via along the under-layer metal line is selected first, and the redundant via along the under-layer metal line that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the candidate redundant via above the single via set up in the first direction of the second coordinate axis is selected, and the over-layer metal layer is covered for the candidate redundant via.

[0087] In some embodiments, assuming that the redundant via along the under-layer metal line is set up in the original chip physical layout, according to the metal line routing of the single via connected in the assumed chip physical layout, the candidate redundant via along the over-layer metal line along the over-layer metal line routing direction is selected from the candidate redundant via of the single via that is not selected currently. The redundant via along the over-layer metal line that meets the preset chip design rule is selected from the candidate redundant via along the over-layer metal line, and the under-layer metal layer is covered for the redundant via along the over-layer metal line, so that the redundant via along the over-layer metal line is connected with the adjacent over-layer metal layer and under-layer metal layer.

[0088] In some embodiments, taking the along-line lower metal line trace direction in the second coordinate axis direction (for example, the y-axis direction) as an example, in some embodiments, assuming that the along-line lower metal line redundant via is arranged in the original chip physical layout, traversing the along-line upper metal line candidate redundant via arranged in the first direction of the second coordinate axis, according to the metal line trace condition of the adjacent metal layer in the assumed chip physical layout, a first along-line upper metal line redundant via that meets the preset chip design rule is selected for the single via that is not currently selected as a redundant via, and the first along-line upper metal line redundant via covers the lower metal layer. Assuming that the along-line lower metal line redundant via and the first along-line upper metal line redundant via are arranged in the original chip physical layout, traversing the along-line upper metal line candidate redundant via arranged in the second direction of the second coordinate axis, according to the metal line trace condition of the adjacent metal layer in the assumed chip physical layout, a second along-line upper metal line redundant via that meets the preset chip design rule is selected for the single via that is not currently selected as a redundant via, and the second along-line upper metal line redundant via covers the lower metal layer. Assuming that the along-line lower metal line redundant via, the first along-line upper metal line redundant via, and the second along-line upper metal line redundant via are arranged in the original chip physical layout, traversing the along-line upper metal line candidate redundant via arranged in the first direction of the first coordinate axis, according to the metal line trace condition of the adjacent metal layer in the assumed chip physical layout, a third along-line upper metal line redundant via that meets the preset chip design rule is selected for the single via that is not currently selected as a redundant via, and the third along-line upper metal line redundant via covers the lower metal layer. Assuming that the along-line lower metal line redundant via, the first along-line upper metal line redundant via, the second along-line upper metal line redundant via, and the third along-line upper metal line redundant via are arranged in the original chip physical layout, traversing the along-line upper metal line candidate redundant via arranged in the second direction of the first coordinate axis, according to the metal line trace condition of the adjacent metal layer in the assumed chip physical layout, a fourth along-line upper metal line redundant via that meets the preset chip design rule is selected for the single via that is not currently selected as a redundant via, and the fourth along-line upper metal line redundant via covers the lower metal layer.

[0089] Figure 3C A layout diagram of the along-line upper metal line redundant via according to one embodiment of the present disclosure is provided. As shown in Figure 3C According to the metal line trace condition of the single via connected in the original chip physical layout, there is enough space to insert a redundant via in the along-line upper metal line trace direction, here, the along-line upper metal line candidate redundant via is preferentially selected, and the along-line upper metal line redundant via that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the left candidate redundant via arranged in the first direction of the first coordinate axis of the single via is selected, and the lower metal layer is covered.

[0090] In some embodiments, assuming that the along-track redundant via is disposed in the original chip physical layout, an off-track redundant via is selected from the single-hole candidate redundant vias of the current unselected redundant via according to the metal line routing of the adjacent metal layer in the assumed chip physical layout. In some embodiments, the off-track metal line routing includes an off-track upper metal line routing (Off track M(n+1)) and an off-track lower metal line routing (Off track Mn). Assuming that the along-track redundant via is disposed in the original chip physical layout, an off-track upper metal line candidate redundant via of the off-track upper metal line routing is selected from the single-hole candidate redundant vias of the current unselected redundant via according to the metal line routing connected by the single-hole in the assumed chip physical layout. An off-track upper metal line redundant via that meets the preset chip design rule is selected from the off-track upper metal line candidate redundant via, and the upper metal layer and the lower metal layer are covered for the off-track upper metal line redundant via, so that the off-track upper metal line redundant via is connected with the adjacent upper metal layer and lower metal layer.

[0091] In some embodiments, taking the along-line lower metal line routing direction as an example in the second coordinate axis direction (e.g., the y-axis direction), assuming that the along-line lower metal line redundant via and the along-line upper metal line redundant via are arranged in the original chip physical layout, traversing the off-line upper metal line candidate redundant via arranged in the first direction of the second coordinate axis, according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, selecting a first off-line upper metal line redundant via that meets the preset chip design rule for the single via that is not currently selected as the redundant via, and covering the upper metal layer and the lower metal layer for the first off-line upper metal line redundant via. Assuming that the along-line lower metal line redundant via, the along-line upper metal line redundant via, and the first off-line upper metal line redundant via are arranged in the original chip physical layout, traversing the off-line upper metal line candidate redundant via arranged in the second direction of the second coordinate axis, according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, selecting a second off-line upper metal line redundant via that meets the preset chip design rule for the single via that is not currently selected as the redundant via, and covering the upper metal layer and the lower metal layer for the second off-line upper metal line redundant via. Assuming that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the first off-line upper metal line redundant via, and the second off-line upper metal line redundant via are arranged in the original chip physical layout, traversing the off-line upper metal line candidate redundant via arranged in the first direction of the first coordinate axis, according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, selecting a third off-line upper metal line redundant via that meets the preset chip design rule for the single via that is not currently selected as the redundant via, and covering the upper metal layer and the lower metal layer for the third off-line upper metal line redundant via. Assuming that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the first off-line upper metal line redundant via, the second off-line upper metal line redundant via, and the third off-line upper metal line redundant via are arranged in the original chip physical layout, traversing the off-line upper metal line candidate redundant via arranged in the second direction of the first coordinate axis, according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, selecting a fourth off-line upper metal line redundant via that meets the preset chip design rule for the single via that is not currently selected as the redundant via, and covering the upper metal layer and the lower metal layer for the fourth off-line upper metal line redundant via.

[0092] Figure 4A A layout schematic diagram of the off-line upper metal line redundant via according to one embodiment of the present disclosure is provided. As shown in FIG. 6, the along-line lower metal line redundant via 601, the along-line upper metal line redundant via 602, the first off-line upper metal line redundant via 603, the second off-line upper metal line redundant via 604, the third off-line upper metal line redundant via 605, and the fourth off-line upper metal line redundant via 606 are arranged in the original chip physical layout. Figure 4AAs shown, according to the metal line routing condition of the single via connected in the original chip physical layout, there is enough space to insert a redundant via in the off-track lower metal line routing direction (Off track Mn) and the off-track upper metal line routing direction. Here, the off-track upper metal line routing candidate redundant via is preferentially selected, and a redundant via along the lower metal line that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the left candidate redundant via set in the first direction of the first coordinate axis of the single via is selected, and the upper and lower metal layers are covered. Figure 4B A layout diagram of an off-track upper metal line redundant via provided according to yet another embodiment of the present disclosure is shown in FIG. 16. As shown in FIG. 16, according to the metal line routing condition of the single via connected in the original chip physical layout, there is enough space to insert a redundant via in the off-track upper metal line routing direction. Here, the off-track upper metal line routing candidate redundant via is preferentially selected, and a redundant via along the lower metal line that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the left candidate redundant via set in the first direction of the first coordinate axis of the single via is selected, and the upper and lower metal layers are covered. Figure 4B As shown, according to the metal line routing condition of the single via connected in the original chip physical layout, there is enough space to insert a redundant via in the off-track upper metal line routing direction. Here, the off-track upper metal line routing candidate redundant via is preferentially selected, and a redundant via along the lower metal line that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis, and the second direction of the first coordinate axis. Therefore, the left candidate redundant via set in the first direction of the first coordinate axis of the single via is selected, and the upper and lower metal layers are covered.

[0093] In some embodiments, assuming that the on-track redundant via and the off-track upper metal line redundant via are arranged in the original chip physical layout, according to the metal line routing condition of the single via connected in the assumed chip physical layout, an off-track lower metal line candidate redundant via in the off-track lower metal line routing direction is selected from the candidate redundant via of the single via that is not currently selected. A redundant via along the lower metal line that meets the preset chip design rule is selected from the off-track lower metal line candidate redundant via, and the upper metal layer and the lower metal layer are covered for the off-track lower metal line redundant via, so that the off-track lower metal line redundant via is connected with the adjacent upper metal layer and lower metal layer.

[0094] In some embodiments, taking the direction of the second coordinate axis (for example, the y-axis direction) as an example, assuming that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the off-line upper metal line redundant via, and the first off-line lower metal line redundant via are arranged in the original chip physical layout, the second off-line lower metal line candidate redundant via arranged in the second coordinate axis first direction is traversed, and according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, the second off-line lower metal line redundant via that meets the preset chip design rule is selected for the single via of the current unselected redundant via, and the upper metal layer and the lower metal layer are covered for the second off-line lower metal line redundant via. Assuming that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the off-line upper metal line redundant via, the first off-line lower metal line redundant via, and the second off-line lower metal line redundant via are arranged in the original chip physical layout, the off-line lower metal line candidate redundant via arranged in the first coordinate axis first direction is traversed, and according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, the third off-line lower metal line redundant via that meets the preset chip design rule is selected for the single via of the current unselected redundant via, and the upper metal layer and the lower metal layer are covered for the third off-line lower metal line redundant via. Assuming that the along-line lower metal line redundant via, the along-line upper metal line redundant via, the off-line upper metal line redundant via, the first off-line lower metal line redundant via, the second off-line lower metal line redundant via, and the third off-line lower metal line redundant via are arranged in the original chip physical layout, the off-line lower metal line candidate redundant via arranged in the first coordinate axis second direction is traversed, and according to the metal line routing condition of the adjacent metal layer in the assumed chip physical layout, the fourth off-line lower metal line redundant via that meets the preset chip design rule is selected for the single via of the current unselected redundant via, and the upper metal layer and the lower metal layer are covered for the fourth off-line lower metal line redundant via.

[0095] Figure 4C A layout schematic diagram of the off-line lower metal line redundant via according to one embodiment of the present disclosure is provided. As shown in FIG. 6, the along-line lower metal line redundant via, the along-line upper metal line redundant via, the off-line upper metal line redundant via, the first off-line lower metal line redundant via, the second off-line lower metal line redundant via, and the third off-line lower metal line redundant via are arranged in the original chip physical layout, and the off-line lower metal line candidate redundant via arranged in the first coordinate axis second direction is traversed. Figure 4CAs shown, according to the metal line routing condition of the single via connected in the original chip physical layout, there is enough space to insert the redundant via in the offline lower metal line routing direction, here, the candidate redundant via of the offline lower metal line routing is selected preferentially, and the redundant via of the offline lower metal line that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis and the second direction of the first coordinate axis. Therefore, the candidate redundant via above the second coordinate axis in the first direction of the second coordinate axis provided by the single via is selected, and the upper and lower metal layers are covered.

[0096] In step S140, the selected redundant via is arranged in the original chip physical layout.

[0097] In some embodiments, after the redundant via is selected for each single via in the original chip physical layout, the selected redundant via (including the data of the redundant via and the metal layer covering the redundant via) and the original chip physical layout are merged to verify the preset chip design rule and electrical connection, and the selected redundant via that passes the verification is arranged in the original chip physical layout. This process not only ensures the correct arrangement of the redundant via, but also avoids design errors that may be caused by manual operation, and improves the automation level and design efficiency of chip design.

[0098] Figure 5 A hierarchical traversal flowchart for arranging a redundant via for a single via according to an embodiment of the present disclosure is provided. As shown in Figure 5 As shown, the redundant via arrangement operation is prioritized in the order of the priority of the arrangement position of the redundant via along the lower metal line direction, along the upper metal line direction, offline upper metal line direction and offline lower metal line direction. Taking the second coordinate axis direction (for example, y-axis direction) as an example, in the direction of the lower metal line routing direction, the redundant via that meets the preset chip design rule is selected in the order of the first direction of the second coordinate axis, the second direction of the second coordinate axis, the first direction of the first coordinate axis and the first direction of the first coordinate axis. This process ensures that each single via can be inserted into the redundant via along the metal line as much as possible under the premise of meeting the preset chip design rule, thereby improving the manufacturing yield and reliability of the chip.

[0099] It should be noted that in each redundant via arrangement position priority and each coordinate axis direction arrangement step, assuming that the currently selected redundant via and the metal layer covered by the redundant via are arranged in the original chip physical layout, the next step of selecting the redundant via is performed according to the metal line routing of the adjacent metal layer in the assumed chip physical layout. In the process of performing the next step of selecting the redundant via, it is verified whether the arrangement of the selected redundant via causes a new chip design rule conflict. Only in the case of passing the verification, the next step of traversal and selection is continued to ensure that each arranged redundant via meets the preset chip design rule. In this way, not only the insertion rate of the redundant via is improved, but also the overall consistency and reliability of the chip design are ensured.

[0100] It should be noted that checking whether each candidate redundant via meets the preset chip design rule includes but is not limited to checking whether the parameters such as space, width, metal pitch and the like meet the preset chip design rule. Only the redundant via that meets the preset chip design rule is selected and arranged into the original chip physical layout, and the program generates a corresponding metal layer to ensure the correct connection of the redundant via with the upper and lower metal lines. It should be noted that after a redundant via is inserted for a single via, the single via is no longer a via that needs to add a redundant via, that is, the redundant via arrangement method according to the embodiment of the present disclosure inserts at most one redundant via for each single via.

[0101] Figure 6 A structural schematic diagram of a redundant via arrangement device provided according to an embodiment of the present disclosure is shown in FIG. 6. As shown in FIG. 6, the redundant via arrangement device 600 according to the embodiment of the present disclosure includes a single via acquisition unit 610, a candidate redundant via determination unit 620, a redundant via selection unit 630 and a redundant via arrangement unit 640. Figure 6 The single via acquisition unit 610 is configured to acquire a plurality of single vias located between adjacent metal layers in an original chip physical layout.

[0102] The candidate redundant via determination unit 620 is configured to determine candidate redundant vias of each single via according to a preset chip design rule and a metal line routing of the single via.

[0103] The redundant via selection unit 630 is configured to select, for each single via, a redundant via with the highest redundant via arrangement position priority and meeting the preset chip design rule from the candidate redundant vias of the single via, and the redundant via arrangement position priority is in a descending order of a direction along a lower metal line, a direction along an upper metal line, a direction away from the upper metal line and a direction away from the lower metal line.

[0104] The redundant via arrangement unit 640 is configured to arrange the selected redundant via into the original chip physical layout.

[0105] The redundant via placement unit 640 is configured to place the selected redundant vias in the physical layout of the original chip.

[0106] The present disclosure also provides an electronic device 700, such as Figure 7 As shown, it includes a memory 720, a processor 710, a power supply component 730, a network interface 740, an input and output interface 750, and a program stored in the memory 720 and executable on the processor 710. When the program is executed by the processor 710, the various processes of the various embodiments of the above method can be implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0107] The present disclosure also provides an integrated circuit layout, which can be implemented using the steps of the above-described method. An integrated circuit layout herein refers to a three-dimensional configuration of two or more components, at least one of which is an active component, and some or all of the interconnections in an integrated circuit, or such a three-dimensional configuration prepared for the manufacture of an integrated circuit.

[0108] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be accomplished by instructions, or by instructions controlling related hardware. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, the present disclosure also provides a storage medium having a computer program or instructions stored thereon. When the computer program or instructions are executed by the processor, the various processes of the various embodiments of the above methods can be implemented.

[0109] Since the instructions stored in the storage medium can execute the steps in the method provided in the embodiment of the present disclosure, the beneficial effects that can be achieved by the method provided in the embodiment of the present disclosure can be achieved. For details, please refer to the previous embodiment and will not be repeated here. The specific implementation of each of the above operations can be referred to the previous embodiment and will not be repeated here.

[0110] In summary, the redundant through-hole layout method provided by the embodiment of the present disclosure selects, for a single through-hole, a redundant through-hole with the highest priority in redundant through-hole layout position and conforming to the preset chip design rules from the candidate redundant through-holes of the single through-hole, and the order of priority in redundant through-hole layout position is from high to low as follows: along the direction of the offline lower metal line, along the direction of the online upper metal line, in the direction of the offline upper metal line, and in the direction of the offline lower metal line. This ensures that the redundant through-holes are laid out preferentially along the original metal line while meeting the preset chip design rules, does not increase additional winding, reduces the situation where redundant through-holes cannot be inserted due to metal line layout restrictions, improves the insertion rate of redundant through-holes, and can effectively utilize the high manufacturing precision and high connection reliability of the lower metal line, further reducing the risk of single through-hole failure.

[0111] It should be noted that the above-mentioned embodiments are merely given as an example for clearness and concision and that no limitations to the disclosed concept are implied. Based on the above, a person skilled in the art will further appreciate changes or modifications to the described embodiments, which changes and modifications will fall within the scope of the concept.

Claims

1. A redundant through-hole layout method, comprising: Obtain multiple single through holes located between adjacent metal layers in the physical layout of the original chip; Determining a candidate redundant through-hole for each of the single through-holes according to preset chip design rules and routing conditions of metal lines connected to the multiple single through-holes; For the single through-hole, a redundant through-hole with the highest redundant through-hole layout position priority and complying with the preset chip design rules is selected from the candidate redundant through-holes of the single through-hole, wherein the redundant through-hole layout position priority order from high to low is along the offline lower metal line direction, along the online upper metal line direction, offline upper metal line direction, and offline lower metal line direction; wherein, under each redundant through-hole layout position priority category, redundant through-holes that comply with the preset chip design rules are selected according to the priority order of the coordinate axis direction with the single through-hole as the coordinate axis center; in each redundant through-hole layout position priority and in each coordinate axis direction layout step under each priority category, it is assumed that the currently selected redundant through-hole and the metal layer covered by it are laid out in the original chip physical layout, and the next step of selecting redundant through-holes is performed according to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout; The selected redundant through holes are arranged in the physical layout of the original chip.

2. The redundant via arrangement method according to claim 1, wherein: The step of selecting, for the single through hole, a redundant through hole having the highest priority in redundant through hole layout position and conforming to the preset chip design rule from candidate redundant through holes of the single through hole, includes: According to the metal line routing conditions of the adjacent metal layers in the original chip physical layout, selecting redundant through holes along the metal line routing direction from the candidate redundant through holes of the plurality of single through holes; Assuming that the along-line redundant through holes are arranged in the original chip physical layout, according to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, offline redundant through holes in the offline metal line routing direction are selected from the candidate redundant through holes of the single through hole for which no redundant through hole is currently selected.

3. The redundant via arrangement method according to claim 2, wherein: The along-line metal line routing direction includes the along-line metal line routing direction of the lower layer metal line and the along-line metal line routing direction of the upper layer metal line, and the selecting, from the plurality of candidate redundant through holes of the single through hole according to the metal line routing conditions of the adjacent metal layers in the original chip physical layout, the along-line redundant through hole in the along-line metal line routing direction includes: According to the routing conditions of the metal lines connected to the multiple single through holes in the physical layout of the original chip, selecting candidate redundant through holes along the lower metal line from the candidate redundant through holes of the multiple single through holes, along the routing direction of the lower metal line; A redundant through hole for the lower metal line along the bottom layer that meets the preset chip design rules is selected from the candidate redundant through holes for the lower metal line along the bottom layer, and the redundant through hole for the lower metal line along the bottom layer is covered with an upper metal layer so that the redundant through hole for the lower metal line along the bottom layer is connected to the adjacent upper metal layer and lower metal layer.

4. The redundant via arrangement method according to claim 3, wherein: The selecting, based on the metal line routing conditions of the adjacent metal layers in the original chip physical layout, redundant through holes along the metal line routing direction from the plurality of candidate redundant through holes of the single through hole further includes: Assuming that the redundant through hole along the lower metal line is arranged in the original chip physical layout, according to the metal line routing situation connected to the single through hole in the assumed chip physical layout, selecting candidate redundant through holes along the upper metal line routing direction from the candidate redundant through holes of the single through hole that is not currently selected as a redundant through hole; Select an upper-layer metal line redundant through hole that meets the preset chip design rule from the candidate upper-layer metal line redundant through holes along the line, cover the lower metal layer with the upper-layer metal line redundant through hole along the line, so that the upper-layer metal line redundant through hole along the line is connected to the adjacent upper metal layer and the lower metal layer.

5. The redundant via arrangement method according to claim 4, wherein: The offline metal line routing direction includes the offline upper metal line routing direction and the offline lower metal line routing direction. The method of assuming that the redundant through holes are arranged in the original chip physical layout and selecting, according to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, the offline redundant through holes in the offline metal line routing direction from the candidate redundant through holes of the single through hole for which no redundant through hole is currently selected, comprises: Assuming that the along-line redundant via is arranged in the original chip physical layout, selecting, based on the metal line routing situation of the single via connected to the single via in the assumed chip physical layout, an offline upper-layer metal line candidate redundant via in the routing direction of the offline upper-layer metal line from candidate redundant vias of the single via that is not currently selected as a redundant via; An offline upper-layer metal line redundant through hole that meets the preset chip design rule is selected from the offline upper-layer metal line candidate redundant through holes, and the offline upper-layer metal line redundant through hole covers the upper metal layer and the lower metal layer, so that the offline upper-layer metal line redundant through hole is connected to the adjacent upper metal layer and the lower metal layer. The redundant via arrangement method according to claim 5 , wherein: The method further comprises: assuming that the redundant through holes are arranged in the original chip physical layout, and selecting, based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, an offline redundant through hole in the offline metal line routing direction from the candidate redundant through holes of the single through hole for which no redundant through hole is currently selected. Assuming that the along-line redundant vias and the offline upper-layer metal line redundant vias are arranged in the original chip physical layout, selecting offline lower-layer metal line candidate redundant vias in the routing direction of the offline lower-layer metal line from candidate redundant vias of the single via that is not currently selected as a redundant via, based on the routing of the metal line connected to the single via in the assumed chip physical layout; An offline lower-layer metal line redundant through hole that meets the preset chip design rule is selected from the offline lower-layer metal line candidate redundant through holes, and the offline lower-layer metal line redundant through hole covers the upper metal layer and the lower metal layer, so that the offline lower-layer metal line redundant through hole is connected to the adjacent upper metal layer and the lower metal layer.

7. The redundant via arrangement method according to claim 6, wherein: The candidate redundant through holes include candidate redundant through holes arranged in at least one direction of the first coordinate axis first direction, the first coordinate axis second direction, the second coordinate axis first direction, and the second coordinate axis second direction with the single through hole as the coordinate axis center, wherein the second coordinate axis direction is the routing direction of the metal line along the lower layer. The method further comprises: selecting a redundant through hole for the lower metal line along the line that meets the preset chip design rule from the candidate redundant through holes for the lower metal line along the line, covering the upper metal layer with the redundant through hole for the lower metal line along the line, so that the redundant through hole for the lower metal line along the line is connected to the adjacent upper metal layer and the lower metal layer, including: Traversing the candidate redundant through holes along the lower metal lines arranged in the first direction of the second coordinate axis, selecting a first redundant through hole along the lower metal line that meets the preset chip design rules for the multiple single through holes according to the metal line routing conditions of the adjacent metal layers in the original chip physical layout, and covering the upper metal layer with the first redundant through hole along the lower metal line; Assuming that the first redundant through hole for the lower metal line is arranged in the original chip physical layout, traversing the candidate redundant through holes for the lower metal line arranged in the second direction of the second coordinate axis, selecting a second redundant through hole for the lower metal line that complies with the preset chip design rule for the single through hole for which no redundant through hole is currently selected, and covering the upper metal layer with the second redundant through hole for the lower metal line; Assuming that the first redundant through hole for the lower metal line and the second redundant through hole for the lower metal line are arranged in the original chip physical layout, traverse the candidate redundant through holes for the lower metal line arranged in the first direction of the first coordinate axis, select a third redundant through hole for the lower metal line that complies with the preset chip design rule for the single through hole for which no redundant through hole is currently selected, and cover the upper metal layer with the third redundant through hole for the lower metal line; Assuming that the first redundant through-hole for the lower metal line, the second redundant through-hole for the lower metal line, and the third redundant through-hole for the lower metal line are arranged in the physical layout of the original chip, the candidate redundant through-holes for the lower metal line arranged in the second direction of the first coordinate axis are traversed, and according to the metal line routing conditions of the adjacent metal layers in the assumed physical layout of the chip, a fourth redundant through-hole for the lower metal line that complies with the chip design rules is selected for the single through-hole for which a redundant through-hole is currently not selected, and the upper metal layer is covered with the fourth redundant through-hole for the lower metal line.

8. The redundant via arrangement method according to claim 7, wherein: The method further comprises: selecting an upper-layer metal line redundant through hole that meets the preset chip design rule from the upper-layer metal line candidate redundant through holes along the line, covering the lower metal layer with the upper-layer metal line redundant through hole along the line, so that the upper-layer metal line redundant through hole along the line is connected to the adjacent upper metal layer and the lower metal layer, including: Assuming that the redundant through holes along the lower metal lines are arranged in the original chip physical layout, traversing the candidate redundant through holes along the upper metal lines arranged in the first direction of the second coordinate axis, selecting a first redundant through hole along the upper metal line that meets the preset chip design rules for the single through hole for which no redundant through hole is currently selected, and covering the lower metal layer with the first redundant through hole along the upper metal line; Assuming that the redundant through hole along the lower metal line and the first redundant through hole along the upper metal line are arranged in the original chip physical layout, traversing the candidate redundant through holes along the upper metal line arranged in the second direction of the second coordinate axis, selecting a second redundant through hole along the upper metal line that complies with the preset chip design rule for the single through hole for which no redundant through hole is currently selected, and covering the lower metal layer with the second redundant through hole along the upper metal line; Assuming that the redundant vias along the lower metal lines, the first redundant vias along the upper metal lines, and the second redundant vias along the upper metal lines are arranged in the original chip physical layout, traversing the candidate redundant vias along the upper metal lines arranged in the first direction of the first coordinate axis, selecting a third redundant via along the upper metal lines that complies with the preset chip design rules for the single via currently unselected, based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, and covering the lower metal layer with the third redundant via along the upper metal lines; Assuming that the redundant through holes along the lower metal lines, the first redundant through holes along the upper metal lines, the second redundant through holes along the upper metal lines, and the third redundant through holes along the upper metal lines are arranged in the original chip physical layout, the candidate redundant through holes along the upper metal lines arranged in the second direction of the first coordinate axis are traversed, and according to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, a fourth redundant through hole along the upper metal lines that complies with the preset chip design rules is selected for the single through hole for which a redundant through hole is not currently selected, and the fourth redundant through hole along the upper metal lines covers the lower metal layer.

9. The redundant via arrangement method according to claim 8, wherein: The selecting an offline upper metal line redundant via that meets the preset chip design rule from the offline upper metal line candidate redundant vias, covering the upper metal layer and the lower metal layer for the offline upper metal line redundant via, so that the offline upper metal line redundant via is connected to the adjacent upper metal layer and the lower metal layer, includes: Assuming that the redundant through holes along the lower metal lines and the redundant through holes along the upper metal lines are arranged in the original chip physical layout, traverse the candidate redundant through holes along the upper metal lines arranged in the first direction of the second coordinate axis, select a first redundant through hole along the upper metal line that meets the preset chip design rules for the single through hole for which no redundant through hole is currently selected, and cover the upper metal layer and the lower metal layer with the first redundant through hole along the lower metal line; Assuming that the redundant vias along the lower metal layer, the redundant vias along the upper metal layer, and the first offline upper metal layer redundant via are arranged in the original chip physical layout, traverse the candidate offline upper metal layer redundant vias arranged in the second direction of the second coordinate axis, and select a second offline upper metal layer redundant via that complies with the preset chip design rules for the single via currently unselected, based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, and cover the upper metal layer and the lower metal layer for the second offline upper metal layer redundant via; Assuming that the lower-layer metal line redundant vias, the upper-layer metal line redundant vias, the first offline upper-layer metal line redundant vias, and the second offline upper-layer metal line redundant vias are arranged in the original chip physical layout, traverse the candidate offline upper-layer metal line redundant vias arranged in the first direction of the first coordinate axis, and select a third offline upper-layer metal line redundant via that complies with the preset chip design rules for the single via for which no redundant via is currently selected, based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, and cover the upper metal layer and the lower metal layer for the third offline upper-layer metal line redundant via; Assuming that the redundant through holes of the lower-layer metal lines along the line, the redundant through holes of the upper-layer metal lines along the line, the first offline upper-layer metal line redundant through holes, the second offline upper-layer metal line redundant through holes and the third offline upper-layer metal line redundant through holes are arranged in the original chip physical layout, the candidate offline upper-layer metal line redundant through holes arranged in the second direction of the first coordinate axis are traversed, and according to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, a fourth offline upper-layer metal line redundant through hole that complies with the preset chip design rules is selected for the single through hole for which a redundant through hole is not currently selected, and the upper metal layer and the lower metal layer are covered for the fourth offline upper-layer metal line redundant through hole.

10. The redundant via arrangement method according to claim 9, wherein: The step of selecting an offline lower-layer metal line redundant via that meets the preset chip design rule from the offline lower-layer metal line candidate redundant vias, covering an upper metal layer and a lower metal layer for the offline lower-layer metal line redundant via, so that the offline lower-layer metal line redundant via is connected to adjacent upper metal layers and lower metal layers, includes: Assuming that the redundant vias along the lower metal line, the redundant vias along the upper metal line, and the offline upper metal line redundant vias are arranged in the original chip physical layout, traverse the candidate offline lower metal line redundant vias arranged in the first direction of the second coordinate axis, and select a first offline lower metal line redundant via that meets the preset chip design rules for the single via currently unselected based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, and cover the upper metal layer and the lower metal layer with the first offline lower metal line redundant via; Assuming that the redundant vias along the lower metal layer, the redundant vias along the upper metal layer, the offline upper metal layer, and the first offline lower metal layer redundant via are arranged in the original chip physical layout, traverse the candidate offline lower metal layer redundant vias arranged in the second direction of the second coordinate axis, and select a second offline lower metal layer redundant via that meets the preset chip design rules for the single via currently unselected based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, and cover the upper metal layer and the lower metal layer for the second offline lower metal layer redundant via; Assuming that the redundant vias along the lower metal line, the redundant vias along the upper metal line, the offline upper metal line, the first offline lower metal line redundant via, and the second offline lower metal line redundant via are arranged in the original chip physical layout, traverse the candidate offline lower metal line redundant vias arranged in the first direction of the first coordinate axis, and select a third offline lower metal line redundant via that complies with the preset chip design rules for the single via currently unselected, based on the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, and cover the upper metal layer and the lower metal layer for the third offline lower metal line redundant via; Assuming that the redundant through holes of the lower-layer metal lines along the line, the redundant through holes of the upper-layer metal lines along the line, the offline upper-layer metal line redundant through holes, the first offline lower-layer metal line redundant through holes, the second offline lower-layer metal line redundant through holes and the third offline lower-layer metal line redundant through holes are arranged in the original chip physical layout, the candidate offline lower-layer metal line redundant through holes arranged in the second direction of the first coordinate axis are traversed, and according to the metal line routing conditions of the adjacent metal layers in the assumed chip physical layout, a fourth offline lower-layer metal line redundant through hole that complies with the preset chip design rules is selected for the single through hole for which a redundant through hole is currently not selected, and the upper metal layer and the lower metal layer are covered for the fourth offline lower-layer metal line redundant through hole.

11. The redundant via arrangement method according to claim 1, wherein: Before arranging the selected redundant through holes in the original chip physical layout, the redundant through hole arrangement method further includes: Data of the selected redundant through holes is merged with the original chip physical layout to perform the preset chip design rule and electrical connection verification, and the selected redundant through holes that pass the verification are arranged in the original chip physical layout.

12. A redundant through-hole arrangement device, comprising: A single through-hole acquisition unit is used to acquire multiple single through-holes located between adjacent metal layers in the physical layout of the original chip; a candidate redundant through-hole determination unit, configured to determine a candidate redundant through-hole for each of the single through-holes according to preset chip design rules and the routing conditions of metal lines connected to the multiple single through-holes; a redundant through-hole selection unit, configured to select, for the single through-hole, a redundant through-hole with the highest redundant through-hole layout position priority and complying with the preset chip design rules from candidate redundant through-holes of the single through-hole, wherein the redundant through-hole layout position priorities are, from high to low, along the direction of the offline lower metal line, along the direction of the online upper metal line, along the direction of the offline upper metal line, and along the offline lower metal line; wherein, under each redundant through-hole layout position priority category, redundant through-holes complying with the preset chip design rules are selected according to the priority order of the coordinate axis direction centered on the single through-hole; and in each redundant through-hole layout position priority and in each coordinate axis direction layout step under each priority category, it is assumed that the currently selected redundant through-hole and the metal layer covered by it are laid out in the original chip physical layout, and the next step of selecting redundant through-holes is performed according to the metal line routing conditions of adjacent metal layers in the assumed chip physical layout; The redundant through hole layout unit is used to layout the selected redundant through holes in the physical layout of the original chip.

13. An integrated circuit layout, implemented using the steps of the method according to any one of claims 1 to 11.

14. An electronic device comprising: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method according to any one of claims 1 to 11.

15. A storage medium having a computer program or instructions stored thereon, wherein the computer program or instructions, when executed by a processor, implements the steps of the method according to any one of claims 1 to 11.

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