Noise reduction circuit and gate drive circuit

Abstract

The present application belongs to the field of display drive technology, and specifically relates to a noise reduction circuit and a gate drive circuit, wherein the noise reduction circuit includes: a noise reduction control unit, which is used to output a noise reduction signal during the non-scanning time of the scanning phase of the current-stage gate drive module under the action of a noise reduction control signal output from a noise reduction control end and a voltage on a drive control node; a noise reduction execution unit, which is used to perform noise reduction processing on the voltages on the drive control node, the drive output end, and the stage transmission output end according to the noise reduction signal; and a threshold correction unit, which is used to place the transistors in the noise reduction execution unit in a reverse bias state during the blanking phase. The present application uses the threshold correction unit to place the transistors in the noise reduction execution unit in a reverse bias state during the blanking phase to offset the forward bias state of the transistors in the noise reduction execution unit during noise reduction, thereby improving the problem of threshold voltage drift of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and particularly relates to a noise reduction circuit and a gate drive circuit. Background Art

[0002] TFT-LCDs (Thin-Film Transistor Liquid Crystal Displays) display images by controlling the transmittance of pixels in the display area. Specifically, under the action of an applied voltage, the liquid crystal molecules within a single pixel deflect, thereby changing the transmittance and displaying color. The display area is composed of pixels arranged in an array, and dynamic display is achieved by switching the pixel state frame by frame.

[0003] The Gate Driver on Array (GOA) is a key circuit for TFT-LCDs to achieve progressive scanning. The noise reduction circuit, which performs noise reduction on key nodes, is the core module for the reliable operation of the GOA. However, the noise reduction transistors in the noise reduction circuit are often biased at a positive gate-source voltage (Vgs) for a long time during operation, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift. This leads to unstable noise reduction and abnormal GOA output signals, affecting the display quality of the display panel.

[0004] Therefore, how to improve the threshold voltage drift of the noise reduction transistor that causes noise reduction instability is a problem that the current baseband needs to solve. Summary of the Invention

[0005] An embodiment of the present application provides a noise reduction circuit and a gate drive circuit, which uses a threshold correction unit to place the transistors in the noise reduction execution unit in a reverse bias state during the blanking phase to offset the forward bias state of the transistors in the noise reduction execution unit during noise reduction, thereby improving the problem of threshold voltage drift of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit.

[0006] In a first aspect, an embodiment of the present application provides a noise reduction circuit, which is applied to a gate drive circuit, wherein the gate drive circuit includes N cascaded gate drive modules, and the nth-stage gate drive module includes at least a drive control node, a drive output terminal, a stage transmission output terminal, and a noise reduction circuit. The noise reduction circuit includes: a noise reduction control unit, wherein a first control terminal of the noise reduction control unit is connected to the noise reduction control terminal, and a second control terminal of the noise reduction control unit is connected to the drive control node, and is configured to output a noise reduction signal during a non-scanning time of a scan phase of a current-stage gate drive module under the action of a noise reduction control signal output by the noise reduction control terminal and a voltage on the drive control node; a noise reduction execution unit, wherein a control terminal of the noise reduction execution unit is connected to an output terminal of the noise reduction control unit, and an output terminal of the noise reduction execution unit is respectively connected to the drive control node, the drive output terminal, and the stage transmission output terminal, and is configured to perform noise reduction processing on the voltages on the drive control node, the drive output terminal, and the stage transmission output terminal according to the noise reduction signal; and a threshold correction unit, wherein the threshold correction unit is connected to the noise reduction execution unit and is configured to reverse bias the transistors in the noise reduction execution unit during a blanking phase.

[0007] Optionally, the noise reduction control unit includes: a first transistor, the control end of the first transistor is connected to the noise reduction control end, and the first end of the first transistor is connected to the control end of the first transistor; a second transistor, the control end of the second transistor is connected to the second end of the first transistor, and the first end of the second transistor is connected to the first end of the first transistor; a third transistor, the control end of the third transistor is connected to the drive control node, the first end of the third transistor is connected to the second end of the first transistor, and the second end of the third transistor is connected to the first low-level end; a fourth transistor, the control end of the fourth transistor is connected to the control end of the third transistor, the first end of the fourth transistor is connected to the second end of the second transistor, and the second end of the fourth transistor is connected to the first low-level end.

[0008] Optionally, the noise reduction execution unit includes: a fifth transistor, the control end of the fifth transistor is connected to the output end of the noise reduction control unit, the first end of the fifth transistor is connected to the drive output end, and the second end of the fifth transistor is connected to the second low-level end; a sixth transistor, the control end of the sixth transistor is connected to the control end of the fifth transistor, the first end of the sixth transistor is connected to the drive control node, and the second end of the sixth transistor is connected to the first low-level end; a seventh transistor, the control end of the seventh transistor is connected to the control end of the fifth transistor, the first end of the seventh transistor is connected to the stage transmission output end, and the second end of the seventh transistor is connected to the second low-level end.

[0009] Optionally, the threshold correction unit includes: an eighth transistor, the control end of the eighth transistor is connected to the control end of the fifth transistor, and the first end of the eighth transistor is connected to the control end of the eighth transistor; a ninth transistor, the control end of the ninth transistor is connected to the second end of the fifth transistor, the first end of the ninth transistor is connected to the second end of the eighth transistor, and the second end of the ninth transistor is connected to the first low-level end.

[0010] Optionally, the threshold correction unit further includes: a tenth transistor, the control end of the tenth transistor is connected to the second end of the first transistor, the first end of the tenth transistor is connected to the control end of the tenth transistor, and the second end of the tenth transistor is connected to the first end of the ninth transistor.

[0011] Optionally, the threshold correction unit includes: an eighth transistor, the control end of the eighth transistor is connected to the second end of the fifth transistor, and the first end of the eighth transistor is connected to the control end of the fifth transistor; a ninth transistor, the control end of the ninth transistor is connected to the first end of the eighth transistor, the first end of the ninth transistor is connected to the second end of the eighth transistor, and the second end of the ninth transistor is connected to the first low-level end.

[0012] Optionally, in the scanning phase, the first low level end and the second low level end output a low level; in the blanking phase, the first low level end and the second low level end first output a low level and then output a high level.

[0013] Optionally, the threshold correction unit includes: an eighth transistor, the control end of the eighth transistor is connected to the control end of the fifth transistor, and the first end of the eighth transistor is connected to the control end of the eighth transistor; a ninth transistor, the control end of the ninth transistor is connected to the correction power supply end, the first end of the ninth transistor is connected to the second end of the eighth transistor, and the second end of the ninth transistor is connected to the first low-level end.

[0014] Optionally, in the scanning stage, the first low level end, the second low level end and the corrected power supply end output a low level; in the blanking stage, the first low level end and the second low level end first output a low level and then output a high level, and the corrected power supply end outputs a high level.

[0015] In a second aspect, an embodiment of the present application provides a gate drive circuit, comprising N cascaded gate drive modules, wherein the n-th level gate drive module comprises: a pull-up unit, wherein the pull-up unit is respectively connected to a drive output terminal of the n-th level gate drive module and a level transmission output terminal of the n-th level gate drive module;

[0016] A pull-down unit, the pull-down unit is connected to the stage transmission output terminal of the n+j-th stage gate driving module, and the pull-down unit is also connected to the pull-up unit through a driving control node; an output unit, the output unit is respectively connected to the clock signal terminal and the driving control node; and a noise reduction circuit, the noise reduction circuit is respectively connected to the driving control node, the driving output terminal and the stage transmission output terminal of the current stage gate driving module.

[0017] The technical solutions provided in the embodiments of the present application have at least the following beneficial effects:

[0018] In the present application, the noise reduction control unit outputs a noise reduction signal, so that the noise reduction execution unit performs noise reduction processing on the voltages on the drive control node, the drive output terminal and the stage transmission output terminal during the non-scanning time of the scanning phase of the current stage; the threshold correction unit is used to make the transistors in the noise reduction execution unit in a reverse bias state during the blanking phase to offset the forward bias state of the transistors in the noise reduction execution unit during noise reduction, thereby improving the problem of drift in the threshold voltage of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 Shown is a structural schematic diagram of a gate drive module provided in an embodiment of the present application.

[0021] Figure 2 FIG. 1 is a circuit diagram of a noise reduction circuit in related art.

[0022] Figure 3 Shown is a structural schematic diagram of a noise reduction circuit provided in an embodiment of the present application.

[0023] Figure 4 Shown is a circuit diagram of a first noise reduction circuit provided in an embodiment of the present application.

[0024] Figure 5 The figure shows a first driving timing diagram provided in an embodiment of the present application.

[0025] Figure 6 FIG. 1 is a circuit diagram of a second noise reduction circuit provided in an embodiment of the present application.

[0026] Figure 7FIG. 1 is a circuit diagram of a third noise reduction circuit provided in an embodiment of the present application.

[0027] Figure 8 FIG. 1 is a circuit diagram of a fourth noise reduction circuit provided in an embodiment of the present application.

[0028] Figure 9 The figure shows a second driving timing diagram provided in an embodiment of the present application.

[0029] Description of reference numerals:

[0030] 100, noise reduction circuit; 110, noise reduction control unit; 120, noise reduction execution unit; 130, threshold correction unit;

[0031] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor;

[0032] Qn, drive control node; Pn, noise reduction control node; Fn, level transmission output terminal; Gn, drive output terminal; LC, noise reduction control terminal; VC, correction power supply terminal; VSS1, first low level terminal; VSS2, second low level terminal. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0034] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0035] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0036] The inventors of this application have found that the gate drive circuit includes N cascaded gate drive modules, such as Figure 1 As shown, the n-th level gate driving module mainly includes a pull-up unit, a pull-down unit, an output unit, a reset unit and a noise reduction circuit. The pull-up unit and the pull-down unit output a Q-point voltage. The pull-up unit and the pull-down unit need to obtain multiple level transmission signals from the upper and lower gate driving modules. The Q-point voltage is the turn-on voltage of the output unit, so that the output unit outputs a gate driving signal to provide a turn-on voltage for the display area. The reset unit is used to avoid the influence between frames. The noise reduction circuit performs noise reduction processing on the signals at each key node; wherein Qn represents the driving control node of the n-th level gate driving module, Gn represents the driving output terminal of the n-th level gate driving module, Fn represents the level transmission output terminal of the n-th level gate driving module, CKn represents the clock signal terminal of the n-th level gate driving module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-3 represents the driving output terminal of the n-3-th level gate driving module, Fn-3 represents the level transmission output terminal of the n-3-th level gate driving module and Fn+4 represents the level transmission output terminal of the n+4-th level gate driving module.

[0037] The normal output of the gate drive module is a necessary condition to ensure the normal display of the picture, so the noise reduction circuit is particularly important for suppressing the noise of the signal. Figure 2 The figure shows a circuit diagram of a noise reduction circuit in the related art. The first transistor T1 and the second transistor T2 are control transistors, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all noise reduction transistors. When the driving control node (i.e., the Q point) in the n-th stage gate driving module is at a low level, the noise reduction control terminal LC continuously outputs a high level. At this time, the first transistor T1 is turned on and the second transistor T2 is turned off, so that the noise reduction control node Pn is at a high level, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on respectively, thereby connecting the driving output terminal Gn, the driving control node Qn and the stage transmission module to the high level. The signal on the output terminal Fn is continuously pulled low to achieve noise reduction processing for each important node in the gate drive module; since the drive output terminal, drive control node and stage transmission output terminal in each stage of the gate drive module are not subjected to noise reduction only during the scanning time of the current stage, the rest of the time is the noise reduction processing period; therefore, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 in the noise reduction circuit need to be in a positive gate-source voltage bias state for a long time, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift, thereby causing the output signal of the GOA circuit to be abnormal, affecting the display effect of the display panel.

[0038] In order to improve the threshold voltage drift problem of the noise reduction transistor, the present application provides a noise reduction circuit, which specifically includes the following embodiments:

[0039] Figure 3FIG. 1 is a schematic structural diagram of a noise reduction circuit provided in an embodiment of the present application; the noise reduction circuit 100 of this embodiment is applied to a gate drive circuit, and the gate drive circuit includes N cascaded gate drive modules; Figure 1 As shown, each gate driving module at least includes a driving control node Qn, a driving output terminal Gn, a stage transmission output terminal Fn and a noise reduction circuit 100.

[0040] like Figure 3 As shown, the noise reduction circuit 100 includes: a noise reduction control unit 110, a first control terminal of the noise reduction control unit 110 is connected to the noise reduction control terminal LC, and a second control terminal of the noise reduction control unit 110 is connected to the drive control node Qn, and is configured to output a noise reduction signal during the non-scanning time of the scanning phase of the current-level gate driving module under the influence of the noise reduction control signal output by the noise reduction control terminal LC and the voltage on the drive control node Qn.

[0041] It should be noted that in the driving technology of display panels, the scanning stage and the blanking stage are key points in timing control. The two together ensure that pixel data is correctly updated and the display is stable. The scanning stage is the stage in which the gate drive circuit activates pixels row by row and writes data. For example, in a display that scans row by row, the gate drive signal selects each row of pixels from top to bottom in turn, and writes the voltage signal to the pixel unit of that row through the data line. The blanking stage is the "interval period" between scans, when the drive circuit stops writing data to switch rows or frames to prevent signal overlap and display distortion.

[0042] In this embodiment, under the combined effect of the noise reduction control signal output by the noise reduction control terminal LC and the voltage on the drive control node Qn, the noise reduction control unit 110 in the n-th stage gate driving module outputs the noise reduction signal during the non-scanning time period of the scanning phase of the n-th stage gate driving module, and does not output the noise reduction signal during the scanning time period of the n-th stage gate driving module.

[0043] In this embodiment, the noise reduction circuit 100 further includes a noise reduction execution unit 120. The control end of the noise reduction execution unit 120 is connected to the output end of the noise reduction control unit 110, and the output end of the noise reduction execution unit 120 is respectively connected to the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn. The noise reduction execution unit 120 is configured to perform noise reduction processing on the voltages on the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn according to the noise reduction signal.

[0044] It should be noted that this embodiment performs noise reduction processing on the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn according to the noise reduction signal. That is, by continuously pulling down the signals on the drive output terminal Gn, the drive control node Qn, and the stage transmission output terminal Fn through the noise reduction execution unit 120, leakage current in the circuit or other transistor abnormalities are avoided, which cause the voltages on the drive output terminal Gn, the drive control node Qn, and / or the stage transmission output terminal Fn to be at a high level, thereby causing display abnormalities such as pixel mischarging.

[0045] In this embodiment, the noise reduction circuit 100 further includes a threshold correction unit 130 , which is connected to the noise reduction execution unit 120 and is configured to place transistors in the noise reduction execution unit 120 in a reverse bias state during the blanking phase.

[0046] It should be noted that, according to the operating principle of the gate drive module, as long as the noise reduction control unit 110 outputs a noise reduction signal, the noise reduction execution unit 120 will perform noise reduction processing on the corresponding important nodes. Furthermore, since the drive output terminal Gn, drive control node Qn, and stage transmission output terminal Fn in each stage of the gate drive module are not subjected to noise reduction only during the current stage's scanning time, and are noise reduction processing periods at other times, the transistors in the noise reduction execution unit 120 need to be in an operating state (i.e., a positive gate-source voltage bias state) for a long period of time, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift, thereby causing the output signal of the gate drive circuit to be abnormal, affecting the display effect of the display panel. However, in this embodiment, the threshold correction unit 130 is used to reverse-bias the transistors in the noise reduction execution unit 120 during the blanking phase to offset the forward bias of the transistors in the noise reduction execution unit 120 during the non-scanning period of the scanning phase, thereby avoiding the problem of threshold voltage drift of the noise reduction transistor.

[0047] It can be seen from this that the present application uses the noise reduction signal output by the noise reduction control unit 110 to enable the noise reduction execution unit 120 to perform noise reduction processing on the voltages on the drive control node Qn, the drive output terminal Gn and the stage transmission output terminal Fn during the non-scanning time of the scanning phase of the current stage; through the threshold correction unit 130, the transistors in the noise reduction execution unit 120 are placed in a reverse biased state during the blanking phase to offset the forward biased state of the transistors in the noise reduction execution unit 120 during noise reduction, thereby improving the problem of drift in the threshold voltage of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit 100.

[0048] Figure 4 FIG. 1 is a circuit diagram of a first noise reduction circuit provided in an embodiment of the present application, as shown in FIG. Figure 4As shown, the noise reduction control unit 110 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4; wherein, the control end of the first transistor T1 is connected to the noise reduction control end LC, and the first end of the first transistor T1 is connected to the control end of the first transistor T1; the control end of the second transistor T2 is connected to the second end of the first transistor T1, and the first end of the second transistor T2 is connected to the first end of the first transistor T1; the control end of the third transistor T3 is connected to the driving control node Qn, the first end of the third transistor T3 is connected to the second end of the first transistor T1, and the second end of the third transistor T3 is connected to the first low-level end VSS1; the control end of the fourth transistor T4 is connected to the control end of the third transistor T3, the first end of the fourth transistor T4 is connected to the second end of the second transistor T2, and the second end of the fourth transistor T4 is connected to the first low-level end VSS1.

[0049] Optionally, in the scanning phase, the first low level terminal VSS1 and the second low level terminal VSS2 output a low level; in the blanking phase, the first low level terminal VSS1 and the second low level terminal VSS2 output a low level first and then a high level.

[0050] It should be noted that the main purpose of the noise reduction control unit 110 of this embodiment is to invert the voltage on the driving control node Qn, that is, when the voltage on the driving control node Qn is high, the noise reduction control unit 110 outputs a low level, and when the voltage on the driving control node Qn is low, the noise reduction control unit 110 outputs a high level; Figure 5 The timing diagram of the noise reduction control unit 110 is used to illustrate the specific working principle of the noise reduction control unit 110:

[0051] (1) When the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all N-type MOS tubes, the noise reduction control terminal LC always outputs a high level in the scanning phase, and the first transistor T1 is continuously turned on; Figure 5 As shown, the scanning phase is divided into time periods t1, t2 and t3, and the blanking phase is divided into time periods t4, t5 and t6.

[0052] (2) At the scanning time (t2) of the current-stage gate driving module, the voltage on the driving control node Qn is at a high level, and the third transistor T3 and the fourth transistor T4 are turned on at the same time, so that the voltages on the node An and the noise reduction control node Pn are both at the first low level output by the first low level terminal VSS1, thereby turning off the second transistor T2 and the noise reduction control unit 110 outputting the first low level; Figure 5 As shown, in the scanning phase, the first low-level terminal VSS1 outputs a first low level, and the voltage on the noise reduction control node Pn is also a first low level.

[0053] (3) During the non-scanning time (t1 and t3) of the scanning phase of the current gate driving module, the voltage on the driving control node Qn is low, and the third transistor T3 and the fourth transistor T4 are turned off, so that the voltage on the node An is high, thereby turning on the second transistor T2, and the noise reduction control unit 110 outputs a high level, i.e., a noise reduction signal; Figure 5 As shown, during the time periods t1 and t3 of the scanning phase, the noise reduction signal on the noise reduction control node Pn is at a high level.

[0054] It should also be noted that the above working principle is described using the example where the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all N-type MOS transistors. When the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are P-type transistors, the working principle is the same but the driving timing is opposite, which will not be repeated here.

[0055] like Figure 4 As shown, the noise reduction execution unit 120 includes a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7; wherein, the control end of the fifth transistor T5 is connected to the output end of the noise reduction control unit 110, the first end of the fifth transistor T5 is connected to the driving output end Gn, and the second end of the fifth transistor T5 is connected to the second low-level end VSS2; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the driving control node Qn, and the second end of the sixth transistor T6 is connected to the first low-level end VSS1; the control end of the seventh transistor T7 is connected to the control end of the fifth transistor T5, the first end of the seventh transistor T7 is connected to the stage transmission output end Fn, and the second end of the seventh transistor T7 is connected to the second low-level end VSS2.

[0056] It should be noted that, here, the working principle of the noise reduction execution unit 120 is described in detail by taking the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 as N-type MOS transistors as an example:

[0057] (1) When the noise reduction control unit 110 outputs the noise reduction signal, that is, the voltage on the noise reduction control node Pn is at a high level, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on at the same time, so that the voltage on the driving output terminal Gn is pulled down to the second low level through the turned-on fifth transistor T5, the voltage on the driving control node Qn is pulled down to the first low level through the turned-on sixth transistor T6, and the voltage on the stage transmission output terminal Fn is pulled down to the first low level through the turned-on seventh transistor T7; Figure 5As shown, in the scanning phase, the clock signal terminal CK outputs a clock signal, and the first low level terminal VSS1 and the second low level terminal VSS2 output a first low level and a second low level, respectively; in addition, the voltage values ​​of the first low level and the second low level may be the same or different; optionally, by adjusting the voltage values ​​of the first low level and the second low level, respectively, the leakage current of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be reduced, thereby improving the stability of the voltage on the noise reduction control node Pn.

[0058] (2) When the noise reduction control unit 110 does not output the noise reduction signal, that is, the voltage on the noise reduction control node Pn is at a low level, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off at the same time, and the noise reduction processing of the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn is stopped.

[0059] like Figure 4 As shown, the threshold correction unit 130 includes an eighth transistor T8 and a ninth transistor T9, the control end of the eighth transistor T8 is connected to the control end of the fifth transistor T5, and the first end of the eighth transistor T8 is connected to the control end of the eighth transistor T8; the control end of the ninth transistor T9 is connected to the second end of the fifth transistor T5, the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, and the second end of the ninth transistor T9 is connected to the first low-level end VSS1.

[0060] It should be noted that, in the blanking phase, if the noise reduction control node Pn is at a low level, and the first low level terminal VSS1 and the second low level terminal VSS2 are at a high level, the transistors in the noise reduction execution unit 120 can be in a reverse bias state, thereby achieving the purpose of reverse correction of the threshold voltage; in this example, the eighth transistor T8 and the ninth transistor T9 are N-type MOS transistors, combined with Figure 5 The timing diagram of the threshold correction unit 130 is described in detail:

[0061] (1) During the blanking phase, during the t4 period, the noise reduction control terminal LC is pulled down from a high level to a low level, so that the noise reduction control unit 110 stops outputting current to the noise reduction control terminal LC;

[0062] (2) During the t5 period of the blanking phase, the second low-level terminal VSS2 is controlled to output a high level, and the first low-level terminal VSS1 is kept at a low potential. At this time, the noise reduction control terminal LC is also at a high potential, so the eighth transistor T8 and the ninth transistor T9 are both turned on, so that the high potential on the noise reduction control terminal LC is released to the first low-level terminal VSS1 through the turned-on eighth transistor T8 and the ninth transistor T9, thereby causing the voltage of the noise reduction control node Pn to turn to a low level;

[0063] (3) During the t6 period of the blanking phase, the first low-level terminal VSS1 and the second low-level terminal VSS2 are controlled to output a high level. At this time, the second end of the fifth transistor T5, the second end of the sixth transistor T6, and the second end of the seventh transistor T7 are all high levels, and the control end of the fifth transistor T5, the control end of the sixth transistor T6, and the control end of the seventh transistor T7 are all low levels, so that the transistors in the noise reduction execution unit 120 (hereinafter referred to as noise reduction transistors) are in a reverse bias state, and the reverse bias state is maintained until the start of the next frame.

[0064] It can be seen from the timing of each signal in the scanning phase and the blanking phase that this embodiment achieves a reverse correction of the threshold voltage of the noise reduction transistor in the blanking phase without affecting the original control logic; optionally, in order to further improve the correction effect of the threshold voltage, the time proportion of the blanking phase can be increased without affecting the display effect.

[0065] Figure 6 FIG. 1 is a circuit diagram of a second noise reduction circuit provided in an embodiment of the present application; Figure 6 The noise reduction circuit 100 shown is Figure 4 The circuit structures of the noise reduction control unit 110 and the noise reduction execution unit 120 are the same, and the only difference is that the connection mode of the two transistors in the threshold correction unit 130 is different; Figure 6 As shown, the threshold correction unit 130 includes an eighth transistor T8 and a ninth transistor T9; the control end of the eighth transistor T8 is connected to the second end of the fifth transistor T5, and the first end of the eighth transistor T8 is connected to the control end of the fifth transistor T5; the control end of the ninth transistor T9 is connected to the first end of the eighth transistor T8, the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, and the second end of the ninth transistor T9 is connected to the first low-level end VSS1.

[0066] It should be noted that Figure 6 and Figure 4 The control logic is the same as Figure 5 The working principle of the threshold correction unit 130 of this embodiment is as follows:

[0067] (1) During the blanking phase, during the t4 period, the noise reduction control terminal LC is pulled down from a high level to a low level, so that the noise reduction control unit 110 stops outputting current to the noise reduction control node Pn;

[0068] (2) During the t5 period of the blanking phase, the second low-level terminal VSS2 is controlled to output a high level, and the first low-level terminal VSS1 is kept at a low potential. At this time, the noise reduction control node Pn is also at a high potential, so the eighth transistor T8 and the ninth transistor T9 are both turned on, so that the high potential on the noise reduction control node Pn is released to the first low-level terminal VSS1 through the turned-on eighth transistor T8 and the ninth transistor T9, thereby causing the voltage of the noise reduction control node Pn to turn to a low level;

[0069] (3) During the t6 period of the blanking phase, the first low-level terminal VSS1 and the second low-level terminal VSS2 are controlled to output a high level. At this time, the second end of the fifth transistor T5, the second end of the sixth transistor T6, and the second end of the seventh transistor T7 are all high levels, and the control end of the fifth transistor T5, the control end of the sixth transistor T6, and the control end of the seventh transistor T7 are all low levels, so that the transistors in the noise reduction execution unit 120 (hereinafter referred to as noise reduction transistors) are in a reverse bias state, and the reverse bias state is maintained until the start of the next frame.

[0070] Figure 7 FIG. 1 is a circuit diagram of a third noise reduction circuit provided in an embodiment of the present application; Figure 7 The noise reduction circuit 100 shown in FIG. Figure 4 The noise reduction circuit 100 shown in FIG. 1 is based on the circuit 100 and is further configured by adding a tenth transistor T10. Figure 7 As shown, the threshold correction unit 130 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; the control end of the eighth transistor T8 is connected to the control end of the fifth transistor T5, and the first end of the eighth transistor T8 is connected to the control end of the eighth transistor T8; the control end of the ninth transistor T9 is connected to the second end of the fifth transistor T5, the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, and the second end of the ninth transistor T9 is connected to the first low-level end VSS1; the control end of the tenth transistor T10 is connected to the second end of the first transistor T1, the first end of the tenth transistor T10 is connected to the control end of the tenth transistor T10, and the second end of the tenth transistor T10 is connected to the first end of the ninth transistor T9.

[0071] It should be noted that Figure 7 and Figure 4 The control logic is the same as Figure 5 The timing diagram shall prevail; Figure 5During the periods t1 and t3 in the noise reduction control unit 110, the potential logics of the node An and the noise reduction control node Pn are the same, that is, both are high levels; at this time, the tenth transistor T10 is turned on by the high potential on the node An, thereby pulling up the potential of the node Kn, and then reducing the drain-source voltage of the eighth transistor T8, thereby achieving the purpose of reducing the leakage current on the noise reduction control node Pn, so that the noise reduction control node Pn is not affected by the leakage of the eighth transistor T8 and the ninth transistor T9 during the scanning stage.

[0072] Figure 8 FIG. 1 is a circuit diagram of a fourth noise reduction circuit provided in an embodiment of the present application; Figure 8 The noise reduction circuit 100 shown is Figure 4 The circuit structures of the noise reduction control unit 110 and the noise reduction execution unit 120 are the same, and the only difference is that the control method of the ninth transistor T9 in the threshold correction unit 130 is different; Figure 8 As shown, the threshold correction unit 130 includes an eighth transistor T8 and a ninth transistor T9; the control end of the eighth transistor T8 is connected to the control end of the fifth transistor T5, and the first end of the eighth transistor T8 is connected to the control end of the eighth transistor T8; the control end of the ninth transistor T9 is connected to the correction power supply end VC, the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, and the second end of the ninth transistor T9 is connected to the first low-level end VSS1.

[0073] Optionally, in the scanning stage, the first low level terminal VSS1, the second low level terminal VSS2 and the corrected power supply terminal VC output low level; in the blanking stage, the first low level terminal VSS1 and the second low level terminal VSS2 first output low level and then output high level, and the corrected power supply terminal VC outputs high level.

[0074] It should be noted that in this embodiment Figure 4 On the basis of the embodiment of the present invention, a correction power supply terminal VC is added to replace the second low-level terminal VSS2 connected to the control terminal of the ninth transistor T9; the main purpose is that when the control correction power supply terminal VC is at a low level, its voltage can be less than or equal to the first low level output by the first low-level terminal VSS1, so that the gate-source voltage of the ninth transistor T9 is less than or equal to 0, thereby reducing the leakage of the ninth transistor T9; Figure 8 The control logic is as follows Figure 9 As shown:

[0075] (1) During the scanning phase (t1, t2, t3), the clock signal terminal CK is controlled to output a clock signal, and the first low-level terminal VSS1, the second low-level terminal VSS2, and the correction power supply terminal VC are controlled to output a first low level, a second low level, and a third low level, respectively. The third low level is less than or equal to the first low level, thereby ensuring the turn-off effect of the ninth transistor T9 during the periods t1 and t3, and avoiding leakage current on the noise reduction control node Pn.

[0076] (2) During the blanking phase, during the t4 period, the first low-level terminal VSS1 and the second low-level terminal VSS2 are controlled to maintain a low potential, while the corrected power supply terminal VC outputs a high level, so that the voltage on the noise reduction control node Pn is pulled down to the first low level through the turned-on eighth transistor T8 and the ninth transistor T9.

[0077] (3) During the t5 period of the blanking phase, the first low-level terminal VSS1 and the second level terminal are controlled to output a high level, so that the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the noise reduction execution unit 120 are in a reverse bias state, thereby achieving a reverse correction of the threshold voltage of the noise reduction transistor.

[0078] To sum up, the noise reduction circuit provided in the present application, on the basis of not affecting the control logic of the noise reduction control unit and the noise reduction execution unit, achieves the purpose of reverse biasing the noise reduction transistor in the blanking stage through the threshold correction unit of various embodiments, so as to delay or offset the threshold voltage drift caused by the forward bias in the scanning stage, thereby avoiding driving abnormalities in the gate drive circuit due to the reduction of noise reduction capability.

[0079] In one embodiment, the embodiment of the present application provides a gate drive circuit, comprising N cascaded gate drive modules, the nth-level gate drive module comprising: a pull-up unit, a pull-down unit, an output unit and a noise reduction circuit, the pull-up unit being respectively connected to the drive output terminal of the ni-th-level gate drive module and the level transmission output terminal of the ni-th-level gate drive module; the pull-down unit being connected to the level transmission output terminal of the n+j-th-level gate drive module, and the pull-down unit being further connected to the pull-up unit through a drive control node; the output unit being respectively connected to the clock signal terminal and the drive control node; and the noise reduction circuit being respectively connected to the drive control node, the drive output terminal and the level transmission output terminal of the current-level gate drive module.

[0080] It should be noted that the specific structure of the gate drive module provided in this embodiment is as follows Figure 1 As shown, the working principle of the gate drive module is described above using i=3, j=4 as an example, which will not be repeated here.

[0081] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0082] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0083] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A noise reduction circuit, characterized in that: Applied to a gate drive circuit, the gate drive circuit includes N cascaded gate drive modules, the n-th level gate drive module includes at least a drive control node, a drive output terminal, a level transmission output terminal and a noise reduction circuit, the noise reduction circuit includes: a noise reduction control unit, wherein a first control terminal of the noise reduction control unit is connected to the noise reduction control terminal, and a second control terminal of the noise reduction control unit is connected to the drive control node, and is configured to output a noise reduction signal during a non-scanning time of a scanning phase of a current-stage gate drive module under the action of a noise reduction control signal output by the noise reduction control terminal and a voltage on the drive control node; a noise reduction execution unit, wherein the control end of the noise reduction execution unit is connected to the output end of the noise reduction control unit, and the output end of the noise reduction execution unit is respectively connected to the drive control node, the drive output end, and the stage transmission output end, and is configured to perform noise reduction processing on the voltages on the drive control node, the drive output end, and the stage transmission output end according to the noise reduction signal; a threshold correction unit, the threshold correction unit being connected to the noise reduction execution unit and configured to place the transistors in the noise reduction execution unit in a reverse bias state during a blanking phase; The noise reduction execution unit includes: a fifth transistor, a control end of the fifth transistor is connected to the output end of the noise reduction control unit, a first end of the fifth transistor is connected to the driving output end, and a second end of the fifth transistor is connected to the second low-level end; The threshold correction unit includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the control terminal of the fifth transistor, and a first terminal of the eighth transistor is connected to the control terminal of the eighth transistor; A ninth transistor, wherein the control end of the ninth transistor is connected to the second end of the fifth transistor, the first end of the ninth transistor is connected to the second end of the eighth transistor, and the second end of the ninth transistor is connected to the first low level end.

2. A noise reduction circuit, characterized in that: Applied to a gate drive circuit, the gate drive circuit includes N cascaded gate drive modules, the n-th level gate drive module includes at least a drive control node, a drive output terminal, a level transmission output terminal and a noise reduction circuit, the noise reduction circuit includes: a noise reduction control unit, wherein a first control terminal of the noise reduction control unit is connected to the noise reduction control terminal, and a second control terminal of the noise reduction control unit is connected to the drive control node, and is configured to output a noise reduction signal during a non-scanning time of a scanning phase of a current-stage gate drive module under the action of a noise reduction control signal output by the noise reduction control terminal and a voltage on the drive control node; a noise reduction execution unit, wherein the control end of the noise reduction execution unit is connected to the output end of the noise reduction control unit, and the output end of the noise reduction execution unit is respectively connected to the drive control node, the drive output end, and the stage transmission output end, and is configured to perform noise reduction processing on the voltages on the drive control node, the drive output end, and the stage transmission output end according to the noise reduction signal; a threshold correction unit, the threshold correction unit being connected to the noise reduction execution unit and configured to place the transistors in the noise reduction execution unit in a reverse bias state during a blanking phase; The noise reduction execution unit includes: a fifth transistor, a control end of the fifth transistor is connected to the output end of the noise reduction control unit, a first end of the fifth transistor is connected to the driving output end, and a second end of the fifth transistor is connected to the second low-level end; The threshold correction unit includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the second terminal of the fifth transistor, and a first terminal of the eighth transistor is connected to the control terminal of the fifth transistor; A ninth transistor, wherein the control end of the ninth transistor is connected to the first end of the eighth transistor, the first end of the ninth transistor is connected to the second end of the eighth transistor, and the second end of the ninth transistor is connected to the first low level end.

3. A noise reduction circuit, characterized in that: Applied to a gate drive circuit, the gate drive circuit includes N cascaded gate drive modules, the n-th level gate drive module includes at least a drive control node, a drive output terminal, a level transmission output terminal and a noise reduction circuit, the noise reduction circuit includes: a noise reduction control unit, wherein a first control terminal of the noise reduction control unit is connected to the noise reduction control terminal, and a second control terminal of the noise reduction control unit is connected to the drive control node, and is configured to output a noise reduction signal during a non-scanning time of a scanning phase of a current-stage gate drive module under the action of a noise reduction control signal output by the noise reduction control terminal and a voltage on the drive control node; a noise reduction execution unit, wherein the control end of the noise reduction execution unit is connected to the output end of the noise reduction control unit, and the output end of the noise reduction execution unit is respectively connected to the drive control node, the drive output end, and the stage transmission output end, and is configured to perform noise reduction processing on the voltages on the drive control node, the drive output end, and the stage transmission output end according to the noise reduction signal; a threshold correction unit, the threshold correction unit being connected to the noise reduction execution unit and configured to place the transistors in the noise reduction execution unit in a reverse bias state during a blanking phase; The noise reduction execution unit includes: a fifth transistor, a control end of the fifth transistor is connected to the output end of the noise reduction control unit, a first end of the fifth transistor is connected to the driving output end, and a second end of the fifth transistor is connected to the second low-level end; The threshold correction unit includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the control terminal of the fifth transistor, and a first terminal of the eighth transistor is connected to the control terminal of the eighth transistor; A ninth transistor, wherein the control end of the ninth transistor is connected to the correction power supply end, the first end of the ninth transistor is connected to the second end of the eighth transistor, and the second end of the ninth transistor is connected to the first low level end.

4. The noise reduction circuit according to any one of claims 1 to 3, characterized in that: The noise reduction control unit includes: a first transistor, wherein a control terminal of the first transistor is connected to the noise reduction control terminal, and a first terminal of the first transistor is connected to the control terminal of the first transistor; a second transistor, wherein a control terminal of the second transistor is connected to the second terminal of the first transistor, and a first terminal of the second transistor is connected to the first terminal of the first transistor; a third transistor, wherein a control terminal of the third transistor is connected to the drive control node, a first terminal of the third transistor is connected to the second terminal of the first transistor, and a second terminal of the third transistor is connected to the first low level terminal; a fourth transistor, wherein a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to the second end of the second transistor, and a second end of the fourth transistor is connected to the first low-level end.

5. The noise reduction circuit according to claim 4, wherein: The noise reduction execution unit includes: a sixth transistor, wherein a control terminal of the sixth transistor is connected to the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the drive control node, and a second terminal of the sixth transistor is connected to the first low-level terminal; A seventh transistor, wherein the control end of the seventh transistor is connected to the control end of the fifth transistor, the first end of the seventh transistor is connected to the stage transmission output end, and the second end of the seventh transistor is connected to the second low level end.

6. The noise reduction circuit according to claim 1, wherein: The noise reduction control unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the control terminal of the first transistor is connected to the noise reduction control terminal, and the first terminal of the first transistor is connected to the control terminal of the first transistor; the control terminal of the second transistor is connected to the second terminal of the first transistor, and the first terminal of the second transistor is connected to the first terminal of the first transistor; the control terminal of the third transistor is connected to the drive control node, the first terminal of the third transistor is connected to the second terminal of the first transistor, and the second terminal of the third transistor is connected to the first low-level terminal; the control terminal of the fourth transistor is connected to the control terminal of the third transistor, the first terminal of the fourth transistor is connected to the second terminal of the second transistor, and the second terminal of the fourth transistor is connected to the first low-level terminal; the threshold correction unit also includes: a tenth transistor, wherein the control end of the tenth transistor is connected to the second end of the first transistor, the first end of the tenth transistor is connected to the control end of the tenth transistor, and the second end of the tenth transistor is connected to the first end of the ninth transistor.

7. The noise reduction circuit according to claim 6, wherein: In the scanning phase, the first low level end and the second low level end output a low level; In the blanking phase, the first low level end and the second low level end first output a low level and then output a high level.

8. The noise reduction circuit according to claim 3, wherein: During the scanning phase, the first low-level terminal, the second low-level terminal and the correction power supply terminal output low levels; In the blanking phase, the first low level end and the second low level end first output a low level and then output a high level, and the corrected power supply end outputs a high level.

9. A gate drive circuit comprising N cascaded gate drive modules, characterized in that: The n-th level gate driver module includes: A pull-up unit, wherein the pull-up unit is respectively connected to the driving output terminal of the n-th level gate driving module and the level transmission output terminal of the n-th level gate driving module; A pull-down unit, the pull-down unit being connected to the stage transmission output terminal of the n+j-th stage gate driving module, and the pull-down unit being further connected to the pull-up unit via a driving control node; an output unit, the output unit being connected to the clock signal terminal and the drive control node respectively; The noise reduction circuit according to any one of claims 1 to 8, wherein the noise reduction circuit is respectively connected to the drive control node, the drive output terminal and the stage transmission output terminal of the current stage gate drive module.

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