Noise reduction circuit and gate drive circuit

Abstract

The present application belongs to the field of display drive technology, and specifically relates to a noise reduction circuit and a gate drive circuit, wherein the noise reduction circuit includes: a first noise reduction module for performing noise reduction processing on the voltages on a drive control node, a drive output terminal, and a stage transmission output terminal; and further for placing the noise reduction transistor in the first noise reduction module in a reverse bias state under the action of a second noise reduction control signal; a second noise reduction module for performing noise reduction processing on the voltages on the drive control node, the drive output terminal, and the stage transmission output terminal; and further for placing the noise reduction transistor in the second noise reduction module in a reverse bias state under the action of the first noise reduction control signal; the present application improves the problem of threshold voltage drift of the noise reduction transistor by placing the noise reduction transistors in the two groups of noise reduction modules in a reverse bias state when not working, thereby offsetting the forward bias state of the noise reduction transistors when alternately working, thereby improving the noise reduction stability of the noise reduction circuit.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and particularly relates to a noise reduction circuit and a gate drive circuit. Background Art

[0002] TFT-LCDs (Thin-Film Transistor Liquid Crystal Displays) display images by controlling the transmittance of pixels in the display area. Specifically, under the action of an applied voltage, the liquid crystal molecules within a single pixel deflect, thereby changing the transmittance and displaying color. The display area is composed of pixels arranged in an array, and dynamic display is achieved by switching the pixel state frame by frame.

[0003] The Gate Driver on Array (GOA) is a key circuit for TFT-LCDs to achieve progressive scanning. The noise reduction circuit, which performs noise reduction on key nodes, is the core module for the reliable operation of the GOA. However, the noise reduction transistors in the noise reduction circuit are often biased at a positive gate-source voltage (Vgs) for a long time during operation, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift. This leads to unstable noise reduction and abnormal GOA output signals, affecting the display quality of the display panel.

[0004] Therefore, how to improve the threshold voltage drift of the noise reduction transistor that causes noise reduction instability is a problem that the current baseband needs to solve. Summary of the Invention

[0005] An embodiment of the present application provides a noise reduction circuit and a gate drive circuit. In the present application, the noise reduction transistors in the two groups of noise reduction modules are in a reverse bias state when not working, so as to offset the forward bias state of the noise reduction transistors when alternatingly working, thereby improving the problem of threshold voltage drift of the noise reduction transistors and improving the noise reduction stability of the noise reduction circuit.

[0006] In a first aspect, an embodiment of the present application provides a noise reduction circuit, which is applied to a gate drive circuit, wherein the gate drive circuit includes N cascaded gate drive modules, and the nth-level gate drive module includes at least a drive control node, a drive output terminal, a stage transmission output terminal and a noise reduction circuit, and the noise reduction circuit includes: a first noise reduction module, wherein the first input terminal of the first noise reduction module is connected to the first noise reduction control terminal, the second input terminal of the first noise reduction module is connected to the drive control node, the third input terminal of the first noise reduction module is connected to the second noise reduction control terminal, and the output terminal of the first noise reduction module is respectively connected to the drive output terminal, the stage transmission output terminal and the drive control node, and is used to perform noise reduction processing on the voltages on the drive control node, the drive output terminal and the stage transmission output terminal under the action of a first noise reduction control signal output by the first noise reduction control terminal and the voltage on the drive control node; and is also used to output a second noise reduction control signal output by the second noise reduction control terminal. a second noise reduction module, wherein the first input terminal of the second noise reduction module is connected to the second noise reduction control terminal, the second input terminal of the second noise reduction module is connected to the drive control node, the third input terminal of the second noise reduction module is connected to the first noise reduction control terminal, and the output terminal of the second noise reduction module is respectively connected to the drive output terminal, the stage transmission output terminal and the drive control node, and is used to perform noise reduction processing on the voltages on the drive control node, the drive output terminal and the stage transmission output terminal under the action of the second noise reduction control signal output by the second noise reduction control terminal and the voltage on the drive control node; and is also used to put the noise reduction transistor in the second noise reduction module in a reverse bias state under the action of the first noise reduction control signal output by the first noise reduction control terminal; wherein the first noise reduction control signal and the second noise reduction control signal have opposite phases.

[0007] In a second aspect, an embodiment of the present application provides a gate drive circuit, comprising N cascaded gate drive modules, the nth-level gate drive module comprising: a pull-up unit, the pull-up unit being respectively connected to the drive output terminal of the ni-th-level gate drive module and the level transmission output terminal of the ni-th-level gate drive module; a pull-down unit, the pull-down unit being connected to the level transmission output terminal of the n+j-th-level gate drive module, and the pull-down unit being further connected to the pull-up unit through a drive control node; an output unit, the output unit being respectively connected to the clock signal terminal and the drive control node; and a noise reduction circuit, the noise reduction circuit being respectively connected to the drive control node, the drive output terminal and the level transmission output terminal of the current-level gate drive module.

[0008] The technical solutions provided in the embodiments of the present application have at least the following beneficial effects:

[0009] (1) In the present application, when the noise reduction transistor in the first noise reduction module performs noise reduction processing on an important node, the noise reduction transistor in the non-working second noise reduction module is placed in a reverse bias state, and when the noise reduction transistor in the second noise reduction module performs noise reduction processing on an important node, the noise reduction transistor in the non-working first noise reduction module is placed in a reverse bias state; therefore, the present application improves the problem of threshold voltage drift of the noise reduction transistor by making the noise reduction transistors in the two groups of noise reduction modules in a reverse bias state when not working, thereby offsetting the forward bias state of the noise reduction transistor when alternately working, and improving the noise reduction stability of the noise reduction circuit.

[0010] (2) The reverse correction of the noise reduction transistor in this application is performed during the non-working period of the noise reduction transistor. The reverse correction time is long, which can effectively suppress the threshold voltage drift while not occupying the scanning time or blanking time, and will not have any impact on the charging rate of the pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0012] Figure 1 Shown is a structural schematic diagram of a gate drive module provided in an embodiment of the present application.

[0013] Figure 2 FIG. 1 is a circuit diagram of a noise reduction circuit in related art.

[0014] Figure 3 Shown is a structural schematic diagram of the first noise reduction circuit provided in an embodiment of the present application.

[0015] Figure 4 The figure shows a driving timing diagram provided in an embodiment of the present application.

[0016] Figure 5 Shown is a structural schematic diagram of a second noise reduction circuit provided in an embodiment of the present application.

[0017] Figure 6 Shown is a circuit diagram of a first noise reduction circuit provided in an embodiment of the present application.

[0018] Figure 7 FIG. 1 is a circuit diagram of a second noise reduction circuit provided in an embodiment of the present application.

[0019] Figure 8 FIG. 1 is a circuit diagram of a third noise reduction circuit provided in an embodiment of the present application.

[0020] Figure 9 FIG. 1 is a circuit diagram of a fourth noise reduction circuit provided in an embodiment of the present application.

[0021] Description of reference numerals:

[0022] 100, noise reduction circuit; 110, first noise reduction module; 111, first noise reduction control unit; 112, first noise reduction execution unit; 1121, first execution subunit; 1122, first correction subunit; 120, second noise reduction module; 121, second noise reduction control unit; 122, second noise reduction execution unit; 1221, second execution subunit; 1222, second correction subunit;

[0023] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor;

[0024] Qn, drive control node; Fn, stage transmission output terminal; Gn, drive output terminal; LC1, first noise reduction control terminal; LC2, second noise reduction control terminal; VSS1, first low level terminal; VSS2, second low level terminal. DETAILED DESCRIPTION

[0025] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0026] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0027] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0028] The inventors of this application have found that the gate drive circuit includes N cascaded gate drive modules, such as Figure 1 As shown, the n-th level gate driving module mainly includes a pull-up unit, a pull-down unit, an output unit, a reset unit and a noise reduction circuit. The pull-up unit and the pull-down unit output a Q-point voltage. The pull-up unit and the pull-down unit need to obtain multiple level transmission signals from the upper and lower gate driving modules. The Q-point voltage is the turn-on voltage of the output unit, so that the output unit outputs a gate driving signal to provide a turn-on voltage for the display area. The reset unit is used to avoid the influence between frames. The noise reduction circuit performs noise reduction processing on the signals at each key node; wherein Qn represents the driving control node of the n-th level gate driving module, Gn represents the driving output terminal of the n-th level gate driving module, Fn represents the level transmission output terminal of the n-th level gate driving module, CKn represents the clock signal terminal of the n-th level gate driving module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-3 represents the driving output terminal of the n-3-th level gate driving module, Fn-3 represents the level transmission output terminal of the n-3-th level gate driving module and Fn+4 represents the level transmission output terminal of the n+4-th level gate driving module.

[0029] The normal output of the gate drive module is a necessary condition to ensure the normal display of the picture, so the noise reduction circuit is particularly important for suppressing the noise of the signal. Figure 2The figure shows a circuit diagram of a noise reduction circuit in the related art. The first transistor T1 and the second transistor T2 are control transistors, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all noise reduction transistors. When the driving control node (i.e., the Q point) in the n-th stage gate driving module is at a low level, the noise reduction control terminal LC continuously outputs a high level. At this time, the first transistor T1 is turned on and the second transistor T2 is turned off, so that the noise reduction control node Pn is at a high level, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on respectively, thereby connecting the driving output terminal Gn, the driving control node Qn and the stage transmission module to the high level. The signal on the output terminal Fn is continuously pulled low to achieve noise reduction processing for each important node in the gate drive module; since the drive output terminal, drive control node and stage transmission output terminal in each stage of the gate drive module are not subjected to noise reduction only during the scanning time of the current stage, the rest of the time is the noise reduction processing period; therefore, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 in the noise reduction circuit need to be in a positive gate-source voltage bias state for a long time, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift, thereby causing the output signal of the GOA circuit to be abnormal, affecting the display effect of the display panel.

[0030] In order to improve the threshold voltage drift problem of the noise reduction transistor, the present application provides a noise reduction circuit, which specifically includes the following embodiments:

[0031] Figure 3 FIG. 1 is a schematic structural diagram of a noise reduction circuit provided in an embodiment of the present application; the noise reduction circuit 100 of this embodiment is applied to a gate drive circuit, and the gate drive circuit includes N cascaded gate drive modules; Figure 1 and Figure 3 As shown, each gate driving module at least includes a driving control node Qn, a driving output terminal Gn, a stage transmission output terminal Fn and a noise reduction circuit 100.

[0032] like Figure 3 As shown, the noise reduction circuit 100 of this embodiment includes a first noise reduction module 110. A first input terminal of the first noise reduction module 110 is connected to the first noise reduction control terminal LC1, a second input terminal of the first noise reduction module 110 is connected to the drive control node Qn, and a third input terminal of the first noise reduction module 110 is connected to the second noise reduction control terminal LC2. The output terminals of the first noise reduction module 110 are respectively connected to the drive output terminal Gn, the stage transmission output terminal Fn, and the drive control node Qn. The first noise reduction module 110 is configured to perform noise reduction processing on the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn in response to a first noise reduction control signal output from the first noise reduction control terminal LC1 and the voltage on the drive control node Qn; and is further configured to reverse bias the noise reduction transistor in the first noise reduction module 110 in response to a second noise reduction control signal output from the second noise reduction control terminal LC2.

[0033] The noise reduction circuit 100 of this embodiment further includes a second noise reduction module 120. A first input terminal of the second noise reduction module 120 is connected to the second noise reduction control terminal LC2, a second input terminal of the second noise reduction module 120 is connected to the drive control node Qn, a third input terminal of the second noise reduction module 120 is connected to the first noise reduction control terminal LC1, and output terminals of the second noise reduction module 120 are respectively connected to the drive output terminal Gn, the stage transmission output terminal Fn, and the drive control node Qn. The second noise reduction module 120 is configured to perform noise reduction processing on the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn in response to a second noise reduction control signal output from the second noise reduction control terminal LC2 and the voltage on the drive control node Qn; and is further configured to reverse bias the noise reduction transistor in the second noise reduction module 120 in response to a first noise reduction control signal output from the first noise reduction control terminal LC1.

[0034] Specifically, the first noise reduction control signal output by the first noise reduction control terminal LC1 and the second noise reduction control signal output by the second noise reduction control terminal LC2 are in opposite phases. That is, Figure 4 As shown, during the working frame of the first noise reduction control signal (i.e., the LC1 working frame), the first noise reduction control signal output by the first noise reduction control terminal LC1 is at a high level, and the second noise reduction control signal output by the second noise reduction control terminal LC2 is at a low level; conversely, during the working frame of the second noise reduction control signal (i.e., the LC2 working frame), the first noise reduction control signal output by the first noise reduction control terminal LC1 is at a low level, and the second noise reduction control signal output by the second noise reduction control terminal LC2 is at a high level; wherein, the phase switching between the first noise reduction control signal and the second noise reduction control signal can be one frame or multiple frames.

[0035] Here, combined Figure 3 and Figure 4 The working principle of the noise reduction circuit 100 of this embodiment is described in detail:

[0036] (1) In the LC1 working frame, the first noise reduction control signal is at a high level and the second noise reduction control signal is at a low level. Since the voltage on the drive control node Qn is at a high level, it is the scanning time of the current gate drive module, so the noise reduction of the important nodes of the gate drive module can only be performed when the drive control node Qn is at a low level. Therefore, under the action of the first noise reduction control signal at a high level and the low level voltage on the drive control node Qn, the first noise reduction module 110 performs noise reduction processing on the voltages on the drive control node Qn, the drive output terminal Gn and the stage transmission output terminal Fn. At the same time, the second noise reduction module 120 does not perform noise reduction processing under the action of the second noise reduction control signal at a low level, but under the action of the first noise reduction control signal at a high level, the second noise reduction module 120 puts the noise reduction transistor in the second noise reduction module 120 in a reverse bias state. That is, when the noise reduction transistor in the first noise reduction module 110 performs noise reduction processing on the important nodes, the noise reduction transistor in the second noise reduction module 120 is in a reverse bias state.

[0037] (2) In the LC2 working frame, the first noise reduction control signal is at a low level and the second noise reduction control signal is at a high level; therefore, under the action of the second noise reduction control signal at a high level and the low level voltage on the driving control node Qn, the second noise reduction module 120 performs noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn. At the same time, the first noise reduction module 110 does not perform noise reduction processing under the action of the first noise reduction control signal at a low level, but under the action of the second noise reduction control signal at a high level, the first noise reduction module 110 causes the noise reduction transistor in the first noise reduction module 110 to be in a reverse bias state; that is, when the noise reduction transistor in the second noise reduction module 120 performs noise reduction processing on the important nodes, the noise reduction transistor in the first noise reduction module 110 is in a reverse bias state.

[0038] It can be seen from this that when the noise reduction transistor in the first noise reduction module 110 performs noise reduction processing on an important node, the noise reduction transistor in the non-operating second noise reduction module 120 is placed in a reverse bias state, and when the noise reduction transistor in the second noise reduction module 120 performs noise reduction processing on an important node, the noise reduction transistor in the non-operating first noise reduction module 110 is placed in a reverse bias state. Therefore, the present application improves the problem of threshold voltage drift of the noise reduction transistor by making the noise reduction transistors in the two groups of noise reduction modules in a reverse bias state when not in operation to offset the forward bias state of the noise reduction transistors when alternately working, thereby improving the noise reduction stability of the noise reduction circuit 100. Furthermore, the present application performs reverse correction of the noise reduction transistor during the non-operating period of the noise reduction transistor. The reverse correction time is long, which can effectively suppress threshold voltage drift while not occupying scanning time or blanking time, and will not have any impact on the pixel charging rate.

[0039] Continue as Figure 3 As shown, the first noise reduction module 110 of this embodiment includes: a first noise reduction control unit 111 and a first noise reduction execution unit 112. The first control terminal of the first noise reduction control unit 111 is connected to the first noise reduction control terminal LC1, and the second control terminal of the first noise reduction control unit 111 is connected to the driving control node Qn. The first noise reduction control unit 111 is configured to output a first noise reduction signal in response to a first noise reduction control signal output from the first noise reduction control terminal LC1 and a voltage on the driving control node Qn. The first control terminal of the first noise reduction execution unit 112 is connected to the output terminal of the first noise reduction control unit 111, and the second control terminal of the first noise reduction execution unit 112 is connected to the second noise reduction control terminal LC2. The output terminal of the first noise reduction execution unit 112 is respectively connected to the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn. The first noise reduction execution unit 112 is configured to perform noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn according to the first noise reduction signal. The first noise reduction execution unit 112 is also configured to reverse-bias the noise reduction transistor in the first noise reduction execution unit 112 according to the second noise reduction control signal.

[0040] The second noise reduction module 120 of this embodiment includes: a second noise reduction control unit 121 and a second noise reduction execution unit 122. The first control terminal of the second noise reduction control unit 121 is connected to the second noise reduction control terminal LC2, and the second control terminal of the second noise reduction control unit 121 is connected to the driving control node Qn. The second noise reduction control unit 121 is configured to output a second noise reduction signal in response to a first noise reduction control signal output from the second noise reduction control terminal LC2 and a voltage on the driving control node Qn. The first control terminal of the second noise reduction execution unit 122 is connected to the output terminal of the second noise reduction control unit 121, and the second control terminal of the second noise reduction execution unit 122 is connected to the first noise reduction control terminal LC1. The output terminal of the second noise reduction execution unit 122 is respectively connected to the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn. The second noise reduction execution unit 122 is configured to perform noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn according to the second noise reduction signal. The second noise reduction execution unit 122 is also configured to reverse bias the noise reduction transistor in the second noise reduction execution unit 122 according to the first noise reduction control signal.

[0041] It should be noted that the specific working principles of the first noise reduction control unit 111 and the second noise reduction control unit 121 are the same, and the working principles of the first noise reduction execution unit 112 and the second noise reduction execution unit 122 are the same. The only difference is that they are controlled by different noise reduction control signals. The following only describes the working principle of one of the noise reduction control units and the noise reduction execution unit in detail.

[0042] In the driving technology of display panels, the scanning phase and the blanking phase are key points in timing control. The two phases together ensure that pixel data is correctly updated and the display is stable. The scanning phase is the phase in which the gate drive circuit activates pixels row by row and writes data. For example, in a display with progressive scanning, the gate drive signal selects each row of pixels from top to bottom and writes the voltage signal to the pixel units of that row through the data line. The blanking phase is the "interval" between scans, when the drive circuit stops writing data to switch rows or frames to prevent signal overlap and display distortion.

[0043] In this embodiment, taking the first noise reduction control unit 111 as an example, under the combined action of the first noise reduction control signal output by the first noise reduction control terminal LC1 and the voltage on the drive control node Qn, the first noise reduction control unit 111 in the n-th stage gate driving module outputs the first noise reduction signal during a non-scanning time period in a scanning phase of the n-th stage gate driving module, and does not output the first noise reduction signal during a scanning time period of the n-th stage gate driving module.

[0044] Taking the first noise reduction execution unit 112 as an example, noise reduction processing is performed on the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn according to the first noise reduction signal output by the first noise reduction control unit 111. That is, by continuously pulling down the signals on the drive output terminal Gn, the drive control node Qn, and the stage transmission output terminal Fn in the gate drive module of this stage by the first noise reduction execution unit 112, leakage current in the circuit or other transistor abnormalities are avoided, which cause the voltages on the drive output terminal Gn, the drive control node Qn, and / or the stage transmission output terminal Fn to be at a high level, thereby preventing display abnormalities such as pixel mischarging.

[0045] Figure 5 FIG2 is a schematic structural diagram of a second noise reduction circuit provided in an embodiment of the present application; Figure 5 and Figure 4 The difference is: Figure 5 Will Figure 4 The first noise reduction execution unit 112 is subdivided into a first execution sub-unit 1121 and a first correction sub-unit 1122 , and the second noise reduction execution unit 122 is subdivided into a second execution sub-unit 1221 and a second correction sub-unit 1222 .

[0046] Specifically, the first noise reduction execution unit 112 includes a first execution subunit 1121 and a first correction subunit 1122. The control end of the first execution subunit 1121 is connected to the output end of the first noise reduction control unit 111, and the output end of the first execution subunit 1121 is respectively connected to the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn, for performing noise reduction processing on the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn according to the first noise reduction signal. The first control end of the first correction subunit 1122 is connected to the first noise reduction control terminal LC1, and the second control end of the first correction subunit 1122 is connected to the second noise reduction control terminal LC2. The output ends of the first correction subunit 1122 are respectively connected to the first execution subunit 1121, for outputting a low level when the first execution subunit 1121 is performing noise reduction processing, and for reverse biasing the noise reduction transistor in the first execution subunit 1121 according to the second noise reduction control signal when the first execution subunit 1121 is not performing noise reduction processing.

[0047] Optionally, the second noise reduction execution unit 122 includes a second execution subunit 1221 and a second correction subunit 1222, wherein the control end of the second execution subunit 1221 is connected to the output end of the second noise reduction control unit 121, and the output end of the second execution subunit 1221 is respectively connected to the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn, for performing noise reduction processing on the voltages on the drive control node Qn, the drive output end Gn, and the stage transmission output end Fn according to the second noise reduction signal; the first control end of the second correction subunit 1222 is connected to the second noise reduction control end LC2, the second control end of the second correction subunit 1222 is connected to the first noise reduction control end LC1, and the output ends of the second correction subunit 1222 are respectively connected to the second execution subunit 1221, for outputting a low level when the second execution subunit 1221 performs noise reduction processing, and for placing the noise reduction transistor in the second execution subunit 1221 in a reverse bias state according to the first noise reduction control signal when the second execution subunit 1221 does not perform noise reduction processing.

[0048] It should be noted that, taking the first noise reduction execution unit 112 as an example, the transistor in the first execution subunit 1121 is a noise reduction transistor. When the first execution subunit 1121 is operating, the first correction subunit 1122 provides a low level to the first execution subunit 1121 under the action of the first noise reduction control signal. This causes the noise reduction transistor in the first execution subunit 1121 to perform noise reduction processing on the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn under the action of the first noise reduction signal and the low level. That is, the noise reduction transistor in the first execution subunit 1121 is in a forward biased state. In addition, when the first execution subunit 1121 is not operating, the first correction subunit 1122 causes the noise reduction transistor in the first execution subunit 1121 to be in a reverse biased state under the action of the second noise reduction control signal. This can offset the forward bias of the noise reduction transistor during operation and improve the problem of threshold voltage drift of the noise reduction transistor. The operating principles of the second execution subunit 1221 and the second correction subunit 1222 are the same as those described above and will not be further described here.

[0049] Figure 6 FIG. 1 is a circuit diagram of a first noise reduction circuit provided in an embodiment of the present application, as shown in FIG. Figure 6 As shown, the first noise reduction control unit 111 and the second noise reduction control unit 121 each include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; wherein the control terminal of the first transistor T1 in the first noise reduction control unit 111 is connected to the first noise reduction control terminal LC1, and the control terminal of the first transistor of the second noise reduction control unit 121 is connected to the second noise reduction control terminal LC2. Optionally, the first terminal of the first transistor T1 is connected to the control terminal of the first transistor T1; the control terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the first terminal of the second transistor T2 is connected to the first terminal of the first transistor T1; the control terminal of the third transistor T3 is connected to the driving control node Qn, the first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, and the second terminal of the third transistor T3 is connected to the first low-level terminal VSS1; the control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3, the first terminal of the fourth transistor T4 is connected to the second terminal of the second transistor T2, and the second terminal of the fourth transistor T4 is connected to the first low-level terminal VSS1.

[0050] It should be noted that the main purpose of the first noise reduction control unit 111 and the second noise reduction control unit 121 of this embodiment is to invert the voltage on the drive control node Qn. That is, when the voltage on the drive control node Qn is at a high level, the first noise reduction control unit 111 or the second noise reduction control unit 121 outputs a low level; when the voltage on the drive control node Qn is at a low level, the first noise reduction control unit 111 or the second noise reduction control unit 121 outputs a high level. The specific working principle of the first noise reduction control unit 111 is explained here:

[0051] (1) When the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all N-type MOS transistors, in the working phase of the first noise reduction control signal, the first noise reduction control terminal LC1 always outputs a high level and continuously turns on the first transistor T1.

[0052] (2) During the scanning time of the current-stage gate driving module, the voltage on the driving control node Qn is at a high level, and the third transistor T3 and the fourth transistor T4 are turned on at the same time, so that the voltages on the node A1n and the first noise reduction control node P1n are both at the first low level output by the first low-level terminal VSS1, thereby turning off the second transistor T2 and causing the first noise reduction control unit 111 to output the first low level.

[0053] (3) During the non-scanning time of the scanning phase of the current-level gate driving module, the voltage on the driving control node Qn is at a low level, and the third transistor T3 and the fourth transistor T4 are turned off at the same time, so that the voltage on the node A1n is at a high level, thereby turning on the second transistor T2, and the first noise reduction control unit 111 outputs a high level, i.e., the first noise reduction signal.

[0054] It should also be noted that the above working principle is described using the example where the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all N-type MOS transistors. When the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are P-type transistors, their working principles are the same but the phases are opposite, which will not be repeated here.

[0055] like Figure 6As shown, the first noise reduction execution unit 112 and the second noise reduction execution unit 122 each include a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; specifically, in the first noise reduction execution unit 112, the control end of the fifth transistor T5 is connected to the output end of the first noise reduction control unit 111, the first end of the fifth transistor T5 is connected to the stage transfer output end Fn, and the second end of the fifth transistor T5 is connected to the second noise reduction control end LC2; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the drive control node Qn, and the second end of the sixth transistor T6 is connected to the second noise reduction control end LC2; the control end of the seventh transistor T7 is connected to the control end of the fifth transistor T5, the first end of the seventh transistor T7 is connected to the drive output end Gn, and the second end of the seventh transistor T7 is connected to the second noise reduction control end LC2.

[0056] In the second noise reduction execution unit 122, the control end of the fifth transistor T5 is connected to the output end of the second noise reduction control unit 121, the first end of the fifth transistor T5 is connected to the stage transmission output end Fn, and the second end of the fifth transistor T5 is connected to the first noise reduction control end LC1; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the driving control node Qn, and the second end of the sixth transistor T6 is connected to the first noise reduction control end LC1; the control end of the seventh transistor T7 is connected to the control end of the fifth transistor T5, the first end of the seventh transistor T7 is connected to the stage transmission output end FnGn, and the second end of the seventh transistor T7 is connected to the first noise reduction control end LC1.

[0057] It should be noted that, taking the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 as N-type MOS transistors as an example, the working principle of the first noise reduction execution unit 112 is described in detail:

[0058] (1) When the first noise reduction control unit 111 outputs the first noise reduction signal, that is, the voltage on the first noise reduction control node P1n is at a high level, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on at the same time; at this time, the second noise reduction control signal output by the second noise reduction control terminal LC2 is at a low level, so that the voltage on the stage transfer output terminal Fn is pulled down through the turned-on fifth transistor T5, the voltage on the drive control node Qn is pulled down through the turned-on sixth transistor T6, and the voltage on the drive output terminal Gn is pulled down through the turned-on seventh transistor T7.

[0059] (2) When the first noise reduction control unit 111 does not output the first noise reduction signal, that is, the voltage on the first noise reduction control node P1n is at a low level, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off, and the noise reduction processing of the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn is stopped.

[0060] In this embodiment, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the first noise reduction execution unit 112 serve as noise reduction transistors in the first noise reduction module 110, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the second noise reduction execution unit 122 serve as noise reduction transistors in the second noise reduction module 120. In this embodiment, the control terminal of the noise reduction transistor is connected to the output terminal of the noise reduction control unit, the first terminal of the noise reduction transistor is connected to the important node, and the second terminal of the noise reduction transistor is connected to the corresponding noise reduction control terminal of another module. This ensures that the noise reduction transistor is in a forward biased state during noise reduction operation and in a reverse biased state during non-noise reduction operation, effectively alleviating the threshold voltage drift problem of the noise reduction transistor.

[0061] Figure 7 FIG. 1 is a circuit diagram of a second noise reduction circuit provided in an embodiment of the present application; Figure 7 The first noise reduction control unit 111 and the second noise reduction control unit 121 in the noise reduction circuit 100 are respectively Figure 6 The same as shown, no further description is given here; Figure 7 and Figure 6 The difference is that the specific circuit structures of the first noise reduction execution unit 112 and the second noise reduction execution unit 122 are different. Figure 7 As shown, the first execution subunit 1121 and the second execution subunit 1221 both include a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7; the first correction subunit 1122 and the second correction subunit 1222 both include an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 and an eleventh transistor T11.

[0062] Specifically, in the first execution sub-unit 1121, the control end of the fifth transistor T5 is connected to the output end of the first noise reduction control unit 111, the first end of the fifth transistor T5 is connected to the stage transmission output end Fn, and the second end of the fifth transistor T5 is connected to the first output end of the first correction sub-unit 1122; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the drive control node Qn, and the second end of the sixth transistor T6 is connected to the second output end of the first correction sub-unit 1122; the control end of the seventh transistor T7 is connected to the control end of the fifth transistor T5, the first end of the seventh transistor T7 is connected to the drive output end Gn, and the second end of the seventh transistor T7 is connected to the third output end of the first correction sub-unit 1122; wherein the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are respectively used as noise reduction transistors of the first noise reduction module 110.

[0063] In the second execution sub-unit 1221, the control end of the fifth transistor T5 is connected to the output end of the second noise reduction control unit 121, the first end of the fifth transistor T5 is connected to the stage transmission output end Fn, and the second end of the fifth transistor T5 is connected to the first output end of the second correction sub-unit 1222; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the drive control node Qn, and the second end of the sixth transistor T6 is connected to the second output end of the second correction sub-unit 1222; the control end of the seventh transistor T7 is connected to the control end of the fifth transistor T5, the first end of the seventh transistor T7 is connected to the drive output end Gn, and the second end of the seventh transistor T7 is connected to the third output end of the second correction sub-unit 1222; wherein the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are respectively used as noise reduction transistors of the second noise reduction module 120.

[0064] It should be noted that the working principles of the first execution subunit 1121 and the second execution subunit 1221 in this embodiment are the same as those in the embodiment of the present invention. Figure 6 The working principles of the first noise reduction execution unit 112 and the second noise reduction execution unit 122 are basically the same, and the only difference is that: Figure 6 The second end of the fifth transistor T5, the second end of the sixth transistor T6 and the second end of the seventh transistor T7 are connected to the noise reduction control end, and Figure 7 The second end of the fifth transistor T5, the second end of the sixth transistor T6 and the second end of the seventh transistor T7 are connected to the three output ends of the execution sub-unit. The working principles of the first execution sub-unit 1121 and the second execution sub-unit 1221 are not described in detail here.

[0065] In the first correction sub-unit 1122, a control terminal of the eighth transistor T8 is connected to the first noise reduction control terminal LC1, a first terminal of the eighth transistor T8 is connected to the second terminal of the fifth transistor T5, and a second terminal of the eighth transistor T8 is connected to the first low-level terminal VSS1; a control terminal of the ninth transistor T9 is connected to the control terminal of the eighth transistor T8, a first terminal of the ninth transistor T9 is connected to the second terminal of the sixth transistor T6, and a second terminal of the ninth transistor T9 is connected to the first low-level terminal VSS1; a control terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8, a first terminal of the tenth transistor T10 is connected to the second terminal of the seventh transistor T7, and a second terminal of the tenth transistor T10 is connected to the first low-level terminal VSS1; a control terminal of the eleventh transistor T11 is connected to the second noise reduction control terminal LC2, a first terminal of the eleventh transistor T11 is connected to the control terminal of the eleventh transistor T11, and a second terminal of the eleventh transistor T11 is connected to the first terminal of the eighth transistor T8, the first terminal of the ninth transistor T9, and the first terminal of the tenth transistor T10, respectively.

[0066] In the second correction sub-unit 1222, a control terminal of the eighth transistor T8 is connected to the second noise reduction control terminal LC2, a first terminal of the eighth transistor T8 is connected to the second terminal of the fifth transistor T5, and a second terminal of the eighth transistor T8 is connected to the first low-level terminal VSS1; a control terminal of the ninth transistor T9 is connected to the control terminal of the eighth transistor T8, a first terminal of the ninth transistor T9 is connected to the second terminal of the sixth transistor T6, and a second terminal of the ninth transistor T9 is connected to the first low-level terminal VSS1; a control terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8, a first terminal of the tenth transistor T10 is connected to the second terminal of the seventh transistor T7, and a second terminal of the tenth transistor T10 is connected to the first low-level terminal VSS1; a control terminal of the eleventh transistor T11 is connected to the first noise reduction control terminal LC1, a first terminal of the eleventh transistor T11 is connected to the control terminal of the eleventh transistor T11, and a second terminal of the eleventh transistor T11 is connected to the first terminal of the eighth transistor T8, the first terminal of the ninth transistor T9, and the first terminal of the tenth transistor T10, respectively.

[0067] It should be noted that, taking the first correction sub-unit 1122 as an example, its specific working principle is as follows:

[0068] (1) When the noise reduction transistors in the first execution sub-unit 1121 perform noise reduction, the first noise reduction control signal is at a high level and the second noise reduction control signal is at a low level. At this time, the high-level first noise reduction control signal turns on the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10, so that the second ends of the noise reduction transistors are respectively connected to the first low-level end VSS1, thereby achieving noise reduction processing on important nodes through the noise reduction transistors in a forward biased state.

[0069] (2) When the noise reduction transistor in the first execution sub-unit 1121 does not perform noise reduction, the first noise reduction control signal is at a low level and the second noise reduction control signal is at a high level; at this time, the high-level second noise reduction control signal turns on the eleventh transistor T11, so that the second end of the noise reduction transistor is connected to the high level, and the non-working noise reduction transistor is in a reverse bias state, which effectively improves the threshold voltage drift problem of the noise reduction transistor.

[0070] Figure 8 FIG. 1 is a schematic structural diagram of a third noise reduction circuit provided in an embodiment of the present application; Figure 8 exist Figure 7 On the basis of adding a second low level terminal VSS2 and a twelfth transistor T12; specifically as Figure 8 As shown: the first correction sub-unit 1122 and the second correction sub-unit 1222 include: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12; the control end of the eighth transistor T8 is connected to the first noise reduction control end LC1 or the second noise reduction control end LC2, the first end of the eighth transistor T8 is connected to the second end of the fifth transistor T5, and the second end of the eighth transistor T8 is connected to the first low-level end VSS1; the control end of the ninth transistor T9 is connected to the control end of the eighth transistor T8, the first end of the ninth transistor T9 is connected to the second end of the sixth transistor T6, and the second end of the ninth transistor T9 is connected to the first low-level end VSS1; the control end of the tenth transistor T10 is connected to the eighth transistor T8 The first end of the tenth transistor T10 is connected to the second end of the seventh transistor T7, and the second end of the tenth transistor T10 is connected to the second low level end VSS2; the control end of the eleventh transistor T11 is connected to the second noise reduction control end LC2 or the first noise reduction control end LC1, the first end of the eleventh transistor T11 is connected to the control end of the eleventh transistor T11, and the second end of the eleventh transistor T11 is respectively connected to the first end of the eighth transistor T8 and the first end of the ninth transistor T9; the control end of the twelfth transistor T12 is connected to the control end of the eleventh transistor T11, the first end of the twelfth transistor T12 is connected to the control end of the twelfth transistor T12, and the second end of the twelfth transistor T12 is connected to the first end of the tenth transistor T10.

[0071] It should be noted that in this embodiment, the second terminals (i.e., node Bn) of the fifth transistor T5 and the sixth transistor T6 are pulled down to the first low level output by the first low-level terminal VSS1 via the eighth transistor T8 and the ninth transistor T9, and the second terminal (node Cn) of the seventh transistor T7 is pulled down to the second low level output by the second low-level terminal VSS2 via the tenth transistor T10. The second terminals of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are then pulled high via the turned-on eleventh transistor T11 and the twelfth transistor T12. By providing two low-level terminals, this embodiment can adjust the voltage values of the first low level and the second low level output by the two low-level terminals, respectively, thereby reducing leakage current of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 and improving the voltage stability at the noise reduction control node. Furthermore, by connecting the second terminal of the fifth transistor T5 and the second terminal of the seventh transistor T7 via the eleventh transistor T11 and the twelfth transistor T12, respectively, short-circuiting the two terminals during the normal noise reduction phase can be avoided.

[0072] Figure 9 FIG. 4 is a schematic structural diagram of a fourth noise reduction circuit provided in an embodiment of the present application; Figure 9 exist Figure 8 A thirteenth transistor T13 is added on the basis of Figure 9 As shown: the first correction sub-unit 1122 and the second correction sub-unit 1222 further include a thirteenth transistor T13, the control end of the thirteenth transistor T13 is connected to the control end of the eleventh transistor T11, the first end of the thirteenth transistor T13 is connected to the output end of the first noise reduction control unit 111 or the output end of the second noise reduction control unit 121, and the second end of the thirteenth transistor T13 is connected to the first low-level end VSS1.

[0073] It should be noted that the addition of the thirteenth transistor makes the output end of the first noise reduction control unit and the output end of the second noise reduction control unit ( Figure 9 The pulling down of the nodes P1n and P2n in the embodiment is not limited to the second transistor. In the reverse correction process, the thirteenth transistor can also complete the pulling down of the nodes P1n and P2n; Figure 6-Figure 9 The circuit structure of the first noise reduction control unit and the second noise reduction control unit shown can also pull down the control end of the noise reduction transistor when the noise reduction is not working, so as to achieve reverse correction of the noise reduction transistor.

[0074] To summarize, the noise reduction circuit provided in the present application, without affecting the pixel charging efficiency, realizes that the noise reduction transistor is in a reverse bias state when not working through the noise reduction execution unit of various embodiments, so as to offset the forward bias state of the noise reduction transistor when alternately working, thereby improving the problem of threshold voltage drift of the noise reduction transistor and avoiding driving abnormalities in the gate drive circuit due to reduced noise reduction capability.

[0075] In one embodiment, the embodiment of the present application provides a gate drive circuit, comprising N cascaded gate drive modules, the nth-level gate drive module comprising: a pull-up unit, a pull-down unit, an output unit and a noise reduction circuit, the pull-up unit being respectively connected to the drive output terminal of the ni-th-level gate drive module and the level transmission output terminal of the ni-th-level gate drive module; the pull-down unit being connected to the level transmission output terminal of the n+j-th-level gate drive module, and the pull-down unit being further connected to the pull-up unit through a drive control node; the output unit being respectively connected to the clock signal terminal and the drive control node; and the noise reduction circuit being respectively connected to the drive control node, the drive output terminal and the level transmission output terminal of the current-level gate drive module.

[0076] It should be noted that the specific structure of the gate drive module provided in this embodiment is as follows Figure 1 As shown, the working principle of the gate drive module is described above using i=3, j=4 as an example, which will not be repeated here.

[0077] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0078] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0079] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A noise reduction circuit, characterized in that: Applied to a gate drive circuit, the gate drive circuit includes N cascaded gate drive modules, the n-th level gate drive module includes at least a drive control node, a drive output terminal, a level transmission output terminal and a noise reduction circuit, the noise reduction circuit includes: a first noise reduction module, wherein a first input terminal of the first noise reduction module is connected to a first noise reduction control terminal, a second input terminal of the first noise reduction module is connected to the drive control node, a third input terminal of the first noise reduction module is connected to a second noise reduction control terminal, and an output terminal of the first noise reduction module is respectively connected to the drive output terminal, the stage transmission output terminal, and the drive control node, and configured to perform noise reduction processing on the voltages on the drive control node, the drive output terminal, and the stage transmission output terminal under the action of a first noise reduction control signal output by the first noise reduction control terminal and the voltage on the drive control node; and further configured to place a noise reduction transistor in the first noise reduction module in a reverse bias state under the action of a second noise reduction control signal output by the second noise reduction control terminal; a second noise reduction module, wherein a first input terminal of the second noise reduction module is connected to the second noise reduction control terminal, a second input terminal of the second noise reduction module is connected to the drive control node, a third input terminal of the second noise reduction module is connected to the first noise reduction control terminal, and an output terminal of the second noise reduction module is respectively connected to the drive output terminal, the stage transmission output terminal, and the drive control node, and configured to perform noise reduction processing on the voltages on the drive control node, the drive output terminal, and the stage transmission output terminal under the action of a second noise reduction control signal output by the second noise reduction control terminal and the voltage on the drive control node; and further configured to place a noise reduction transistor in the second noise reduction module in a reverse bias state under the action of a first noise reduction control signal output by the first noise reduction control terminal; The first noise reduction control signal and the second noise reduction control signal have opposite phases.

2. The noise reduction circuit according to claim 1, wherein: The first noise reduction module includes: a first noise reduction control unit, wherein a first control end of the first noise reduction control unit is connected to the first noise reduction control end, and a second control end of the first noise reduction control unit is connected to the drive control node, and is configured to output a first noise reduction signal under the action of a first noise reduction control signal output by the first noise reduction control end and a voltage on the drive control node; a first noise reduction execution unit, wherein a first control terminal of the first noise reduction execution unit is connected to an output terminal of the first noise reduction control unit, a second control terminal of the first noise reduction execution unit is connected to the second noise reduction control terminal, and an output terminal of the first noise reduction execution unit is respectively connected to the drive control node, the drive output terminal, and the stage transmission output terminal, and the first noise reduction execution unit is configured to perform noise reduction processing on the voltages on the drive control node, the drive output terminal, and the stage transmission output terminal according to the first noise reduction signal; and further configured to place a noise reduction transistor in the first noise reduction execution unit in a reverse bias state according to the second noise reduction control signal; The second noise reduction module includes: a second noise reduction control unit, wherein a first control terminal of the second noise reduction control unit is connected to the second noise reduction control terminal, and a second control terminal of the second noise reduction control unit is connected to the drive control node, and is configured to output a second noise reduction signal under the action of the first noise reduction control signal output by the second noise reduction control terminal and the voltage on the drive control node; a second noise reduction execution unit, wherein the first control terminal of the second noise reduction execution unit is connected to the output terminal of the second noise reduction control unit, the second control terminal of the second noise reduction execution unit is connected to the first noise reduction control terminal, and the output terminal of the second noise reduction execution unit is respectively connected to the drive control node, the drive output terminal, and the stage transmission output terminal, and is configured to perform noise reduction processing on the voltages on the drive control node, the drive output terminal, and the stage transmission output terminal according to the second noise reduction signal; and is further configured to place the noise reduction transistor in the second noise reduction execution unit in a reverse bias state according to the first noise reduction control signal.

3. The noise reduction circuit according to claim 2, wherein: The first noise reduction execution unit includes: a first execution subunit, wherein the control end of the first execution subunit is connected to the output end of the first noise reduction control unit, and the output end of the first execution subunit is respectively connected to the drive control node, the drive output end, and the stage transmission output end, and is configured to perform noise reduction processing on the voltages on the drive control node, the drive output end, and the stage transmission output end according to the first noise reduction signal; a first correction subunit, wherein a first control terminal of the first correction subunit is connected to the first noise reduction control terminal, a second control terminal of the first correction subunit is connected to the second noise reduction control terminal, and an output terminal of the first correction subunit is connected to the first execution subunit, and is configured to output a low level when the first execution subunit performs noise reduction processing, and further configured to place the noise reduction transistor in the first execution subunit in a reverse bias state according to the second noise reduction control signal when the first execution subunit does not perform noise reduction processing; The second noise reduction execution unit includes: a second execution subunit, wherein the control end of the second execution subunit is connected to the output end of the second noise reduction control unit, and the output end of the second execution subunit is respectively connected to the drive control node, the drive output end, and the stage transmission output end, and is configured to perform noise reduction processing on the voltages on the drive control node, the drive output end, and the stage transmission output end according to the second noise reduction signal; A second correction subunit, wherein the first control end of the second correction subunit is connected to the second noise reduction control end, the second control end of the second correction subunit is connected to the first noise reduction control end, and the output end of the second correction subunit is connected to the second execution subunit, and is used to output a low level when the second execution subunit performs noise reduction processing, and is also used to put the noise reduction transistor in the second execution subunit into a reverse bias state according to the first noise reduction control signal when the second execution subunit does not perform noise reduction processing.

4. The noise reduction circuit according to claim 2 or 3, characterized in that: The first noise reduction control unit includes: a first transistor, wherein the control terminal of the first transistor is connected to the first noise reduction control terminal, and the first terminal of the first transistor is connected to the control terminal of the first transistor; a second transistor, wherein a control terminal of the second transistor is connected to the second terminal of the first transistor, and a first terminal of the second transistor is connected to the first terminal of the first transistor; a third transistor, wherein a control terminal of the third transistor is connected to the drive control node, a first terminal of the third transistor is connected to the second terminal of the first transistor, and a second terminal of the third transistor is connected to the first low level terminal; a fourth transistor, wherein a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to the second end of the second transistor, and a second end of the fourth transistor is connected to the first low-level end; The second noise reduction control unit includes: a first transistor, wherein the control terminal of the first transistor is connected to the second noise reduction control terminal, and the first terminal of the first transistor is connected to the control terminal of the first transistor; a second transistor, wherein a control terminal of the second transistor is connected to the second terminal of the first transistor, and a first terminal of the second transistor is connected to the first terminal of the first transistor; a third transistor, wherein a control terminal of the third transistor is connected to the drive control node, a first terminal of the third transistor is connected to the second terminal of the first transistor, and a second terminal of the third transistor is connected to the first low level terminal; a fourth transistor, wherein a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to the second end of the second transistor, and a second end of the fourth transistor is connected to the first low-level end.

5. The noise reduction circuit according to claim 2, wherein: The first noise reduction execution unit includes: a fifth transistor, wherein a control terminal of the fifth transistor is connected to the output terminal of the first noise reduction control unit, a first terminal of the fifth transistor is connected to the stage transmission output terminal, and a second terminal of the fifth transistor is connected to the second noise reduction control terminal; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the driving control node, and a second terminal of the sixth transistor is connected to the second noise reduction control terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the fifth transistor, a first terminal of the seventh transistor is connected to the driving output terminal, and a second terminal of the seventh transistor is connected to the second noise reduction control terminal; The second noise reduction execution unit includes: a fifth transistor, wherein a control terminal of the fifth transistor is connected to the output terminal of the second noise reduction control unit, a first terminal of the fifth transistor is connected to the stage transmission output terminal, and a second terminal of the fifth transistor is connected to the first noise reduction control terminal; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the driving control node, and a second terminal of the sixth transistor is connected to the first noise reduction control terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the fifth transistor, a first terminal of the seventh transistor is connected to the driving output terminal, and a second terminal of the seventh transistor is connected to the first noise reduction control terminal; The fifth transistor, the sixth transistor and the seventh transistor are used as noise reduction transistors in the first noise reduction module and the second noise reduction module respectively.

6. The noise reduction circuit according to claim 3, wherein: The first execution subunit includes: a fifth transistor, wherein a control terminal of the fifth transistor is connected to the output terminal of the first noise reduction control unit, a first terminal of the fifth transistor is connected to the stage transmission output terminal, and a second terminal of the fifth transistor is connected to the output terminal of the first correction sub-unit; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the drive control node, and a second terminal of the sixth transistor is connected to the output terminal of the first correction sub-unit; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the fifth transistor, a first terminal of the seventh transistor is connected to the driving output terminal, and a second terminal of the seventh transistor is connected to the output terminal of the first correction sub-unit; The second execution subunit includes: a fifth transistor, wherein a control terminal of the fifth transistor is connected to the output terminal of the second noise reduction control unit, a first terminal of the fifth transistor is connected to the stage transmission output terminal, and a second terminal of the fifth transistor is connected to the output terminal of the second correction sub-unit; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the drive control node, and a second terminal of the sixth transistor is connected to the output terminal of the second correction sub-unit; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the fifth transistor, a first terminal of the seventh transistor is connected to the driving output terminal, and a second terminal of the seventh transistor is connected to the output terminal of the second correction sub-unit; The fifth transistor, the sixth transistor and the seventh transistor are used as noise reduction transistors in the first noise reduction module and the second noise reduction module respectively.

7. The noise reduction circuit according to claim 6, wherein: The first correction subunit includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the first noise reduction control terminal, a first terminal of the eighth transistor is connected to the second terminal of the fifth transistor, and a second terminal of the eighth transistor is connected to the first low-level terminal; a ninth transistor, wherein a control terminal of the ninth transistor is connected to the control terminal of the eighth transistor, a first terminal of the ninth transistor is connected to the second terminal of the sixth transistor, and a second terminal of the ninth transistor is connected to the first low-level terminal; a tenth transistor, wherein a control terminal of the tenth transistor is connected to the control terminal of the eighth transistor, a first terminal of the tenth transistor is connected to the second terminal of the seventh transistor, and a second terminal of the tenth transistor is connected to the first low-level terminal; an eleventh transistor, wherein the control terminal of the eleventh transistor is connected to the second noise reduction control terminal, the first terminal of the eleventh transistor is connected to the control terminal of the eleventh transistor, and the second terminal of the eleventh transistor is respectively connected to the first terminal of the eighth transistor, the first terminal of the ninth transistor, and the first terminal of the tenth transistor; The second correction subunit includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the second noise reduction control terminal, a first terminal of the eighth transistor is connected to the second terminal of the fifth transistor, and a second terminal of the eighth transistor is connected to the first low-level terminal; a ninth transistor, wherein a control terminal of the ninth transistor is connected to the control terminal of the eighth transistor, a first terminal of the ninth transistor is connected to the second terminal of the sixth transistor, and a second terminal of the ninth transistor is connected to the first low-level terminal; a tenth transistor, wherein a control terminal of the tenth transistor is connected to the control terminal of the eighth transistor, a first terminal of the tenth transistor is connected to the second terminal of the seventh transistor, and a second terminal of the tenth transistor is connected to the first low-level terminal; an eleventh transistor, wherein the control end of the eleventh transistor is connected to the first noise reduction control end, the first end of the eleventh transistor is connected to the control end of the eleventh transistor, and the second end of the eleventh transistor is respectively connected to the first end of the eighth transistor, the first end of the ninth transistor, and the first end of the tenth transistor.

8. The noise reduction circuit according to claim 6, wherein: The first correction subunit includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the first noise reduction control terminal, a first terminal of the eighth transistor is connected to the second terminal of the fifth transistor, and a second terminal of the eighth transistor is connected to the first low-level terminal; a ninth transistor, wherein a control terminal of the ninth transistor is connected to the control terminal of the eighth transistor, a first terminal of the ninth transistor is connected to the second terminal of the sixth transistor, and a second terminal of the ninth transistor is connected to the first low-level terminal; a tenth transistor, wherein a control terminal of the tenth transistor is connected to the control terminal of the eighth transistor, a first terminal of the tenth transistor is connected to the second terminal of the seventh transistor, and a second terminal of the tenth transistor is connected to the second low-level terminal; an eleventh transistor, wherein the control terminal of the eleventh transistor is connected to the second noise reduction control terminal, the first terminal of the eleventh transistor is connected to the control terminal of the eleventh transistor, and the second terminal of the eleventh transistor is connected to the first terminal of the eighth transistor and the first terminal of the ninth transistor respectively; a twelfth transistor, wherein a control terminal of the twelfth transistor is connected to the control terminal of the eleventh transistor, a first terminal of the twelfth transistor is connected to the control terminal of the twelfth transistor, and a second terminal of the twelfth transistor is connected to the first terminal of the tenth transistor; The second correction subunit includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the second noise reduction control terminal, a first terminal of the eighth transistor is connected to the second terminal of the fifth transistor, and a second terminal of the eighth transistor is connected to the first low-level terminal; a ninth transistor, wherein a control terminal of the ninth transistor is connected to the control terminal of the eighth transistor, a first terminal of the ninth transistor is connected to the second terminal of the sixth transistor, and a second terminal of the ninth transistor is connected to the first low-level terminal; a tenth transistor, wherein a control terminal of the tenth transistor is connected to the control terminal of the eighth transistor, a first terminal of the tenth transistor is connected to the second terminal of the seventh transistor, and a second terminal of the tenth transistor is connected to the second low-level terminal; an eleventh transistor, wherein the control terminal of the eleventh transistor is connected to the first noise reduction control terminal, the first terminal of the eleventh transistor is connected to the control terminal of the eleventh transistor, and the second terminal of the eleventh transistor is connected to the first terminal of the eighth transistor and the first terminal of the ninth transistor respectively; a twelfth transistor, wherein the control end of the twelfth transistor is connected to the control end of the eleventh transistor, the first end of the twelfth transistor is connected to the control end of the twelfth transistor, and the second end of the twelfth transistor is connected to the first end of the tenth transistor.

9. The noise reduction circuit according to claim 7 or 8, characterized in that: The first correction subunit further includes: a thirteenth transistor, wherein a control terminal of the thirteenth transistor is connected to the control terminal of the eleventh transistor, a first terminal of the thirteenth transistor is connected to the output terminal of the first noise reduction control unit, and a second terminal of the thirteenth transistor is connected to the first low-level terminal; The second correction subunit further includes: a thirteenth transistor, wherein the control end of the thirteenth transistor is connected to the control end of the eleventh transistor, the first end of the thirteenth transistor is connected to the output end of the second noise reduction control unit, and the second end of the thirteenth transistor is connected to the first low-level end.

10. A gate drive circuit comprising N cascaded gate drive modules, characterized in that: The n-th level gate driver module includes: A pull-up unit, wherein the pull-up unit is respectively connected to the driving output terminal of the n-th level gate driving module and the level transmission output terminal of the n-th level gate driving module; A pull-down unit, the pull-down unit being connected to the stage transmission output terminal of the n+j-th stage gate driving module, and the pull-down unit being further connected to the pull-up unit via a driving control node; an output unit, the output unit being connected to the clock signal terminal and the drive control node respectively; The noise reduction circuit according to any one of claims 1 to 9, wherein the noise reduction circuit is respectively connected to the drive control node, the drive output terminal and the stage transmission output terminal of the current stage gate drive module.

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