A shift register reinforced circuit structure resistant to single event upset

Abstract

The present invention provides a shift register reinforcement circuit structure resistant to single-particle upsets, relating to the field of integrated circuit reliability design. The circuit comprises: an enable control module, a shift register circuit, and an output control selection module. The enable control module can be configured in a redundant mode or a single-group activation mode. When in the single-group activation mode, an enable signal drives all triggers one-to-one, and data is shifted and transmitted step by step in the shift register circuit. When in the redundant mode, the triggers correspond to each other in pairs to form a group of main triggers and backup triggers. The enable signal drives each group of main triggers and backup triggers to work simultaneously, so that the same data is synchronously written into the main triggers and backup triggers. The output control selection module is used to monitor the data flow state of the shift register circuit in real time and verify the trigger state. If a single-particle upset or timing deviation is detected, an error correction mechanism is immediately triggered to ensure data integrity.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit reliability design, and in particular to a shift register reinforcement circuit structure resistant to single event upset. Background Art

[0002] A single-event upset (SEU) is a transient fault phenomenon in integrated circuits caused by high-energy charged particles. When high-energy particles penetrate sensitive areas of a chip, their ionization can cause unexpected state changes in memory cells or logic circuits. As semiconductor processes advance toward the nanometer scale, the critical charge of devices decreases, significantly increasing the susceptibility to SEUs and making them a key threat to high-reliability electronic systems.

[0003] A shift register is a fundamental storage device in digital circuits. Composed of multiple cascaded flip-flops, it can shift stored binary data bit by bit in a specific direction (left or right). Its core function is to control the sequential movement of data using a clock signal. It is widely used in fields such as data format conversion, timing control, and arithmetic processing. Its flexible data movement capabilities make it a cornerstone component for serial-to-parallel conversion, timing control, and data processing in digital systems.

[0004] However, in aerospace applications, shift registers, due to their cascaded structure and timing dependencies, are highly susceptible to the combined effects of space radiation, leading to multiple reliability issues. When high-energy charged particles penetrate the device, they can trigger a single-event upset (SEE), causing a flip-flop in a register to flip abnormally. This error can then propagate through the shift operation, causing data contamination.

[0005] In existing technologies, SEU mitigation strategies are mainly divided into fault-tolerant designs such as triple-mode redundancy and error detection and correction. They also include methods such as radiation-resistant process reinforcement using silicon-on-insulator (SOI) or silicon carbide (SiC) materials. Conventional fault-tolerant design methods have problems such as increased area and power consumption, voting delays, additional storage overhead, and limited real-time performance. Process reinforcement design is expensive and difficult to be compatible with commercial design processes.

[0006] However, as applications expand into extreme environments like deep space exploration and high-density integration, existing solutions face bottlenecks in energy efficiency, tolerance to multiple bit upsets, and dynamic recovery efficiency. Traditional static redundancy and verification mechanisms struggle to balance reliability and performance requirements, especially under high-frequency, low-power constraints. Therefore, a new hardened architecture is urgently needed that can achieve efficient SEU immunity within limited resources while remaining compatible with mainstream design methodologies to address the demanding reliability challenges of next-generation electronic systems. Summary of the Invention

[0007] In order to effectively reduce the area overhead of traditional reinforcement designs and to fit the commercial process design flow as closely as possible, the present invention designs a shift register reinforcement circuit structure that utilizes the inherent characteristics of the shift register and is flexible and configurable to resist single-particle upsets, thereby realizing the error detection function without sacrificing performance.

[0008] Specifically, the present invention provides a shift register reinforcement circuit structure resistant to single event upsets, comprising: an enable control module, a shift register circuit, and an output control selection module; wherein the enable control module is configured to generate different enable signals after decoding an external address signal terminal based on an external control and enable signal, thereby configuring different enable modes, wherein the enable modes include a redundant mode or a single group activation mode;

[0009] The shift register circuit is a configurable shift register array composed of multiple stages of flip-flops. When in a single-group activation mode, an enable signal drives all flip-flops one-to-one, and data is shifted and transmitted stage by stage in the shift register circuit. When in a redundant mode, the flip-flops are arranged in pairs to form a group of primary flip-flops and backup flip-flops. The enable signal drives each group of primary flip-flops and backup flip-flops to operate simultaneously, so that the same data is synchronously written into the primary flip-flops and backup flip-flops, forming a double copy of redundant storage.

[0010] The output control selection module is used to monitor the data flow status of the shift register circuit in real time and perform logical judgment; when in single-group activation mode, the output control selection module directly outputs the data output by the shift register circuit; when in redundant mode, the output control selection module compares the data output by the main trigger and the backup trigger in real time. If the data is consistent, the current valid group data is output; if the data is inconsistent, no data is output.

[0011] As a further explanation of the present invention, the enable control module is provided with a clock signal terminal, a reset signal terminal, a control signal terminal, an external enable signal terminal, an address signal terminal and an enable control network output terminal, and the enable control module includes an address decoder; after the enable control module receives the clock signal, reset signal and control signal, it selects the address signal terminal through the address decoder to generate different enable signal outputs to realize the configuration of redundant mode or single group activation mode.

[0012] As a further illustration of the present invention, when the control signal is at a low level, the enable control module is configured in a single group activation mode, and when the control signal is at a high level, the enable control module is configured in a redundant mode.

[0013] As a further illustration of the present invention, each flip-flop includes a standard input terminal, a clock terminal, an output terminal, and an enable control terminal, wherein the standard input terminal is used to receive external input data;

[0014] The output terminal is connected to the standard input terminal of the next stage trigger, which is used to directly output data or shift the data to the next stage trigger under clock drive;

[0015] The enable control terminal is connected to the corresponding external enable signal terminal in the enable control module and a single enable terminal in the enable control network output terminal, and is used to receive the enable signal output by the enable control module.

[0016] As a further illustration of the present invention, a single enable terminal of the enable control network output terminal is simultaneously connected to the enable control terminals of two triggers, so that the triggers correspond to each other in pairs to form a group of a main trigger and a backup trigger.

[0017] As a further illustration of the present invention, the output control selection module includes a control selector and an error judgment module, and the data output end of the shift register circuit is connected to the control selector and the error judgment module at the same time;

[0018] When in single-group activation mode, the error judgment module is turned off, and the control selector directly outputs the data output by the shift register circuit; when in redundant mode, the control selector is turned off, and the error judgment module compares the data output by the main trigger and the backup trigger in real time. If the data is consistent, the current valid group data is output; if the data is inconsistent, no data is output.

[0019] As a further explanation of the present invention, the output control selection module switches the data output path by selecting an enable signal, and the selection enable signal is respectively connected to the control selector and the error judgment module. When in the single group activation mode, the selection enable signal is maintained at a high level, thereby activating the control selector and turning off the error judgment module; when in the redundant mode, the selection enable signal is maintained at a low level, thereby activating the error judgment module and turning off the control selector.

[0020] As a further illustration of the present invention, the error judgment module includes a plurality of XOR gate circuits and a plurality of two-choose-one selectors, the output ends of the main trigger and the backup trigger of the same group are connected to the same XOR gate circuit, the output end of each main trigger is connected to a two-choose-one selector, and the XOR gate circuit and the two-choose-one selector connected to the output end of the same main trigger are connected to each other;

[0021] When in redundant mode, the XOR gate circuit compares the data output by the main trigger and the backup trigger in real time. If the data are consistent, the data output by the main trigger is output by the two-to-one selector. If the data are inconsistent, the output signal of the two-to-one selector is turned off.

[0022] As a further explanation of the present invention, the XOR gate circuit controls the state of the two-to-one selector through the error indication signal it outputs; if the data is consistent, the error indication signal remains at a low level, and the two-to-one selector outputs the data output by the main trigger; if the data is inconsistent, the error indication signal remains at a high level, and the output signal of the two-to-one selector is turned off.

[0023] As a further illustration of the present invention, if the data are consistent, the error indication signal is also transmitted to the host processor, which controls the discarding of the erroneous data and resends the relevant correct data to the standard data input terminal of the corresponding trigger.

[0024] Compared with the prior art, the present invention has the following beneficial technical effects:

[0025] The shift register reinforcement circuit structure resistant to single-event upsets provided by the present invention achieves efficient fault tolerance while reducing hardware overhead through dynamic enable control, synchronous writing of redundant data, and an intelligent switching mechanism, and is suitable for high-reliability application scenarios.

[0026] Other features and advantages of this technical solution will be described in the subsequent description, and in part will become apparent from the description, or understood by practicing this technical solution. The objectives and other advantages of this technical solution can be achieved and obtained through the structures specifically pointed out in the written description and the accompanying drawings.

[0027] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the present technical solution and constitute a part of the specification. Together with the embodiments of the present technical solution, they are used to explain the present technical solution and do not constitute a limitation of the present technical solution. In the accompanying drawings:

[0029] Figure 1 The present invention provides an overall architecture of a shift register reinforcement circuit structure resistant to single event upset.

[0030] Figure 2 This is a structural diagram of the enabling control module in the present invention.

[0031] Figure 3 This is a core structure diagram of the shift register circuit in the present invention.

[0032] Figure 4 This is the core structure diagram of the output control selection module in the present invention. DETAILED DESCRIPTION

[0033] The preferred embodiments of the present technical solution are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present technical solution and are not used to limit the present technical solution.

[0034] like Figure 1 As shown, the present invention provides a shift register reinforcement circuit structure resistant to single event upset, comprising: an enable control module, a shift register circuit and an output control selection module; wherein the enable control module is used to generate different enable signals after decoding the external address signal terminal according to the external control and enable signals, thereby configuring different enable modes, wherein the enable modes include redundant mode and single group activation mode; the shift register circuit is a configurable shift register array composed of multiple stages of triggers. When in the single group activation mode, the enable signal drives all triggers one-to-one, and the data is shifted and transmitted stage by stage in the shift register circuit; when in the redundant mode, The triggers correspond to each other in pairs to form a group of main triggers and backup triggers. The enable signal drives each group of main triggers and backup triggers to work simultaneously, so that the same data is synchronously written into the main triggers and backup triggers, forming a double copy redundant storage; the output control selection module is used to monitor the data flow status of the shift register circuit in real time and perform logical judgment; when in the single group activation mode, the output control selection module directly outputs the data output by the shift register circuit; when in the redundant mode, the output control selection module compares the data output by the main trigger and the backup trigger in real time. If the data is consistent, the current valid group data is output; if the data is inconsistent, no data is output.

[0035] Specifically, such as Figure 2As shown, the enable control module is equipped with a clock signal terminal (CK), a reset signal terminal (RST), a control signal terminal (CTRL), an external enable signal terminal (EN[0:31]), an address signal terminal (ADDR), and an enable control network output terminal (EN[0:15]). The enable control module includes an address decoder that receives the control signal (CTRL) and dynamically distributes the enable signals. When CTRL = 0 (single-group active mode), the external enable signal EN[0:31] is directly transmitted to 32 flip-flops. When CTRL = 1 (redundant mode), the address decoder maps EN[0:15] into 16 groups of enable signals (E0-E15). Each group simultaneously drives a primary flip-flop (such as flip-flop 0) and a backup flip-flop (such as flip-flop 16), achieving dual-copy synchronous writing. After receiving the clock signal, reset signal, and control signal, the enable control module selects the address signal terminal through the address decoder to generate different enable signal outputs, enabling configuration in redundant mode or single-group active mode. When the control signal is low, the enable control module is in single-group activation mode. The external enable signal (EN[0:31]) drives the enable signals of all triggers one by one (EN[0] corresponds to trigger 0, and so on, EN

[31] corresponds to trigger 31). The data is input through the D end of the trigger and is shifted step by step under the clock drive. When the control signal is high, the enable control module is configured in redundant mode. The enable signal of the enable control module is dynamically distributed to multiple groups through the address decoder. For example, if the EN[0] signal is connected to Figure 3 On the E0 signal in the MCU, the primary trigger (e.g., trigger 0) and the backup trigger (e.g., trigger 16) are activated simultaneously, forming a pair of pairs to achieve simultaneous writing of the same data, forming dual-copy redundant storage. The reset signal (RST) forces all enable signals to zero, ensuring that the system initialization state is controllable.

[0036] Specifically, such as Figure 3As shown, the core structure of the shift register circuit is a configurable shift register array composed of multiple stages of triggers connected end to end in a cascade manner. It is used to realize the function of bit-by-bit data transmission, has serial loading and segment control functions, and is suitable for flexible switching of high-speed data processing and fault tolerance performance. The specific circuit structure consists of a D-type flip-flop chain structure and an enable control network connected to it, wherein the D-type flip-flop chain structure is mainly composed of D-type flip-flops with different numbers, and each flip-flop contains a standard input terminal (D), a clock terminal (CLK), an output terminal (Q) and an enable control terminal (E), wherein the standard input terminal is used to receive external input data; the output terminal is connected to the standard input terminal of the next-level flip-flop, which is used to directly output data or shift the data to the next-level flip-flop under clock drive; the enable control terminal is connected to the corresponding external enable signal terminal in the enable control module and a single enable terminal in the output terminal of the enable control network, which is used to receive the enable signal output by the enable control module. Specifically, the enable control network controls the activation state of different flip-flops through the E0-E15 signal lines, realizes the dynamic selection of the data path, and facilitates the realization of the function of redundant information storage.

[0037] More specifically, a single enable terminal of the enable control network output terminal is connected to the enable control terminals of two triggers at the same time, so that the triggers correspond to each other to form a set of main trigger and backup trigger. Figure 3 As shown, the primary group of flip-flops consists of flip-flops 0-15, and the backup group of flip-flops consists of flip-flops 16-31. The D terminal of each group of flip-flops is cascaded with the Q terminal of the previous flip-flop, forming a serial shift chain. For example, the D terminal of flip-flop 0 in the primary group receives external input data, and its Q terminal outputs it to the D terminal of flip-flop 1. The backup groups are cascaded in the same manner. The enable control terminal (E) of each flip-flop is tied to the corresponding enable signal (for example, E0 controls flip-flops 0 and 16). When the enable signal is valid, data is input from the first-stage flip-flop and transmitted to each stage one by one. In redundant mode, the primary and backup groups of flip-flops receive data synchronously and store it independently. The primary and backup groups shift data in parallel, and data is written to the primary and backup flip-flops of the same group synchronously using the same enable signal (for example, E0). A single-event upset only affects one group of shift registers (for example, flip-flop 0 is abnormal), while the data integrity of the other group (flip-flop 16) remains intact.

[0038] Specifically, such as Figure 4 As shown, the output control selection module includes a control selector and an error judgment module, and the data output end of the shift register circuit is connected to the control selector and the error judgment module at the same time; when in the single group activation mode, the error judgment module is turned off, and the control selector directly outputs the data output by the shift register circuit; when in the redundant mode, the control selector is turned off, and the error judgment module compares the data output by the main trigger and the backup trigger in real time. If the data is consistent, the current valid group data is output; if the data is inconsistent, no data is output.

[0039] Specifically, the output control selection module switches the data output path (for example, selecting Q0-Q15 or Q0-Q31 as the current valid output segment) by selecting the enable signal (SELEN). The enable signal is respectively connected to the control selector and the error judgment module. When in the single-group activation mode, the enable signal is kept at a high level, thereby activating the control selector and turning off the error judgment module; when in the redundant mode, the enable signal is kept at a low level, thereby activating the error judgment module and turning off the control selector.

[0040] Specifically, the error judgment module includes multiple XOR gate circuits and multiple binary selectors. The output ends of the main trigger and the backup trigger in the same group are connected to the same XOR gate circuit. The output end of each main trigger is connected to a binary selector. The XOR gate circuit and the binary selector connected to the output end of the same main trigger are connected to each other. When in redundant mode, the XOR gate circuit compares the data output by the main trigger and the backup trigger in real time. If the data are consistent, the data output by the main trigger is output by the binary selector. If the data are inconsistent, the output signal of the binary selector is turned off.

[0041] Furthermore, the XOR gate circuit uses the error indication signal to verify the trigger state: if a single-particle upset or timing deviation is detected, the error correction mechanism is immediately triggered to ensure data integrity. Specifically, the XOR gate circuit controls the state of the two-to-one selector through the error indication signal it outputs. If the data is consistent, the error indication signal remains low, and the two-to-one selector outputs the data output by the main trigger. If the data is inconsistent, the error indication signal remains high, shutting off the output signal of the two-to-one selector. If the data is consistent, the error indication signal is also transmitted to the upper processor, which controls the discarding of the erroneous data and resending the relevant correct data to the standard data input of the corresponding trigger.

[0042] The working process of the output control selection module is as follows: After the SELEN signal is decoded, the current valid trigger group is selected and the result is output (such as Q0-Q15 in redundant mode or Q0-Q31 in single-group activation mode), and the Q-end data of the corresponding trigger is output to the downstream circuit. If the circuit is in single-group activation mode, the SELEN signal remains at a high level, and it acts as the enable end of the control selector to open the control selector. The XOR gate circuit used for comparison will not be activated, and Q0-Q31 will be output; when the circuit is in redundant mode, the SELEN signal remains at a low level, the control selector is turned off, and the XOR gate circuit is activated by the SELEN signal. The redundant data output by the main and standby group triggers (such as Q0 and Q16) are compared in real time. If the data is consistent, the error indication signal remains low and the current valid group data is output; if inconsistency is detected (such as abnormal status of Q0 and Q16, such as Figure 4The error indication signal is transmitted to the upper processor, indicating that the data at that time is wrong. The upper processor identifies the error and performs further processing, such as controlling the discard of data and resending related data to restore its correct state. At the same time, the error indication signal serves as an enable signal for the two-to-one selector. When the error indication signal is low, the data output by the two-to-one selector (such as Q0) of the main group trigger is output; if the error indication signal is high, the two-to-one selector will not output any value until the system value is restored and the system operates normally.

[0043] In summary, the overall workflow of the above-mentioned shift register reinforcement circuit structure against single event upset is divided into three stages: the initialization stage, in which the reset signal of the enabling control module clears all triggers (such as Figure 3 The enable control module is configured in redundant mode or single-group active mode, with the primary and backup groups of flip-flops synchronously loaded with initial data. During normal operation, the enable control module's control signals switch to single-group active mode, meaning all enable signals are connected to EN[0:31]. Separate enable signals control the enable of each flip-flop, data is shifted and transmitted on demand, and the error comparison logic is disabled. When a task needs to run in redundant mode, it is configured in redundant mode. During this phase, when an error is detected, the XOR gate triggers an error indication signal to notify the host processor of an error in the register chain. The two-selector selector shuts down the signal output via the error indication signal. Simultaneously, the host processor recognizes the error and disables the enable of the non-erroneous flip-flops, retaining the data in the relevant flip-flops. The enable signal of the flip-flop with the error is then enabled, and the correct data is rewritten. After error recovery, the enable signal is enabled again, and the register chain continues to operate normally. Through dynamic enable control, synchronous writing of redundant data, and an intelligent switching mechanism, this design achieves efficient fault tolerance while reducing hardware overhead, making it suitable for high-reliability applications.

[0044] Obviously, those skilled in the art may make various changes and modifications to this technical solution without departing from the spirit and scope of this technical solution. Thus, if these modifications and variations of this technical solution fall within the scope of the claims of this technical solution and their equivalents, this technical solution is intended to include these modifications and variations.

Claims

1. A shift register reinforcement circuit structure resistant to single event upset, characterized in that: include: Enable control module, shift register circuit and output control selection module; wherein, The enable control module is used to generate different enable signals after decoding the external address signal terminal according to the external control and enable signals, thereby configuring different enable modes, wherein the enable modes include a redundant mode or a single group activation mode; The shift register circuit is a configurable shift register array composed of multiple stages of flip-flops. When in a single-group activation mode, an enable signal drives all flip-flops one-to-one, and data is shifted and transmitted stage by stage in the shift register circuit. When in a redundant mode, the flip-flops are arranged in pairs to form a group of primary flip-flops and backup flip-flops. The enable signal drives each group of primary flip-flops and backup flip-flops to operate simultaneously, so that the same data is synchronously written into the primary flip-flops and backup flip-flops, forming a double copy of redundant storage. The output control selection module is used to monitor the data flow state of the shift register circuit in real time and perform logic judgment; when in single-group activation mode, the output control selection module directly outputs the data output by the shift register circuit; when in redundant mode, the output control selection module compares the data output by the main trigger and the backup trigger in real time. If the data are consistent, the current valid group data is output; if the data are inconsistent, no data is output; The output control selection module includes a control selector and an error judgment module, and the data output end of the shift register circuit is connected to the control selector and the error judgment module at the same time; When in single-group activation mode, the error judgment module is turned off, and the control selector directly outputs the data output by the shift register circuit; when in redundant mode, the control selector is turned off, and the error judgment module compares the data output by the main trigger and the backup trigger in real time. If the data is consistent, the current valid group data is output; if the data is inconsistent, no data is output.

2. The single event upset resistant shift register reinforcement circuit structure according to claim 1, wherein: The enable control module is provided with a clock signal terminal, a reset signal terminal, a control signal terminal, an external enable signal terminal, an address signal terminal and an enable control network output terminal, and the enable control module includes an address decoder; after receiving the clock signal, reset signal and control signal, the enable control module selects the address signal terminal through the address decoder to generate different enable signal outputs to realize the configuration of redundant mode or single group activation mode.

3. The single event upset resistant shift register reinforcement circuit structure according to claim 2, wherein: When the control signal is at a low level, the enable control module is configured in a single group activation mode, and when the control signal is at a high level, the enable control module is configured in a redundant mode.

4. The single event upset resistant shift register reinforcement circuit structure according to claim 2, wherein: Each trigger contains a standard input terminal, a clock terminal, an output terminal, and an enable control terminal, among which, The standard input terminal is used to receive external input data; The output terminal is connected to the standard input terminal of the next stage trigger, which is used to directly output data or shift the data to the next stage trigger under clock drive; The enable control terminal is connected to the corresponding external enable signal terminal in the enable control module and a single enable terminal in the enable control network output terminal, and is used to receive the enable signal output by the enable control module.

5. The single event upset resistant shift register reinforcement circuit structure according to claim 4, wherein: A single enable terminal of the enable control network output terminal is connected to the enable control terminals of two triggers at the same time, so that the triggers correspond to each other in pairs to form a group of a main trigger and a backup trigger.

6. The single event upset resistant shift register reinforcement circuit structure according to claim 1, wherein: The output control selection module switches the data output path by selecting an enable signal. The select enable signal is respectively connected to the control selector and the error judgment module. When in the single group activation mode, the select enable signal is maintained at a high level, thereby activating the control selector and turning off the error judgment module; when in the redundant mode, the select enable signal is maintained at a low level, thereby activating the error judgment module and turning off the control selector.

7. The single event upset resistant shift register reinforcement circuit structure according to claim 1, wherein: The error judgment module includes a plurality of XOR gate circuits and a plurality of two-choose-one selectors, the output ends of the main trigger and the backup trigger of the same group are connected to the same XOR gate circuit, the output end of each main trigger is connected to a two-choose-one selector, and the XOR gate circuit and the two-choose-one selector connected to the output end of the same main trigger are connected to each other; When in redundant mode, the XOR gate circuit compares the data output by the main trigger and the backup trigger in real time. If the data are consistent, the data output by the main trigger is output by the two-to-one selector. If the data are inconsistent, the output signal of the two-to-one selector is turned off.

8. The single event upset resistant shift register reinforcement circuit structure according to claim 7, wherein: The XOR gate circuit controls the state of the two-to-one selector through the error indication signal it outputs; if the data is consistent, the error indication signal remains at a low level, and the two-to-one selector outputs the data output by the main trigger; if the data is inconsistent, the error indication signal remains at a high level, and the output signal of the two-to-one selector is turned off.

9. The single event upset resistant shift register reinforcement circuit structure according to claim 8, wherein: If the data are consistent, the error indication signal is also transmitted to the host processor, which controls the discarding of the erroneous data and resends the relevant correct data to the standard data input terminal of the corresponding trigger.

Images