Memory system

Abstract

A memory system includes a first memory bank. The first memory bank includes a plurality of first memory cells, a first switching circuit, and a first region column decoder. The first memory cell is coupled to a first bit line. The first switching circuit is configured to selectively couple the first bit line to the first region data line according to a voltage on the first region column select line. The first region column decoder is configured to selectively couple the first region column select line to the global column select line and selectively couple the first region column select line to a reference ground voltage.

Description

Technical Field

[0001] The present invention relates to a system, and more particularly to a memory system. Background Art

[0002] As the requirement for the capacity of the memory system gradually increases, the number of memory banks in the memory system also increases. In this case, how to reduce the area of the memory system has become an important issue in the design of the memory system. Summary of the Invention

[0003] The present invention provides a memory system, which can reduce the manufacturing cost of the memory system.

[0004] The present invention provides a memory system, including a first memory bank. The first memory bank includes a plurality of first memory cells, a first switching circuit, and a first regional column decoder. The first memory cells are coupled to a first bit line. The first switching circuit is configured to selectively couple the first bit line to a first regional data line according to a voltage on a first regional column selection line. The first regional column decoder is configured to selectively couple the first regional column selection line to a global column selection line, and selectively couple the first regional column selection line to a reference ground voltage.

[0005] Based on the above, the memory system provided by the present invention can share a column decoder between different memory banks at a lower hardware cost, thereby reducing the manufacturing cost of the memory system. Brief Description of the Drawings

[0006] Drawings are included to provide a further understanding of the present invention, and the drawings are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0007] Figure 1 A circuit schematic diagram showing a memory system according to Embodiment 1 of the present invention;

[0008] Figure 2 Showing Figure 1 A circuit schematic diagram of the memory bank in;

[0009] Figure 3A Showing Figure 1 A circuit block diagram of the memory bank selection circuit in;

[0010] Figure 3B Showing Figure 3A A waveform schematic diagram of the memory bank selection circuit in.

[0011] Description of Reference Numerals

[0012] 1: Memory system;

[0013] 10: Memory bank selection circuit;

[0014] 11, 12: Row decoders;

[0015] 13: Column decoder;

[0016] 14: Switching circuit;

[0017] 15: Region column decoder;

[0018] 141, 142: Switches;

[0019] BL1, BL2: Bit lines;

[0020] BNKCSL, BNKCSL_n, BNKCSL_n_weak: Selection signals;

[0021] D1: Diode circuit;

[0022] GCSL1, GCSL2: Global column selection lines;

[0023] GND: Reference ground voltage;

[0024] INV1, INV2: Inverters;

[0025] LCSL1, LCSL2: Region column selection lines;

[0026] LDQ: Region data line;

[0027] MB1, MB2: Memory banks;

[0028] MC: Memory cell;

[0029] NM1~NM3, PM1~PM3: Transistors;

[0030] P1~P4: Current paths;

[0031] SA1, SA2: Sense amplifiers;

[0032] SW1~SW4: Switches;

[0033] Vdiode: Anode voltage;

[0034] VDD: Reference operating voltage;

[0035] WL1~WLn: Word lines. Detailed implementation manners

[0036] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0037] Figure 1 A circuit schematic diagram showing Memory System 1 according to Embodiment 1 of the present invention. Memory System 1 includes memory banks MB1 and MB2, a memory bank selection circuit 10, row decoders 11 and 12, and a column decoder 13. In this embodiment, memory banks MB1 and MB2 are respectively controlled by corresponding column decoders 11 and 12, and memory banks MB1 and MB2 share the same column decoder 13. That is to say, the word lines in memory bank MB1 can be driven by row decoder 11, and the word lines in memory bank MB2 can be driven by row decoder 12. Additionally, column decoder 13 can drive the corresponding columns in memory banks MB1 and MB2 through global column selection lines. Since one global column selection line is simultaneously connected to the corresponding columns in memory banks MB1 and MB2 respectively, Memory System 1 also needs to select memory banks MB1 and MB2 through memory bank selection circuit 10, so that the selected memory bank operates through the global column selection line, and the unselected memory bank does not receive the control of the global column selection line. In this way, only one column decoder 13 in Memory System 1 is required to control both memory banks MB1 and MB2, thus effectively reducing the manufacturing cost of Memory System 1.

[0038] Figure 2 show Figure 1 A circuit schematic diagram of memory bank MB1 in [the figure]. Memory bank MB1 includes a plurality of memory cells MC, sense amplifiers SA1 and SA2, a switch circuit 14, and a local column decoder 15. Memory cells MC are arranged in an array form. Memory cells MC in the same row are coupled to the same word line, and memory cells MC in the same column are coupled to the same bit line. Memory cells MC can be, for example, applied to a dynamic random access memory (DRAM), which includes a selector and a storage element connected in series. The selector can receive the control of the word line, enabling the storage element to read and / or write through the bit line. In some embodiments, memory cells MC in the same column are also coupled to the same source line. Sense amplifiers SA1 and SA2 are respectively coupled to the bit lines of the corresponding columns in memory bank MB1 to read the bit lines of the corresponding columns. Switch circuit 14 includes a plurality of switches, which are respectively coupled to the corresponding sense amplifiers. Switch circuit 14 receives the control of local column decoder 15 to selectively provide the sensing results of sense amplifiers SA1 and SA2 to local data line LDQ. More specifically, local column decoder 15 receives selection signals BNKCSL_n and BNKCSL_n_weak, and then selectively couples the local column selection line of each column to the corresponding global column selection line, and selectively couples the local column selection line of each column to the reference ground voltage.

[0039] InFigure 2 In order to facilitate the description, only two columns in the memory bank MB1 are shown for illustration. However, those skilled in the art can of course vary Figure 2 the number of rows and / or columns of the memory bank MB1 in [the figure], all of which fall within the scope of variations of the memory system 1 embodiment.

[0040] In some embodiments, when the memory bank MB1 is selected, the corresponding selection signals BNKCSL_n and BNKCSL_n_weak can be provided to the regional column decoder 15, enabling the regional column decoder 15 to control the switch circuit 14 to be conductive according to the signal transmitted on the global column selection line, and read the data from the memory cell MC. When the memory bank MB1 is not selected, the regional column decoder 15 can control the switch circuit 14 to be nonconductive according to the corresponding selection signals BNKCSL_n and BNKCSL_n_weak.

[0041] Specifically, in the memory bank MB1, the sense amplifier of each column is connected to a corresponding switch in the switch circuit 14 to control whether to couple the sense amplifier of each column to the regional data line LDQ. Further, each switch control terminal in the switch circuit 14 is coupled to a corresponding regional column selection line, and each regional column selection line is coupled to two switches of the regional column decoder 15. One switch of the regional column decoder 15 receives the selection signal BNKCSL_n to control whether to couple the global column selection line to the control terminal of the switch in the switch circuit 14, and the other switch of the regional column decoder 15 receives the selection signal BNKCSL_n_weak to selectively couple the control terminal of the switch in the switch circuit 14 to the reference ground voltage GND.

[0042] For example, take Figure 2Taking the first column of the memory bank MB1 as an example, the memory cells MC in the first column of the memory bank MB1 are connected to the bit line BL1. After the sense amplifier SA1 is coupled to the bit line BL1 for reading, the switch 141 in the switch circuit 14 receives the control of the regional column decoder 15 through the regional column selection line LCSL1, and accordingly determines whether to provide the reading result of the sense amplifier SA1 to the regional data line LDQ. In the regional column decoder 15, the switches SW1 and SW2 are coupled to the control end of the switch 141 through the regional column selection line LCSL1 to respectively control the voltage of the control end of the switch 141 according to the selection signals BNKCSL_n and BNKCSL_n_weak. More specifically, the switch SW1 is coupled between the global column selection line GCSL1 and the control end of the switch in the switch circuit 14, and the control end of the switch SW1 receives the selection signal BNKCSL_n. The switch SW2 is coupled between the control end of the switch in the switch circuit 14 and the reference ground voltage GND, and the control end of the switch SW2 receives the selection signal BNKCSL_n_weak.

[0043] Further, when the memory bank MB1 is selected, the in-phase selection signals BNKCSL_n and BNKCSL_n_weak can be provided to the regional column decoder 15. However, since the voltage of the selection signal BNKCSL_n has a greater pull-down amplitude compared to the voltage of the selection signal BNKCSL_n_weak, the switch signal SW1 has a stronger driving ability, thus dominating the voltage of the control end of the switch in the switch circuit 14. For example, when the memory bank MB is selected, the selection signal BNKCSL_n is pulled down from the reference operating voltage VDD to the reference ground voltage GND, for example. The selection signal BNKCSL_n is pulled down from the reference operating voltage VDD to a preset voltage (for example, the threshold voltage of the switch SW2). In Figure 2 the example, the switches SW1 and SW2 are a P-type transistor and an N-type transistor respectively. When the memory bank MB1 is selected, the selection signal BNKCSL_n pulled down to the reference ground voltage GND can turn on the switch SW1, coupling the global column selection line GCSL1 to the control end of the switch 141. In addition, the selection signal BNKCSL_n_weak pulled down to the threshold voltage can control the switch SW2 to be slightly conductive or weakly conductive, causing the control end of the switch 141 to discharge to the reference ground terminal GND.

[0044] Further, assuming that the voltage on the global column select line GCSL1 is a high voltage corresponding to logic 1, when the switch SW1 is turned on and the global column select line GCSL1 is coupled to the control terminal of the switch 141, the control terminal of the switch 141 can be charged according to the current path P1. In addition, when the switch SW2 is turned on and the reference ground voltage GND is coupled to the control terminal of the switch 141, the control terminal of the switch 141 can be discharged by the current path P2. Specifically, the select signal BNKCSL_n can control the switch SW1 in the saturation region, and the select signal BNKCSL_n_weak can control the switch SW2 in, for example, the sub-threshold region or the linear region. The voltage difference between the select signals BNKCSL_n and BNKCSL_n_weak causes a difference in the driving capabilities of the switches SW1 and SW2. In the case where the switches SW1 and SW2 respectively provide the current paths P1 and P2 to charge and discharge the control terminal of the switch 141, the switch SW1 can dominate the voltage of the control terminal of the switch 141 through its stronger driving capability, thereby charging the control terminal of the switch 141 to the same voltage as that on the global column select line GCSL1, that is, pulling it up to a high voltage corresponding to logic 1.

[0045] Since they are controlled by the select signals BNKCSL_n and BNKCSL_n_weak with different voltage amplitudes, the switches SW1 and SW2 have different driving capabilities. For example, when the memory bank MB1 is selected, the equivalent impedance of the switch SW1 is lower than that of the switch SW2, such that the current flowing through the current path P1 is greater than the current flowing through the current path P2, thereby causing the voltage of the control terminal of the switch 141 to be dominated by the voltage on the global column select line GCSL1.

[0046] In addition, taking the second column of the memory bank MB1 as an example, assuming that the voltage on the global column select line GCSL2 is a low voltage corresponding to logic 0, when the switch SW3 is turned on and the global column select line GCSL2 is coupled to the local column select line LCSL2, the control terminal of the switch 142 can be discharged according to the current path P3. In addition, when the switch SW4 is turned on and the reference ground voltage GND is coupled to the local column select line LCSL2, the control terminal of the switch 142 can be discharged by the current path P4. However, when the switch SW3 is discharging, due to the characteristics of the P-type transistor, the switch SW3 can only discharge the control terminal of the switch 142 to the threshold voltage of the P-type transistor in the switch SW3. In this way, the switch 142 that is not fully discharged will cause an error to occur when the memory bank MB1 is being read. Therefore, as an auxiliary, the switch SW4 can simultaneously provide the current path P4 to discharge the control terminal of the switch 142 to the reference ground voltage GND, so that the switch 142 can be surely turned off (nonconductive), thereby improving the operation of the memory system 1.

[0047] Briefly speaking, in memory bank MB1, the regional column decoder 15 provides two switches for the read operation switches of each column in the switching circuit 14. These two switches are respectively controlled by the selection signals BNKCSL_n and BNKCSL_n_weak, have different driving capabilities, and can couple the global column selection line or the reference ground voltage to the control terminal of the read operation switch respectively. In this way, the voltage on the control terminal of the read operation switch can be dominated by the voltage on the global column selection line through the switch controlled by the selection signal BNKCSL_n. At the same time, as an auxiliary, the switch controlled by the selection signal BNKCSL_n_weak can provide a discharge path without affecting the logic of the control terminal of the read operation switch, so that when the voltage on the global column selection line is a low voltage corresponding to logic 0, it helps the control terminal of the read operation switch to discharge to the reference ground voltage, thus improving the read operation of the memory system 1.

[0048] Figure 3A shows Figure 1 The circuit block diagram of the memory bank selection circuit 10 in. The memory bank selection circuit 10 can be used to receive the selection signal BNKCSL to generate selection signals BNKCSL_n and BNKCSL_n_weak that are in phase but have different voltage amplitudes. The memory bank selection circuit includes inverters INV1, INV2 and a diode circuit D1. The inverter INV1 is coupled between the reference operating voltage VDD and the reference ground voltage GND. The input terminal of the inverter INV1 receives the selection signal BNKCSL and generates the selection signal BNKCSL_n at the output terminal. The inverter INV2 is coupled between the reference operating voltage VDD and the diode circuit D1 and is coupled to the reference ground voltage GND through the diode circuit D1. The input terminal of the inverter INV2 receives the selection signal BNKCSL and generates the selection signal BNKCSL_n_weak at the output terminal.

[0049] Specifically, the inverter INV1 includes transistors PM1 and NM1 connected in series between the reference operating voltage VDD and the reference ground voltage GND. The inverter INV2 includes transistors PM2 and NM2 connected in series between the reference operating voltage VDD and the diode circuit D1. The diode circuit D1 includes transistors PM3 and NM3 connected in a diode-connected manner. The anode of the diode circuit D1 is coupled to the source of the transistor NM2, and the cathode of the diode circuit D1 is coupled to the reference ground voltage GND. In this way, the memory bank selection circuit 10 can generate selection signals BNKCSL_n and BNKCSL_n_weak with different amplitudes according to the coupling relationship of the inverters INV1, INV2 and the diode circuit D1.

[0050] Figure 3B showsFigure 3A Waveform schematic diagram of the middle memory bank selection circuit 10. Figure 3B The selection signals BNKCSL, BNKCSL_n, BNKCSL_n_weak, and the anode voltage Vdiode of the inverter INV2 and the diode circuit D1 are shown.

[0051] As Figure 3B shown, when the selection signal BNKCSL switches from a low voltage to a high voltage, BNKCSL_n can be pulled down by the inverter INV1 from the reference operating voltage VDD to the reference ground voltage GND. At the same time, the pulled-up selection signal BNKCSL also turns on the transistor NM2, causing the diode circuit D1 to turn on and the anode voltage Vdiode of the diode circuit D1 to be maintained at the threshold voltage of the diode circuit D1. Further, the lifted anode voltage Vdiode of the diode circuit D1 can cause the selection signal BNKCSL_n_weak generated by the inverter INV2 to be pulled down with a gentler slope, so that the fall time of the selection signal BNKCSL_n is less than the fall time of the selection signal BNKCSL_n_weak. In addition, due to the diode circuit D1 coupled to the source of the transistor NM2, the inverter INV2 can only pull down the selection signal BNKCSL_n_weak to the threshold voltage of the diode circuit D1, which is higher than the reference ground voltage GND to which the inverter INV1 pulls down the selection signal BNKCSL_n.

[0052] In this way, when the selection signal BNKCSL switches from a low voltage to a high voltage, the selection signal BNKCSL_n can be pulled down by the inverter INV1 from the reference operating voltage VDD to the reference ground voltage GND, and the selection signal BNKCSL_n_weak can be pulled down by the inverter INV2 and the diode circuit D1 from the reference operating voltage VDD to the threshold voltage of the diode circuit D1. Therefore, the selection signals BNKCSL_n, BNKCSL_n_weak with different voltage amplitudes generated by the memory bank selection circuit 10 can perform switch operations in the regional column decoder 15 under different driving capabilities, thus effectively improving the operation of the memory system 1.

[0053] In summary, the memory system of the present invention can effectively reduce the hardware cost of the regional column decoder while sharing the column decoder and at the same time maintain the correct read operation. More precisely, for each column of the memory bank, the regional column decoder only needs to set two transistors to correctly control the read operation of each column. Therefore, while reducing the hardware cost, the operation of the memory system is also maintained correctly.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A memory system, comprising: A first memory bank, comprising: A plurality of first memory cells, coupled to a first bit line; and A first switch circuit configured to selectively couple the first bit line to a first local data line according to a voltage on a first local column selection line; and A first local column decoder configured to selectively couple the first local column selection line to a global column selection line and selectively couple the first local column selection line to a reference ground voltage.

2. The memory system according to claim 1, wherein when the plurality of first memory cells of the first memory bank are selected, the first local column decoder couples the first local column selection line to the global column selection line and simultaneously couples the first local column selection line to the reference ground voltage.

3. The memory system according to claim 1, wherein the first local column decoder includes a first switch and a second switch, the first switch being coupled between the local column selection line and the global column selection line, and the second switch being coupled between the local column selection line and the reference ground voltage.

4. The memory system according to claim 3, wherein when the plurality of first memory cells of the first memory bank are selected, the first switch couples the first local column selection line to the global column selection line, the second switch couples the first local column selection line to the reference ground voltage, and the driving ability of the first switch is stronger than that of the second switch.

5. The memory system according to claim 4, wherein the first switch is a P-type metal-oxide-semiconductor transistor, the second switch is an N-type metal-oxide-semiconductor transistor, and the phases of a first selection signal and a second selection signal are the same.

6. The memory system according to claim 5, wherein when the plurality of first memory cells of the first memory bank are selected, the first selection signal and the second selection signal are pulled down, and the falling time of the first selection signal is less than the falling time of the second selection signal.

7. The memory system according to claim 1, further comprising: A second memory bank, comprising: A plurality of second memory cells, coupled to a second bit line; and A second switch circuit configured to selectively couple the second bit line to a second local data line according to a voltage on a second local column selection line; and A second local column decoder configured to selectively couple the second local column selection line to the global column selection line and selectively couple the second local column selection line to the reference ground voltage.

8. The memory system according to claim 7, wherein when the plurality of first memory cells of the first memory bank are selected, the plurality of second memory cells of the second memory bank are not selected.

9. The memory system according to claim 1, further comprising: A memory bank selection circuit, coupled to the first local column decoder, the memory bank selection circuit being configured to generate a first selection signal and a second selection signal for controlling the operation of the first local column decoder.

10. The memory system according to claim 9, wherein the memory bank selection circuit comprises: A diode circuit having two ends, one of which is used to receive the reference ground voltage; A first inverter coupled between the reference operating voltage and the reference ground voltage, the first inverter configured to receive a selection signal to generate the first selection signal; And A second inverter coupled between the reference operating voltage and the other end of the diode circuit, the second inverter being used to receive the selection signal to generate the second selection signal.

11. The memory system according to claim 10, wherein the first selection signal is between the reference operating voltage and the reference ground voltage, and the second selection signal is between the reference operating voltage and the threshold voltage of the diode circuit.

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