Memory, operation method thereof and memory system

Abstract

The embodiment of the invention discloses a memory, an operation method thereof and a memory system, the memory comprises a memory cell array, and the memory cell array comprises a plurality of memory cells; a bit line coupled to the plurality of memory cells; a word line coupled to the plurality of memory cells; a peripheral circuit coupled to the bit lines and the word lines, the peripheral circuit configured to apply a first voltage to a selected word line of the plurality of word lines in a first period to turn on the cell transistors of the memory cells coupled to the selected word line; in the first period, a second voltage is applied to at least one dummy word line in the plurality of word lines to turn on the cell transistor of the memory cell coupled to the at least one dummy word line.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a memory, an operation method thereof, and a memory system. Background Art

[0002] With the continuous development of current science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor storage device in computers. How to improve the read performance of dynamic random access memory has been a key research topic in this field. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory, an operation method thereof, and a memory system.

[0004] According to a first aspect of the present disclosure, there is provided a memory, comprising:

[0005] A memory cell array including a plurality of memory cells;

[0006] Bit lines coupled to the plurality of memory cells;

[0007] Word lines coupled to the plurality of memory cells;

[0008] A peripheral circuit coupled to the bit lines and the word lines, the peripheral circuit being configured to:

[0009] Apply a first voltage to a selected word line among the plurality of word lines during a first period to turn on a cell transistor of a memory cell coupled to the selected word line;

[0010] Apply a second voltage to at least one dummy word line among the plurality of word lines during the first period to turn on a cell transistor of a memory cell coupled to the at least one dummy word line.

[0011] According to a second aspect of the present disclosure, there is provided a memory system, the memory system comprising:

[0012] One or more memories as described in the first aspect of the present disclosure;

[0013] A memory controller coupled to the memory and configured to control the memory.

[0014] According to a third aspect of the present disclosure, there is provided an operation method of a memory, the memory comprising a memory cell array including a plurality of memory cells, bit lines and word lines coupled to the plurality of memory cells; the operation method comprising:

[0015] During a first period, a first voltage is applied to a selected word line among the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line;

[0016] During the first period, a second voltage is applied to at least one dummy word line among the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line.

[0017] The peripheral circuit provided by an embodiment of the present disclosure is configured to: during a first period of a read operation, apply a first voltage to a selected word line among a plurality of normal word lines. After turning on the cell transistor of the memory cell coupled to the selected word line, the cell capacitor in the memory cell shares charges with the bit line. During the first period, a second voltage is applied to at least one dummy word line to turn on the cell transistor of the memory cell coupled to the dummy word line, so that the cell capacitor of the memory cell is coupled to the bit line, and the bit line capacitance C can be adjusted BL , for example, adjusting the proportion of the fixed capacitance in the bit line capacitance C BL thereby increasing the sensing margin and not increasing the area of the peripheral circuit. Description of the Drawings

[0018] Figure 1 is a schematic diagram of a memory including a peripheral circuit provided by an embodiment of the present disclosure;

[0019] Figure 2 is a schematic structural diagram of a memory cell array including memory cells provided by an embodiment of the present disclosure;

[0020] Figure 3 is a schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure;

[0021] Figure 4 is a block diagram of a memory including a memory cell array and a peripheral circuit provided by an embodiment of the present disclosure;

[0022] Figure 5 is a schematic structural diagram of a memory including a peripheral circuit provided by an embodiment of the present disclosure;

[0023] Figure 6 is another schematic diagram of a memory including a peripheral circuit provided by an embodiment of the present disclosure;

[0024] Figure 7a is a schematic illustration of voltage changes on a bit line and a complementary bit line during a read operation provided by an embodiment of the present disclosure Figure 1 ;

[0025] Figure 7b is a schematic illustration of voltage changes on a bit line and a complementary bit line during a read operation provided by an embodiment of the present disclosureFigure 2 ;

[0026] Figure 8 Schematic diagram of the composition of the bit line capacitor provided by the embodiment of the present disclosure;

[0027] Figure 9 Schematic diagram showing the change of a sensing margin with other capacitors provided by the embodiment of the present disclosure

[0028] Figure 10 Schematic diagram of any two memory blocks in the memory bank provided by the embodiment of the present disclosure;

[0029] Figure 11 Schematic circuit diagram of a memory bank including a sense amplifier provided by the embodiment of the present disclosure;

[0030] Figure 12 is Figure 11 Signal timing during the read operation performed by the sense amplifier shown Figure 1 ;

[0031] Figure 13 is Figure 11 Signal timing during the read operation performed by the sense amplifier shown Figure 2 ;

[0032] Figure 14 is Figure 11 Signal timing during the read operation performed by the sense amplifier shown Figure 3 ;

[0033] Figure 15 is Figure 11 Signal timing during the read operation performed by the sense amplifier shown Figure 4 ;

[0034] Figure 16 Another schematic circuit diagram of a memory including a sense amplifier provided by the embodiment of the present disclosure;

[0035] Figure 17 is Figure 16 Signal timing diagram during the read operation performed by the sense amplifier shown;

[0036] Figure 18 Schematic circuit diagram of a memory including a row decoder and a word line driver provided by the embodiment of the present disclosure;

[0037] Figure 19 Schematic block diagram showing the composition of an exemplary electronic device according to an embodiment of the present disclosure;

[0038] Figure 20 Schematic block diagram of the composition of an exemplary solid state drive (SSD) according to an embodiment of the present disclosure;

[0039] Figure 21 Schematic block diagram of an exemplary memory according to an embodiment of the present disclosure;

[0040] Figure 22 Flow schematic diagram of an operation method of a memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0041] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present disclosure can be fully communicated to those skilled in the art. In the following description, the present disclosure gives a large number of specific details in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details.

[0042] The present disclosure can at least partially understand the terms according to their use in the context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or property in a singular sense, or can be used to describe a combination of features, structures, or properties in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey singular usage or convey plural usage. Additionally, the term "based on" can be understood as not necessarily intended to convey a set of exclusive factors, and instead can allow for the existence of additional factors that are not necessarily explicitly described. The terms "comprising" and / or "including", when used in this specification, determine the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. The term "and / or" includes any and all combinations of the related listed items.

[0043] Figure 1 Schematic diagram of a memory including a peripheral circuit provided by an embodiment of the present disclosure. As Figure 1 shown, the memory 10 includes a memory cell array 100 and a peripheral circuit 200 coupled to the memory cell array 100. Here, the memory cell array 100 can be a DRAM memory cell array 100, where the memory cells 110 can be arranged in a two-dimensional plane.

[0044] In some embodiments, the DRAM memory cell 110 may be a 1T1C cell composed of a transistor 300 and a capacitor 400. The capacitor 400 stores one-bit data in the form of charge or electrons. In one example, more charge stored in the capacitor 400 may represent data "1", and less charge stored in the capacitor 400 may represent data "0". The transistor 300 is used to access, read, and write data. The gate of the transistor 300 is connected to the word line, the first source-drain is connected to the bit line 120, and the second source-drain is connected to the capacitor 400. The electrical signal applied to the word line 130 can control the opening or closing of the transistor 300. When the transistor 300 is open, the capacitor 400 is conductive to the bit line 120, enabling electrons to enter the capacitor 400 through the bit line 120 to write data "1", or discharging the capacitor 400 through the bit line 120 to write data "0". When the transistor 300 is closed, the capacitor 400 is isolated from the bit line 120, thus preserving the previously written data or charge. In addition, the stored data in the capacitor 400 can be read by measuring the amount of charge. Since the transistors in the DRAM memory cell are very small, the electrons in the capacitor will slowly leak. Therefore, over time, the capacitor needs to be refreshed to charge the leaked electrons.

[0045] Continuing to refer to Figure 1 , the memory cell array 100 can be organized into multiple bank groups (BGs). The number of bank groups can be 2, 4, 8, etc. A bank group is composed of multiple banks. The number of banks can be 4, 8, etc. The number of bank groups and the number of banks within a group determine how many banks the memory cell array 100 includes. Each bank can be activated individually to perform pre-charge, read, and write operations, etc.

[0046] A bank may include one or more sub-arrays, which may also be referred to as memory blocks (Blocks). Each memory block includes multiple memory cell rows and multiple memory cell columns. The memory cells in a memory cell row are coupled to the same word line 130, that is, the word line 130 is connected to the gates of the memory cells 110 located in the same row. The word line 130 selects which row of the multiple memory cell rows is activated to perform read or write operations. When a word line 130 is activated, all the capacitors 400 in that row are connected to the corresponding bit line 120, thus activating all the memory cells in that row. The memory cells in a memory cell column are coupled to the same bit line 120, that is, the bit line 120 is connected to the sources of the memory cells 110 located in the same column. The bit line 120 can select one memory cell column to be activated, or the bit line 120 can also select multiple memory cell columns to be activated in burst mode.

[0047] Figure 2Schematic diagram of a memory cell array including memory cells provided by an embodiment of the present disclosure. As Figure 2 shown, the transistor 300 includes a semiconductor pillar 310 extending in the vertical direction. The semiconductor pillar 310 is used to form a first source / drain 311, a channel region 312, and a second source / drain 313 of the transistor. In one example, the first source / drain 311 and the second source / drain 312 can be formed by implanting the same type of doping ions at both ends of the semiconductor pillar 310. The doping ions can be P-type doping ions or N-type doping ions. The P-type doping ions include, but are not limited to, boron (B), aluminum (Al), etc. The N-type doping ions include, but are not limited to, phosphorus (P) or arsenic (As), etc. The middle section of the semiconductor pillar 210 may not be implanted with doping ions to form a channel region, or may be implanted with doping ions of a different type from both ends to form the channel region 312. For example, if P-type doping ions are implanted at both ends of the semiconductor pillar 310, then N-type doping ions are implanted in the middle section, and vice versa. The material of the semiconductor pillar 310 may include silicon (e.g., single-crystalline silicon, polycrystalline silicon), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or any other suitable material.

[0048] The transistor 300 further includes a gate structure located on the sidewall of the semiconductor pillar 310. The gate structure includes a gate oxide layer 320 and a gate layer 330. The gate oxide layer 320 is located between the gate layer 330 and the sidewall of the semiconductor pillar 310. The material of the gate oxide layer 320 may include silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiOx), hafnium silicon oxynitride (HfSiON). The material of the gate layer 330 may include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, metal silicide, metal nitride, or any combination thereof. In some embodiments, the gate layer 330 may include a metal nitride layer and a metal layer stacked in sequence. For example, a titanium nitride layer (TiN) and a tungsten layer, and the titanium nitride layer is located between the tungsten layer and the gate oxide layer 320. The gate structure may be located on one sidewall of the semiconductor pillar 310 to form a single-gate transistor; or may be located on two opposite sidewalls of the semiconductor pillar 310 to form a double-gate transistor. Figure 2 The transistor with a vertical channel structure in is also called a vertical channel transistor. In some other embodiments, the transistor 300 in the memory cell 110 may also be various types of transistors such as a planar transistor.

[0049] Each capacitor 400 corresponds to a transistor 300, and the capacitor 400 can vertically extend above the transistor 300. The capacitor 400 includes a lower plate 410, a dielectric layer 420 surrounding the lower plate 410, and an upper plate 430 surrounding the dielectric layer 420. Among them, the lower plate 410 can be electrically connected to the first source / drain 311 of the transistor 300 through a capacitive contact plug 440. The materials of the lower plate 410 and the upper plate 430 both include conductive materials, and the conductive materials include but are not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. The material of the dielectric layer 420 can include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric materials (such as doped silicon oxide, silicon fluoroglass) or any combination thereof. It should be understood that Figure 2 The depicted memory cell 110 is for illustrative purposes only and can be changed in other examples. It should be understood that although not shown Figure 2 additional components of the memory cell array 301 can also be formed, and the additional components include but are not limited to bit line contact plugs, capacitive contact plugs, capacitive support layers, etc.

[0050] Return to reference Figure 1 , the peripheral circuit 200 can be coupled to the memory cell array 100 through the bit line 120 and the word line 130. The peripheral circuit 200 can include any suitable analog, digital, and mixed signal circuits for applying voltage signals and / or current signals to the memory cell 110 via the bit line 120 and the word line 130 and sensing voltage signals and / or current signals from the memory cell 110 to implement the write operation and read operation of the memory cell array. The peripheral circuit 200 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Figure 3 A schematic diagram of a peripheral circuit 200 provided by an embodiment of the present disclosure. The peripheral circuit 200 can include: an address buffer 210, a row decoder 220, a word line driver 230, a sense amplifier 240, a column decoder 250, a control logic unit 260 (including a command decoder 270), an input / output buffer 280, etc. In one example, the control circuit corresponding to each memory bank can include a sense amplifier 240, a word line driver 230, a row decoder 220, a column decoder 250, etc., that is, different memory banks do not share these control circuits. In some embodiments, the control circuit corresponding to all memory banks can include a control logic circuit 260, an address buffer 210, an input / output buffer 280, etc. It should be understood that in some examples, additional peripheral circuits not shown in Figure 3 can also be included, such as a row address latch, a column address latch, a refresh control circuit, a memory bank group / memory bank controller, etc.

[0051] The sense amplifier 240 is connected to the bit line 120. The sense amplifier 240 can sense minute voltage fluctuations on the bit line 120, and amplify the small voltage swing of the bit line 120 to a logic level during a read operation, that is, restore the stored value of the capacitor 400 in the memory cell 110 according to the voltage fluctuation of the bit line 120.

[0052] The word line driver 230 is connected to the word line 130. The word line driver 230 can be configured to generate different control voltages to drive the word line 130. In one example, the word line driver 230 can be configured to provide a control conduction voltage to the selected word line according to the row selection signal output by the row decoder 220, so as to turn on the transistor of the memory cell coupled to the selected word line.

[0053] The address buffer 210 can receive the address information ADDR from the memory controller or the host. In one embodiment, the address lines connected to the address buffer 210 are multiplexed. The address buffer 210 receives the row address information when the row strobe signal RAS is valid, and receives the column address information when the column strobe signal CAS is valid. The row address information includes the address of the bank group, the address of the bank, and the row address. The column address information includes the column address. The address buffer 210 transmits the addresses of the bank group and the bank to the bank group / bank controller, transmits the row address to the row decoder 220, and transmits the column address to the column decoder 250.

[0054] The row decoder 220 can be configured to decode a uniquely selected word line from the row address, and can connect the selected word line to the word line driver 230 for providing a control voltage. In some examples, the row decoder 220 is connected to the address buffer 210 through a row address latch. The row address latch can be configured to latch the row address sent by the address buffer 210. In another embodiment, the row address latch is configured to latch the row address to be refreshed sent by the refresh control circuit.

[0055] The column decoder 250 can be configured to decode a uniquely selected bit line from the column address, or decode multiple selected bit lines from the column address in burst mode. The column decoder 250 can also be configured to generate a column selection signal according to the column address. The column selection signal is used to transfer the stored data of the sense amplifier 240 corresponding to the selected bit line to the data line, and is transferred to the data input / output buffer 280 by the data line. In some examples, the column decoder 250 is connected to the address buffer 210 through a column address latch. The column address latch can be configured to latch the column address sent by the address buffer 210.

[0056] The control logic circuit 260 can receive various commands CMD from a memory controller or a host and generate various control signals for controlling memory operations. The control logic circuit 260 can include a command decoder 270, which is configured to receive various commands CMD and generate various control signals. The control logic circuit 260 can read data from or write data to the memory cell array 100 by using the control signals, or perform other operations. In one example, the control logic circuit 260 can receive an activation command ACT and a read command READ to read data from the memory cells. The control logic circuit 260 can also receive a refresh command REF to control the refresh circuit to perform a refresh operation on a certain row. The input / output buffer 280 can receive data from a host or a memory controller or transmit data to a host or a memory controller.

[0057] In some embodiments, the memory cell array 100 and the peripheral circuit 200 can be located on different wafers. Figure 4 A schematic framework diagram of a memory provided by an embodiment of the present disclosure is shown in Figure 4 As shown, the memory includes a memory cell array wafer W1 and a peripheral circuit wafer W2 that are connected to each other. The memory cell array wafer W1 includes a memory cell array 100, Figure 4 The schematic structural diagram of the memory cell array is not drawn in detail herein. In one example, the memory cell array 100 can include memory cells as shown in Figure 2 As shown, the memory cell includes a transistor having a vertical channel structure and a capacitor located on one side of the transistor, and the memory cells are arranged in an array along intersecting first direction (e.g., X direction) and second direction (e.g., Y direction). In some embodiments, as shown in Figure 4 As shown, the memory cell array wafer W1 includes a first substrate 101, and the transistors can be formed within the first substrate 101, such as forming semiconductor pillars through the first substrate 101. The first substrate 101 includes but is not limited to a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator, germanium-on-insulator, or silicon-germanium-on-insulator, etc. At least one of these substrates can also be used for other substrates (such as the second substrate) mentioned later in this article.

[0058] The word lines 130 extend through the transistor array along the first direction (X direction) and are connected to the gates of a plurality of transistors arranged side by side along the first direction. The bit lines 120 are located on the side of the transistors away from the capacitors, and the bit lines extend along the second direction (Y direction) and are connected to the sources of a plurality of transistors arranged side by side along the second direction.

[0059] In some embodiments, the memory cell array wafer W1 further includes word line contact plugs 150, bit line contact plugs 140, an array interconnect layer 160, and a first bonding layer 170. Figure 5A schematic diagram of the array interconnect layer 160 and the first bonding layer 170 of the memory cell array wafer W1 is shown, as Figure 5 shown, the first bonding layer 170 includes a plurality of first pads T1 exposed on the surface of the memory cell array wafer W1, and first through-silicon vias TS connecting the first pads T1 and the array interconnect layer 160. The first pads T1 are used to connect to the second pads B1 in the peripheral circuit wafer W1. The array interconnect layer 160 includes one or more metal wiring layers, and may also include conductive vias. The array interconnect layer is used for re-wiring so that the word line contact plug 150 and the bit line contact plug 140 can be connected to the first pads T1. In this embodiment, as Figure 5 shown, the array interconnect layer 160 includes metal wiring layers AM1, AM2, and AM3 stacked in sequence, a plurality of conductive vias AV1 connecting adjacent metal wiring layers AM1 and AM2, and a plurality of conductive vias AV2 connecting adjacent metal wiring layers AM2 and AM3. One end of the word line contact plug 150 is connected to the word line 130, and the other end is connected to the array interconnect layer 160. One end of the bit line contact plug 140 is connected to the bit line 120, and the other end is connected to the array interconnect layer 160. The word line contact plug 150 and the bit line contact plug 160 can both be connected to at least one of the metal wiring layers M1, M2, and M3.

[0060] Figure 5 A schematic diagram of the structure of the peripheral circuit wafer W2 is also shown. The peripheral circuit wafer W2 is used to form the peripheral circuit 200. The peripheral circuit 200 includes various devices composed of MOS transistors. The MOS transistors may include PMOS transistors and NMOS transistors. As Figure 5 shown, the MOS transistors may be formed in the second substrate 201 of the peripheral circuit wafer W2. A plurality of MOS transistors may form devices in the peripheral circuit such as sense amplifiers and word line drivers. The peripheral circuit wafer W2 further includes a second bonding layer 204 and a peripheral interconnect layer 203 connected to the second bonding layer 204. Among them, the second bonding layer 204 includes a plurality of second pads B1 exposed on the surface of the peripheral wafer, and second through-silicon vias BS connecting the second pads B1 and the peripheral interconnect layer 203. The peripheral interconnect layer 203 includes a plurality of metal wiring layers and a plurality of conductive plugs. The peripheral interconnect layer 203 can not only realize the interconnection between the devices of the peripheral circuit, but also connect some devices to the second pads B1, so that when the second pads B1 and the first pads T1 are connected, these devices can be coupled to the word lines and bit lines. In this embodiment, as Figure 5As shown, the peripheral interconnect layer 203 includes metal wiring layers CM1, CM2, CM3, CM4, CTM stacked in sequence, and conductive vias V1P, V2P, V3P, TV connecting adjacent metal wiring layers. The peripheral interconnect layer 203 and the second substrate 201 can be connected through conductive plugs 202. It should be understood that the number of metal wiring layers in the array interconnect layer 160 and the peripheral interconnect layer 203 should not be limited and can be designed as needed.

[0061] In some embodiments, a bonding technique can be used to bond the memory cell array wafer W1 and the peripheral circuit wafer W2, that is, multiple first pads T1 and corresponding second pads B1 are bonded to achieve electrical connection. In other embodiments, they can also be physically and electrically connected in any other way.

[0062] It should be understood that Figure 5 This is only a schematic diagram of the architecture of a memory provided by the embodiments of the present disclosure. In other embodiments, the memory cell array and the peripheral circuit can be arranged in any form. For example, the memory cell array and the peripheral circuit can also be arranged on the same wafer. The memory cell array and the peripheral circuit can be independently arranged in different regions on the same wafer, or some peripheral circuits can also be arranged in the region where the memory cell array is located.

[0063] In some embodiments, as Figure 2 and Figure 4 shown, the DRAM memory cell can adopt a vertical channel transistor. Among them, the capacitor array is located on one side of the transistor array, and multiple bit lines are located on the other side of the transistor array. In this DRAM structure, the small spacing between adjacent bit lines results in a coupling capacitance between adjacent bit lines that will affect the read operation. In one example, in the charge sharing stage of the read operation, if the stored values of adjacent memory cells are opposite, for example, one memory cell stores data "1", and the two memory cells adjacent to it on both sides store data "0", then when reading the data of the middle memory cell, the coupling capacitance between them will reduce the sensing margin of the middle memory cell, possibly resulting in data read errors.

[0064] To increase the sensing margin of the memory cell in the read operation, in some embodiments, MOS transistors or metal capacitors can be added to the signal path from the bit line to the sense amplifier. For example, MOS transistors can be added to the peripheral circuit wafer W2 as Figure 4 shown, or the length of the metal line coupled to the bit line can be extended to increase the coupling capacitance of the metal line, etc., so as to adjust the coupling capacitance on the signal path from the memory cell to the sense amplifier, and then increase the sensing margin. However, this will increase the area of the chip and also require a relatively large adjustment to the layout of the peripheral circuit.

[0065] Another embodiment of the present disclosure provides yet another memory that can improve the sensing margin in a read operation. Figure 6 Schematic diagram of yet another memory provided by an embodiment of the present disclosure. As Figure 6 shown, the memory includes: a memory cell array 100, bit lines 120, word lines 130, and a peripheral circuit 200, where:

[0066] The memory cell array 100 includes a plurality of memory cells 110, the bit lines 120 are coupled to the plurality of memory cells 110, and the word lines 130 are coupled to the plurality of memory cells 110;

[0067] The peripheral circuit 200 is coupled to the bit lines 120 and the word lines 130, and the peripheral circuit 200 is configured to:

[0068] In a first period of a read operation, a first voltage is applied to a selected word line 131-1 among the plurality of word lines 130 to turn on the cell transistors of the memory cells coupled to the selected word line 131-1;

[0069] In the first period, a second voltage is applied to at least one dummy word line 132 among the plurality of word lines 130 to turn on the cell transistors of the memory cells coupled to the at least one dummy word line 132.

[0070] As Figure 6 shown, the memory cell array 100 includes a plurality of memory cell rows and a plurality of memory cell columns, the word lines 130 are coupled to one memory cell row, and the bit lines 120 are coupled to one memory cell column. Specifically, the word lines 130 connect the gates of each memory cell in one memory cell row, and the bit lines 120 connect the sources of each memory cell in one memory cell column. In one example, the extending direction of the word lines 130 is parallel to the extending direction of the memory cell rows, for example, the X direction. The extending direction of the bit lines 120 is parallel to the extending direction of the memory cell columns, for example, the Y direction. Each bit line 120 is connected to a sense amplifier, and the sense amplifier is used to amplify the voltage on the bit line to a recognizable logic level during a data read operation to read out the data.

[0071] In some embodiments, the read operation of the memory includes: a precharge stage, a charge sharing stage, and a sense amplification and write-back stage. It should be understood that when the sense amplifier senses and amplifies the voltage of one bit line, it also needs another bit line to provide a reference voltage. Here, the bit line that provides the reference voltage is called a complementary bit line. The bit line and the complementary bit line can be located in different memory blocks of the same memory bank, or in the same memory block of the same memory bank.

[0072] Figure 7a and Figure 7b show schematic diagrams of the voltage changes on the bit line and the complementary bit line during the read operation. As Figure 7a and Figure 7bAs shown, during the pre-charge phase p1, all bit lines (including bit line BL and complementary bit line BL_n) in the selected memory bank are pre-charged to a pre-charge voltage, such as VDD / 2.

[0073] Next, during the charge sharing phase p2, a row is opened according to the row address, and the cell capacitors of all memory cells in this row will be coupled to their corresponding bit lines. As Figure 7a shown, if the data stored in a cell capacitor is "1", such as being charged to VDD, then some charge will flow from the cell capacitor to the bit line BL, causing the voltage on the bit line BL to increase slightly; similarly, as Figure 7b shown, if the data stored in a cell capacitor is "0", such as being discharged to Vss, then some charge will flow from the bit line BL to the cell capacitor, causing the voltage on the bit line BL to decrease slightly; this behavior of sharing bit line charge and cell capacitor charge between the cell capacitor and the bit line BL is called charge sharing. The charge sharing process between the cell capacitor and the bit line BL will slightly change the voltage level on the bit line. And the memory cells coupled to the complementary bit line BL_n are not opened, so the complementary bit line BL_n remains at the pre-charge voltage unchanged during the charge sharing phase p2.

[0074] During the sense amplification and write-back phase p3, the sense amplifier can sense the voltage changes on the bit lines and, based on these changes, amplify the voltages of the bit line BL and the complementary bit line BL_n to different logic levels. As Figure 7a shown, if the voltage on the bit line BL increases during the charge sharing phase, then the sense amplifier will pull up the voltage of the bit line BL to the logic level corresponding to data "1", such as pulling it up to VDD, and pull down the voltage of the complementary bit line BL_n to the logic level corresponding to data "0", such as pulling it down to the ground level Vss. As Figure 7b shown, if the voltage on the bit line BL decreases during the charge sharing phase, then the sense amplifier will pull down the voltage of the bit line BL, such as pulling it down to Vss, and pull up the voltage of the complementary bit line BL_n, such as pulling it up to VDD.

[0075] The sensing margin refers to the change amount ΔV of the voltage on the bit line BL due to charge sharing with the cell capacitor after the voltage on the bit line BL stabilizes during the charge sharing phase p2. The larger the sensing margin, the more accurately the sense amplifier can resolve the data stored in the cell capacitor. The sensing margin is affected by the coupling capacitance on the signal path from the memory cell to the sense amplifier. Here, the coupling capacitance on the signal path from the memory cell to the sense amplifier is collectively referred to as the bit line capacitance C BL .

[0076] In the read operation of the memory cell, as Figure 8 shown, the bit line capacitance C BLIncluding: coupling capacitor C between bit lines BL-BL and coupling capacitor C between bit lines and word lines BL-WL and coupling capacitor C on the signal line from bit lines to sense amplifiers BL-SA . Exemplarily, C BL-SA can be caused by array interconnect layer 160, first bonding layer 170, second bonding layer 204, peripheral interconnect layer 203, conductive plug 202, etc. in Figure 5 .

[0077] In some embodiments, when the proportion of C BL-BL in bit line capacitance C BL is relatively large, when reading the stored values 0001000 (or 1110111) of multiple adjacent storage units, for the isolated data, such as the 1 in the previous data or the 0 in the previous parentheses, their sensing margins are affected by the coupling capacitor and will decrease, and there may be problems with data reading errors.

[0078] Figure 9 Shows a schematic diagram of the sensing margin changing with other capacitors. Here, other capacitors refer to the other capacitors C BL in bit line capacitance C BL-BL except C others . Other capacitor C others can be regarded as a fixed capacitor, and the fixed capacitor can be understood as that these capacitors will not fluctuate greatly due to different stored values of adjacent storage units and can be basically considered fixed. Other capacitor C others can include C BL-WL and C BL-SA . Taking C BL-WL as an example, in the charge sharing stage, a relatively large word line voltage is applied to the word lines coupled to adjacent storage units to turn on their cell transistors, and the voltage change on the bit lines is very small compared to the word line voltage. Therefore, the coupling capacitance between them is basically only affected by the word line voltage. Whether the stored value in the storage unit is "1" or "0", the influence on C BL-WL is not significant, and C BL-WL can be considered fixed. However, the capacitance C BL-BL between bit lines will be significantly affected by the stored value in the storage unit, so it cannot be regarded as a fixed capacitor.

[0079] In this embodiment, when the stored values of multiple adjacent storage units are 0001000, it is measured that the coupling capacitor C BL-BL between the bit line coupled to the storage unit with the stored value "1" and the bit line on one side of it is about 3 fF, then the coupling capacitor between it and the bit lines on both sides is about 6 fF. If other capacitor C others is adjusted from 3 fF to a larger value, as shown in Figure 9The illustrated sensing margin varies with other capacitor C others schematic diagram of the change.

[0080] As Figure 9 shown, when other capacitor C others is adjusted from 3 fF to approximately 7 fF - 8 fF, the sensing margin gradually increases; however, when the fixed capacitor continues to increase, the sensing margin instead begins to decrease. It can be explained that when the proportion of other capacitor C others increases, the proportion of C BL-BL in the bit line capacitor C BL decreases, which can increase the sensing margin; but when other capacitor C others continues to increase, the bit line capacitor C BL increases, which instead leads to a decrease in the sensing margin. When other capacitor C others takes a value at an equilibrium point, the maximum sensing margin can be obtained. In the embodiments of the present disclosure, through testing, when other capacitor C others occupies approximately half of the bit line capacitor C BL , the sensing margin can reach a relatively large value (including the maximum value).

[0081] In the DRAM layout of some embodiments, the capacitance value of other capacitor C others is small, such as approximately 3 fF, and cannot make the sensing margin reach a relatively large value (including the maximum value). Therefore, if a better sensing margin is desired, it is necessary to increase other capacitor C BL in the bit line capacitor C others .

[0082] In the embodiments of the present disclosure, as Figure 6 and Figure 8 shown, multiple word lines 130 include normal word lines 131 and dummy word lines 132. The storage units coupled to the normal word lines 131 are used to store data. The selected word line 131-1 is any one of the normal word lines 131, and the storage unit coupled to the selected word line 131-1 is the selected storage unit. The storage units coupled to the dummy word lines 132 are not used to store data. Therefore, the storage units coupled to the dummy word lines 132 can also be referred to as dummy storage units.

[0083] The embodiments of the present disclosure propose that in the charge sharing stage of the read operation, in addition to connecting the selected storage unit to the bit line, the dummy storage unit is also connected to the bit line. The capacitance value of the unit capacitor of the dummy storage unit is C cell . When the dummy storage unit is connected to the bit line, other capacitor C other includes C BL-WL , C BL-SA and one or more C cell . In some embodiments, the capacitance value C cellis approximately 3.5 fF. When a dummy word line 132 is turned on, the capacitance of other capacitors C other with a capacitance value of 3 fF + 3.5 fF = 6.5 fF can make the sensing margin close to Figure 9 the optimal value of the sensing margin in

[0084] It should be understood that the number of dummy word lines 132 that are turned on (i.e., to which the second voltage is applied) should not be limited and can be determined according to different sensing margins and the relationship between other capacitors C others and according to the capacitance values of the unit capacitors of the dummy memory cells. The number of dummy word lines 132 that are turned on can be one, two, or even more.

[0085] In some embodiments, the dummy memory cells are used to increase the voltage change amount ΔV on the bit line during the charge sharing stage by adjusting the bit line capacitance C BL , and the dummy memory cells do not change the voltage change amount of the bit line by contributing or sharing charges. In one example, before the dummy memory cells are connected to the bit line, the dummy memory cells are configured to have the same voltage as the bit line, such as having the same pre-charge voltage, which can avoid the storage voltage of the dummy memory cells affecting the data reading of the selected memory cell.

[0086] In some embodiments, the first time period can be the charge sharing stage of the above-mentioned reading operation. During the first time period, the unit capacitor of the selected memory cell coupled to the selected word line 131-1 performs charge sharing with the bit line, and the unit capacitor of the dummy memory cell coupled to the dummy word line 132 is used to adjust the bit line capacitance C BL to adjust the sensing margin of the bit line.

[0087] In the embodiments of the present disclosure, during the first time period of the reading operation, a first voltage is applied to the selected word line among multiple normal word lines 131. After the unit transistor of the memory cell coupled to the selected word line is turned on, the unit capacitor in the memory cell performs charge sharing with the bit line. At the same time, during the first time period, a second voltage is applied to at least one dummy word line 132 to turn on the unit transistor of the memory cell coupled to the dummy word line 132, so that the unit capacitor of the memory cell is coupled to the bit line, and the bit line capacitance C BL (for example, adjusting the proportion of the fixed capacitance in the bit line capacitance C BL ) can be adjusted, thereby adjusting the sensing margin (for example, increasing the sensing margin) without increasing the area of the peripheral circuit.

[0088] In some embodiments, as Figure 8 shown, the dummy word lines 132 can be located on both sides of multiple normal word lines 131. Figure 8For example, two dummy word lines 132 are respectively provided on both sides of the whole formed by multiple normal word lines 131. Among them, the dummy word lines Dummy WL0 and Dummy WL1 are close to the normal word line WL0, and the dummy word lines DummyWL2 and Dummy WL3 are close to the normal word line WLn-1. It should be understood that the number of dummy word lines 132 on each side can also be one (as shown in Figure 6 ), or greater than two. Exemplarily, the number of dummy word lines 132 on both sides can be equal.

[0089] In another embodiment, the dummy word line 132 can also be located between any two adjacent normal word lines 131. The number of dummy word lines 132 can be one or more. In still some other embodiments, some dummy word lines 132 can be located on both sides of the whole formed by multiple normal word lines 131, and some other dummy word lines 132 can be located between any two adjacent normal word lines 131.

[0090] In some embodiments, one of the other functions of the dummy memory cells coupled to the dummy word line 132 includes: protecting the normal memory cells coupled to the normal word lines 131 at the edges, such as protecting the memory cells coupled to the normal word line WL0 and the normal word line WLn-1. In other words, the dummy memory cells can protect the normal memory cells at the edges, so that the normal memory cells at the edges have the same surrounding environment as other normal memory cells, so as to improve the accuracy of accessing data of the normal memory cells at the edges. Since the dummy memory cells themselves have other functions, it can be considered that the dummy memory cells adjust the bit line capacitance C BL Just adding the function of the dummy memory cells. Therefore, the method of increasing the sensing margin by turning on the dummy word line 132 in this embodiment can save more chip area than the method of adding MOS transistors or metal capacitors described above.

[0091] In some embodiments, a bank includes multiple memory blocks Block, and each of the multiple memory blocks includes a normal word line WL and a dummy word line Dummy WL. In an example, the multiple memory blocks in the bank can have the same array structure, and the number of bit lines, normal word lines, and dummy word lines coupled to the multiple memory blocks is also the same.

[0092] In a specific embodiment, each of the multiple memory blocks can have an array structure as shown in Figure 8 shown, Figure 10 shows a schematic diagram of any two of the multiple memory blocks, as shown in Figure 10As shown, two memory blocks Block include the same number of bit lines 120, normal word lines 131, and dummy word lines 132. The number of dummy word lines 132 in each memory block is 4. Two dummy word lines 132 are provided on each side of the whole formed by multiple normal word lines 131 along the extending direction of the bit lines.

[0093] In some embodiments, the bit lines and complementary bit lines coupled to the sense amplifier can be in different memory blocks of the same memory bank, or can also be in the same memory block of the same memory bank. In this embodiment, as Figure 10 shown, one end of the sense amplifier 240 is connected to a bit line 120 in one memory block Block, and the other end is connected to a bit line 120 in another memory block. The two memory blocks Block coupled to the same sense amplifier can be adjacent.

[0094] Figure 11 A circuit schematic diagram of a memory bank including a sense amplifier is shown. Figure 11 The sense amplifier 240 in Figure 10 can be any one of the sense amplifiers 240. The sense amplifier 240 is coupled to the first memory block Block m and the second memory block Block m - 1. Taking a normal word line in the first memory block Block m, such as WL1, being activated to perform a read operation as an example, the voltage timing diagram applied to the dummy word line in the read operation will be described in detail. As Figure 11 shown, the normal word line WL1 in the first memory block Block m is activated to become the selected word line, and the bit line connected to the sense amplifier 240 in the second memory block Block m - 1 serves as the complementary bit line BL_n to participate in the read operation.

[0095] Continue to refer to Figure 11 , the sense amplifier 240 includes two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2. The sources of transistors P1 and P2 are connected to the power supply node SAP, and the sources of transistors N1 and N2 are connected to the power supply node SAN. The drain of transistor N1, the drain of transistor P1, the gate of transistor P2, and the gate of transistor N2 are connected, and the connection point is the sense node Saa. The drain of transistor N2, the drain of transistor P2, the gate of transistor P1, and the gate of transistor N1 are connected, and the connection point is the sense node Sab.

[0096] The sensing node Saa is connected to the bit line BL, and the sensing node Sab is connected to the complementary bit line BL_n. The sense amplifier 240 further includes precharge transistors N3, N4, and a balancing transistor N5. The drains of the precharge transistors N3, N4 are respectively connected to the bit line BL and the complementary bit line BL_n, their sources are connected to the power supply node Veq, and their gates are controlled by the precharge signal bleq. When bleq is activated (e.g., at a high level), the precharge transistors N3, N4 conduct, providing a precharge voltage Veq to the bit line BL and the complementary bit line BL_n. The source and drain of the balancing transistor N5 are respectively connected to the bit line BL and the complementary bit line BL_n, providing a conduction path between the bit line BL and the complementary bit line BL_n to balance the voltages of the bit line BL and the complementary bit line BL_n during the precharge stage. The gate of the balancing transistor N5 is also controlled by bleq and conducts when bleq is activated.

[0097] The memory further includes column selection transistors N6, N7. The source of the column selection transistor N6 is connected to the bit line BL, the drain is connected to the local data line ldl (local data line), the source of the column selection transistor N7 is connected to the complementary bit line BL_n, the drain is connected to the differential local data line ldlb, and the gates of the column selection transistors N6, N7 are connected to the column selection line and controlled by the column selection signal cls. When cls is activated (e.g., at a high level), the column selection transistors N6, N7 conduct, transmitting the data latched by the sense amplifier to the local data line ldl.

[0098] Figure 12 For Figure 11 a signal timing diagram during the read operation performed by the shown sense amplifier, as Figure 12 shown. From time t0 to t1, all word lines (including the normal word line WL and the dummy word line Dummy WL) are applied with the control turn-off voltage Vwln; the precharge signal bleq is at a high level, turning on the precharge transistors N3, N4, and the equalizing transistor N5, precharging both the bit line BL and the complementary bit line BL_n to the precharge voltage Veq. This period is the precharge stage, and the bit line BL, the complementary bit line BL_n, and the sense amplifier 240 are in a balanced state during this period. The voltages of the power supply nodes SAP, SAN are both the equalizing voltage Vblp, and no strong drive voltage is provided to the sense amplifier.

[0099] During the period from t1 to t2, i.e., the first period, bleq switches to a low level, turning off the pre-charge transistors N3, N4 and the balance transistor N5, and stopping the supply of the pre-charge voltage Veq to the bit line BL and the complementary bit line BL_n. The selected word line WL sel is applied with a first voltage Vpp, turning on the cell transistor of the selected memory cell coupled to the selected word line WL sel, such that the cell capacitor of the selected memory cell shares charge with the bit line, and a slight change occurs in the voltage of the bit line BL. The period from t1 to t2 is referred to as the charge sharing stage.

[0100] During this period, a second voltage Vdumwl is applied to at least one dummy word line, turning on the cell transistor of the dummy memory cell coupled to the dummy word line, such that the cell capacitor of the dummy memory cell is connected to the bit line, and the bit line capacitance C of the bit line BL is adjusted BL , thereby increasing the voltage change amount ΔV of the bit line, i.e., increasing the sensing margin.

[0101] During the period from t2 to t3, also referred to as the sense amplification and write-back stage, the power supply node SAP switches to a high power supply voltage Vcc, the power supply node SAN switches to a ground voltage Vss, and the sense amplifier is driven to amplify the voltages on the sense nodes Saa and Sab (i.e., the bit line BL and the complementary bit line BL_n), such that the voltages of the bit line BL and the complementary bit line BL_n respectively reach the logic levels corresponding to data "1" or "0" in order to read out the data. In addition, during this period, the selected word line WL sel is still applied with the first voltage Vpp and thus is in an on state, and the bit line BL can charge the cell capacitor of the selected memory cell to refresh the data in the memory cell.

[0102] In some embodiments, as Figure 12 shown, during this period, the dummy word line is applied with a control turn-off voltage Vwln, turning off the cell transistor of the dummy memory cell, such that the cell capacitor of the dummy memory cell is no longer connected to the bit line. It can be understood that when the sense amplifier starts to amplify the voltage of the bit line after charge sharing, the sensing margin has been utilized, so the cell transistor of the dummy memory cell can be allowed to be turned off during this period.

[0103] After the moment t3, bleq switches to a high level, causing the pre-charge transistors N3, N4 and the balance transistor N5 to turn on, and supplying the pre-charge voltage Veq to the bit line BL and the complementary bit line BL_n again.

[0104] In addition, from time t0 to time t3, the column selection signal cls is always at a low level, causing the column selection transistors N6 and N7 to be in an off state. After time t3, cls can be switched to a high level to transfer the data latched by the sense amplifier to the local data line ldl and then to the data input / output buffer. The column selection signal cls can be obtained based on the column address information in the read command. From time t0 to time t3, a precharge voltage Veq is applied to both the local data line ldl and the differential local data line ldlb.

[0105] In some embodiments, the peripheral circuit is configured to: apply a precharge voltage to the bit line and apply a second voltage to at least one dummy word line during a second period before a first period.

[0106] The second period can be any period before the first period. That is, when applying a precharge voltage to the bit line during any period before the second period, the dummy word line can be turned on to charge or discharge the cell capacitor of the dummy memory cell to the precharge voltage.

[0107] In some embodiments, the second period may include the precharge stage. The second voltage is applied to the dummy word line starting from the first moment of the precharge stage until the end of the charge sharing stage. The first moment can be any moment in the precharge stage excluding the end moment. The second period is from the first moment to the start moment of the charge sharing stage.

[0108] Figure 13 For Figure 11 Another signal timing diagram during the read operation performed by the shown sense amplifier, compared with Figure 12 is different in the voltage application timing of the dummy word line. As Figure 13 shown, in this embodiment, at the first moment t11 after the start of the precharge stage for a period of time, the second voltage Vdumwl is applied to the dummy word line and maintained until the end moment t2 of the charge sharing stage when the application stops. In another embodiment, the second voltage Vdumwl is applied to the dummy word line starting at the same time when the bleq signal switches to a high level.

[0109] In this embodiment, during at least part of the precharge stage, the second voltage is applied to the dummy word line, so that the cell capacitor of the dummy memory cell is connected to the bit line and is charged or discharged to be equal to the bit line voltage. In this way, during the charge sharing stage, the dummy memory cell does not contribute charge to the bit line or share the charge of the bit line, and the accuracy of data reading of the selected memory cell can be avoided from being affected.

[0110] In some embodiments, the peripheral circuit is further configured to:

[0111] amplify the voltage of the bit line after charge sharing during a third period after the second period;

[0112] In a fourth period after the third period, a precharge voltage is applied to the bit line;

[0113] In the third period and the fourth period, a second voltage is applied to at least one of the dummy word lines.

[0114] The third period may be a sense amplification and write-back stage, and the sense amplifier amplifies the voltage of the bit line after charge sharing is performed. In the fourth period, the precharge voltage is reapplied to the bit line. In this embodiment, the second voltage is applied to the dummy word line during the third period and the fourth period until the end of the fourth period.

[0115] Figure 14 For Figure 11 Another signal timing diagram during the read operation performed by the shown sense amplifier, different from Figure 13 in the voltage application timing of the dummy word line. In this embodiment, as Figure 14 shown, a second voltage Vdumwl is applied to the dummy word line starting from the first moment t11 in the precharge stage and is maintained until the second moment t4 after the end of the sense amplification and write-back stage. The fourth period is from the end moment t3 of the sense amplification and write-back stage to the second moment t4. Here, the read operation also includes the fourth period.

[0116] Although the application of the second voltage to the dummy word line can also be stopped during the sense amplification and write-back stage, if the cell transistor of the dummy memory cell is turned off at this time, the voltage of its cell capacitor is equal to the voltage of the bit line after the amplification operation, that is, the stored voltage of the cell capacitor is relatively large. It can be understood that if the cell transistor is to be turned on, then it is required that the difference Vgs between the gate voltage and the second source-drain voltage is greater than the threshold voltage Vth. If the stored voltage of the cell capacitor is relatively large, making the second source-drain voltage of the cell transistor relatively large, then a larger gate voltage, that is, a larger second voltage Vdumwl, is required to turn on the cell transistor. In this embodiment, stopping the application of the second voltage Vdumwl at the second moment t4 after the end of the sense amplification and write-back stage and during the period when the precharge voltage is reapplied to the bit line again can make the stored voltage of the cell capacitor equal to the precharge voltage Veq, and the precharge voltage Veq is less than the voltage of the bit line after the amplification operation, so the second voltage Vdumwl can be reduced, thereby saving power consumption.

[0117] In some embodiments, the read operation stage of the memory cell coupled to the selected word line includes a second period, a first period, a third period, and a fourth period; the peripheral circuit is further configured to:

[0118] In other periods, a second voltage is applied to at least one dummy word line; wherein, the other periods are the periods between the end moment of the fourth period and the start moment of the second period of the next read operation stage.

[0119] In this embodiment, the second period, the first period, the third period, and the fourth period of the read operation, and other periods between adjacent read operations constitute all the periods when the memory is in the powered state. In other words, in this embodiment, when the memory is in the powered state, the second voltage is always applied to the dummy word line.

[0120] Figure 15 For Figure 11 Another signal timing diagram during the read operation performed by the illustrated sense amplifier, different from Figure 14 in the voltage application timing of the dummy word line. In this embodiment, as Figure 15 shown, when the memory is in the powered state, the second voltage Vdumwl is always applied to the dummy word line, so that the dummy word line is always in the open state, and the cell capacitor of the dummy memory cell is always connected to the bit line to provide a fixed capacitance. Then, during the charge sharing stage, the sensing margin of the bit line can be improved. And such a setting can maintain the original read operation steps, eliminating the need to adjust the read operation steps, thereby shortening the product cycle.

[0121] In some embodiments, the second voltage Vdumwl applied to the dummy word line is less than the first voltage Vpp applied to the selected word line. As described above, the larger the storage voltage in the memory cell, the larger the gate voltage required to turn on the cell transistor. The storage voltage of the dummy memory cell is the pre-charge voltage Veq, and the maximum storage voltage of the selected memory cell is VDD. Usually, Veq = VDD / 2. Therefore, the second voltage Vdumwl applied to the dummy word line can be less than the first voltage Vpp applied to the selected word line.

[0122] Figure 16 A circuit schematic diagram of another memory including a sense amplifier provided by an embodiment of the present disclosure. As Figure 11 shown, the sense amplifier 240 includes transistors P1, P2, N1, and N2 in the memory. The sources of transistors P1 and P2 are connected to the power supply node SAP, and the sources of transistors N1 and N2 are connected to the power supply node SAN. The drain of transistor N1, the drain of transistor P1, and the gate of transistor P2 are connected, and the connection point is the sense node Sab. The drain of transistor N2 is connected to the drain of transistor P2 and the gate of transistor P1, and the connection point is the sense node Saa.

[0123] The sense amplifier 240 further includes offset cancellation transistors N8 and N9. The bit line BL is connected to the sense node Sab through the offset cancellation transistor N8, and the complementary bit line BL_n is connected to the sense node Saa through the offset cancellation transistor N9. The gates of the offset cancellation transistors N8 and N9 are controlled by an offset cancellation signal blsa, and when blsa is activated (e.g., at a high level), the offset cancellation transistors N8 and N9 are turned on.

[0124] The sense amplifier further includes isolation transistors N10 and N11. The bit line BL is also connected to the sense node Saa through the isolation transistor N10, and the complementary bit line BL_n is connected to the sense node Sab through the isolation transistor N11. The gates of the isolation transistors N10 and N11 are controlled by an isolation signal blsb, and when blsb is activated (e.g., at a high level), the isolation transistors N10 and N11 are turned on. In addition, the bit line BL is also connected to the gate of the transistor N1, and the complementary bit line BL_n is also connected to the gate of the transistor N2.

[0125] The sense amplifier 240 further includes a precharge transistor N12. The drain of the precharge transistor N12 is connected to the sense node Saa or Sab. The gate is controlled by a precharge signal bleq, and when bleq is activated (e.g., at a high level), the precharge transistor N12 is turned on to provide a precharge voltage Veq to the sense node Saa or Sab.

[0126] The memory further includes a power supply module 290, which is connected to the power supply nodes SAP and SAN and is configured to provide different voltages to the power supply nodes SAP and SAN, such as providing an equalization voltage Vblp, a high power supply voltage Vcc, and a ground voltage Vss.

[0127] In addition, the same as Figure 11 the memory shown, it further includes column selection transistors N6, N7. The column selection transistor N6 connects the bit line Bl and the local data line ldl, and the column selection transistor N7 connects the complementary bit line BL_n and the differential local data line ldlb. Their gates are controlled by a column selection signal cls.

[0128] Exemplarily, the precharge transistors N3, N4, N12, the balance transistor N5, the column selection transistors N6, N7, the offset cancellation transistors N8 and N9, and the isolation transistors N10 and N11 can all be NMOS transistors.

[0129] Figure 17 For Figure 16 the signal timing diagram during the read operation performed by the sense amplifier shown, as Figure 17As shown, during the time period from t0 to t1, i.e., the pre-charging stage, the offset cancellation signal blsa, isolation signal blsb, and pre-charging signal bleq are at high level, turning on the offset cancellation transistors N8 and N9, isolation transistors N10 and N11, and pre-charging transistor N12, pre-charging the bit line BL, complementary bit line BL_n, sense nodes Saa and Sab to the pre-charging voltage Veq. The voltages of the power supply nodes SAP and SAN are both the equalizing voltage Vblp.

[0130] During the pre-charging stage, all normal word lines are applied with the control turn-off voltage Vwln and are in the off state. However, during at least part of the pre-charging stage, at least one dummy word line is applied with the second voltage Vdumwl, such that the cell capacitors of the dummy memory cells coupled to the dummy word line are charged to the pre-charging voltage Veq. Exemplarily, as in Figure 17 Example 1, the second voltage Vdumwl can be applied to the dummy word line at the first moment t11 after a period of time from the start of the pre-charging stage, or the second voltage Vdumwl can also be applied to the dummy word line at the start moment t0 of the pre-charging stage.

[0131] During the time period from t1 to t2, blsa remains at high level to keep the offset cancellation transistors N8 and N9 in the on state, with the gate and drain of transistor N1 connected, and the gate and drain of transistor N2 connected. Bleq switches to low level, turning off the pre-charging transistor N12 and stopping the supply of the pre-charging voltage Veq to the sense nodes Saa or Sab. Blsb switches to low level, turning off the isolation transistors N10 and N11 to prevent the voltages of the sense nodes Saa and Sab from affecting each other. The power supply node SAP switches to the high power supply voltage Vcc, and the power supply node SAN switches to the ground voltage Vss, providing a driving voltage to the sense amplifier. This time period is the offset calibration stage. During this stage, the voltage difference between the sense nodes Saa and Sab (i.e., the bit line BL and the complementary bit line BL_n) is equal to the threshold voltage difference between the two NMOS transistors N1 and N2. The voltage difference between the sense nodes Saa and Sab is used to compensate for the threshold voltage mismatch between the two NMOS transistors N1 and N2 in the subsequent sense amplification stage. Therefore, the voltage difference between the sense nodes Saa and Sab during this stage is also referred to as the compensation voltage.

[0132] During the offset calibration stage, all normal word lines are still applied with the control turn-off voltage Vwln and are in the off state. And as in Figure 17 Example 1, at least one dummy word line is still applied with the second voltage Vdumwl, such that the cell capacitors of the dummy memory cells maintain the same voltage as the bit line.

[0133] In the time period from t2 to t3, that is, the first time period, that is, the charge sharing stage, blsa switches to a low level, the offset cancellation transistors N8 and N9 are turned off, and the sense nodes Saa and Sab store the above compensation voltage. The voltages of the power supply nodes SAP and SAN are restored to the equilibrium voltage Vblp.

[0134] In the charge sharing stage, the selected word line is applied with the first voltage Vpp to turn on the cell transistor of the selected memory cell coupled to the selected word line. The cell capacitor and the bit line perform charge sharing, causing a slight change in the voltage on the bit line BL again, but the voltage on the complementary bit line BL_N remains unchanged.

[0135] In the charge sharing stage, the second voltage Vdumwl is continuously applied to at least one dummy word line, so that the cell capacitor of the dummy memory cell is connected to the bit line to adjust the bit line capacitance C of the bit line BL BL , thereby increasing the voltage change amount of the bit line, that is, increasing the sensing margin.

[0136] In the time period from t3 to t4, that is, the third time period, that is, the sense amplification and write-back stage, the power supply node SAP is gradually pulled up to the high power supply voltage Vcc, the power supply node SAN is gradually pulled down to the ground voltage Vss, and the sense amplifier performs pre-sensing. At the moment of t31, as blsb switches to a high level, the isolation transistors N10 and N11 are turned on, and the voltages on the bit line BL and the complementary bit line BL_n are transmitted to the sense nodes Saa and Sab, and the sense amplifier starts to amplify the voltages on the bit line BL and the complementary bit line BL_n in order to read out the data. In this time period, the selected word line is still applied with the first voltage Vpp, and the bit line BL can write back data to the cell capacitor of the selected memory cell.

[0137] In the sense amplification and write-back stage, since the compensation voltage is stored on the sense nodes Saa and Sab (as well as the bit line BL and the complementary bit line BL_n), the mismatch voltage caused by the threshold voltage mismatch between the two NMOS transistors N1 and N2 in the sense amplifier can be compensated, so that the voltage difference between the bit line BL and the complementary bit line BL_n can truly reflect the data in the selected memory cell, improving the accuracy of the data read by the sense amplifier.

[0138] After the moment of t4, bleq and blsa switch back to a high level again, and the bit line BL and the complementary bit line BL_n are pre-charged to the pre-charge voltage Veq again. The power supply nodes SAP and SAN switch back to the equilibrium voltage Vblp again.

[0139] In the sense amplification and write-back stage (that is, the time period from t4 to t5), the second voltage Vdumwl is continuously applied to the dummy word line until it stops being applied at the moment of t6 after the moment of t5.

[0140] In this embodiment, when the read operation includes an offset cancellation stage, the storage voltage of the cell capacitor of the dummy storage cell can be made the same as the bit line voltage before the offset cancellation stage, so as to reduce the impact on the offset cancellation stage. In this embodiment, a second voltage is applied to the dummy word line starting from the first moment t11 of the pre-charge stage until the moment t6 after the sense amplification and write-back stages end. With such a setting, the second voltage can be a relatively small voltage, thereby saving power consumption.

[0141] In some other embodiments, as Figure 17 shown in Example 2, the second voltage Vdumwl can also be applied to the dummy word line only during the charge sharing stage (i.e., the first time period). In still some other embodiments, the second voltage can be applied to the dummy word line during the offset cancellation stage and the charge sharing stage, or during a partial time period adjacent to the offset cancellation stage in the pre-charge stage, the offset cancellation stage, and the charge sharing stage. In yet some other embodiments, as Figure 17 shown in Example 3, the second voltage Vdumwl can also be applied to the dummy word line all the time when the memory is in the powered state.

[0142] In some embodiments, as Figure 10 shown, the storage cell array includes a plurality of storage blocks, and each sense amplifier is connected to one bit line in each of two storage blocks. Among them, the storage block where the selected word line is located is the first storage block, and the other storage block whose bit line is connected to the same sense amplifier as the bit line of the first storage block is the second storage block. In other words, one bit line in each of the first storage block and the second storage block is connected to the sense amplifier, and the selected word line is one of the multiple word lines in the first storage block;

[0143] The peripheral circuit is configured to: while applying the second voltage to the first dummy word line in the first storage block, apply the second voltage to the second dummy word line in the second storage block.

[0144] The sense amplifier senses the data of the storage cell using two bit lines. To accurately read the data, it is necessary to ensure that the voltages and capacitance values of the two bit lines used are matched with each other. Therefore, in this embodiment, the second voltage is applied to the first dummy word line in the first storage block and the second dummy word line in the second storage block simultaneously, so that the bit line capacitances C of the bit line BL and the complementary bit line BL_n participating in the read operation BL are the same, which can improve the accuracy of the read operation.

[0145] Here, applying the second voltage to the first dummy word line in the first storage block and the second dummy word line in the second storage block simultaneously includes: when the timing of applying the first voltage to the first dummy word line in the first storage block is any one of the above, such as Figure 12 、 Figure 13 、 Figure 14 、Figure 15 and Figure 17 According to the timing shown in Figure 17 , the same second voltage is synchronously applied to the first dummy word line in the first memory block and the second dummy word line in the second memory block.

[0146] In some embodiments, the number of first dummy word lines in the first memory block to which the second voltage is applied is equal to the number of second dummy word lines in the second memory block to which the second voltage is applied. That is, if several dummy word lines are opened in the first memory block, then the same number of dummy word lines are opened in the second memory block.

[0147] In some embodiments, the peripheral circuit is configured to:

[0148] Obtain an active row address;

[0149] According to the active row address, determine the first dummy row address in the first memory block and the second dummy row address in the second memory block; based on the first dummy row address and the second dummy row address, determine the first dummy word line and the second dummy word line;

[0150] Determine a selected word line based on the active row address.

[0151] Exemplarily, the active row address is sent to the memory along with an activate command ACT. When the command decoder of the memory receives the activate command ACT, the address buffer receives and caches the active row address. The active row address may include a bank group address, a bank address, and a row address to be activated. Among them, the bank group address and the bank address can be transmitted to the bank group / bank controller to determine a selected bank, and the row address is transmitted to the row decoder to determine a selected word line from the selected bank.

[0152] In some embodiments, one or more dummy word lines in all memory blocks within a memory bank can be controlled to be opened and turned off simultaneously. Then, based on the bank address, all the dummy row addresses to be activated within the memory bank can be determined, and all the dummy row addresses include the first dummy row address and the second dummy row address. In a specific implementation, during a read operation, at least one dummy word line in each of all memory blocks within the selected memory bank is simultaneously applied with and simultaneously stopped from being applied with the second voltage, and the number of dummy word lines to which the second voltage is applied in different memory blocks is equal, so that the dummy word lines of the first memory block and the second memory block can be opened and turned off simultaneously.

[0153] In some embodiments, one or more dummy word lines of all memory blocks in a bank group may also be controlled to be simultaneously turned on and simultaneously turned off. Then, based on the bank group address, all dummy row addresses to be activated in the bank group can be determined, and the all dummy row addresses include a first dummy row address and a second dummy row address. In other words, one or more dummy word lines in each memory block in the bank group where the read operation is performed are activated (here, the number of activated dummy word lines in different memory blocks is equal) so that the first dummy word line and the second dummy word line are activated.

[0154] In some embodiments, it may also be possible to determine the first dummy row address and the second dummy row address based on the row address. The row address corresponding to any normal word line in the memory block can turn on at least one dummy word line in the memory block and can also turn on at least one dummy word line in the memory block coupled to the same group of sense amplifiers as the memory block. The present disclosure places no limitation on the circuit for implementing this function.

[0155] In some embodiments, as Figure 18 shown, after receiving the row address, the row decoder 220 outputs a row selection signal, and the row selection signal is sent to the word line driver 230 corresponding to the selected word line WL sel, and controls the word line driver 230 corresponding to the selected word line WL sel to output a first voltage. In some embodiments, the input end of the word line driver 230 corresponding to the dummy word line 132 may be connected to the input end of the word line driver 230 corresponding to each normal word line 131 in the memory block, so that when the row decoder 220 sends a row selection signal to the word line driver 230 corresponding to any normal word line 131, the row selection signal is synchronously sent to the word line driver 230 corresponding to the dummy word line 132, so that when any normal word line 131 in the memory block becomes the selected word line and is turned on, the dummy word line 132 can be synchronously turned on.

[0156] In some embodiments, a logic gate circuit 700 is provided at the input end of the word line driver 230 corresponding to the dummy word line 132. A plurality of first input ends In1 of the logic gate circuit 700 are respectively connected to the input ends of the word line drivers 230 corresponding to each normal word line 131 in the memory block, and a first output end Out1 of the logic gate circuit 700 is connected to the word line driver 230 corresponding to the dummy word line 132. The logic gate circuit 700 is configured to control the word line driver 230 corresponding to the dummy word line 132 to generate a second voltage when any one of the first input ends In1 receives a row selection signal.

[0157] The logic gate circuit 700 further includes a second output terminal Out2, which is used to connect to the second input terminal In2 of the logic gate circuit corresponding to the dummy word line in the memory block that is coupled to the same group of sense amplifiers as this memory block. The second output terminal Out2 of the logic gate circuit 700 is used to output a first control signal to the memory block that is coupled to the same group of sense amplifiers as this memory block when any one of the first input In1 terminals receives a row selection signal. When the logic gate circuit 700 receives either the first control signal or the column selection signal, it controls the word line driver 230 to generate a second voltage.

[0158] In some embodiments, the logic gate circuit 700 further includes a third input terminal In3, which is used to receive a second control signal, and the second control signal is used to determine whether to enable this dummy word line. Based on the second control signal corresponding to each dummy word line, it can be determined whether to turn on one or more dummy word lines in the memory block during the first period.

[0159] In some other embodiments, it can also be that one or more dummy word lines of all memory blocks in the memory cell array are controlled to be turned on and off simultaneously. Then, each time the memory performs a read operation, one or more dummy word lines in each memory block are activated (here, the number of activated dummy word lines in different memory blocks is equal), so that the first dummy word line and the second dummy word line are activated.

[0160] It should be understood that in some embodiments, it can also be that when the memory is in a powered state, at least one dummy word line in each memory block of all memory blocks in the memory cell array is always applied with the second voltage. The number of dummy word lines applied with the second voltage in different memory blocks is equal. Such a setting can eliminate the related circuits for voltage control of the dummy word lines, save chip area, and simplify the read operation steps.

[0161] The embodiments provided in the present disclosure are applicable to and not limited to dynamic random access memory (DRAM) and static random access memory (SRAM). Among them, DRAM includes but is not limited to double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR). Double data rate synchronous dynamic random access memory further includes DDR4, DDR5, and DDR6, etc. Low power double data rate synchronous dynamic random access memory further includes LPDDR4, LPDDR5, and LPDDR6, etc.

[0162] The embodiments of the present disclosure further provide a memory system, including: a memory controller and a memory as described in any of the above embodiments; the memory controller is configured to control the memory.

[0163] The following will further describe Figures 19 to 21 the memory and the memory system.

[0164] Figure 19 FIG. shows a schematic block diagram of the composition of an exemplary electronic device according to an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 20 shown, the electronic device 1 may include a host and a memory system 30. The memory system 30 includes a memory controller 20 and one or more memories 10. The host may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host may be configured to send data to the memory 10 or receive data from the memory 10. The memory controller 20 is coupled to the memory 10 and the host and is configured to control the memory 10. The memory controller 20 may manage the data stored in the memory 10 and communicate with the host.

[0165] The memory controller 20 may be configured to control the operations of the memory 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 20 is further configured to process an error correction code (ECC) for data read from or written to the memory 10. The memory controller 20 may also perform any other suitable functions, such as formatting the memory 10.

[0166] In some specific embodiments, the memory controller 20 and one or more memories 10 may be integrated into various types of electronic devices. For example, the memory controller 20 may be integrated into the north bridge of a computer motherboard or directly integrated into a computer CPU, and multiple memories 10 may be integrated into a memory module. That is, the memory system 30 may be implemented and packaged into different types of terminal electronic products.

[0167] The memory controller 20 can send data to the host / receive data from the host, and can send a command CMD and an address ADDR to the memory 10. The memory controller 20 may include a command generator 21, an address generator 22, a device interface 23, and a host interface 24. The host interface 24 can receive a command CMD and an address ADDR from the host. The command generator 21 can generate an access command, etc., by decoding the command CMD received from the host, and can provide the access command to the memory 10 through the device interface 23. The access command may be a signal instructing the memory 10 to write or read data by accessing a row of the memory cell array 100 corresponding to the address ADDR. The address generator 22 in the memory controller 20 can generate a row address and a column address to be accessed in the memory cell array 100 by decoding the address ADDR received from the host interface 24. In addition, the memory 10 can generate an address of a bank to be accessed when the memory cell array 100 includes a plurality of banks.

[0168] In addition, the memory controller 20 can control memory operations such as writing and reading by providing various signals to the memory 10 via the device interface 23. For example, the memory controller 20 can provide a write command to the memory 10. The write command is used to instruct the memory 10 to perform a write operation to store data in the memory 10.

[0169] In some embodiments, the memory 10 may be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. Only DRAM will be described as an example below.

[0170] Figure 20 Schematic diagram of a block diagram of the composition of an exemplary solid state drive (SSD) according to an embodiment of the present disclosure. Here, the SSD can be understood as a kind of the foregoing Figure 19 memory system, and in this example, the DRAM can be used as a buffer memory.

[0171] As Figure 20As shown, the SSD 30a may include an SSD controller 20a, a buffer memory 10a, and a non-volatile memory 40. The SSD controller 20a may provide a physical connection between the host and the SSD 30a. That is, the SSD controller 20a may provide an interface between the host and the SSD 30a in accordance with the bus format of the host. The SSD controller 20a may decode instructions provided from the host. The SSD controller 20a may access the non-volatile memory 40 based on the decoding result. The buffer memory 20a may temporarily store write data provided from the host or data read from the non-volatile memory 40. When the host issues a read request, if the data present in the non-volatile memory 40 is cached, the buffer memory 10a may support a cache function for directly providing the cached data to the host. The data transfer rate through the bus format of the host (e.g., SATA or SAS) is much higher than the data transfer rate of the memory channel of the SSD 30a. That is, when the interface speed of the host is significantly high, the performance degradation due to the speed difference may be minimized by providing a high-capacity buffer memory 10a. Additionally, the buffer memory 10a may store an address mapping table of the non-volatile memory 40. The buffer memory 10a may include, but is not limited to, DRAM. The non-volatile memory 40 is set as the storage medium of the SSD 30a. The non-volatile memory 40 may include, but is not limited to, NAND-type memory.

[0172] Figure 21 Schematic diagram of the composition block diagram of an exemplary memory according to an embodiment of the present disclosure. Here, the memory may be understood as a type of the memory system described above. In this example, DRAM may be used as the storage medium. Figure 19 In the above, the memory system may be understood as a type of the memory system described above. In this example, DRAM may be used as the storage medium.

[0173] As Figure 21 shown, the memory 30b can be easily attached or installed to an electronic device or detached from the electronic device 1 through the illustrated interface. The memory 30b may include a plurality of volatile memories 10b (e.g., DRAM) and a memory controller 20b. The memory module memory 30b may be used to write data, store data, obtain (or read) data, and / or erase data under the control of a controller of a processor of a computer. In some embodiments, the controller memory controller 20b may communicate with DRAM using at least one communication protocol or technical standard commonly associated with, for example, dual in-line memory modules (DIMMs), registered DIMMs (RDIMMs), low-loaded DIMMs (LRDIMMs), unregistered DIMMs (UDIMMs), etc.

[0174] It should be noted that Figure 20 the buffer memory 10a in Figure 21 and the volatile memory 10b in Figure 19An application scenario of the memory 10.

[0175] Embodiments of the present disclosure also provide an operation method for a memory. The memory includes a memory cell array. The memory cell array includes a plurality of memory cells. Bit lines and word lines are coupled to the plurality of memory cells. As Figure 22 shown, the operation method of the memory includes:

[0176] Step S100: In a first period, apply a first voltage to a selected word line among a plurality of word lines to turn on the cell transistors of the memory cells coupled to the selected word line;

[0177] Step S200: In the first period, apply a second voltage to at least one dummy word line among the plurality of word lines to turn on the cell transistors of the memory cells coupled to the at least one dummy word line.

[0178] In some embodiments, in the first period, the cell capacitors of the memory cells coupled to the selected word line and the bit lines perform charge sharing. The cell capacitors of the dummy memory cells coupled to the dummy word lines are used to adjust the bit line capacitance to adjust the sensing margin of the bit lines.

[0179] Exemplarily, the first period may be the charge sharing stage of a read operation.

[0180] In some embodiments, the operation method further includes: in a second period before the first period, apply a precharge voltage to the bit lines and apply a second voltage to at least one dummy word line.

[0181] Exemplarily, the second period may include the precharge stage of a read operation, and the precharge stage is before the charge sharing stage.

[0182] In some embodiments, the operation method further includes: in a third period after the second period, amplify the voltage of the bit lines after charge sharing;

[0183] In a fourth period after the third period, apply a precharge voltage to the bit lines;

[0184] In the third period and the fourth period, apply a second voltage to at least one dummy word line.

[0185] Exemplarily, the third period may be the sense amplification and writeback stage of a read operation.

[0186] In some embodiments, the read operation stage of the memory cells coupled to the selected word line includes the second period, the first period, the third period, and the fourth period; the operation method further includes:

[0187] During other time periods, a second voltage is applied to at least one dummy word line; wherein, the other time periods are the time periods between the end time of the fourth time period and the start time of the second time period of the next read operation phase.

[0188] Here, the second time period, the first time period, the third time period, and the fourth time period of each read operation, as well as the other time periods between adjacent read operations, constitute all the time periods when the memory is in the powered state. In other words, when the memory is in the powered state, a second voltage is always applied to at least one dummy word line.

[0189] In some embodiments, the second voltage is less than the first voltage.

[0190] In some embodiments, the memory cell array includes a plurality of memory blocks, each memory block includes a plurality of memory cells, the plurality of memory blocks include a first memory block and a second memory block, one bit line of the first memory block and the second memory block is connected to the same sense amplifier, and the selected word line is located in the first memory block;

[0191] The operation method further includes: while applying the second voltage to the first dummy word line in the first memory block, applying the second voltage to the second dummy word line in the second memory block.

[0192] In some embodiments, the operation method further includes:

[0193] Obtaining an active row address;

[0194] According to the active row address, determining a first dummy row address in the first memory block and a second dummy row address in the second memory block; determining the first dummy word line and the second dummy word line based on the first dummy row address and the second dummy row address;

[0195] Determining the selected word line based on the active row address.

[0196] In the operation method provided by the embodiments of the present disclosure, during the first time period of the read operation, a first voltage is applied to the selected word line among multiple normal word lines. After turning on the cell transistor of the memory cell coupled to the selected word line, the cell capacitor in the memory cell and the bit line perform charge sharing. At the same time, during the first time period, a second voltage is applied to at least one dummy word line, turning on the cell transistor of the memory cell coupled to the dummy word line, so that the cell capacitor of the memory cell is connected to the bit line, which can adjust the bit line capacitance CBL, such as adjusting the proportion of the fixed capacitance in the bit line capacitance CBL, thereby increasing the sensing margin and not increasing the area of the peripheral circuit.

[0197] Regarding the method in the above embodiments, its specific execution method has been described in detail in the embodiments of the product corresponding to the method, and will not be elaborated here.

[0198] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0199] The features disclosed in several device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0200] As mentioned above, it is only the implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that, Comprising: A memory cell array including a plurality of memory cells; Bit lines coupled to the plurality of memory cells; Word lines coupled to the plurality of memory cells; A peripheral circuit coupled to the bit lines and the word lines, the peripheral circuit being configured to: During a first period, apply a first voltage to a selected word line among the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line; During the first period, apply a second voltage to at least one dummy word line among the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line.

2. The memory according to claim 1, wherein During the first period, a cell capacitor of a memory cell coupled to the selected word line shares charge with the bit line.

3. The memory according to claim 2, wherein The peripheral circuit is configured to: During a second period before the first period, apply a precharge voltage to the bit line and apply the second voltage to at least one of the dummy word lines.

4. The memory according to claim 3, characterized in that, The peripheral circuit is further configured to: During a third period after the second period, amplify the voltage of the bit line after charge sharing is performed; During a fourth period after the third period, apply the precharge voltage to the bit line; During the third period and the fourth period, apply the second voltage to at least one of the dummy word lines.

5. The memory according to claim 4, characterized in that, A read operation stage for a memory cell coupled to the selected word line includes the second period, the first period, the third period, and the fourth period; The peripheral circuit is further configured to: During other periods, apply the second voltage to at least one of the dummy word lines; wherein, the other periods are periods between the end moment of the fourth period and the start moment of the second period of the next read operation stage.

6. The memory according to any one of claims 1 to 5, characterized in that, The memory cell array includes a plurality of memory blocks, each memory block including the plurality of memory cells; the plurality of memory blocks include a first memory block and a second memory block, and one bit line of each of the first memory block and the second memory block is connected to the same sense amplifier; The peripheral circuit is configured to: While applying the second voltage to a first dummy word line in the first memory block, apply the second voltage to a second dummy word line in the second memory block.

7. The memory according to claim 6, wherein The peripheral circuit is configured to: Obtain an active row address; According to the active row address, determine a first dummy row address in the first memory block and a second dummy row address in the second memory block; Based on the first dummy row address and the second dummy row address, determine the first dummy word line and the second dummy word line; Based on the active row address, determine the selected word line.

8. The memory according to claim 1, wherein The second voltage is less than the first voltage.

9. The memory according to claim 1, characterized in that, The word lines include the dummy word lines and normal word lines, and the selected word line is any one of the normal word lines; wherein: The dummy word lines are located on both sides of the plurality of normal word lines; or, the dummy word lines are located between any two adjacent normal word lines.

10. A memory system, characterized in that, The memory system includes: One or more memories as described in claims 1 to 9; A memory controller coupled to the memory and configured to control the memory.

11. A method for operating a memory, characterized in that, The memory includes a memory cell array, the memory cell array includes a plurality of memory cells, bit lines and word lines are coupled to the plurality of memory cells; the operation method includes: In a first period, a first voltage is applied to a selected word line among the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line; In the first period, a second voltage is applied to at least one dummy word line among the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line.

12. The method for operating a memory according to claim 11, wherein In the first period, a cell capacitor of a memory cell coupled to the selected word line and the bit line perform charge sharing.

13. The method for operating a memory according to claim 12, characterized in that, The method further includes: In a second period before the first period, a precharge voltage is applied to the bit line, and a second voltage is applied to at least one dummy word line.

14. The method for operating a memory according to claim 13, wherein The method further includes: In a third period after the second period, the voltage of the bit line after charge sharing is amplified; In a fourth period after the third period, the precharge voltage is applied to the bit line; In the third period and the fourth period, the second voltage is applied to at least one dummy word line.

15. The method for operating a memory according to claim 14, characterized in that, The read operation stage of the memory cell coupled to the selected word line includes the second period, the first period, the third period and the fourth period; The operation method further includes: In other periods, the second voltage is applied to at least one dummy word line; wherein, the other periods are the periods between the end of the fourth period and the start of the second period of the next read operation stage.

16. The method for operating a memory according to any one of claims 11 to 15, characterized in that, The memory cell array includes a plurality of memory blocks, each memory block includes the plurality of memory cells, the plurality of memory blocks include a first memory block and a second memory block, and one bit line of the first memory block and the second memory block is connected to the same sense amplifier; The operation method further includes: While applying the second voltage to a first dummy word line in the first memory block, the second voltage is applied to a second dummy word line in the second memory block.

17. The method for operating a memory according to claim 16, wherein, The method further includes: Obtaining an active row address; According to the active row address, determining a first dummy row address in the first memory block and a second dummy row address in the second memory block; Based on the first dummy row address and the second dummy row address, determining the first dummy word line and the second dummy word line; Based on the active row address, determining the selected word line.

18. The method for operating a memory according to claim 11, characterized in that, The second voltage is less than the first voltage.

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