Low-power-consumption EEPROM storage circuit based on controllable clock and control method thereof

Abstract

The invention discloses a low-power-consumption EEPROM (Electrically Erasable Programmable Read-Only Memory) storage circuit based on a controllable clock and a control method thereof, the circuit comprises an oscillator current selection circuit, an oscillation starting circuit and a frequency dividing circuit, the output end of the oscillator current selection circuit is connected with the input end of the oscillation starting circuit, and the output end of the oscillation starting circuit is connected with the input end of the frequency dividing circuit. The method comprises the following steps: dynamically adjusting the reference current according to a control signal, and outputting a control current signal; generating a clock signal frequency according to the control current signal; and performing frequency division output according to the clock signal frequency to generate a charge pump clock signal. According to the embodiment of the invention, the most suitable clock can be selected according to the amount of the input data, and the power consumption of the EEPROM during working is reduced. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a low-power EEPROM storage circuit based on a controllable clock and its control method. Background Art

[0002] As a non-volatile memory, EEPROM can maintain stability for a long time after data is written. Even when the system is powered off, the data can still remain unchanged. This characteristic makes it widely used in scenarios that require permanent data storage, such as configuration parameter storage in embedded systems, industrial automation equipment, and automotive electronic systems. However, when writing data to EEPROM, it is necessary to achieve programming of the storage unit through electron migration, which inevitably leads to significant power consumption. Especially during data writing, EEPROM requires a relatively high voltage and current, resulting in higher power consumption and heat. If these heats are not effectively managed, it may cause local overheating of the device, thereby affecting the stability of system performance and shortening the service life of the memory and the entire system. In addition, the read and write operations of EEPROM depend on the system clock frequency and instruction cycle, which means that the configuration of the system clock directly affects its performance and energy consumption efficiency. At high clock frequencies, although the data access speed is increased, the power consumption will also increase significantly, thus having a negative impact on the overall energy efficiency ratio.

[0003] In summary, the technical problems existing in the related art need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose a low-power EEPROM storage circuit based on a controllable clock and its control method, which can select the most suitable clock according to the amount of input data, reducing the power consumption when EEPROM works.

[0005] To achieve the above object, on the one hand, an embodiment of this application proposes a low-power EEPROM storage circuit based on a controllable clock. The circuit includes an oscillator current selection circuit, an oscillation starting circuit, and a frequency division circuit. The output end of the oscillator current selection circuit is connected to the input end of the oscillation starting circuit, and the output end of the oscillation starting circuit is connected to the input end of the frequency division circuit, where:

[0006] The oscillator current selection circuit is used to dynamically adjust the magnitude of the reference current according to the control signal and output a control current signal;

[0007] The oscillation starting circuit is used to generate a clock signal frequency according to the control current signal;

[0008] The frequency division circuit is used to perform frequency division output according to the clock signal frequency and generate a charge pump clock signal.

[0009] In some embodiments, the oscillator current selection circuit includes a reference current input module, a control signal module, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first current mirror module, a second current mirror module, a third current mirror module, a fourth current mirror module, a fifth current mirror module, a sixth current mirror module, a seventh current mirror module, an eighth current mirror module, a ninth current mirror module, and a thirty-first MOS transistor. The negative input terminal of the reference current input module is connected to the gate of the third MOS transistor and receives a first external control signal SHDN. The positive input terminal of the reference current input module is connected to a second external control signal SHDNN. The output terminal of the reference current input module is connected to the drain of the first MOS transistor. The gate of the first MOS transistor is connected to a bias voltage signal. The source of the first MOS transistor is connected to the drain of the second MOS transistor. The source of the second MOS transistor is connected to a high level. The gates of the second MOS transistor, the drain of the third MOS transistor, the gate of the fourth MOS transistor, the input terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module are connected. The source of the third MOS transistor is connected to a high level. The source of the fourth MOS transistor is connected to the drain of the fourth MOS transistor and is connected to a high level. The output terminals of the control signal module are all connected to the signal input terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module. The first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module are connected in sequence. The source of the thirty-first MOS transistor is connected to the output terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module. The gate of the thirty-first MOS transistor is connected to a bias voltage signal.

[0010] In some embodiments, the first current mirror module includes a fifth MOS transistor, the second current mirror module includes a sixth MOS transistor and a seventh MOS transistor, the third current mirror module includes an eighth MOS transistor and a ninth MOS transistor, the fourth current mirror module includes a tenth MOS transistor and an eleventh MOS transistor, the fifth current mirror module includes a twelfth MOS transistor and a thirteenth MOS transistor, the sixth current mirror module includes a fourteenth MOS transistor, a fifteenth MOS transistor and a sixteenth MOS transistor, the seventh current mirror module includes a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor and a twenty-first MOS transistor, the eighth current mirror module includes a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, a twenty-eighth MOS transistor, a twenty-ninth MOS transistor and a thirtieth MOS transistor, the ninth current mirror module includes a thirty-second MOS transistor, a thirty-third MOS transistor, a thirty-fourth MOS transistor, a thirty-fifth MOS transistor, a thirty-sixth MOS transistor, a thirty-seventh MOS transistor, a thirty-eighth MOS transistor, a thirty-ninth MOS transistor, a fortieth MOS transistor, a forty-first MOS transistor, a forty-second MOS transistor, a forty-third MOS transistor, a forty-fourth MOS transistor, a forty-fifth MOS transistor, a forty-sixth MOS transistor, a forty-seventh MOS transistor and a forty-eighth MOS transistor. The drain of the fifth MOS transistor, the gates of the sixth MOS transistor, the eighth MOS transistor, the tenth MOS transistor, the twelfth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor and the twentieth MOS transistor are connected. The gates of the twenty-second MOS transistor, the twenty-third MOS transistor, the twenty-fourth MOS transistor, the twenty-fifth MOS transistor, the twenty-sixth MOS transistor, the twenty-seventh MOS transistor, the twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirty-second MOS transistor, the thirty-third MOS transistor, the thirty-fourth MOS transistor, the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-seventh MOS transistor, the thirty-eighth MOS transistor, the thirty-ninth MOS transistor, the fortieth MOS transistor, the forty-first MOS transistor, the forty-second MOS transistor, the forty-third MOS transistor, the forty-fourth MOS transistor, the forty-fifth MOS transistor, the forty-sixth MOS transistor and the forty-seventh MOS transistor are connected.The sources of the fifth MOS transistor, the seventh MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the sixteenth MOS transistor, the twenty-first MOS transistor, the thirtieth MOS transistor, and the forty-eighth MOS transistor are all connected to a high level. The gates of the seventh MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the sixteenth MOS transistor, the twenty-first MOS transistor, the thirtieth MOS transistor, and the forty-eighth MOS transistor are all connected to the control signal module. The source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor. The source of the eighth MOS transistor is connected to the drain of the ninth MOS transistor. The source of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor. The source of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor. The source of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor. The source of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor. The source of the seventeenth MOS transistor is connected to the drain of the eighteenth MOS transistor. The source of the eighteenth MOS transistor is connected to the drain of the nineteenth MOS transistor. The source of the nineteenth MOS transistor is connected to the drain of the twentieth MOS transistor. The source of the twentieth MOS transistor is connected to the drain of the twenty-first MOS transistor. The source of the twenty-second MOS transistor is connected to the drain of the twenty-third MOS transistor. The source of the twenty-third MOS transistor is connected to the drain of the twenty-fourth MOS transistor. The source of the twenty-fourth MOS transistor is connected to the drain of the twenty-fifth MOS transistor. The source of the twenty-fifth MOS transistor is connected to the drain of the twenty-sixth MOS transistor. The source of the twenty-sixth MOS transistor is connected to the drain of the twenty-seventh MOS transistor. The source of the twenty-seventh MOS transistor is connected to the drain of the twenty-eighth MOS transistor. The source of the twenty-eighth MOS transistor is connected to the drain of the twenty-ninth MOS transistor. The source of the twenty-ninth MOS transistor is connected to the drain of the thirtieth MOS transistor. The source of the thirty-second MOS transistor is connected to the drain of the thirty-third MOS transistor. The source of the thirty-third MOS transistor is connected to the drain of the thirty-fourth MOS transistor. The source of the thirty-fourth MOS transistor is connected to the drain of the thirty-fifth MOS transistor. The source of the thirty-fifth MOS transistor is connected to the drain of the thirty-sixth MOS transistor. The source of the thirty-sixth MOS transistor is connected to the drain of the thirty-seventh MOS transistor. The source of the thirty-seventh MOS transistor is connected to the drain of the thirty-eighth MOS transistor. The source of the thirty-eighth MOS transistor is connected to the drain of the thirty-ninth MOS transistor. The source of the thirty-ninth MOS transistor is connected to the drain of the fortieth MOS transistor,The source electrode of the fortieth MOS transistor is connected to the drain electrode of the forty-first MOS transistor, the source electrode of the forty-first MOS transistor is connected to the drain electrode of the forty-second MOS transistor, the source electrode of the forty-second MOS transistor is connected to the drain electrode of the forty-third MOS transistor, the source electrode of the forty-third MOS transistor is connected to the drain electrode of the forty-fourth MOS transistor, the source electrode of the forty-fourth MOS transistor is connected to the drain electrode of the forty-fifth MOS transistor, the source electrode of the forty-fifth MOS transistor is connected to the drain electrode of the forty-sixth MOS transistor, the source electrode of the forty-sixth MOS transistor is connected to the drain electrode of the forty-seventh MOS transistor, and the source electrode of the forty-seventh MOS transistor is connected to the drain electrode of the forty-eighth MOS transistor.

[0011] In some embodiments, the starting circuit includes the fifty-third MOS transistor, the fifty-fourth MOS transistor, the fifty-fifth MOS transistor, the fifty-sixth MOS transistor, the fifty-seventh MOS transistor, the fifty-eighth MOS transistor, the fifty-ninth MOS transistor, the sixtieth MOS transistor, the sixty-first MOS transistor, the sixty-second MOS transistor, the sixty-third MOS transistor, the sixty-fourth MOS transistor, the sixty-fifth MOS transistor, the sixty-sixth MOS transistor, the sixty-seventh MOS transistor, the second capacitor, the third capacitor, the fourth capacitor, the third inverter, and the fourth inverter. Among them, the gates of the fifty-third MOS transistor, the fifty-fourth MOS transistor, the fifty-ninth MOS transistor, and the sixtieth MOS transistor are connected; the drain of the fifty-third MOS transistor is connected to the source of the fifty-fourth MOS transistor; the drain of the fifty-fourth MOS transistor, the source of the fifty-fifth MOS transistor, the gate of the fifty-fifth MOS transistor, the gates of the fifty-sixth MOS transistor, the fifty-seventh MOS transistor, the fifty-eighth MOS transistor, the drain of the sixty-third MOS transistor, the gate of the sixty-fourth MOS transistor, and the gate of the sixty-fifth MOS transistor are connected; the drain of the fifty-fifth MOS transistor is connected to the source of the fifty-sixth MOS transistor; the drain of the fifty-sixth MOS transistor is connected to the source of the fifty-seventh MOS transistor; the drain of the fifty-seventh MOS transistor is connected to the source of the fifty-eighth MOS transistor; the drain of the fifty-ninth MOS transistor, the drain of the sixty-first MOS transistor, the gate of the sixty-second MOS transistor, and the first end of the second capacitor are connected; the gate of the sixty-first MOS transistor, the input terminal of the third inverter, the first end of the fourth capacitor, the drain of the sixty-seventh MOS transistor, and the drain of the sixty-five MOS transistor are connected; the source of the sixty-fourth MOS transistor is connected to its drain and connected to a high level; the drain of the sixtieth MOS transistor, the drain of the sixty-second MOS transistor, the drain of the sixty-sixth MOS transistor, the first end of the third capacitor, and the gate of the sixty-seventh MOS transistor are connected; the output terminal of the third inverter is connected to the input terminal of the fourth inverter; the drains of the fifty-eighth MOS transistor, the source of the sixty-third MOS transistor, the sources of the sixty-fifth MOS transistor, the sixty-first MOS transistor, the sixty-second MOS transistor, the sixty-sixth MOS transistor, the second end of the second capacitor, the second end of the third capacitor, and the second end of the fourth capacitor are all connected to a high level; the sources of the fifty-third MOS transistor, the fifty-ninth MOS transistor, the sixtieth MOS transistor, and the sixty-seventh MOS transistor are all connected to the power supply voltage; the gates of the sixty-third MOS transistor and the sixty-sixth MOS transistor are both connected to the first external control signal SHDN.

[0012] In some embodiments, the frequency division circuit includes a decoder, a divide-by-two module, a divide-by-four module, and a multiplexer. A first output terminal of the decoder is connected to a first input terminal of the multiplexer. An output terminal of the divide-by-two module is connected to a second input terminal of the multiplexer. An output terminal of the divide-by-four module is connected to a third input terminal of the multiplexer. A second output terminal of the decoder is connected to an input terminal of the divide-by-two module. A third output terminal of the decoder is connected to an input terminal of the divide-by-four module. The divide-by-two module and the divide-by-four module are connected in cascade, where:

[0013] The decoder is configured to convert a control signal into a selection signal;

[0014] The divide-by-two module is configured to output a divide-by-two charge pump clock signal according to the frequency of the clock signal;

[0015] The divide-by-four module is configured to output a divide-by-four charge pump clock signal according to the frequency of the clock signal;

[0016] The multiplexer is configured to select and output the divide-by-two charge pump clock signal or the divide-by-four charge pump clock signal according to the selection signal.

[0017] In some embodiments, the divide-by-two module includes a first inverter, a first NAND gate, a first AND gate, a second AND gate, a second NOR gate, a second NAND gate, a third NAND gate, a first OR gate, and a fourth NAND gate. An input terminal of the first inverter is connected to the decoder. An output terminal of the first inverter, a first input terminal of the first NAND gate, and a first input terminal of the second NAND gate are connected. A second input terminal of the first NAND gate, a second input terminal of the third NAND gate, and an output terminal of the second NOR gate are connected. An output terminal of the first NAND gate is connected to a second input terminal of the first AND gate. A first input terminal of the first AND gate, a first input terminal of the third NAND gate, and the divide-by-four module are connected. An output terminal of the first AND gate is connected to a first input terminal of the second NOR gate. An output terminal of the second AND gate is connected to a second input terminal of the second NOR gate. A first input terminal of the second AND gate, an output terminal of the third NAND gate, and a second input terminal of the fourth NAND gate are connected. A second terminal of the second AND gate, a second input terminal of the second NAND gate, and an output terminal of the fourth NAND gate are connected. An output terminal of the second NAND gate, a first input terminal of the first OR gate, and the divide-by-four module are connected. A second input terminal of the first OR gate is connected to the divide-by-four module. An output terminal of the first OR gate is connected to a first input terminal of the fourth NAND gate.

[0018] In some embodiments, the quadruple-frequency module includes a sixth NAND gate, a third AND gate, a fourth AND gate, a fourth NOR gate, a seventh NAND gate, an eighth NAND gate, a second OR gate, and a ninth NAND gate. Among them, the first input terminal of the sixth NAND gate and the first input terminal of the seventh NAND gate are connected to the decoder. The second input terminal of the sixth NAND gate, the second terminal of the eighth NAND gate, and the second input terminal of the eighth NAND gate are connected to the output terminal of the fourth NOR gate. The output terminal of the sixth NAND gate is connected to the second input terminal of the third AND gate. The first input terminal of the third AND gate, the first input terminal of the eighth NAND gate, and the second input terminal of the second OR gate are connected to the frequency division module. The output terminal of the third AND gate is connected to the first input terminal of the fourth NOR gate. The output terminal of the fourth AND gate is connected to the second input terminal of the fourth NOR gate. The first input terminal of the fourth AND gate and the output terminal of the eighth NAND gate are connected to the second input terminal of the ninth NAND gate. The second input terminal of the fourth AND gate and the second input terminal of the seventh NAND gate are connected to the output terminal of the ninth NAND gate. The output terminal of the seventh NAND gate and the first input terminal of the second OR gate are connected to the multiplexer. The output terminal of the second OR gate is connected to the first input terminal of the ninth NAND gate.

[0019] To achieve the above object, on the other hand, an embodiment of the present application proposes a control method for a low-power EEPROM storage circuit based on a controllable clock. The method includes the following steps:

[0020] Dynamically adjust the magnitude of the reference current according to the control signal and output a control current signal;

[0021] Generate a clock signal frequency according to the control current signal;

[0022] Perform frequency division output according to the clock signal frequency to generate a charge pump clock signal.

[0023] In some embodiments, it further includes controlling the turn-on and turn-off of each stage of the current mirror through the control signal, and then outputting the control current signal.

[0024] In some embodiments, the performing frequency division output according to the clock signal frequency to generate a charge pump clock signal includes:

[0025] Convert the control signal into a selection signal;

[0026] Output a divided-by-two charge pump clock signal and a divided-by-four charge pump clock signal according to the clock signal frequency;

[0027] Combine the selection signal to select and output the divided-by-two charge pump clock signal or the divided-by-four charge pump clock signal to generate the charge pump clock signal.

[0028] The embodiments of the present application include at least the following beneficial effects: The present application provides a low-power EEPROM storage circuit based on a controllable clock and a control method thereof. The scheme dynamically adjusts the size of the reference current according to the control signal and outputs a control current signal. According to the number of "1"s in the written data, it dynamically adjusts the current output to the oscillator, and then selects a suitable and minimum current to generate a clock through the oscillator circuit, and then generates a clock signal frequency according to the control current signal. The current matching the current written into the bitecell is given by the current selection circuit to generate a suitable clock, and finally the clock signal frequency is divided and output according to the clock signal frequency. The original frequency is used during the operation of the charge pump. When the output voltage of the charge pump is stable, it is divided into two or four, which further reduces the operating power consumption, so that the EEPROM can select the most suitable clock according to the amount of input data and select the clock with the lowest power consumption as much as possible. At the same time, the power consumption of the EEPROM during operation is further reduced by the frequency division selection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of a low-power EEPROM storage circuit based on a controllable clock provided in an embodiment of the present application;

[0030] Figure 2 It is a schematic flow chart of the steps of a control method of a low-power EEPROM storage circuit based on a controllable clock provided in an embodiment of the present application;

[0031] Figure 3 is a schematic diagram of the principle of an oscillator current selection circuit provided in an embodiment of the present application;

[0032] Figure 4 is a schematic diagram of the principle of an oscillator circuit provided in an embodiment of the present application;

[0033] Figure 5 is a schematic diagram of the principle of the frequency division circuit provided in the embodiment of the present application;

[0034] Figure 6 It is a schematic diagram of the principle of the frequency division selection circuit provided in the embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0036] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0037] The terms "at least one", "a plurality of", "each", "any one", etc. used in the present application, at least one includes one, two or more than two, a plurality includes two or more than two, each refers to each of the corresponding plurality, and any one refers to any one of the plurality.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0039] In the related art, the write operation of the EEPROM involves the control of electron migration in the storage unit. Specifically, the write operation changes the number of electrons in the floating gate by applying a high voltage to the floating gate capacitor, thereby adjusting the threshold voltage of the storage unit. After applying the programming voltage, electrons enter the floating gate region through the tunneling effect, which changes the threshold voltage of the storage unit and completes the data writing. Although this process realizes the permanent storage of data, due to the involvement of high voltage and high current, the energy consumption is relatively large, and it will generate stress on the physical structure of the memory, which may lead to device aging and reduced reliability. The write operation time is relatively long, and each erase and write operation will cause cumulative loss to the storage unit, ultimately resulting in performance degradation of the memory after multiple writes.

[0040] In view of this, in the embodiments of the present application, a low-power EEPROM storage circuit based on a controllable clock is provided. By means of the controllable clock to reduce the circuit power consumption, the most suitable charge pump clock frequency is selected according to the number of "1"s to be written into the bitcell in the EEPROM, so as to reduce the power consumption when the charge pump works, and further reduce the power consumption of the EEPROM. The solution includes: an oscillator current selection circuit, which is used to control the magnitude of the input current, and then select a suitable and minimum current to generate a clock through the oscillator circuit; a startup circuit, which generates a suitable clock by using the current that matches the written bitecell given by the current selection circuit; a frequency division circuit, which divides the clock generated by the oscillator by two or four and then selects the divided clock for output; a frequency division selection circuit, which uses the original frequency during the operation of the charge pump and changes to two or four frequency division when the output voltage of the charge pump is stable, further reducing the operating power consumption. The embodiments of the present invention enable the EEPROM to select the most suitable clock according to the amount of input data, select the clock with the lowest power consumption as much as possible, and at the same time further reduce the power consumption of the EEPROM during operation through the frequency division selection circuit.

[0041] Referring to Figure 1 , Figure 1 is a flowchart of a low-power EEPROM storage circuit based on a controllable clock provided by the embodiments of the present invention. Referring to Figure 1 , the circuit includes an oscillator current selection circuit, a startup circuit and a frequency division circuit. The output end of the oscillator current selection circuit is connected to the input end of the startup circuit, and the output end of the startup circuit is connected to the input end of the frequency division circuit, where:

[0042] The oscillator current selection circuit is used to dynamically adjust the magnitude of the reference current according to the control signal and output a control current signal;

[0043] In this embodiment, the oscillator selection circuit dynamically adjusts the current output to the oscillator according to the number of "1"s in the written data. The external write "1" signal is directly used as the control signals CTRL<0>-CTRL<7> to control the turn-on and turn-off of each stage of current mirror (RANK0-RANK8), and then control the current input to the startup circuit. That is, the oscillator current selection circuit selects a suitable current to drive the oscillator to generate the required lowest clock frequency according to the amount of written data and applies it to the charge pump; the frequency division selection circuit further reduces the clock frequency when the charge pump reaches the highest voltage to reduce the power consumption.

[0044] Specifically, as Figure 3As shown, the oscillator current selection circuit includes a reference current input module, a control signal module, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a first current mirror module, a second current mirror module, a third current mirror module, a fourth current mirror module, a fifth current mirror module, a sixth current mirror module, a seventh current mirror module, an eighth current mirror module, a ninth current mirror module, and a thirty-first MOS transistor. The negative input terminal of the reference current input module is connected to the gate of the third MOS transistor and receives a first external control signal SHDN. The positive input terminal of the reference current input module is connected to a second external control signal SHDNN. The output terminal of the reference current input module is connected to the drain of the first MOS transistor. The gate of the first MOS transistor is connected to a bias voltage signal. The source of the first MOS transistor is connected to the drain of the second MOS transistor. The source of the second MOS transistor is connected to a high level. The gates of the second MOS transistor, the drain of the third MOS transistor, the gate of the fourth MOS transistor, the input terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module are connected. The source of the third MOS transistor is connected to a high level. The source of the fourth MOS transistor is connected to its drain and is connected to a high level. The output terminals of the control signal module are all connected to the signal input terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module. The first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module are connected in sequence. The source of the thirty-first MOS transistor is connected to the output terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module. The gate of the thirty-first MOS transistor is connected to a bias voltage signal.

[0045] More specifically, as Figure 3As shown, the first current mirror module includes the fifth MOS transistor M5, the second current mirror module includes the sixth MOS transistor M6 and the seventh MOS transistor M7, the third current mirror module includes the eighth MOS transistor M8 and the ninth MOS transistor M9, the fourth current mirror module includes the tenth MOS transistor M10 and the eleventh MOS transistor M11, the fifth current mirror module includes the twelfth MOS transistor M12 and the thirteenth MOS transistor M13, the sixth current mirror module includes the fourteenth MOS transistor M14, the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16, the seventh current mirror module includes the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20 and the twenty-first MOS transistor M21, the eighth current mirror module includes the twenty-second MOS transistor M22, the twenty-third MOS transistor M23, the twenty-fourth MOS transistor M24, the twenty-fifth MOS transistor M25, the twenty-sixth MOS transistor M26, the twenty-seventh MOS transistor M27, the twenty-eighth MOS transistor M28, the twenty-ninth MOS transistor M29 and the thirtieth MOS transistor M30, the ninth current mirror module includes the thirty-second MOS transistor M32, the thirty-third MOS transistor M33, the thirty-fourth MOS transistor M34, the thirty-fifth MOS transistor M35, the thirty-sixth MOS transistor M36, the thirty-seventh MOS transistor M37, the thirty-eighth MOS transistor M38, the thirty-ninth MOS transistor M39, the fortieth MOS transistor M40, the forty-first MOS transistor M41, the forty-second MOS transistor M42, the forty-third MOS transistor M43, the forty-fourth MOS transistor M44, the forty-fifth MOS transistor M45, the forty-sixth MOS transistor M46, the forty-seventh MOS transistor M47 and the forty-eighth MOS transistor M48. The drain of the fifth MOS transistor, the gate of the sixth MOS transistor, the gate of the eighth MOS transistor, the gate of the tenth MOS transistor, the gate of the twelfth MOS transistor, the gate of the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, the gate of the seventeenth MOS transistor, the gate of the eighteenth MOS transistor, the gate of the nineteenth MOS transistor, and the gate of the twentieth MOS transistor are connected. The gates of the twenty-second MOS transistor, the twenty-third MOS transistor, the twenty-fourth MOS transistor, the twenty-fifth MOS transistor, the twenty-sixth MOS transistor, the twenty-seventh MOS transistor, the twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirty-second MOS transistor, the thirty-third MOS transistor, the thirty-fourth MOS transistor, the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-seventh MOS transistor, the thirty-eighth MOS transistor, the thirty-ninth MOS transistor, the fortieth MOS transistor, the forty-first MOS transistor, the forty-second MOS transistor, the forty-third MOS transistor, the forty-fourth MOS transistor, the forty-fifth MOS transistor, the forty-sixth MOS transistor, and the forty-seventh MOS transistor are connected.The sources of the fifth MOS transistor, the seventh MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the sixteenth MOS transistor, the twenty-first MOS transistor, the thirtieth MOS transistor, and the forty-eighth MOS transistor are all connected to a high level. The gates of the seventh MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the sixteenth MOS transistor, the twenty-first MOS transistor, the thirtieth MOS transistor, and the forty-eighth MOS transistor are all connected to the control signal module. The source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor. The source of the eighth MOS transistor is connected to the drain of the ninth MOS transistor. The source of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor. The source of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor. The source of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor. The source of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor. The source of the seventeenth MOS transistor is connected to the drain of the eighteenth MOS transistor. The source of the eighteenth MOS transistor is connected to the drain of the nineteenth MOS transistor. The source of the nineteenth MOS transistor is connected to the drain of the twentieth MOS transistor. The source of the twentieth MOS transistor is connected to the drain of the twenty-first MOS transistor. The source of the twenty-second MOS transistor is connected to the drain of the twenty-third MOS transistor. The source of the twenty-third MOS transistor is connected to the drain of the twenty-fourth MOS transistor. The source of the twenty-fourth MOS transistor is connected to the drain of the twenty-fifth MOS transistor. The source of the twenty-fifth MOS transistor is connected to the drain of the twenty-sixth MOS transistor. The source of the twenty-sixth MOS transistor is connected to the drain of the twenty-seventh MOS transistor. The source of the twenty-seventh MOS transistor is connected to the drain of the twenty-eighth MOS transistor. The source of the twenty-eighth MOS transistor is connected to the drain of the twenty-ninth MOS transistor. The source of the twenty-ninth MOS transistor is connected to the drain of the thirtieth MOS transistor. The source of the thirty-second MOS transistor is connected to the drain of the thirty-third MOS transistor. The source of the thirty-third MOS transistor is connected to the drain of the thirty-fourth MOS transistor. The source of the thirty-fourth MOS transistor is connected to the drain of the thirty-fifth MOS transistor. The source of the thirty-fifth MOS transistor is connected to the drain of the thirty-sixth MOS transistor. The source of the thirty-sixth MOS transistor is connected to the drain of the thirty-seventh MOS transistor. The source of the thirty-seventh MOS transistor is connected to the drain of the thirty-eighth MOS transistor. The source of the thirty-eighth MOS transistor is connected to the drain of the thirty-ninth MOS transistor. The source of the thirty-ninth MOS transistor is connected to the drain of the fortieth MOS transistor. The source of the fortieth MOS transistor is connected to the drain of the forty-first MOS transistor. The source of the forty-first MOS transistor is connected to the drain of the forty-second MOS transistor. The source of the forty-second MOS transistor is connected to the drain of the forty-third MOS transistor. The source of the forty-third MOS transistor is connected to the drain of the forty-fourth MOS transistor. The source of the forty-fourth MOS transistor is connected to the drain of the forty-fifth MOS transistor,The source electrode of the forty-fifth MOS transistor is connected to the drain electrode of the forty-sixth MOS transistor, the source electrode of the forty-sixth MOS transistor is connected to the drain electrode of the forty-seventh MOS transistor, and the source electrode of the forty-seventh MOS transistor is connected to the drain electrode of the forty-eighth MOS transistor.

[0046] In summary, the oscillator current selection circuit controls different numbers of current mirrors (including the RANK0 current mirror to the RANK8 current mirror) through external control signals (such as CTL<0> to CTL<7>). For each stage of the current mirror (except that RANK0 represents all-0 writing), through the gate connections of all MOS transistors in each stage of the current mirror, the output clock frequency of the oscillator is made to match the amount of data written, thereby minimizing power consumption to the greatest extent while meeting the writing requirements. The oscillator current selection circuit includes a reference current input module I BN4_REF, which controls the flow of the reference current through the switching transistor M1. The switching transistor M1 decides whether to conduct the reference current to the subsequent current mirror under the action of the external control signal SHDN. The current mirror module includes multiple MOS transistors, such as M2, M5, M6, M8, M10, M12, etc. These MOS transistors respectively correspond to different current mirrors from RANK0 to RANK8, and their on states are controlled by the external control signals CTL<0> to CTL<7>, determining the amount of current flowing through each current mirror. The control signal module controls the gates of each stage of MOS transistors (M7, M9, M11, M13, M15, M17, M19, M21, M23, M25, M27, M29, M31, M33, M35, M37, M39, M41, M43, M45, M47, etc.) through CTL<0> to CTL<7>, enabling different current mirror branches to be turned on or off as needed, forming different current paths to match the clock frequency required by the oscillator. Finally, through the cascading of the MOS transistors from M22 to M48, OSC2_I BP is adjusted and output, provided to the oscillator driving module. The MOS transistor M31 is used to ensure that the currents of all branches converge consistently, and its operating state is controlled by the bias voltage G_VBN to ensure the stability and efficiency of the entire current selection circuit.

[0047] The startup circuit is used to generate a clock signal frequency according to the control current signal;

[0048] In this embodiment, the startup circuit is used to generate a clock signal and then input it to the frequency division circuit.

[0049] Specifically, as Figure 4As shown, the oscillation circuit includes the fifty-third MOS transistor M53, the fifty-fourth MOS transistor M54, the fifty-fifth MOS transistor M55, the fifty-sixth MOS transistor M56, the fifty-seventh MOS transistor M57, the fifty-eighth MOS transistor M58, the fifty-ninth MOS transistor M59, the sixtieth MOS transistor M60, the sixty-first MOS transistor M61, the sixty-second MOS transistor M62, the sixty-third MOS transistor M63, the sixty-fourth MOS transistor M64, the sixty-fifth MOS transistor M65, the sixty-sixth MOS transistor M66, the sixty-seventh MOS transistor M67, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the third inverter INV3 and the fourth inverter INV4. Among them, the gates of the fifty-third MOS transistor, the fifty-fourth MOS transistor, the fifty-ninth MOS transistor and the sixtieth MOS transistor are connected; the drain of the fifty-third MOS transistor is connected to the source of the fifty-fourth MOS transistor; the drain of the fifty-fourth MOS transistor, the source of the fifty-fifth MOS transistor, the gate of the fifty-fifth MOS transistor, the gates of the fifty-sixth MOS transistor, the fifty-seventh MOS transistor, the fifty-eighth MOS transistor, the drain of the sixty-third MOS transistor, the gate of the sixty-fourth MOS transistor and the gate of the sixty-fifth MOS transistor are connected; the drain of the fifty-fifth MOS transistor is connected to the source of the fifty-sixth MOS transistor; the drain of the fifty-sixth MOS transistor is connected to the source of the fifty-seventh MOS transistor; the drain of the fifty-seventh MOS transistor is connected to the source of the fifty-eighth MOS transistor; the drains of the fifty-ninth MOS transistor, the sixty-first MOS transistor, the gate of the sixty-second MOS transistor and the first end of the second capacitor are connected; the gates of the sixty-first MOS transistor, the input terminal of the third inverter, the first end of the fourth capacitor, the drain of the sixty-seventh MOS transistor and the drain of the sixty-fifth MOS transistor are connected; the source of the sixty-fourth MOS transistor is connected to its drain and connected to a high level; the drains of the sixtieth MOS transistor, the sixty-second MOS transistor, the sixty-sixth MOS transistor, the first end of the third capacitor and the gate of the sixty-seventh MOS transistor are connected; the output terminal of the third inverter is connected to the input terminal of the fourth inverter; the drains of the fifty-eighth MOS transistor, the source of the sixty-third MOS transistor, the sources of the sixty-fifth MOS transistor, the sixty-first MOS transistor, the sixty-second MOS transistor, the sixty-sixth MOS transistor, the second end of the second capacitor, the second end of the third capacitor and the second end of the fourth capacitor are all connected to a high level; the sources of the fifty-third MOS transistor, the fifty-ninth MOS transistor, the sixtieth MOS transistor and the sixty-seventh MOS transistor are all connected to the power supply voltage; the gates of the sixty-third MOS transistor and the sixty-sixth MOS transistor are both connected to the first external control signal SHDN.

[0050] The frequency division circuit is used to perform frequency division output according to the clock signal frequency to generate a charge pump clock signal.

[0051] In this embodiment, the frequency division circuit includes a decoder, a divide-by-two circuit, a divide-by-four circuit, and a frequency division selection circuit. The decoder is used to receive an external input signal and convert it into a frequency division control signal. The divide-by-two and divide-by-four circuits are used to perform divide-by-two and divide-by-four processing on the clock signal. The frequency division selection circuit outputs a corresponding frequency division signal through a multiplexing circuit according to the frequency division control signal of the decoder.

[0052] Specifically, the frequency division circuit includes a decoder, a divide-by-two module, a divide-by-four module, and a multiplexer. The first output terminal of the decoder is connected to the first input terminal of the multiplexer. The output terminal of the divide-by-two module is connected to the second input terminal of the multiplexer. The output terminal of the divide-by-four module is connected to the third input terminal of the multiplexer. The second output terminal of the decoder is connected to the input terminal of the divide-by-two module. The third output terminal of the decoder is connected to the input terminal of the divide-by-four module. The divide-by-two module and the divide-by-four module are connected in cascade. Among them:

[0053] The decoder is used to convert the control signal into a selection signal;

[0054] The divide-by-two module is used to output a divide-by-two charge pump clock signal according to the clock signal frequency;

[0055] Specifically, as Figure 5 shown, the divide-by-two module includes a first inverter INV1, a first NAND gate NAND1, a first AND gate AND1, a second AND gate AND2, a second NOR gate NOR2, a second NAND gate NAND2, a third NAND gate NAND3, a first OR gate OR1, and a fourth NAND gate NAND4. Among them, the input terminal of the first inverter is connected to the decoder. The output terminal of the first inverter, the first input terminal of the first NAND gate, and the first input terminal of the second NAND gate are connected. The second input terminal of the first NAND gate, the second input terminal of the third NAND gate, and the output terminal of the second NOR gate are connected. The output terminal of the first NAND gate is connected to the second input terminal of the first AND gate. The first input terminal of the first AND gate, the first input terminal of the third NAND gate are connected to the divide-by-four module. The output terminal of the first AND gate is connected to the first input terminal of the second NOR gate. The output terminal of the second AND gate is connected to the second input terminal of the second NOR gate. The first input terminal of the second AND gate, the output terminal of the third NAND gate are connected to the second input terminal of the fourth NAND gate. The second terminal of the second AND gate, the second input terminal of the second NAND gate are connected to the output terminal of the fourth NAND gate. The output terminal of the second NAND gate, the first input terminal of the first OR gate are connected to the divide-by-four module. The second input terminal of the first OR gate is connected to the divide-by-four module. The output terminal of the first OR gate is connected to the first input terminal of the fourth NAND gate.

[0056] The divide-by-four module is used to output a divide-by-four charge pump clock signal according to the clock signal frequency;

[0057] Specifically, as Figure 5As shown, the quarter-frequency module includes the sixth NAND gate NAND6, the third AND gate AND3, the fourth AND gate AND4, the fourth NOR gate NOR4, the seventh NAND gate NAND7, the eighth NAND gate NAND8, the second OR gate OR2, and the ninth NAND gate NAND9. Among them, the first input terminal of the sixth NAND gate and the first input terminal of the seventh NAND gate are connected to the decoder. The second input terminal of the sixth NAND gate, the second terminal of the eighth NAND gate, and the second input terminal of the eighth NAND gate are connected to the output terminal of the fourth NOR gate. The output terminal of the sixth NAND gate is connected to the second input terminal of the third AND gate. The first input terminal of the third AND gate, the first input terminal of the eighth NAND gate, and the second input terminal of the second OR gate are connected to the half-frequency module. The output terminal of the third AND gate is connected to the first input terminal of the fourth NOR gate. The output terminal of the fourth AND gate is connected to the second input terminal of the fourth NOR gate. The first input terminal of the fourth AND gate and the output terminal of the eighth NAND gate are connected to the second input terminal of the ninth NAND gate. The second input terminal of the fourth AND gate and the second input terminal of the seventh NAND gate are connected to the output terminal of the ninth NAND gate. The output terminal of the seventh NAND gate and the first input terminal of the second OR gate are connected to the multiplexer. The output terminal of the second OR gate is connected to the first input terminal of the ninth NAND gate.

[0058] The multiplexer is used to select and output a half-frequency charge pump clock signal or a quarter-frequency charge pump clock signal according to the selection signal.

[0059] Furthermore, in this embodiment, the frequency division circuit includes multiple half-frequency modules and quarter-frequency modules, and the frequency division circuit is composed of multiple half-frequency units and quarter-frequency units. The half-frequency module contains multiple logic gates and inverters to generate a half-frequency signal. The quarter-frequency module is similarly composed of multiple logic gates and is cascaded with the half-frequency module. The frequency division circuit also includes a multiplexer (Multiplexer 4 to 1) for selecting and outputting frequency division signals of different frequencies. Among them, the selection signals (SEL<0> to SEL<3>) are used to control the input selection of the multiplexer to select and output a half-frequency or quarter-frequency signal according to the state of the charge pump, ensuring that the power consumption of the system is optimized in different operating states. The design of this frequency division circuit also includes a decoder (Decoder). The decoder converts the control signal into selection signals (SEL<0> to SEL<3>) to control the input selection of the multiplexer, ensuring that the correct frequency division signal is output at the appropriate time point. The logic control part performs logical operations on the control signal (such as X_EEPROM_EN) through the combination of AND gates and NOT gates to control the operating state of the frequency division module, making the selection of the frequency division signal consistent with the operating state of the system. The control logic in the quarter-frequency module also includes inverters to ensure that the signals are logically synchronized and eliminate the interference caused by the clock phase shift.

[0060] In summary, in the embodiment of the present invention, a reference current is input through IBN4_REF, and the control signals SHDN and SHDNN are used to start and turn off the circulation of the reference current respectively. The drains of MOS transistors M1 and M2 are connected and used as the load of the current mirror of M2. MOS transistors M2, M5, M11, and M12 are used to copy the current as a current mirror. The gate of MOS transistor M2 is connected to the drain of M3, and MOS transistor M4 is used for capacitor filtering. MOS transistors M6 to M11 are used as loads to copy the current to M19. Capacitors C1, C2, and C3 are respectively connected to the gate of M14, the gate of M19, and the drain of M19, and are used for clock generation through charge and discharge. MOS transistor M13 is used to feedback the output signal to form two positive and negative voltages to charge and discharge capacitors C1, C2, and C3 to form a clock signal. The frequency division circuit Clock_Selector_01 includes a frequency division circuit and a frequency division selection circuit. The input clock signal CLK is obtained through buffering by two inverters and input to the frequency division circuit Clock_Selector_01. Then, the frequency division signal CLK_OSC1 is output through a multiplexing circuit, and the working level of the charge pump is adapted through the Level_Shifter level conversion circuit.

[0061] Please refer to Figure 2 , the embodiment of the present application further provides a control method for a low-power EEPROM storage circuit based on a controllable clock, which can implement the above-mentioned low-power EEPROM storage circuit based on a controllable clock. The method includes the following steps:

[0062] S100. Dynamically adjust the magnitude of the reference current according to the control signal and output a control current signal;

[0063] In some specific embodiments, through the distribution of the reference current IBN4_REF, in combination with a multi-stage current mirror and a control signal, the output current of the oscillator is adjusted, thereby changing the operating frequency of the oscillator and realizing dynamic management of power consumption. For example Figure 3As shown, the reference current IBN4_REF is the input signal of this circuit, and its on / off is controlled by an external switch through the SHDN signal. Specifically, when the SHDN signal is activated, IBN4_REF is introduced into the subsequent circuit through the transistor M1. The SHDN signal generates the SHDNN signal through an inverter, enabling the start / stop control of the oscillator in different states. The reference current is input through the transistor M2, filtered by the MOS capacitor of M4, and then input into the multi-stage current mirror network. The current mirrors are distributed step by step from RANK0 to RANK8, and are respectively composed of the following transistors: RANK0 is composed of M5, which serves as the initial unit of the current mirror network and represents the current required by the oscillator when there is no "1" written; RANK1 is cascaded with M5 through M6 to further adjust the initially allocated current; RANK2 is similar to the previous stage through M8, generating the current magnitude required for writing 2 "1"s; RANK3 uses M10 as a continuation of RANK2 to further refine the current distribution; RANK4 is connected after RANK3 through M12 to provide the allocated current for higher levels; RANK5 is composed of M14 and M15, generating a larger current through a parallel design; RANK6 is composed of M17, M18, M19, and M20, and multiple transistors are connected in parallel to shunt current to support high-load requirements; RANK7 includes multiple transistors from M22 to M30, achieving a large current driving ability through large-scale parallel connection; RANK8 includes a transistor network from M32 to M48, serving as the final stage of the current mirror and outputting the current required by the oscillator when all "1"s are written. Through the design of each stage of the current mirror, the distribution ratio of the current is controlled by the control signals CTL<0> to CTL<7>. These control signals correspond to the selection switches of the current mirrors, adjusting the relationship between the total W / L ratio of each stage of the current mirror and the W / L ratio of M2, and finally achieving the dynamic adjustment of the output current of the oscillator. The output current of the current mirror is introduced into the oscillator output terminal OSC2_I BP through the transistor M31 to form the working current of the oscillator. By changing the states of the control signals CTL<0> to CTL<7>, the output frequency of the oscillator can be adjusted. For example, when CTL<0> is "1" and other signals are "0", the output frequency is twice the reference frequency (2FRE1); when CTL<4> is "1" and other signals are "0", the output frequency is 1.5 times the reference frequency (1.5FRE1); when all control signals are "1", the output frequency of the oscillator reaches the maximum value (5 + 15 / 16)FRE1. This frequency adjustment mechanism realizes the refined management of the oscillator power consumption. In the low-power state, the oscillator can operate at a lower frequency, thereby reducing energy consumption; while in the high-performance state, the frequency of the oscillator can be increased to meet the application requirements.

[0064] S200. Generate the clock signal frequency according to the control current signal;

[0065] In some specific embodiments, such as Figure 4 shown is an oscillator circuit, where the dashed part is the starting-up circuit for generating a clock signal. VREG is the power supply voltage, and through the cooperation of transistor M49 and the external trimming filter capacitor C1, filtering processing is performed on VREG to provide a stable power supply voltage signal. SHDNN is the control signal of the oscillator, and after passing through an inverter, the signal SHDN is generated. SHDN and SHDNN cooperate to jointly control the working state of the oscillator. When SHDN is "0", the oscillator stops working and enters the low-power mode; when SHDNN is "1", the oscillator enters the normal working state.

[0066] The output current of the current selection module is converted into a voltage by transistors M49 and M50 and then input to the subsequent circuit, and capacitors C2 and C3 are charged through the current mirror structure formed by M59 and M60, thereby driving transistor M67. At the same time, the output current of M50 is also copied to the load composed of transistors M54 to M58 through the current mirror M53, and then further copied to transistor M65 through the output of M58, forming a multi-stage current mirror link. The gate signal of M67 controls the charging process of capacitor C4, and the voltage of the upper plate of C4 will gradually increase with charging and finally feedback to the gate of transistor M61. When the voltage of C4 rises to a certain value, M61 is turned on, triggering the discharge of C2 and completing the generation of a clock for one oscillation period. The above process repeats in the circuit, and finally the stable generation of the output clock signal is achieved.

[0067] S300. Divide the frequency according to the clock signal frequency to generate a charge pump clock signal;

[0068] It should be noted that in some embodiments, step S300 may include: S310. Convert the control signal into a selection signal; S320. Output a divided-by-two charge pump clock signal and a divided-by-four charge pump clock signal according to the clock signal frequency; S330. Combine the selection signal to select and output a divided-by-two charge pump clock signal or a divided-by-four charge pump clock signal to generate a charge pump clock signal.

[0069] In some specific embodiments, such as Figure 5As shown, the circuit adopts a multi-stage frequency division design to achieve the frequency division processing of the input clock signal. The input clock signal CLK is input through the IN2 port of the multiplexing circuit module. After being processed by the divide-by-two circuit of this module, the divided-by-two signal is output and used as the input of the IN1 port of the clock selection circuit (Multiplexer4to1). At the same time, the output divided-by-two signal enters the next-stage divide-by-two circuit to generate a divided-by-four signal. The divided-by-four signal is not only used as the input signal of the IN0 port of Multiplexer4to1, but also participates in more complex clock distribution. The Multiplexer4to1 circuit receives the output signal from the Decoder module. The Decoder selects and outputs different clock signals according to different control signals from SEL<0> to SEL<3>. The internal Decoder circuit realizes the decoding process of different input signals through combinational logic to ensure that the required divided-frequency clock signal can be output under various working conditions. In addition, the frequency division design of the clock signal combines dynamic logic circuits. Through the enabling of the X_EEPROM_EN signal, the frequency of the output signal can be further adjusted according to external requirements, so as to meet the needs of various complex application scenarios. While realizing the frequency division function, the entire frequency division circuit also reduces the power consumption through logic optimization, ensuring efficient operation in the low-power mode.

[0070] As Figure 6 shown, the frequency division selection circuit consists of multiple input ports and control signals. Its core function is to select an appropriate input signal according to the selection signals (SEL<0> to SEL<3>) and output it to the VOUT port. The input ports IN0, IN1, IN2, and IN3 of this circuit correspond to different signal sources respectively. Among them, IN0, IN1, and IN2 are different frequency signals generated by the previous-stage frequency division circuit, while IN3 is an external input signal. Specifically, when SEL<0> is at a high level, the signal of IN0 will be transmitted to VOUT through the switch; when SEL<1> is at a high level, the signal of IN1 is selected and output; similarly, when SEL<2> or SEL<3> is activated, the signals of IN2 or IN3 are output to VOUT respectively. Each input port is connected to the corresponding switch module, and the switch module is directly controlled by the selection signal, ensuring the efficient selection and transmission of the input signal. In addition, to ensure the stability of the output signal, all input signals will be processed by a buffer after passing through the switch. The addition of the buffer not only enhances the driving ability of the signal, but also effectively avoids signal distortion or attenuation during transmission.

[0071] In summary, in the oscillator current selection module of the embodiment of the present invention, according to the number of externally detected "1"s written, the enable signals of CTL<0> to CTL<7> are controlled to turn on different numbers of current mirrors, thereby controlling the magnitude of the output current. The magnitude of the output current affects the clock frequency output by the oscillator. At this time, the clock frequency output by the oscillator exactly meets the minimum requirement of the number of "1"s written. The write power consumption of the circuit is reduced to the greatest extent. When the charge pump output is stable, the frequency division control circuit outputs a lower clock frequency, and the power consumption is reduced as much as possible on the premise of ensuring that the charge pump can maintain the current output voltage. The overall power consumption of the system is further reduced, that is, by the oscillator current selection circuit to judge the number of "1"s written, and then control the oscillator to generate the minimum clock frequency required by the charge pump, effectively reducing the write power consumption of the EEPROM. At the same time, the dynamic power after the charge pump is stabilized is further reduced by the frequency divider, which has very important practical application value for improving the battery life of mobile devices and portable devices, enhancing the user experience, and extending the service life of the devices.

[0072] It can be understood that the content in the above method embodiments is applicable to the system embodiments of the present invention. The functions specifically implemented by the system embodiments of the present invention are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0073] The preferred embodiments of the embodiments of the present application have been described above with reference to the drawings, and thus do not limit the scope of rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of rights of the embodiments of the present application.

Claims

1. A low-power EEPROM storage circuit based on a controllable clock, characterized in that, The circuit includes an oscillator current selection circuit, a starting oscillation circuit, and a frequency division circuit. The output terminal of the oscillator current selection circuit is connected to the input terminal of the starting oscillation circuit, and the output terminal of the starting oscillation circuit is connected to the input terminal of the frequency division circuit, where: The oscillator current selection circuit is configured to dynamically adjust the magnitude of a reference current according to a control signal and output a control current signal; The starting oscillation circuit is configured to generate a clock signal frequency according to the control current signal; The frequency division circuit is configured to perform frequency division output according to the clock signal frequency and generate a charge pump clock signal.

2. The circuit according to claim 1, characterized in that, The oscillator current selection circuit includes a reference current input module, a control signal module, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first current mirror module, a second current mirror module, a third current mirror module, a fourth current mirror module, a fifth current mirror module, a sixth current mirror module, a seventh current mirror module, an eighth current mirror module, a ninth current mirror module, and a thirty-first MOS transistor. The negative input terminal of the reference current input module is connected to the gate of the third MOS transistor and receives a first external control signal SHDN. The positive input terminal of the reference current input module is connected to a second external control signal SHDNN. The output terminal of the reference current input module is connected to the drain of the first MOS transistor. The gate of the first MOS transistor is connected to a bias voltage signal. The source of the first MOS transistor is connected to the drain of the second MOS transistor. The source of the second MOS transistor is connected to a high level. The gates of the second MOS transistor, the drain of the third MOS transistor, the gate of the fourth MOS transistor, the input terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module are connected. The source of the third MOS transistor is connected to a high level. The source of the fourth MOS transistor is connected to the drain of the fourth MOS transistor and is connected to a high level. The output terminals of the control signal module are all connected to the signal input terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module. The first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module are connected in sequence. The sources of the thirty-first MOS transistor are all connected to the output terminals of the first current mirror module, the second current mirror module, the third current mirror module, the fourth current mirror module, the fifth current mirror module, the sixth current mirror module, the seventh current mirror module, the eighth current mirror module, and the ninth current mirror module. The gate of the thirty-first MOS transistor is connected to a bias voltage signal.

3. The circuit according to claim 2, wherein The first current mirror module includes a fifth MOS transistor, the second current mirror module includes a sixth MOS transistor and a seventh MOS transistor, the third current mirror module includes an eighth MOS transistor and a ninth MOS transistor, the fourth current mirror module includes a tenth MOS transistor and an eleventh MOS transistor, the fifth current mirror module includes a twelfth MOS transistor and a thirteenth MOS transistor, the sixth current mirror module includes a fourteenth MOS transistor, a fifteenth MOS transistor and a sixteenth MOS transistor, the seventh current mirror module includes a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor and a twenty-first MOS transistor, the eighth current mirror module includes a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, a twenty-eighth MOS transistor, a twenty-ninth MOS transistor and a thirtieth MOS transistor, the ninth current mirror module includes a thirty-second MOS transistor, a thirty-third MOS transistor, a thirty-fourth MOS transistor, a thirty-fifth MOS transistor, a thirty-sixth MOS transistor, a thirty-seventh MOS transistor, a thirty-eighth MOS transistor, a thirty-ninth MOS transistor, a fortieth MOS transistor, a forty-first MOS transistor, a forty-second MOS transistor, a forty-third MOS transistor, a forty-fourth MOS transistor, a forty-fifth MOS transistor, a forty-sixth MOS transistor, a forty-seventh MOS transistor and a forty-eighth MOS transistor. The drain of the fifth MOS transistor, the gates of the sixth MOS transistor, the eighth MOS transistor, the tenth MOS transistor, the twelfth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor and the twentieth MOS transistor are connected. The gates of the twenty-second MOS transistor, the twenty-third MOS transistor, the twenty-fourth MOS transistor, the twenty-fifth MOS transistor, the twenty-sixth MOS transistor, the twenty-seventh MOS transistor, the twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirty-second MOS transistor, the thirty-third MOS transistor, the thirty-fourth MOS transistor, the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-seventh MOS transistor, the thirty-eighth MOS transistor, the thirty-ninth MOS transistor, the fortieth MOS transistor, the forty-first MOS transistor, the forty-second MOS transistor, the forty-third MOS transistor, the forty-fourth MOS transistor, the forty-fifth MOS transistor, the forty-sixth MOS transistor and the forty-seventh MOS transistor are connected.The sources of the fifth MOS transistor, the seventh MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the sixteenth MOS transistor, the twenty-first MOS transistor, the thirtieth MOS transistor, and the forty-eighth MOS transistor are all connected to a high level. The gates of the seventh MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the sixteenth MOS transistor, the twenty-first MOS transistor, the thirtieth MOS transistor, and the forty-eighth MOS transistor are all connected to the control signal module. The source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor. The source of the eighth MOS transistor is connected to the drain of the ninth MOS transistor. The source of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor. The source of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor. The source of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor. The source of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor. The source of the seventeenth MOS transistor is connected to the drain of the eighteenth MOS transistor. The source of the eighteenth MOS transistor is connected to the drain of the nineteenth MOS transistor. The source of the nineteenth MOS transistor is connected to the drain of the twentieth MOS transistor. The source of the twentieth MOS transistor is connected to the drain of the twenty-first MOS transistor. The source of the twenty-second MOS transistor is connected to the drain of the twenty-third MOS transistor. The source of the twenty-third MOS transistor is connected to the drain of the twenty-fourth MOS transistor. The source of the twenty-fourth MOS transistor is connected to the drain of the twenty-fifth MOS transistor. The source of the twenty-fifth MOS transistor is connected to the drain of the twenty-sixth MOS transistor. The source of the twenty-sixth MOS transistor is connected to the drain of the twenty-seventh MOS transistor. The source of the twenty-seventh MOS transistor is connected to the drain of the twenty-eighth MOS transistor. The source of the twenty-eighth MOS transistor is connected to the drain of the twenty-ninth MOS transistor. The source of the twenty-ninth MOS transistor is connected to the drain of the thirtieth MOS transistor. The source of the thirty-second MOS transistor is connected to the drain of the thirty-third MOS transistor. The source of the thirty-third MOS transistor is connected to the drain of the thirty-fourth MOS transistor. The source of the thirty-fourth MOS transistor is connected to the drain of the thirty-fifth MOS transistor. The source of the thirty-fifth MOS transistor is connected to the drain of the thirty-sixth MOS transistor. The source of the thirty-sixth MOS transistor is connected to the drain of the thirty-seventh MOS transistor. The source of the thirty-seventh MOS transistor is connected to the drain of the thirty-eighth MOS transistor. The source of the thirty-eighth MOS transistor is connected to the drain of the thirty-ninth MOS transistor. The source of the thirty-ninth MOS transistor is connected to the drain of the fortieth MOS transistor,The source electrode of the fortieth MOS transistor is connected to the drain electrode of the forty-first MOS transistor, the source electrode of the forty-first MOS transistor is connected to the drain electrode of the forty-second MOS transistor, the source electrode of the forty-second MOS transistor is connected to the drain electrode of the forty-third MOS transistor, the source electrode of the forty-third MOS transistor is connected to the drain electrode of the forty-fourth MOS transistor, the source electrode of the forty-fourth MOS transistor is connected to the drain electrode of the forty-fifth MOS transistor, the source electrode of the forty-fifth MOS transistor is connected to the drain electrode of the forty-sixth MOS transistor, the source electrode of the forty-sixth MOS transistor is connected to the drain electrode of the forty-seventh MOS transistor, and the source electrode of the forty-seventh MOS transistor is connected to the drain electrode of the forty-eighth MOS transistor.

4. The circuit according to claim 1, characterized in that, The starting oscillation circuit includes the fifty-third MOS transistor, the fifty-fourth MOS transistor, the fifty-fifth MOS transistor, the fifty-sixth MOS transistor, the fifty-seventh MOS transistor, the fifty-eighth MOS transistor, the fifty-ninth MOS transistor, the sixtieth MOS transistor, the sixty-first MOS transistor, the sixty-second MOS transistor, the sixty-third MOS transistor, the sixty-fourth MOS transistor, the sixty-fifth MOS transistor, the sixty-sixth MOS transistor, the sixty-seventh MOS transistor, the second capacitor, the third capacitor, the fourth capacitor, the third inverter, and the fourth inverter. Among them, the gates of the fifty-third MOS transistor, the fifty-fourth MOS transistor, the fifty-ninth MOS transistor, and the sixtieth MOS transistor are connected; the drain of the fifty-third MOS transistor is connected to the source of the fifty-fourth MOS transistor; the drains of the fifty-fourth MOS transistor, the source of the fifty-fifth MOS transistor, the gate of the fifty-fifth MOS transistor, the gates of the fifty-sixth MOS transistor, the fifty-seventh MOS transistor, the fifty-eighth MOS transistor, the drain of the sixty-third MOS transistor, the gate of the sixty-fourth MOS transistor, and the gate of the sixty-fifth MOS transistor are connected; the drain of the fifty-fifth MOS transistor is connected to the source of the fifty-sixth MOS transistor; the drain of the fifty-sixth MOS transistor is connected to the source of the fifty-seventh MOS transistor; the drain of the fifty-seventh MOS transistor is connected to the source of the fifty-eighth MOS transistor; the drains of the fifty-ninth MOS transistor, the sixty-first MOS transistor, the gate of the sixty-second MOS transistor, and the first end of the second capacitor are connected; the gate of the sixty-first MOS transistor, the input end of the third inverter, the first end of the fourth capacitor, the drain of the sixty-seventh MOS transistor, and the drain of the sixty-fifth MOS transistor are connected; the source of the sixty-fourth MOS transistor is connected to its drain and connected to a high level; the drains of the sixtieth MOS transistor, the sixty-second MOS transistor, the sixty-sixth MOS transistor, the first end of the third capacitor, and the gate of the sixty-seventh MOS transistor are connected; the output end of the third inverter is connected to the input end of the fourth inverter; the drains of the fifty-eighth MOS transistor, the source of the sixty-third MOS transistor, the sources of the sixty-fifth MOS transistor, the sixty-first MOS transistor, the sixty-second MOS transistor, the sixty-sixth MOS transistor, the second end of the second capacitor, the second end of the third capacitor, and the second end of the fourth capacitor are all connected to a high level; the sources of the fifty-third MOS transistor, the fifty-ninth MOS transistor, the sixtieth MOS transistor, and the sixty-seventh MOS transistor are all connected to the power supply voltage; the gates of the sixty-third MOS transistor and the sixty-sixth MOS transistor are both connected to the first external control signal SHDN.

5. The circuit according to claim 1, characterized in that, The frequency division circuit includes a decoder, a divide-by-two module, a divide-by-four module, and a multiplexer. The first output terminal of the decoder is connected to the first input terminal of the multiplexer. The output terminal of the divide-by-two module is connected to the second input terminal of the multiplexer. The output terminal of the divide-by-four module is connected to the third input terminal of the multiplexer. The second output terminal of the decoder is connected to the input terminal of the divide-by-two module. The third output terminal of the decoder is connected to the input terminal of the divide-by-four module. The divide-by-two module and the divide-by-four module are connected in cascade, where: The decoder is configured to convert a control signal into a selection signal; The divide-by-two module is configured to output a divide-by-two charge pump clock signal according to the frequency of the clock signal; The divide-by-four module is configured to output a divide-by-four charge pump clock signal according to the frequency of the clock signal; The multiplexer is configured to select and output the divide-by-two charge pump clock signal or the divide-by-four charge pump clock signal according to the selection signal.

6. The circuit according to claim 5, wherein, The divide-by-two module includes a first inverter, a first NAND gate, a first AND gate, a second AND gate, a second NOR gate, a second NAND gate, a third NAND gate, a first OR gate, and a fourth NAND gate. Among them, the input terminal of the first inverter is connected to the decoder. The output terminal of the first inverter, the first input terminal of the first NAND gate, and the first input terminal of the second NAND gate are connected. The second input terminal of the first NAND gate, the second input terminal of the third NAND gate, and the output terminal of the second NOR gate are connected. The output terminal of the first NAND gate is connected to the second input terminal of the first AND gate. The first input terminal of the first AND gate, the first input terminal of the third NAND gate, and the divide-by-four module are connected. The output terminal of the first AND gate is connected to the first input terminal of the second NOR gate. The output terminal of the second AND gate is connected to the second input terminal of the second NOR gate. The first input terminal of the second AND gate, the output terminal of the third NAND gate, and the second input terminal of the fourth NAND gate are connected. The second terminal of the second AND gate, the second input terminal of the second NAND gate, and the output terminal of the fourth NAND gate are connected. The output terminal of the second NAND gate, the first input terminal of the first OR gate, and the divide-by-four module are connected. The second input terminal of the first OR gate is connected to the divide-by-four module. The output terminal of the first OR gate is connected to the first input terminal of the fourth NAND gate.

7. The circuit according to claim 5, characterized in that, The frequency division module includes a sixth NAND gate, a third AND gate, a fourth AND gate, a fourth NOR gate, a seventh NAND gate, an eighth NAND gate, a second OR gate and a ninth NAND gate. Among them, the first input terminal of the sixth NAND gate, the first input terminal of the seventh NAND gate are connected to the decoder. The second input terminal of the sixth NAND gate, the second terminal of the eighth NAND gate, the second input terminal of the eighth NAND gate are connected to the output terminal of the fourth NOR gate. The output terminal of the sixth NAND gate is connected to the second input terminal of the third AND gate. The first input terminal of the third AND gate, the first input terminal of the eighth NAND gate, the second input terminal of the second OR gate are connected to the frequency division module. The output terminal of the third AND gate is connected to the first input terminal of the fourth NOR gate. The output terminal of the fourth AND gate is connected to the second input terminal of the fourth NOR gate. The first input terminal of the fourth AND gate, the output terminal of the eighth NAND gate are connected to the second input terminal of the ninth NAND gate. The second input terminal of the fourth AND gate, the second input terminal of the seventh NAND gate are connected to the output terminal of the ninth NAND gate. The output terminal of the seventh NAND gate, the first input terminal of the second OR gate are connected to the multiplexer. The output terminal of the second OR gate is connected to the first input terminal of the ninth NAND gate.

8. A control method for a low-power EEPROM storage circuit based on a controllable clock, characterized in that, The method includes the following steps: Dynamically adjust the magnitude of the reference current according to the control signal and output a control current signal; Generate a clock signal frequency according to the control current signal; Perform frequency division output according to the clock signal frequency to generate a charge pump clock signal.

9. The method according to claim 8, characterized in that It further includes controlling the turn-on and turn-off of each stage of current mirror through the control signal, and then outputting the control current signal.

10. The method according to claim 8, wherein The performing frequency division output according to the clock signal frequency to generate a charge pump clock signal includes: Convert the control signal into a selection signal; Output a divided-by-two charge pump clock signal and a divided-by-four charge pump clock signal according to the clock signal frequency; Combine the selection signal to select and output the divided-by-two charge pump clock signal or the divided-by-four charge pump clock signal to generate the charge pump clock signal.

Images