Method and device for detecting characteristics of memory chip and electronic equipment

Abstract

The invention discloses a method and a device for detecting characteristics of a memory chip, and electronic equipment. The method comprises the steps that a main control unit writes preset data with low level into a memory chip, an on-chip termination resistance value, associated with a data queue signal, of the memory chip is set to be a first preset value, and a driving strength resistance value, associated with the data queue signal, of the main control unit is set to be a second preset value, the second preset value is greater than the first preset value; providing the sampling level with a third preset value for the memory chip; and reading data from the memory chip, comparing the read data with preset data to obtain a comparison result, and determining whether the memory chip has the on-chip termination resistance characteristic or not based on the comparison result. According to the working principle that the single end of the memory chip pulls up the ODT terminal, whether the memory chip supports the on-chip termination resistance characteristic or not can be determined only according to the comparison result, and therefore the cost and complexity for detecting whether the memory chip supports the ODT characteristic or not are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and in particular, to a method and apparatus for detecting characteristics of a memory chip, and an electronic device. Background Art

[0002] In the prior art, an external oscilloscope is generally used to measure the voltage amplitude of the low level of the DQ (Data Queue) signal transmission of LPDDR3 (Low Power Double Data Rate 3, the third generation of low-power double data rate random access memory) to determine whether the LPDDR3 die supports the ODT (On-Die Termination) characteristic.

[0003] However, the above method is expensive and complex, and cannot detect a large number of LPDDR3 models one by one. Summary of the Invention

[0004] The present invention provides a method and apparatus for detecting characteristics of a memory chip, and an electronic device, which can reduce the cost and complexity of detecting whether the memory chip supports the ODT characteristic.

[0005] In one aspect of the present invention, a method for detecting characteristics of a memory chip is provided. The method includes: writing preset data with a low level into the memory chip by a main control unit, setting the on-die termination resistance value associated with the data queue signal of the memory chip to a first preset value, setting the drive strength resistance value associated with the data queue signal of the main control unit to a second preset value, where the second preset value is greater than the first preset value; providing a sampling level with a third preset value to the memory chip by the main control unit; reading data from the memory chip by the main control unit, and comparing the read data with the preset data to obtain a comparison result; and determining whether the memory chip has an on-die termination resistance characteristic based on the comparison result by the main control unit.

[0006] In another aspect of the present invention, there is provided an apparatus for detecting the characteristics of a memory chip. The apparatus includes a main control unit electrically coupled to the memory chip. The on-chip termination resistance value associated with the data queue signal of the memory chip is set to a first preset value. The main control unit is configured to: set the driving strength resistance value associated with the data queue signal of the main control unit to a second preset value, where the second preset value is greater than the first preset value; write preset data with a low level into the memory chip; provide a sampling level with a third preset value to the memory chip; read data from the memory chip, and compare the read data with the preset data to obtain a comparison result; and determine whether the memory chip has an on-chip termination resistance characteristic based on the comparison result.

[0007] In yet another aspect of the present invention, there is provided an electronic device. The electronic device includes a memory configured to store an executable program; and a processor configured to execute the program such that the electronic device performs the above method for detecting the characteristics of a memory chip.

[0008] According to the technical solution of the present invention, the main control unit writes preset data with a low level into the memory chip. The on-chip termination resistance value associated with the data queue signal of the memory chip is set to a first preset value, and the driving strength resistance value associated with the data queue signal of the main control unit is set to a second preset value, where the second preset value is greater than the first preset value. A sampling level with a third preset value is provided to the memory chip, data is read from the memory chip, and the read data is compared with the preset data to obtain a comparison result. Based on the comparison result, it is determined whether the memory chip has an on-chip termination resistance characteristic. In this way, there is no need to use an external oscilloscope for detection. Instead, by utilizing the working principle of the single-ended pull-up ODT terminal of the memory chip, the driving strength resistance value of the main control unit DQ signal, the ODT resistance value of the memory chip, and the sampling level provided by the main control unit to the memory chip are set. It is only necessary to determine whether the memory chip has an on-chip termination resistance characteristic according to the comparison result, thereby reducing the cost and complexity of detecting whether the memory chip supports the ODT characteristic. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a flowchart of a method for detecting the characteristics of a memory chip according to an embodiment of the present invention; Figure 2 It is a test flowchart of a method for detecting the characteristics of a memory chip according to an embodiment of the present invention; Figure 3 It is an interaction schematic diagram between the main control unit and the LPDDR3 particles of a method for detecting the characteristics of a memory chip according to an embodiment of the present invention; Figure 4Schematic diagram of the master control unit and LPDDR3 particles for the method of detecting memory chip characteristics according to an embodiment of the present invention; Figure 5 Schematic diagram of the structure of the device for detecting memory chip characteristics according to an embodiment of the present invention; Figure 6 Schematic diagram of the structure of the electronic device according to an embodiment of the present invention. Detailed implementation manners

[0010] To describe in detail the technical content, achieved objectives and effects of the present invention, the following is described in conjunction with the embodiments and with reference to the accompanying drawings.

[0011] In the prior art, the method of using an external oscilloscope is generally adopted. By measuring the voltage amplitude of the low level of the DQ signal transmission of LPDDR3, it is determined whether the LPDDR3 particles support the ODT characteristic. However, this method is expensive and complex, and it is impossible to detect numerous LPDDR3 models one by one.

[0012] To solve at least the above technical problems, the present disclosure provides a method for detecting memory chip characteristics. According to the present disclosure, a master control unit writes preset data with a low level into the memory chip. The on-chip termination resistance value associated with the data queue signal of the memory chip is set to a first preset value, and the drive strength resistance value associated with the data queue signal of the master control unit is set to a second preset value, where the second preset value is greater than the first preset value. A sampling level with a third preset value is provided to the memory chip, data is read from the memory chip, and the read data is compared with the preset data to obtain a comparison result. Based on the comparison result, it is determined whether the memory chip has the on-chip termination resistance characteristic. In this way, instead of using an external oscilloscope for detection, by utilizing the working principle of the single-ended pull-up ODT terminal of the memory chip, setting the drive strength resistance value of the DQ signal of the master control unit, the ODT resistance of the memory chip, and the sampling level provided by the master control unit to the memory chip, it can be determined whether the memory chip has the on-chip termination resistance characteristic only according to the comparison result, thereby reducing the cost and complexity of detecting whether the memory chip supports the ODT characteristic.

[0013] Hereinafter, the technical solutions according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings. In addition, LPDDR3 particles are described as an example of the memory chip. It should be understood that the memory chip of the present disclosure may also be other suitable memory types.

[0014] Figure 1 is a flowchart showing a method 100 for detecting memory chip characteristics according to an embodiment of the present disclosure. Referring to Figure 1 , the method 100 includes the following steps 102 to 108.

[0015] In step 102, the main control unit writes preset data with a low level into the memory chip. The on-chip termination resistance value of the memory chip associated with the data queue signal is set to a first preset value, and the drive strength resistance value of the main control unit associated with the data queue signal is set to a second preset value, where the second preset value is greater than the first preset value.

[0016] In some embodiments, the method 100 may further include: setting the drive strength resistance value of the main control unit associated with the data queue signal to the second preset value, where the drive strength resistance value includes the pull-up drive strength resistance value and the pull-down drive strength resistance value associated with the data queue signal. In some embodiments, both the pull-up drive strength resistance value and the pull-down drive strength resistance value are equal to the second preset value.

[0017] In step 104, the main control unit provides a sampling level with a third preset value to the memory chip.

[0018] In some embodiments, the method 100 may further include: obtaining the low-level voltage amplitude of the data queue transmission line; determining the third preset value based on the low-level voltage amplitude of the data queue transmission line; and setting the sampling level provided to the memory chip to the third preset value.

[0019] In this way, the sampling level provided by the main control unit to a memory chip such as an LPDDR3 particle can be flexibly set according to the low-level voltage amplitude of the data queue transmission line.

[0020] In step 106, the main control unit reads data from the memory chip and compares the read data with the preset data to obtain a comparison result.

[0021] In step 108, the main control unit determines whether the memory chip has an on-chip termination resistance characteristic based on the comparison result.

[0022] In some embodiments, if the comparison result is consistent, it is determined that the memory chip does not have an on-chip termination resistance characteristic; and if the comparison result is inconsistent, it is determined that the memory chip has an on-chip termination resistance characteristic.

[0023] In this way, if the memory chip such as LPDDR3 supports the ODT feature, the low-level voltage amplitude of the DQ signal transmission line will be greater than the sampling level, and thus the low level of the DQ signal cannot be correctly sampled, resulting in inconsistent data writing and reading by the main controller. If the memory chip such as LPDDR3 does not support the ODT feature, the low level of its DQ signal transmission line is not affected by ODT and is less than the sampling level, and thus the low level of the DQ signal can be correctly sampled, resulting in consistent data writing and reading by the main controller. Therefore, according to the comparison result, it can be determined whether the memory chip such as LPDDR3 particles supports the ODT feature, reducing the cost and complexity of detecting whether the memory chip such as LPDDR3 particles supports the ODT feature.

[0024] In some embodiments, the input / output power supply voltage and the ground voltage are obtained, and the low-level voltage amplitude of the data queue transmission line is determined according to the pull-down drive strength resistance value, the on-chip termination resistance value, the input / output power supply voltage, and the ground voltage.

[0025] In some embodiments, determining the low-level voltage amplitude of the data queue transmission line according to the pull-down drive strength resistance value, the on-chip termination resistance value, the input / output power supply voltage, and the ground voltage includes determining the low-level voltage amplitude through the following formula: Vol = Rdqdrv_down÷(Rdqdrv_down + Rdqodt)×(VDDQ - VSSQ); In the formula, Vol represents the low-level voltage amplitude of the data queue transmission line, Rdqdrv_down represents the pull-down drive strength resistance value, Rdqodt represents the on-chip termination resistance value, VDDQ represents the input / output power supply voltage, and VSSQ represents the ground voltage.

[0026] In this way, when the data queue signal is at a low level, the current will form a path through the pull-down resistor and the on-chip termination resistor. The pull-down drive strength resistance value and the on-chip termination resistor value determine the total resistance of the circuit, while the input / output power supply voltage and the ground voltage determine the voltage difference of the circuit. Through these parameters, the current in the circuit can be calculated, and then the low-level voltage amplitude of the data queue transmission line can be calculated according to the resistance distribution principle.

[0027] In some embodiments, the input / output power supply voltage and the ground voltage are obtained based on the low-level voltage amplitude of the data queue transmission line, and the third preset value is determined based on the input / output power supply voltage and the ground voltage.

[0028] In some embodiments, determining the third preset value based on the input / output power supply voltage and the ground voltage includes determining the third preset value through the following formula: V3 = 50%×(VDDQ - VSSQ); In the formula, V3 represents the third preset value, VDDQ represents the input / output power supply voltage, and VSSQ represents the ground terminal voltage.

[0029] In this way, by determining the third preset value based on the input / output power supply voltage and the ground terminal voltage, the third preset value can be set at the middle position.

[0030] In the following, application scenarios of a method and apparatus for detecting memory chip characteristics and an electronic device according to an embodiment of the present invention will be described by way of examples.

[0031] Figure 2 is a flowchart showing a method for detecting memory chip characteristics according to an embodiment of the present invention. In this embodiment, the memory chip is an LPDDR3 particle. Refer to Figure 2 , the method includes the following steps 201 to step 208.

[0032] In step 201, set the ODT resistance value (Rdqodt) associated with the DQ signal of the LPDDR3 particle to a first preset value.

[0033] In step 202, set both the pull-up drive strength resistance value (Rdqdrv_pull) and the pull-down drive strength resistance value (Rdqdrv_down) associated with the DQ signal of the main control unit to a second preset value.

[0034] In this embodiment, the second preset value is greater than the first preset resistance value.

[0035] In step 203, the main control unit writes preset data with a low level into the memory chip.

[0036] In step 204, the main control unit provides a sampling level (VrefDQ) with a third preset value to the LPDDR3 particle.

[0037] In some embodiments, step 204 specifically includes the following (1) to (4).

[0038] (1) Obtain the low-level voltage amplitude of the DQ transmission line, specifically including the following (1-1) to (1-2).

[0039] (1-1) Obtain the input / output (IO) power supply voltage and the ground terminal (GND) voltage.

[0040] (1-2) Determine the low-level voltage amplitude of the DQ transmission line according to the pull-down drive strength resistance value, the ODT resistance value, the input / output power supply voltage, and the ground terminal voltage, specifically as follows: Vol = Rdqdrv_down ÷ (Rdqdrv_down + Rdqodt) × (VDDQ - VSSQ); Wherein, Vol represents the low-level voltage amplitude of the DQ transmission line, Rdqdrv_down represents the pull-down drive strength resistance value, Rdqodt represents the ODT resistance value. According to the LPDDR3 jedec standard, it can take values of 240 ohm, 120 ohm or 60 ohm. VDDQ represents the input / output power supply voltage, and VSSQ represents the ground terminal voltage.

[0041] (2) Determine the third preset value based on the low-level voltage amplitude of the DQ transmission line.

[0042] In some embodiments, it specifically includes the following (2-1) to (2-1).

[0043] (2-1) Obtain the input / output power supply voltage and the ground terminal voltage based on the low-level voltage amplitude of the DQ transmission line.

[0044] (2-2) Determine the third preset value based on the input / output power supply voltage and the ground terminal voltage. Specifically: V3 = 50% × (VDDQ - VSSQ); Wherein, V3 represents the third preset value, VDDQ represents the input / output power supply voltage. According to the LPDDR3 jedec standard, the typical value is 1.2V, and VSSQ represents the ground terminal voltage, which can be regarded as 0V.

[0045] (3) Set the sampling level provided to the LPDDR3 chip to the third preset value.

[0046] In this embodiment, the sampling level provided to the LPDDR3 chip is not fixedly set to 50% × (VDDQ - VSSQ). It can be adjusted according to Vol obtained from different Rdqdrv_down and Rdqodt, as long as Vol > VrefDQ is satisfied on the LPDDR3 that supports the ODT characteristic.

[0047] (4) The main control unit provides the sampling level with the third preset value to the LPDDR3 chip.

[0048] In step 205, the main control unit reads data from the LPDDR3 chip.

[0049] In step 206, compare the read data with the preset data to obtain a comparison result.

[0050] In step 207, if the comparison result is consistent, it is determined that the LPDDR3 chip does not have the ODT characteristic.

[0051] In step 208, if the comparison result is inconsistent, it is determined that the LPDDR3 particle has the ODT characteristic.

[0052] Figure 3 FIG. is a schematic interaction diagram between a main control unit and an LPDDR3 particle in a method for detecting memory chip characteristics according to an embodiment of the present invention. Figure 4 FIG. shows an input / output schematic diagram between a main control unit and an LPDDR3 particle in a method for detecting memory chip characteristics according to an embodiment of the present invention. Refer to Figure 3 and Figure 4 , the main control unit includes a DRV (drive) module and a VrefDQ control module, the LPDDR3 particle includes an ODT module, and the specific working principle of the method for detecting memory chip characteristics according to the embodiment of the present invention is as follows.

[0053] The high-level voltage amplitude Voh of the DQ transmission line is specifically: Voh = VDDQ - VSSQ.

[0054] If the LPDDR3 particle supports the ODT characteristic, the low-level voltage amplitude of the DQ transmission line is specifically: Vol = Rdqdrv_down÷(Rdqdrv_down + Rdqodt)×(VDDQ - VSSQ).

[0055] Considering that VSSQ is the GND voltage of 0V, then: Vol = Rdqdrv_down÷(Rdqdrv_down + Rdqodt)×VDDQ.

[0056] Because Rdqdrv_down > Rdqodt, and VrefDQ = 50%×(VDDQ - VSSQ) is set, at this time Vol > VrefDQ, the LPDDR3 particle cannot correctly sample the DQ low level Vol, so the main control SOC fails to write the preset data with a low level to the LPDDR3, and the written and read data must be different.

[0057] If the LPDDR3 particle does not support the ODT characteristic, that is, Rdqodt does not exist and the resistance value is infinite, the low-level voltage amplitude Vol of the DQ transmission line = 0V.

[0058] Similarly, Rdqdrv_down > Rdqodt, the main control SOC sets VrefDQ = 50%×(VDDQ - VSSQ), at this time Vol < VrefDQ, the LPDDR3 particle can correctly sample the DQ low level Vol, so the main control SOC will successfully write the preset data with a low level to the LPDDR3, and the written and read data are the same.

[0059] Figure 5 is a block diagram showing an apparatus 500 for detecting characteristics of a memory chip according to an embodiment of the present invention. Referring to Figure 5 , the apparatus 500 includes a main control unit 502.

[0060] The main control unit 502 is electrically coupled to the memory chip, and an on-chip termination resistance value associated with a data queue signal of the memory chip is set to a first preset value.

[0061] The main control unit 502 is configured to set a drive strength resistance value associated with the data queue signal of the main control unit to a second preset value, where the second preset value is greater than the first preset value. The main control unit 502 is configured to write preset data with a low level into the memory chip, and provide a sampling level with a third preset value to the memory chip. The main control unit 502 is configured to read data from the memory chip, and compare the read data with the preset data to obtain a comparison result. In addition, the main control unit 502 is configured to determine whether the memory chip has an on-chip termination resistance characteristic based on the comparison result.

[0062] It should be understood that the main control unit 502 may be further configured to execute each step or action in the method described above, which will not be elaborated here.

[0063] According to another aspect of the present invention, Figure 6 is a schematic diagram showing an electronic device 600 according to an embodiment of the present invention. Referring to Figure 6 , the electronic device 600 includes a memory 602 and a processor 604. The memory 602 is configured to store an executable program that can run on the processor 604. The processor 604 is configured to execute the program such that the electronic device implements each step or action of the method for detecting characteristics of a memory chip described above.

[0064] In summary, the present invention provides a method and apparatus for detecting the characteristics of a memory chip, and an electronic device. The main control unit writes preset data with a low level into the memory chip. The on-chip termination resistance value associated with the data queue signal of the memory chip is set to a first preset value, and the driving strength resistance value associated with the data queue signal of the main control unit is set to a second preset value, where the second preset value is greater than the first preset value. A sampling level with a third preset value is provided to the memory chip, data is read from the memory chip, and the read data is compared with the preset data to obtain a comparison result. Based on the comparison result, it is determined whether the memory chip has an on-chip termination resistance characteristic. In this way, there is no need to use an external oscilloscope for detection. Instead, by utilizing the working principle of the single-ended pull-up ODT terminal of the memory chip, the driving strength resistance value of the DQ signal of the main control unit, the ODT resistance value of the memory chip, and the sampling level provided by the main control unit to the memory chip are set. If it is a memory chip supporting the ODT characteristic, the low-level voltage amplitude of the DQ signal transmission line will be greater than the sampling level, and thus the low level of the DQ signal cannot be correctly sampled, resulting in inconsistent data writing and reading by the main control. However, if it is a memory chip not supporting the ODT characteristic, the low level of its DQ signal transmission line is not affected by ODT and will be less than the sampling level, and thus the low level of the DQ signal can be correctly sampled, resulting in consistent data writing and reading by the main control. Therefore, it can be determined whether the memory chip supports the ODT characteristic according to the comparison result, thereby reducing the cost and complexity of detecting whether the memory chip supports the ODT characteristic.

[0065] The above are only the embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in the relevant technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A method for detecting the characteristics of a memory chip, characterized in that, Including: The main control unit writes preset data with a low level into the memory chip. The on-chip termination resistance value of the memory chip associated with the data queue signal is set to a first preset value, and the drive strength resistance value of the main control unit associated with the data queue signal is set to a second preset value, where the second preset value is greater than the first preset value; The main control unit provides a sampling level with a third preset value to the memory chip; The main control unit reads data from the memory chip and compares the read data with the preset data to obtain a comparison result; And The main control unit determines whether the memory chip has an on-chip termination resistance characteristic based on the comparison result.

2. The method according to claim 1, wherein The main control unit determines whether the memory chip has an on-chip termination resistance characteristic based on the comparison result, including: If the comparison result is consistent, it is determined that the memory chip does not have an on-chip termination resistance characteristic; and If the comparison result is inconsistent, it is determined that the memory chip has an on-chip termination resistance characteristic.

3. The method according to claim 1, characterized in that, It also includes: Setting the drive strength resistance value of the main control unit associated with the data queue signal to the second preset value, where the drive strength resistance value includes the pull-up drive strength resistance value and the pull-down drive strength resistance value associated with the data queue signal.

4. The method according to claim 3, characterized in that It also includes: Obtaining the low-level voltage amplitude of the data queue transmission line; Determining the third preset value based on the low-level voltage amplitude of the data queue transmission line; And Setting the sampling level provided to the memory chip to the third preset value.

5. The method according to claim 4, wherein Obtaining the low-level voltage amplitude of the data queue transmission line includes: Obtaining the input / output power supply voltage and the ground terminal voltage; and Determining the low-level voltage amplitude of the data queue transmission line according to the pull-down drive strength resistance value, the on-chip termination resistance value, the input / output power supply voltage, and the ground terminal voltage.

6. The method according to claim 5, wherein Determining the low-level voltage amplitude of the data queue transmission line according to the pull-down drive strength resistance value, the on-chip termination resistance value, the input / output power supply voltage, and the ground terminal voltage includes determining the low-level voltage amplitude through the following formula: Vol = Rdqdrv_down÷(Rdqdrv_down + Rdqodt)×(VDDQ - VSSQ); In the formula, Vol represents the low-level voltage amplitude of the data queue transmission line, Rdqdrv_down represents the pull-down drive strength resistance value, Rdqodt represents the on-chip termination resistance value, VDDQ represents the input / output power supply voltage, and VSSQ represents the ground terminal voltage.

7. The method according to claim 4, characterized in that, Determining the third preset value based on the low-level voltage amplitude of the data queue transmission line includes: Obtaining the input / output power supply voltage and the ground terminal voltage based on the low-level voltage amplitude of the data queue transmission line; and Determining the third preset value based on the input / output power supply voltage and the ground terminal voltage.

8. The method according to claim 7, characterized in that, Determining the third preset value based on the input / output power supply voltage and the ground terminal voltage includes determining the third preset value through the following formula: V3 = 50%×(VDDQ - VSSQ); Wherein, V3 represents the third preset value, VDDQ represents the input / output power supply voltage, and VSSQ represents the ground terminal voltage.

9. The method according to claim 1, characterized in that The memory chip includes LPDDR3 memory.

10. A device for detecting the characteristics of a memory chip, characterized in that, Comprising: A main control unit electrically coupled to the memory chip, and the on-chip termination resistance value of the memory chip associated with the data queue signal is set to a first preset value. The main control unit is configured to: Set the drive strength resistance value of the main control unit associated with the data queue signal to a second preset value, and the second preset value is greater than the first preset value; Write preset data with a low level into the memory chip; Provide a sampling level with a third preset value to the memory chip; Read data from the memory chip, and compare the read data with the preset data to obtain a comparison result; And Determine whether the memory chip has an on-chip termination resistance characteristic based on the comparison result.

11. An electronic device, characterized in that, Comprising: A memory configured to store an executable program; And A processor configured to execute the program such that the electronic device executes the method according to any one of claims 1 to 9.

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