Frequency set point function test method, device, equipment and medium

Abstract

The invention relates to the technical field of testing, in particular to a frequency set point function testing method and device, equipment and a medium, and the method comprises the steps: setting a target memory, setting a working point by adopting a first frequency, and writing a binary data array into a target memory unit in the target memory; setting a target memory to set a working point by adopting a second frequency, reading data in the target memory unit to obtain first read data, and writing the binary data array into the memory unit; setting the target memory to set a working point by adopting the first frequency, and reading the data in the target memory unit again to obtain second read data; and determining a test result according to the first read data, the second read data and preset expected read data. Therefore, the problems of low speed and poor time efficiency of the method for testing the function of the frequency set point in the memory chip can be solved.

Description

Technical Field

[0001] This application relates to the field of testing technologies, and in particular, to a method, device, equipment, and medium for testing a frequency set point function. Background Art

[0002] The frequency set point function (FSP) enables a storage chip to maintain normal operation after switching key parameters without performing new training. After enabling the FSP function, LPDDR (Low Power Double DataRate SDRAM, dynamic random access memory) can switch the command bus (CA bus) between two different operating frequencies as the voltage swing and terminal resistance change.

[0003] In the prior art, the testing method for the frequency set point function in a storage chip has a high testing time complexity and is difficult to meet the timeliness requirements of mass production testing. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method, device, equipment, and medium for testing a frequency set point function, which can effectively solve the problems of slow speed and poor timeliness of the testing method for the frequency set point function in a storage chip, etc.

[0005] In a first aspect, embodiments of this application provide a method for testing a frequency set point function, including: Enable the read and write functions of the first group of mode registers in the target memory, set the target memory to operate at a first frequency set point, and write a binary data array into a target storage unit in the target memory; Enable the read and write functions of the second group of mode registers in the target memory, set the target memory to operate at a second frequency set point, read the data in the target storage unit to obtain a first read data, and write the binary data array into the storage unit; Enable the read and write functions of the first group of mode registers in the target memory, set the target memory to operate at a first frequency set point, and read the data in the target storage unit again to obtain a second read data; Determine a test result according to the first read data, the second read data, and a preset expected read data.

[0006] In some embodiments, before enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to operate at a first frequency set point, and writing a binary data array into a target storage unit in the target memory, the method further includes: Initialize and set each group of mode registers, specifically including: during the power-on process of the target memory, and when setting the target memory to operate at a working point with a first frequency, use first parameter data to set the first group of mode registers; During the power-on process of the target memory, and when setting the target memory to operate at a working point with a second frequency, use second parameter data to set the second group of mode registers.

[0007] In some embodiments, it further includes: according to the working point set by the adopted frequency of the target memory, encapsulate the codes corresponding to initializing and setting each group of mode registers respectively, and correspondingly obtain a first sub-vector module and a second sub-vector module; use the first sub-vector module to set the first group of mode registers; use the second sub-vector module to set the second group of mode registers.

[0008] In some embodiments, enabling the read and write functions of the first group of mode registers in the target memory and setting the target memory to operate at a working point with a first frequency includes: During the power-on process of the target memory, write first configuration data into the target register in the target memory through a register write instruction, so as to achieve operating at the working point with the first frequency, enabling the read and write functions of the first group of mode registers, and executing an impedance calibration command and a latching command on the target memory; Enabling the read and write functions of the second group of mode registers in the target memory and setting the target memory to operate at a working point with a second frequency includes: During the power-on process of the target memory, write second configuration data into the target register in the target memory through a register write instruction, so as to achieve operating at the working point with the second frequency, enabling the read and write functions of the second group of mode registers, and executing an impedance calibration command and a latching command on the target memory.

[0009] In some embodiments, both the first configuration data and the second configuration data include: an operation code for enabling the read and write functions of the frequency set point, an operation code for controlling the switching of the frequency set working point, and an operation code for setting the level of the reference voltage pin.

[0010] In some embodiments, reading the data in the target storage unit includes: Using the automatic test equipment to sample the levels of each data input and output pin on the data bus of the target memory; Determining the test result according to the first read data, the second read data, and the preset expected read data includes: Compare the levels of each digit in the first read data and the second read data with a reference level respectively; if it is lower than the reference level, a first result is obtained, and if it is higher than the reference level, a second result is obtained; wherein, the expected read data includes the reference level corresponding to the digit, and the reference level is determined by the power supply voltage.

[0011] In some embodiments, the test frequency corresponding to the first frequency setting working point is 3200 Mbps; the test frequency corresponding to the second frequency setting working point is 4266 Mbps.

[0012] In a second aspect, an embodiment of the present application provides a frequency setting point function test device, including: A write data module, configured to enable the read and write functions of the first set of mode registers in the target memory, set the target memory to adopt the first frequency setting working point, and write a binary data array into the target storage unit in the target memory; A read and write data module, configured to enable the read and write functions of the second set of mode registers in the target memory, set the target memory to adopt the second frequency setting working point, read the data in the target storage unit to obtain first read data, and write the binary data array into the storage unit; A read data module, configured to enable the read and write functions of the first set of mode registers in the target memory, set the target memory to operate with the first frequency setting working point, and read the data in the target storage unit again to obtain second read data; A test result determination module, configured to determine a test result according to the first read data, the second read data, and a preset expected read data.

[0013] In a third aspect, an embodiment of the present application provides a terminal device, which includes a processor and a memory. The memory stores a computer program, and the processor is configured to execute the computer program to implement a frequency setting point function test method provided in the first aspect of the present application.

[0014] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed on a processor, it implements a frequency setting point function test method provided in the first aspect of the present application.

[0015] The embodiments of the present application have the following beneficial effects: In this application, by enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to operate at a working point with a first frequency setting, writing a binary data array into the target storage unit in the target memory; enabling the read and write functions of the second group of mode registers in the target memory, setting the target memory to operate at a working point with a second frequency setting, reading the data in the target storage unit to obtain a first read data, and writing the binary data array into the storage unit; enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to operate at a working point with a first frequency setting, reading the data in the target storage unit again to obtain a second read data; determining the test result based on the first read data, the second read data, and a preset expected read data. In this application, at a frequency setting working point, the corresponding mode register group is enabled, and data is written to the storage unit. At another frequency setting working point, another mode register group is enabled, and the data in the storage unit is read. By comparing the expected read data with the read data, the test result is obtained to verify whether the data is damaged due to frequency switching. The implementation method of this application is simple, the test speed is fast, and the applicability is relatively high. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of this application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of this application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0017] Figure 1 FIG. shows a schematic structural diagram of a replicable mode register involved in the frequency setting point function test method of the embodiments of this application; Figure 2 FIG. shows another parameter setting schematic diagram of the replicable mode register in the frequency setting point function test method of the embodiments of this application; Figure 3 FIG. shows a flowchart of the frequency setting point function test method of the embodiments of this application; Figure 4 FIG. shows a data schematic diagram of a binary data array involved in the frequency setting point function test method of the embodiments of this application; Figure 5 FIG. shows a schematic structural diagram of a frequency setting point function test device of the embodiments of this application.

[0018] MAIN ELEMENT SYMBOL DESCRIPTION: 510 - Write data module; 520 - Read and write data module; 530 - Read data module; 540 - Test result determination module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0020] The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Thus, the detailed description of the embodiments of the present application provided in the figures is not intended to limit the scope of the present application that is claimed, but is merely representative of selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0021] In the following, the terms "including", "having" and their cognates that may be used in various embodiments of the present application are only intended to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or precluding the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0022] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in a general use dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0023] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the embodiments described below and the features in the embodiments may be combined with each other.

[0024] The present application provides an automatic test system. Exemplarily, the automatic test system includes an automatic test device and a target memory. The automatic test device is communicatively connected to the target memory to perform an automatic test on the target memory. The target memory includes a replicable mode register and a storage unit. The target memory includes, but is not limited to, LPDDR4.

[0025] In the prior art, the Frequency Set Point (FSP) function is a new media characteristic that emerged with LPDDR4. It enables the storage chip to maintain normal operation after switching key parameters without new training. After enabling the FSP function, LPDDR can switch the CA bus between two different operating frequencies with changes in the voltage swing and terminal resistance. When parameters such as the supply voltage, terminal resistance, and register data change, the storage chip needs to perform new training to ensure the accuracy of the drive frequency point and data sampling point during the test process, preventing the chip from being in an untrained state, which may lead to the loss of communication with the host controller. Enabling the FSP function can achieve the normal operation of the storage chip by copying the mode register parameters of all CA buses and other mode registers that change with the operating frequency, thus eliminating the need for new training. Changing the FSP-WR bit enables the MR (Mode Register) parameters to be changed for an alternative frequency set point without affecting the current operation. Once all necessary parameters are written to the standby set point, changing the FSP operation bit will switch the operation to use all new parameters (within tFC), eliminating the possibility of communication loss caused by partial configuration changes. Here, tFC is the transition time, which refers to the time required for the FSP operation bit (FSP-OP) to change to the new frequency set point to take full effect. Further, tFC is a timing parameter related to the operation of the DRAM chip, specifically representing the delay time during the FSP (Frequency Set Point) switching process. It is an important time constraint to ensure the normal operation of the FSP function. The replicable mode register has two sets of physical registers. Assume they are Group A (the first set of mode registers) and Group B (the second set of mode registers), as Figure 1 shown. The mode registers with replicable register functions are Mode Register MR1, Mode Register MR2, Mode Register MR3, Mode Register MR11, Mode Register MR12, Mode Register MR14, and Mode Register MR22. These replicated registers use the same mode register address.

[0026] The frequency set point function test method of the embodiments of the present application mainly includes four items: mode register initialization, frequency point storage sequence design, memory matrix test algorithm, and test result data analysis. In the embodiments of the present application, the frequency set point (FSP) enables the CA bus to switch between two different operating frequencies with changes in voltage and impedance matching. For example, the operating frequency corresponding to the first frequency set working point is 3200 Mbps; the operating frequency corresponding to the second frequency set working point is 4266 Mbps.

[0027] The following will illustrate the frequency set point function test method with some specific embodiments.

[0028] Exemplarily, the frequency set point function test method includes the following steps: S000, initialize the mode register.

[0029] In the embodiments of the present application, the read / write access of each group of mode registers is controlled by the Bit FSP-WR (Frequency Set Point Write / Read) of the mode register 13 (abbreviated as MR13), and the operating point is controlled by the Bit FSP-OP (Frequency Set Point Operation Mode) of MR13. Exemplarily, MR13 includes 8 data bits, namely OP[0]-OP[7].

[0030] For the FSP-OP operation, FSP-OP represents the frequency set operating point. It is mainly enabled by MR13 OP[7], and the data bit defaults to 0. The DRAM (Dynamic Random Access Memory) uses the mode register N to set the FSP operation [0], that is, switch the group A mode register to the frequency point 0 (the first frequency set operating point). If the MR13 OP[7] data bit is written as 1, the DRAM uses the mode register N to set the FSP operation [1], that is, switch the group B mode register to the frequency point 1 (the second frequency set operating point). When the FSP-OP changes from 0 to 1, the reference voltage pin (VRCG) must change from normal current to high current, and this operation is achieved by setting MR13 OP[3] to 1 correspondingly. When the FSP-OP changes from 1 to 0, VRCG must change from high current to normal current, and this operation is achieved by setting MR13 OP[3] to 0 correspondingly.

[0031] Among them, in the FSP-WR operation, FSP-WR represents the frequency set point read / write. It is mainly enabled by MR13 OP[6], and the data bit defaults to 0. The data is written into the mode register N of the FSP operation [0] through the MRW command, that is, a write operation is performed on the group A mode register. If the MR13 OP[6] data bit is written as 1, the data is written into the mode register N of the FSP operation [1] through the MRW command, that is, a write operation is performed on the group B mode register. The MRW (Mode Register Write) instruction is a command used to write data to the mode register (Mode Register). The mode register is an important part for storing and configuring the working parameters of the memory chip. Through the MRW instruction, these parameters can be flexibly set and modified to meet different working requirements.

[0032] Perform initialization settings on each group of mode registers, specifically including: S010, during the power-on process of the target memory, and when the target memory is set to operate at the first frequency setting working point, the first set of mode registers is set using the first parameter data.

[0033] S020, during the power-on process of the target memory, and when the target memory is set to operate at the second frequency setting working point, the second set of mode registers is set using the second parameter data.

[0034] Exemplarily, this application mainly completes the fixed-point frequency switching verification at 3200 / 4266Mpbs. As Figure 2 shown, during the power-on process of the target memory, for mode registers MR1, MR2, MR3, MR11, MR12, MR14, MR22, at the test frequency of 3200Mpbs, the corresponding parameter settings of the mode registers are D1A, D1B, D1C, D1E, D1F, D1G, D1H respectively. At the test frequency of 4266Mpbs, the corresponding parameter settings of the mode registers are D2A, D2B, D2C, D2E, D2F, D2G, D2H. This operation realizes the configuration of timing and characteristic parameters according to the chip data manual during the power-on process of the die itself. By writing the corresponding frequency register through the MRW instruction, this sequence can be defined at the ATE code level and instantiated as a sub-vector module MRSET.

[0035] It can be understood that according to the frequency setting working point adopted by the target memory, the codes for initializing and setting the corresponding groups of mode registers are respectively encapsulated, and the first sub-vector module MRSET1 and the second sub-vector module MRSET2 are correspondingly obtained. The first set of mode registers is set using the first sub-vector module; the second set of mode registers is set using the second sub-vector module.

[0036] Mode register 13 (abbreviated as MR13) of this application includes 8 digits, namely OP[0]-OP[7]. Among them, OP[7] is used to control the selection of the frequency setting working point to be used, and OP[6] is used to control the reading and writing of which group of mode registers. OP[7]=0 indicates that the first frequency setting working point is adopted, and the corresponding test frequency is 3200Mbps; OP[6]=0 indicates enabling the reading and writing functions of the first set of mode registers. The following introduces the control method for switching the frequency setting working point and the control method for enabling the reading and writing functions of each group of mode registers: Step1: Write #00 (corresponding binary is 00000000) to mode register 13. The data on each digit is shown in Table 1. After the die internally receives a main control signal similar to that sent by the ATE, the configuration is written through MRW, thereby selecting group A mode registers and performing the operation of switching to frequency point 0. This step is equivalent to the frequency information storage stage at 3200.

[0037] Table 1 Each digit in MR13 (Part 1)

[0038] Step2: Store the frequency information of 3200 into the Group A mode register. Therefore, the write operation can be completed sequentially through the sub-vector module MRSET1 set by initialization, strictly set to the default value matching the current frequency. At this time, after the MRSET1 module completes the configuration of the Group A mode register, the storage of the 3200 frequency point information is completed.

[0039] Step3: Execute the ZQCAL and ZQLatch commands, and the storage chip (target memory) completes data calibration and latching. In the LPDDR4 chip, the ZQCAL and ZQLatch commands are usually used for data calibration and latching. Specifically, the ZQCAL command is used for impedance calibration. The output driver of the LPDDR4 chip needs to adjust the impedance according to the external environment (such as temperature, voltage, etc.) to ensure the quality of signal transmission. The ZQCAL command will trigger the chip to automatically adjust the impedance parameters to ensure signal integrity. The ZQLatch command is used to latch the calibrated impedance parameters. After calibration, the ZQLatch command will fix the calibrated impedance value for subsequent read and write operations.

[0040] Step4: Store the frequency point information of 4266. Similar to Step1 - 2, switch the data in MR13 to #C8 (corresponding binary is 11001000), and the selected write configuration is the Group B mode register, frequency point 1. At this time, it should be noted that when switching the frequency point from 0 to 1, the VRCG needs to be set high synchronously, and the data written in MR13 is shown in Table 2. OP[7]=0 indicates that the first frequency setting working point is adopted, and the corresponding test frequency is 3200Mbps; OP[6]=0 indicates enabling the read and write functions of the first group of mode registers.

[0041] Table 2 Each digit in MR13 (Part 2)

[0042] Step5: After completing the configuration of the 4266 frequency point, execute the ZQCAL and ZQLatch commands, and the storage chip (target memory) completes data calibration and latching.

[0043] The following describes the frequency setting point function test method of the embodiment of the present application based on the above control method for switching the frequency setting working point and the control method for enabling the read and write functions of each group of mode registers.

[0044] Figure 3A flowchart of a frequency setpoint function test method according to an embodiment of the present application is shown. Exemplarily, the frequency setpoint function test method includes the following steps: S100, enable the read / write function of the first set of mode registers in the target memory, set the target memory to operate at a first frequency setpoint, and write the binary data array into the target storage unit in the target memory.

[0045] S200, enable the read / write function of the second set of mode registers in the target memory, set the target memory to operate at a second frequency setpoint, read the data in the target storage unit to obtain a first read data, and write the binary data array into the storage unit.

[0046] S300, enable the read / write function of the first set of mode registers in the target memory, set the target memory to operate at the first frequency setpoint, and read the data in the target storage unit again to obtain a second read data.

[0047] S400, determine the test result according to the first read data, the second read data, and the preset expected read data.

[0048] The present application places no restrictions on the read / write order of the first set of mode registers and the second set of mode registers. Data is written at one frequency setpoint and read at another frequency setpoint.

[0049] In one embodiment, enabling the read / write function of the first set of mode registers in the target memory and setting the target memory to operate at a first frequency setpoint includes: During the power-on process of the target memory, write the first configuration data into the target register in the target memory by means of a register write instruction, so as to operate at the first frequency setpoint and enable the read / write function of the first set of mode registers, and execute an impedance calibration command and a latch command on the target memory. For example, complete data calibration and latching by executing the ZQCAL command (impedance calibration command) and the ZQLatch command (latch command). Then, after the power-on of the target memory is completed, write the binary data array into the target storage unit in the target memory.

[0050] Enabling the read / write function of the second set of mode registers in the target memory and setting the target memory to operate at a second frequency setpoint includes: During the power-on process of the target memory, the second configuration data is written into the target register in the target memory through a register write instruction, so as to operate at the second frequency setting working point, enable the read and write functions of the second group of mode registers, and execute an impedance calibration command and a latching command on the target memory. For example, by executing the ZQCAL command (impedance calibration command) and the ZQLatch command (latching command), data calibration and latching are completed. Then, after the power-on of the target memory is completed, the binary data array is written into the target storage unit in the target memory.

[0051] It can be understood that the target register includes multiple data bits; both the first configuration data and the second configuration data include: an operation code for enabling the read and write functions of the frequency setting point, an operation code for controlling the switching of the frequency setting working point, and an operation code for setting the level of the reference voltage pin. The operation code for enabling the read and write functions of the frequency setting point (corresponding to 0 / 1 in binary) is used to control the enabling of the read and write functions of the first group of mode registers or the second group of mode registers; the operation code for controlling the switching of the frequency setting working point (corresponding to 0 / 1 in binary) is used to control the selection of the first frequency setting working point or the second frequency setting working point. The operation code for setting the level of the reference voltage pin (corresponding to 0 / 1 in binary) is used to control the level of the reference voltage pin. Among them, the target register is MR13, the first configuration data is #00, and the second configuration data is #C8.

[0052] In one embodiment, reading the data in the target storage unit includes: Using the levels of each data input / output pin (DQ pin) on the data bus of the target memory by an automatic test equipment. For example, the ATE collects the high and low levels of each DQ pin on the data bus of the target memory.

[0053] Determining the test result according to the first read data, the second read data, and the preset expected read data includes: Comparing the levels of each digit in the first read data and the second read data with the reference level respectively; if it is lower than the reference level, the first result is obtained, and if it is higher than the reference level, the second result is obtained; among them, the expected read data includes the reference level corresponding to each digit, and the reference level is determined by the power supply voltage.

[0054] For example, comparing the levels of each digit in the first read data with the reference level. Set the reference level to 0.5*VDDQ. If the value of the digit in the first read data is lower than the reference level, it is determined as "0", and if it is higher than the reference level, it is determined as "1". Therefore, by comparing the collected data bits, if they do not match, it is determined as a failure, and if they match, it is determined as a pass.

[0055] The following introduces the frequency setting point function test method of the present application based on LPDDR4: S510, Configure the test environment. Ensure that the ATE device is well-connected, check the power supply and signal integrity. Set the ambient temperature to 27°C and humidity to 50% to avoid environmental interference.

[0056] S520, Load the test program. Load the test program into the ATE system to ensure that the program can execute FSP-related commands.

[0057] S530, Initialize the memory control parameters.

[0058] Set the basic parameters of memory control, such as address mapping, timing configuration, and voltage setting; ensure that the selected initial frequency complies with the LPDDR4 specification.

[0059] S540, At a test frequency of 3200 Mbps, during the power-on process of the target memory, write #00 (binary 00000000) to the MR13 register through a register write instruction for configuration. That is, the invocation of the A-group mode register. When the target memory is powered on and stable, write a binary data array to the storage unit at a frequency of 3200. The binary data array format is as Figure 4 shown.

[0060] S550, At a test frequency of 4266 Mbps, during the power-on process of the target memory, write #C8 to the MR13 mode register through a register write instruction for configuration. That is, the invocation of the B-group mode register. When the target memory is powered on and stable, read the data in the storage unit through a read operation at a frequency of 4266 Mbps to obtain the first read data.

[0061] S560, At a test frequency of 4266 Mbps, during the power-on process of the target memory, write #C8 to the MR13 register through a register write instruction for configuration, that is, the invocation of the B-group register. When the target memory is powered on and stable, write a binary data array to the storage unit at a test frequency of 4266 Mbps.

[0062] S570, At a test frequency of 3200 Mbps, during the power-on process of the target memory, write #00 to the MR13 mode register through a register write instruction for configuration. That is, the invocation of the A-group mode register. When the target memory is powered on and stable, read the data in the storage unit at a frequency of 3200 to obtain the second read data.

[0063] S580, Compare the first read data with the expected data, and compare the second read data with the expected data to obtain the result of whether the test passes.

[0064] In the prior art, mode registers are usually used for static configuration (such as fixed frequency / voltage), while in this application, by dynamically switching the MR group, frequency hopping in a real scenario is simulated. In this application, for the first time: write at the first frequency (the first frequency sets the operating point) → read at the second frequency (the second frequency sets the operating point) to detect the residual interference of high-frequency data at low frequencies; for the second time: restore the first frequency → read again to verify whether the data is damaged due to frequency switching. This application can not only accurately locate transient data errors caused by frequency switching, but also improve the test coverage rate, and is especially suitable for the reliability verification of high-frequency memories (such as LPDDR5, HBM).

[0065] In summary, compared with the prior art, the advantages of this application are as follows: (1) Improved test efficiency: The time complexity of traditional testing is high, and it is difficult to meet the timeliness requirements of mass production testing. The testing method of this application shortens the testing time by more than 40%, improves the coverage rate of fault modes that can be checked, and is suitable for mass production testing.

[0066] (2) Strong compatibility: It can be widely applied to the mass production testing of memory chips, the quality verification of each generation of DDR and LPDDR4 / 4X / 5 / 5X, as well as reliability evaluation, and the failure analysis of memory products.

[0067] Figure 5 Fig. shows a schematic structural diagram of a frequency setting point function testing device according to an embodiment of this application. Exemplarily, the frequency setting point function testing device includes: a write data module 510, a read-write data module 520, a read data module 530, and a test result determination module 540.

[0068] The write data module 510 is used to enable the read-write function of the first group of mode registers in the target memory, set the target memory to operate at the first frequency, and write a binary data array into the target storage unit in the target memory; The read-write data module 520 is used to enable the read-write function of the second group of mode registers in the target memory, set the target memory to operate at the second frequency, read the data in the target storage unit to obtain a first read data, and write the binary data array into the storage unit; The read data module 530 is used to enable the read-write function of the first group of mode registers in the target memory, set the target memory to operate at the first frequency, and read the data in the target storage unit again to obtain a second read data; The test result determination module 540 is used to determine the test result according to the first read data, the second read data, and a preset expected read data.

[0069] It can be understood that the device in this embodiment corresponds to the frequency setpoint function test method in the above embodiment. The optional items in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0070] This application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory. Among them, the memory stores a computer program, and the processor runs the computer program, so that the terminal device executes the above frequency setpoint function test method or the functions of each module in the above frequency setpoint function test device. The terminal device is an automated test device.

[0071] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application.

[0072] The memory can be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. Among them, the memory is used to store the computer program, and after receiving the execution instruction, the processor can execute the computer program accordingly.

[0073] The present application also provides a computer-readable storage medium for storing the computer program used in the above terminal device. For example, the computer-readable storage medium may include, but is not limited to: various media capable of storing program codes such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0074] In several embodiments provided by the present application, it should be understood that the disclosed apparatus and method can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the apparatus, method, and computer program product according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0075] In addition, in each embodiment of the present application, each functional module or unit may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0076] If the above functions are implemented in the form of software functional modules and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0077] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

Claims

1. A method for testing a frequency setpoint function, characterized in that Including: Enable the read and write functions of the first group of mode registers in the target memory, set the target memory to work at a first frequency setting point, and write the binary data array into the target storage unit in the target memory; Enable the read and write functions of the second group of mode registers in the target memory, set the target memory to work at a second frequency setting point, read the data in the target storage unit to obtain a first read data, and write the binary data array into the storage unit; Enable the read and write functions of the first group of mode registers in the target memory, set the target memory to work at a first frequency setting point, and read the data in the target storage unit again to obtain a second read data; Determine the test result according to the first read data, the second read data and a preset expected read data.

2. The frequency setting point function test method according to claim 1, characterized in that Before enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to work at a first frequency setting point, and writing the binary data array into the target storage unit in the target memory, the method further includes: Perform initialization settings on each group of mode registers, specifically including: during the power-on process of the target memory and when setting the target memory to work at a first frequency setting point, set the first group of mode registers with first parameter data; During the power-on process of the target memory and when setting the target memory to work at a second frequency setting point, set the second group of mode registers with second parameter data.

3. The frequency setting point function test method according to claim 2, wherein Also including: According to the frequency setting working point adopted by the target memory, encapsulate the codes corresponding to the initialization settings of each group of mode registers respectively to obtain a first sub-vector module and a second sub-vector module; use the first sub-vector module to set the first group of mode registers; use the second sub-vector module to set the second group of mode registers.

4. The frequency setting point function test method according to claim 1, characterized in that The enabling the read and write functions of the first group of mode registers in the target memory and setting the target memory to work at a first frequency setting point includes: During the power-on process of the target memory, write first configuration data into the target register in the target memory through a register write instruction to achieve working at the first frequency setting point and enabling the read and write functions of the first group of mode registers, and execute an impedance calibration command and a latch command on the target memory; The enabling the read and write functions of the second group of mode registers in the target memory and setting the target memory to work at a second frequency setting point includes: During the power-on process of the target memory, write second configuration data into the target register in the target memory through a register write instruction to achieve working at the second frequency setting point and enabling the read and write functions of the second group of mode registers, and execute an impedance calibration command and a latch command on the target memory.

5. The frequency set point function test method according to claim 4, characterized in that, Both the first configuration data and the second configuration data include: an operation code for enabling the frequency setting point read and write function, an operation code for controlling the switching of the frequency setting working point, and an operation code for setting the level of the reference voltage pin.

6. The frequency setting point function test method according to claim 1, characterized in that Reading the data in the target storage unit includes: Using the levels of each data input / output pin on the data bus of the target memory by an automatic test equipment; Determining the test result according to the first read data, the second read data and a preset expected read data includes: Comparing the levels of each digit in the first read data and the second read data with a reference level respectively; if it is lower than the reference level, a first result is obtained, and if it is higher than the reference level, a second result is obtained; wherein, the expected read data includes the reference level of the corresponding digit, and the reference level is determined by the power supply voltage.

7. The frequency set point function test method according to any one of claims 1-6, characterized in that The test frequency corresponding to the first frequency setting working point is 3200 Mbps; the test frequency corresponding to the second frequency setting working point is 4266 Mbps.

8. A frequency setpoint function test device, characterized in that, Including: A write data module, configured to enable the read / write function of the first group of mode registers in the target memory, set the target memory to adopt the first frequency setting working point, and write the binary data array into the target storage unit in the target memory; A read / write data module, configured to enable the read / write function of the second group of mode registers in the target memory, set the target memory to adopt the second frequency setting working point, read the data in the target storage unit to obtain the first read data, and write the binary data array into the storage unit; A read data module, configured to enable the read / write function of the first group of mode registers in the target memory, set the target memory to operate at the first frequency setting working point, and read the data in the target storage unit again to obtain the second read data; A test result determination module, configured to determine the test result according to the first read data, the second read data and a preset expected read data.

9. A terminal device, characterized in that, The terminal device includes a processor and a memory, the memory stores a computer program, and the processor is configured to execute the computer program to implement the frequency setting point function test method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a computer program, and when the computer program is executed on a processor, it implements the frequency setting point function test method according to any one of claims 1-7.

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