Semiconductor packaging structure and manufacturing method thereof
By adopting a double ball grid array design in the semiconductor package, the adhesion of the second ball planting ball planting in the first ball planting gap is used to form a redistributed conductive line, which solves the problems of ball grid array cracks and line detours, and improves the quality and life of the package.
Patent Information
- Application Number
- CN202410080169.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-19
- Publication Date
- 2025-07-22
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The ball grid arrays in semiconductor packages are prone to cracks during thermal cycle testing or production, resulting in the short life cycle of the chip product. At the same time, the line detour problem in the connecting line redistribution layer affects signal delay.
A double ball grid array design is adopted, wherein the first ball grid array is used for signal connection, and the implanted balls of the second ball grid array are arranged in the transverse gap between the first ball grid and adhered by a reflow step to form a redistributed conductive circuit to enhance the cured adhesion range of the ball grid and reduce the circuit bend.
It effectively improves the problem of ball planting cracks, extends the number of thermal cycle tests and product life cycle of semiconductor packaging, and reduces the signal delay of connecting lines to betrayed.
Smart Images
Figure CN120356867A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor packaging technology, which can be applied to the ball grid array of chip packaging, and particularly relates to a packaging technology for extending the life cycle of the ball implantation in the ball grid array. Background Art
[0002] In the ball grid array of semiconductor packaging, cracks may occur in the ball implantation of BGA during the thermal cycle test or the manufacturing process. These cracks may cause many quality defects such as a too short life cycle of the chip product. In addition, in the wafer-level packaging of traditional technologies, the re-distributed layer (RDL) of the connection lines needs to plan many signal connection lines, and the distances of many detoured lines may cause signal delay due to being too long or other parasitic effects, affecting the overall instruction cycle.
[0003] The packaging improvement technology proposed by the present invention can significantly improve the aforementioned ball implantation cracks and reduce the trouble of line detouring in the re-distributed layer of the connection lines, thereby improving the quality of semiconductor packaging. Summary of the Invention
[0004] In one aspect, a semiconductor packaging structure provided by the present invention includes: a substrate having a top side and a bottom side; a first ball grid array disposed on the bottom side of the substrate, the first ball grid array having a plurality of first ball implantations, wherein the first ball grid array has a signal connection function between the substrate and an external printed circuit board; and a second ball grid array disposed on the bottom side of the substrate, the second ball grid array having a plurality of second ball implantations, and the second ball implantations are disposed in the horizontal gaps between the first ball implantations on the bottom side.
[0005] In one embodiment, the semiconductor packaging structure further includes an integrated circuit disposed above the top side of the substrate.
[0006] In one embodiment, the first ball implantations are made of a conductive material, and the second ball implantations are made of a conductive material or a non-conductive material.
[0007] In one embodiment, during the reflow step, the melt flow of at least a part of the first ball implantations in the first ball grid array adheres to at least a part of the second ball implantations in the second ball grid array.
[0008] In one embodiment, the second ball implantations are made of an electrically conductive material. The mutually attached second ball implantations and first ball implantations form a re-distributed conductive line under the bottom side. In the re-distributed conductive line, a conduction circuit is formed between two first ball implantations through the attached second ball implantations.
[0009] In one embodiment, the setting of the second ball implantations increases the curing and attachment range of the first ball implantations on the bottom side of the substrate when melting.
[0010] In one embodiment, in the reflow step, the second solder balls melt in the lateral gaps between the first solder balls to form an attachment structure, and the attachment structure reduces the outward protrusion height of the first solder balls on the bottom side.
[0011] In one embodiment, the first and second ball grid arrays are fabricated by different ball grid array processes respectively.
[0012] In one embodiment, between the first solder balls and the second solder balls, they are not stacked on the bottom side respectively.
[0013] In one embodiment, at least one second solder ball is disposed in the lateral gap between two first solder balls. Alternatively, at least one second solder ball is disposed in the lateral gap between four first solder balls.
[0014] In one embodiment, the first solder ball has a first lateral protrusion disposed on a first lateral side of the first solder ball facing the second solder ball; or the second solder ball has a second lateral protrusion disposed on a second lateral side of the second solder ball facing the first solder ball. In the reflow step, the first and second solder balls are melt-attached to each other through the first lateral protrusion or the second lateral protrusion.
[0015] In one aspect, the present invention provides a method for manufacturing a semiconductor package structure, comprising: providing a substrate having a top side and a bottom side, with an integrated circuit disposed above the top side of the substrate; performing a first ball grid array process on the bottom side to generate a plurality of first solder balls; performing a second ball grid array process on the bottom side to generate a plurality of second solder balls, the second solder balls being disposed in the lateral gaps between the first solder balls on the bottom side; and performing a reflow step, in which the melt flow of at least a part of the first solder balls in the first ball grid array and the melt flow of at least a part of the second solder balls in the second ball grid array have an attachment relationship.
[0016] The following is a detailed description through specific embodiments to more easily understand the purpose, technical content, features and achieved effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram showing a semiconductor package structure according to an embodiment of the present invention.
[0018] Figures 2A to 2D A schematic diagram showing the layout of the first and second solder balls according to two embodiments of the present invention.
[0019] Figures 3A to 3D A schematic diagram showing the manufacturing process of the first and second ball grid arrays according to an embodiment of the present invention.
[0020] Figures 4A to 4G A schematic diagram showing the combination of the first lateral protrusion and the second lateral protrusion according to multiple embodiments of the present invention.
[0021] Figure 5 Schematic diagram showing that in an embodiment of the present invention, on the bottom side, the outer protrusion height of the first solder ball is higher than that of the second solder ball.
[0022] Symbol description in the figure
[0023] 10: Semiconductor package structure
[0024] 110: Substrate
[0025] 110t: Top side
[0026] 110b: Bottom side
[0027] 120: First ball grid array
[0028] 122: First solder ball
[0029] 122e: First lateral protrusion
[0030] 130: Second ball grid array
[0031] 132: Second solder ball
[0032] 132e: Second lateral protrusion
[0033] Eh: Outer protrusion height
[0034] Gp: Lateral gap
[0035] IC: Integrated circuit
[0036] PCB: External printed circuit board Detailed implementation manners
[0037] The drawings in the present invention are all schematic, mainly intended to show the mutual connection relationship between the components of each component unit. The operation or function range of each component unit is described according to the following embodiments.
[0038] Refer to Figure 1, in one aspect, a semiconductor package structure 10 provided by the present invention includes: a substrate 110 having a top side 110t and a bottom side 110b; a first ball grid array 120 disposed on the bottom side 110b of the substrate 110. The first ball grid array 120 has a plurality of first solder balls 122 (under the bottom side 110b, the larger solder balls represent the first solder balls 122, and the first ball grid array 120 is composed of a plurality of first solder balls 122; the smaller solder balls represent the second solder balls 132, and the second ball grid array 130 is composed of a plurality of second solder balls 132). Among them, the first ball grid array 120 has a signal connection function between the substrate 110 and an external printed circuit board PCB, and this signal connection function can be generated by electrically connecting the substrate 110 and the external printed circuit board PCB through the first solder balls 122; and a second ball grid array 130 disposed on the bottom side 110b of the substrate 110. The second ball grid array 130 has a plurality of second solder balls 132, and the second solder balls 132 are disposed in the lateral gap Gp between the first solder balls 122 on the bottom side 110b. The semiconductor package structure 10 of the present invention can be, for example, a wafer-level package structure, other related package structures, or a circuit board with a similar solder ball structure. Among them, the first and second ball grid arrays 120 and 130 are made by different ball grid array processes. The manufacturing materials of the first and second ball grid arrays 120 and 130 can be the same material or different materials as needed. The first and second solder balls 122 and 132 can be the same size or different sizes as needed. For a detailed description, reference can be made to the description of other embodiments. In the dual ball grid array design of the present invention, the first ball grid array 120 has a signal connection function between the substrate 110 and the external printed circuit board PCB, that is, the first solder balls 122 of the first ball grid array 120 can be signal contacts corresponding to the external printed circuit board PCB, while the second solder balls 132 of the second ball grid array 130 are not limited to signal contacts corresponding to the external printed circuit board PCB (for example, the second solder balls 132 do not correspond to signal contacts of the external printed circuit board PCB). The purposes of this design at least include: improving the common solder ball cracks in the prior art (for example: increasing the solder ball volume by the attachment method between the first and second solder balls 122 and 132, reducing the stress influence; providing side protection for the first solder balls 122 in the first ball grid array 120, reducing the possibility of lateral damage to the first solder balls 122; or, when the thermal conductivity coefficient of the material of the second solder balls 132 is lower than that of the material of the first solder balls 122, the second solder balls 132 can delay the cooling rate of the first solder balls 122 after a reflow step, etc., to maintain the stable degree of curing attachment of the first solder balls 122), and reducing the troubles caused by line routing or overlong lines in the connection line redistribution layer.
[0039] Continue to refer to Figure 1, In one embodiment, the semiconductor package structure 10 further includes an integrated circuit IC disposed above the top side 110t of the substrate 110. There is an electrical connection between the integrated circuit IC and the substrate 110. Through the substrate 110, the integrated circuit IC can be signal-connected (or electrically connected) to a plurality of first solder balls 122 on the bottom side 110b of the substrate 110. The connection method is, for example, wafer-level packaging or wire bonding, etc.
[0040] Referring to Figure 1 、 Figure 2A , where the horizontal direction is determined according to the plane direction (or horizontal direction) of the substrate 110, and the vertical direction is the direction from the substrate 110 to the external printed circuit board PCB or the integrated circuit IC.
[0041] In one embodiment, the first solder balls 122 are made of a conductive material, and the second solder balls 132 are made of a conductive material or a non-conductive material. The substrate 110 and the first ball grid array 120 form a part of the electrical connection required for signal connection between the integrated circuit IC and the external printed circuit board PCB. Figure 2A Illustrates the states of the first and second solder balls 122 and 132 on the bottom side 110b before the reflow step. The number, size, and position of the first and second solder balls 122 and 132 are only for illustration. After the reflow step, the first and second solder balls 122 and 132 may still remain unattached to each other, similar to Figure 2A shown. Or, as Figure 2B shown, an attachment is formed between the first and second solder balls 122 and 132 during the reflow step. When the second solder balls 132 are made of a conductive material, through the conductivity of the second solder balls 132, an electrically conductive path between the two first solder balls 122 can be provided. Figure 2B In the embodiment shown in Figure 2C , the second solder balls 132 are attached to the first solder balls 122 after melting. In other embodiments, it may also be that the first solder balls 122 are attached to the second solder balls 132 after melting, or the first and second solder balls 122 and 132 are attached to each other. In addition, referring to Figure 2D is Figure 2C the attachment structure formed by the second solder balls 132 during melting. Here, the attachment structure is solely composed of the second solder balls 132. In another embodiment, the melted second solder balls 132 may also be attached to the surrounding first solder balls 122.
[0042] The non-conductive material of the second solder ball 132, for example, the central part of the solder ball is a conductive material, and the surface of the solder ball is coated with a non-conductive material. When the second solder ball 132 is partially melted, it can still maintain non-conductive characteristics. Alternatively, the second solder ball 132 can be made of non-conductive material, or the whole can be non-conductive material. Among them, when adhesion occurs between the first and second solder balls 122 and 132, different potentials can be maintained between the first and second solder balls 122 and 132, that is, there is no electrical conduction between the first and second solder balls 122 and 132.
[0043] In one embodiment, during the reflow step, the melt flow of at least a part of the first solder balls 122 in the first ball grid array 120 adheres to at least a part of the second solder balls 132 in the second ball grid array 130. Among them, the melted part of the first solder balls 122 during the reflow step can adhere to the second solder balls 132 due to the action of surface tension and the like. It is also possible that both the first and second solder balls 122 and 132 are melted and adhered to each other. This depends on the design and materials of the first and second solder balls 122 and 132.
[0044] In one embodiment, the second solder ball 132 is made of an electrically conductive material. The mutually adhering second solder ball 132 and the first solder ball 122 form a redistribution conductive line under the bottom side 110b. This redistribution conductive line is not the connection line redistribution layer above the top side 110t, but the conductance path formed between the first and second solder balls 122 and 132 on the bottom side 110b. In the redistribution conductive line, for example, in a CMOS circuit, in addition to connecting signals to the designated first solder ball 122 through multiple layers of connection lines, signals can also be connected to the designated first solder ball 122 through the electrical conduction between the second solder ball 132 and the first solder ball 122.
[0045] In one embodiment, the setting of the second solder ball 132 can increase the curing adhesion range of the first solder ball 122 on the bottom side 110b of the substrate 110 when the first solder ball 122 is melted. For example, the setting of the second solder ball 132 increases the action range of the surface tension of the first solder ball 122 in the molten state, which can extend outward to the lateral second solder ball 132 and adhere to the second solder ball 132 after curing. In this way, the curing adhesion range of the first solder ball 122 can be increased after curing. Alternatively, the first and second solder balls 122 and 132 are mutually melted and adhered to jointly increase the curing adhesion range on the bottom side 110b.
[0046] In one embodiment, during the reflow step, the second solder ball 132 melts in the lateral gap Gp between the first solder balls 122 to form an adhesion structure, and the adhesion structure can reduce the outward protrusion height Eh of the first solder ball 122 on the bottom side 110b ( Figure 5) Among them, the second solder ball 132 reduces the exposed portion on the side of the first solder ball 122, and can provide side protection for the first solder ball 122. Among them, the second solder ball 132 reduces the length of the first solder ball 122 protruding beyond the outer edge of the bottom side 110b, and reduces the possibility of damage to each first solder ball 122 from the side due to excessive protruding length.
[0047] In one embodiment, the first and second ball grid arrays 120 and 130 are respectively fabricated by different ball grid array processes (refer to Figures 3A to 3D ). Thus, the second ball grid array 130 can set the second solder balls 132 in the lateral gap Gp between the first solder balls 122 according to different requirements. Thus, due to being limited by the same ball grid array process, the ball planting plans and materials used for the first and second ball grid arrays 120 and 130 can be the same or different.
[0048] In one embodiment, between the first solder ball 122 and the second solder ball 132, they are respectively not stacked on the bottom side 110b. In other words, the first solder ball 122 and the second solder ball 132 are arranged in the same layer level on the bottom side 110b.
[0049] The setting method of the second solder ball 132 between the first solder balls 122 can have various choices according to needs. In one embodiment, at least one second solder ball 132 is set in the lateral gap Gp between two first solder balls 122, for example Figure 2A the second solder ball 132 in the upper left side is located between two first solder balls 122. Or, at least one second solder ball 132 is set in the lateral gap Gp between four first solder balls 122 (for example, Figure 2A in the lower right side, within the central area surrounded by four first solder balls 122, a second solder ball 132 is set). In one embodiment, there may also be no second solder ball 132 between some of the first solder balls 122 (for example, Figure 2A in other positions in, there is no second solder ball 132 between some of the first solder balls 122), which depends on needs.
[0050] In one embodiment, for the first solder balls 122 located at the edge of the substrate 110, the stress they bear is usually much higher than that of the first solder balls 122 in the central part, and the second solder balls 132 are mainly distributed between the first solder balls 122 at the edge of the substrate 110.
[0051] In the design of the first and second solder balls 122 and 132, there can be various choices according to needs, please refer to Figures 4A to 4G . In multiple embodiments, the first solder ball 122 has a first lateral protrusion 122e ( Figure 4A , Figure 4C , Figure 4E , Figure 4G), is disposed on a first lateral side (the same side as the first lateral protrusion 122e) of the first solder ball 122 facing the second solder ball 132; or, the second solder ball 132 has a second lateral protrusion 132e ( Figure 4B , Figure 4C , Figure 4D , Figure 4F , Figure 4G ), is disposed on a second lateral side (the same side as the second lateral protrusion 132e) of the second solder ball 132 facing the first solder ball 122. During the reflow step, the first and second solder balls 122 and 132 are melt-attached to each other through the first lateral protrusion 122e or the second lateral protrusion 132e.
[0052] In one embodiment, the heat dissipation effect of the second solder ball 132 is lower than that of the first solder ball 122. For example, the thermal conductivity coefficient of the material of the second solder ball 132 is lower than that of the first solder ball 122, or the external contact area of the second solder ball 132 is lower than that of the first solder ball 122, etc. During the cooling process after the reflow step, the second solder balls 132 located on both sides of the first solder ball 122 have the effect of delaying the temperature drop of the first solder ball 122, delaying the curing time of the first solder ball 122, and strengthening the attachment effect between the first solder ball 122 and the bottom side 110b.
[0053] If necessary, according to the present invention, a third ball grid array process can also be performed to more diversely produce the effect of assisting each first solder ball 122 in the first ball grid array 120.
[0054] In one aspect, the present invention provides a method for manufacturing a semiconductor package structure, including: providing a substrate having a top side and a bottom side, and an integrated circuit is disposed above the top side of the substrate; performing a first ball grid array process on the bottom side to generate a plurality of first solder balls; performing a second ball grid array process on the bottom side to generate a plurality of second solder balls, and the second solder balls are disposed in the lateral gaps between the first solder balls on the bottom side; and performing a reflow step, in which the melt flow of at least a part of the first solder balls in the first ball grid array is attached to at least a part of the second solder balls in the second ball grid array, or the melt flow of at least a part of the second solder balls in the second ball grid array is attached to at least a part of the first solder balls in the first ball grid array, or the melt flow of at least a part of the second solder balls in the second ball grid array and the melt flow of at least a part of the first solder balls in the first ball grid array are attached to each other. For the detailed content of each step, please refer to the description of the foregoing embodiments and will not be elaborated herein.
[0055] According to the technology of the present invention, the possibility of the first solder ball cracking is greatly reduced. Thus, the number of thermal cycle tests that the semiconductor package structure can withstand, or the product life cycle, can be extended.
[0056] The present invention has been described above with reference to the embodiments. However, as described above, it is only for facilitating the understanding of the content of the present invention by those skilled in the art, and is not used to limit the scope of the rights of the present invention. Under the same spirit of the present invention, those skilled in the art can conceive of various equivalent changes. For example, a first and a second ball grid array are provided on a substrate, wherein the first ball grid array forms the signal contact function on the bottom side of the substrate, and a plurality of second solder balls of the second ball grid array are disposed in the lateral gaps between the first solder balls on the bottom side, etc. In addition, the number and size of each element and structure in the drawings are only for illustration, and the user can decide the adoption method according to needs. The scope of the present invention should cover the combination between different embodiments or all other equivalent changes.
Claims
1. A semiconductor package structure, comprising: A substrate having a top side and a bottom side; A first ball grid array disposed on the bottom side of the substrate, the first ball grid array having a plurality of first solder balls, wherein the first ball grid array has a signal connection function between the substrate and an external printed circuit board; and A second ball grid array disposed on the bottom side of the substrate, the second ball grid array having a plurality of second solder balls, the second solder balls being disposed in the lateral gaps between the first solder balls on the bottom side.
2. The semiconductor package structure according to claim 1, wherein, It further includes an integrated circuit disposed above the top side of the substrate.
3. The semiconductor package structure according to claim 1, wherein, The first solder balls are made of a conductive material, and the second solder balls are made of a conductive material or a non-conductive material.
4. The semiconductor package structure according to claim 1, wherein, In a reflow step, the melt flow of at least a portion of the first solder balls in the first ball grid array adheres to at least a portion of the second solder balls in the second ball grid array; or, at least a portion of the second solder balls adheres to at least a portion of the first solder balls in the first ball grid array.
5. The semiconductor package structure as described in claim 4, wherein, The second solder balls are made of an electrically conductive material, and the adhered second solder balls and the first solder balls form a redistributed conductive line under the bottom side, wherein in the redistributed conductive line, at least two of the first solder balls are electrically connected through the adhered second solder balls.
6. The semiconductor package structure according to claim 4, wherein, The second solder balls increase the solidification adhesion range of the first solder balls on the bottom side during melting.
7. The semiconductor package structure as described in claim 4, wherein, In a reflow step, the second solder balls melt in the lateral gaps between the first solder balls to form an adhesion structure, and the adhesion structure reduces the outward protrusion height of the first solder balls on the bottom side.
8. The semiconductor package structure as claimed in claim 1, wherein, The first and second ball grid arrays are respectively made by different ball grid array manufacturing processes.
9. The semiconductor package structure as described in claim 1, wherein, The first solder balls and the second solder balls are respectively disposed on the bottom side in a non-stacked manner.
10. The semiconductor package structure as described in claim 9, wherein, The first ball grid array and the second ball grid array are located on the same tier.
11. The semiconductor package structure according to claim 1, wherein, At least one second solder ball is disposed in the lateral gap between two of the first solder balls.
12. The semiconductor package structure according to claim 1, wherein, At least one second solder ball is disposed in the lateral gap between four of the first solder balls.
13. The semiconductor package structure as described in claim 1, wherein, The first solder balls have first lateral protrusions disposed on a first lateral side of the first solder balls facing the second solder balls; or, the second solder balls have second lateral protrusions disposed on a second lateral side of the second solder balls facing the first solder balls, wherein in a reflow step, the first and second solder balls are melt-attached through the first lateral protrusions or the second lateral protrusions.
14. A method for manufacturing a semiconductor package structure, comprising: Providing a substrate having a top side and a bottom side, wherein an integrated circuit is disposed above the top side of the substrate; Performing a first ball grid array manufacturing process on the bottom side to generate a plurality of first solder balls; Performing a second ball grid array manufacturing process on the bottom side to generate a plurality of second solder balls, the second solder balls being disposed in the lateral gaps between the first solder balls on the bottom side; and Perform a reflow step, wherein in the reflow step, the molten flow of at least some of the first solder balls in the first ball grid array adheres to at least some of the second solder balls in the second ball grid array, or wherein the molten flow of at least some of the second solder balls in the second ball grid array adheres to at least some of the first solder balls in the first ball grid array, or wherein the molten flow of at least some of the second solder balls in the second ball grid array adheres to the molten flow of at least some of the first solder balls in the first ball grid array.